Hardware Designs Dashboard

This dashboard gives the current status of Comportable designs within the OpenTitan project. See the Hardware Development Stages for description of the hardware stages and how they are determined.

Module Version Life Stage Design Stage Verification Stage Commit ID Notes
aes 0.5 L1 D2 V0  

 

alert_handler 0.5 L1 D1 V0  

will be verified at top level; formal at block level

entropy_src 0.5 L0      

 

flash_ctrl 0.5 L1 D1 V0  

 

gpio 1.0 L2 D3 V3 a463868

 

1.1 L1 D2 V2 f3039d7

Rolled back to D2 as the register module is updated

hmac 0.5 L2 D3 V3 635afdb

 

0.6 L1 D2 V1 48fd7fd

Rolled back to D2 in order to add the first alert

i2c 0.5 L1 D0 V0  

 

nmi_gen 0.5 L1 D0 V0  

will be verified at top level; formal at block level

padctrl 0.5 L1 D1 V0  

will be verified at top level; formal at block level

pinmux 0.5 L1 D1 V0  

will be verified at top level; formal at block level

rv_core_ibex 0.5 L1 D2 V1  

 

rv_dm 0.5 L1 D0 V0  

 

rv_plic 0.5 L1 D0 V0  

will be verified at top level; formal at block level

rv_timer 0.5 L2 D3 V3 a463868

 

0.6 L1 D2 V2 f3039d7

Rolled back to D2 as the register module is updated

spi_device 0.5 L1 D1 V1 553ca95

 

tlul 0.5 L2 D3 V3 f723f32

the target for this entry is the autogenerated xbar_main within top_earlgrey.

1.0 L1 D1 V1 2366287

Rolled back to D1V1 as more features (like multi-clock) are being updated

uart 1.0 L2 D3 V3 92e4298

 

1.1 L1 D2 V2 f3039d7

Rolled back to D2 as the register module is updated