Overview

This document specifies the ADC controller IP functionality. This IP block implements control and filter logic for an analog block that implements a dual ADC. This module conforms to the Comportable guideline for peripheral functionality. See that document for integration overview within the broader top level system.

Features

The IP block implements the following features:

• Register interface to dual ADC analog block
• Support for 2 ADC channels
• Support for 8 filters on the values from the channels
• Support ADCs with 10-bit output (two reserved bits in CSR)
• Support for debounce timers on the filter output
• Run on a slow always-on clock to enable usage while the device is sleeping
• Low power periodic scan mode for monitoring ADC channels

Description

The ADC controller is a simple front-end to an analog block that allows filtering and debouncing of the analog signals.

Compatibility

The ADC controller programming interface is not based on any existing interface.

Theory of Operation

The block diagram shows a conceptual view of the ADC controller state machine and filters.

Hardware Interface

Referring to the Comportable guideline for peripheral device functionality, the module adc_ctrl has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: clk_aon_i

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO: none

Inter-Module Signals: Reference

Inter-Module Signals
Port Name Package::Struct Type Act Width Description
wkup_req logic uni req 1
tl tlul_pkg::tl req_rsp rsp 1

Interrupts:

Interrupt NameTypeDescription
match_doneEvent

ADC match or measurement event done

fatal_fault

This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures:

Countermeasure IDDescription

End-to-end bus integrity scheme.

Signals

In addition to the interrupts and bus signals, the tables below lists additional IOs.

Signal Direction Description
adc_o output Output controls to the actual AST ADC module. Contains signals such as power down control and ADC channel select.
adc_i input Input data from AST ADC module. Contains ADC data output as well as data valid indication.

Design Details

Sampling state machine

The state machine that takes ADC samples follows a very simple pattern:

1. Power up ADC: The controller issues the power up command to the ADC.

2. Wait for ADC turn on: The controller waits for the number of clock cycles programmed in adc_pd_ctl.pwrup_time which should be set to match the ADC power up delay.

3. Take sample Channel 0: The ADC is requested to sample channel 0. When the ADC signals complete the value is stored in adc_chn_val[0].adc_chn_value. Note that the time taken in this step depends on the properties of the ADC.

4. Take sample Channel 1: The ADC is requested to sample channel 1. When the ADC signals complete the value is stored in adc_chn_val[1].adc_chn_value. Note that the time taken in this step depends on the properties of the ADC.

5. Evaluate Filters: The filters are evaluated and debounce logic applied (see next section).

6. Scan type check: At this point if the adc_pd_ctl.lp_mode bit is clear scanning continues at step (3). If the bit is set the next step depends on how many samples have hit the filters. If more than adc_lp_sample_ctl.lp_sample_cnt samples have hit then continuous scanning continues at step (3) else periodic scanning will continue at the next step (7).

7. Power off ADC: The controller issues the power down command to the ADC.

8. Wait sleep time: The controller will wait for the next sample timer to time out before restarting at step (1).

In active operation the controller is in continuous scanning mode:

• The ADC is continually powered on.
• The sampling cycle time is the time taken for the ADC to take two samples (450us) plus internal processing time (4 clock cycles) from the ADC controller.
• The debounce timer will trigger the filter_status and interrupt after a configurable number of matching ADC samples have been seen, as determined by adc_sample_ctl.

For low power operation the periodic scanning mode can be used. In this mode samples are taken using a slower periodic sampling cycle time with the ADC powered down most of the time. Once a small number of cycles have hit the filter with periodic scanning then the controller switches to continuous scanning in order to more accurately debounce the signal. In low power mode:

• The ADC is periodically powered up to take samples; this interval is determined by adc_pd_ctl.wakeup_time.
• Similar to normal operation, the ADC power-up delay is controlled by adc_pd_ctl.pwrup_time.
• Once the ADC is powered up, two samples are taken and compared to the filter thresholds.
• If a configurable number of matches, as determined by adc_lp_sample_ctl, are seen, the ADC controller transitions to normal operation for continuous sampling.

Although it can be used at any time, the periodic operation mode and use of the slow clock allows the ADC controller to continue to scan when most of the chip is in sleep or power-down modes. The controller can be configured to issue a wakeup to the rest of the chip.

If a filter is enabled for wakeup in adc_wakeup_ctl and filter_status indicates a match, a wakeup is generated to the system power manager.

Filters and debounce

There are two reserved bits in ADC filter control registers for future use. In the current implementation, ADC has 10-bit granularity. Each step is 2.148mV. It covers 0-2.2V.

The ADC controller implements eight pairs of filters that feed the debounce logic. Each pair has a filter for channel 0 and a filter for channel 1.

A filter consists of a max value, a min value and a cond flag indicating if the filter is hit by a sample inside or outside the range.

• Inside the range: the filter is hit if minvaluemax.
• Outside the range: inverse of inside, so the filter is hit if value < min or value > max.

Some example filters:

• Inside min=7, max=23: any value between and including 7 and 23 will hit.
• Outside min=7, max=23: any value less than 7 or greater than 23 will hit.
• Inside min=7, max=7: the value must be exactly 7 to hit (sample noise may make an exact hit unlikely).
• Inside min=0, max=7: the value must be less than 8 to hit.
• Outside min=8, max=0xFFF: the value must be less than 8 to hit (alternate method).
• Inside min=0, max=0xFFF: any value will hit. This may be useful to exclude one channel from the filter.
• Outside min=0, max=0xFFF: no value will hit. If set for either channel the filter is effectively disabled.

All pairs of filters that are enabled in adc_chn0_filter_ctl[7:0] and adc_chn1_filter_ctl[7:0] are evaluated after each pair of samples has been taken. The filter result is passed to the periodic scan counter if enabled and not at its limit otherwise the result is passed to the debounce counter. The list below describes how the counters interpret the filter results:

• If no filters are hit then the counter will reset to zero.
• If one or more filters are hit but the set hit differs from the previous evaluation the counter resets to zero.
• If one or more filters are hit and either none was hit in the previous evaluation or the same set was hit in the previous evaluation and the counter is not at its threshold then the counter will increment.
• If one or more filters are hit and the same set was hit in the previous evaluation and the counter is at its threshold then the counter stays at the threshold.
• If the counter is the periodic scan counter and it reaches its threshold, as defined by adc_lp_sample_ctl.lp_sample_cnt, then continuous scanning is enabled and the debounce counter will be used for future evaluations.
• If the counter is the debounce counter and it reaches its threshold, as defined by adc_sample_ctl.np_sample_cnt, then:
• An interrupt is raised if the threshold is met for the first time.
• If a series of interrupts and matches are seen, these registers only record the value of the last debounced hit.
• The adc_intr_status register is updated by setting the bits corresponding to filters that are hit (note that bits that are already set will not be cleared). This will cause the block to raise an interrupt if it was not already doing so.
• If a filter is a hit and is also enabled in adc_wakeup_ctl the corresponding filter generates a wakeup.
• Note that the debounce counter will remain at its threshold until the set of filters are changed by software to debounce a different event or if the current match changes.
• This implies that a stable matching event continuously matches until some condition in the system (changed filter settings, changed ADC output, software issued fsm reset in adc_fsm_rst) alters the result.

Because scanning continues the adc_intr_status register will reflect any debounced events that are detected between the controller raising an interrupt and the status bits being cleared (by having 1 written to them). However, the adc_chn_val[0].adc_chn_value_intr and adc_chn_val[1].adc_chn_value_intr registers record the value at the time the interrupt was first raised and thus reflect the filter state from that point.

The interface between the ADC controller and the ADC is diagrammed below. The interface is from the perspective of the ADC controller. Before operation can begin, the ADC controller first powers on the ADC by setting adc_o.pd to 0. The controller then waits for the ADC to fully power up, as determined by adc_pd_ctl.pwrup_time.

Once the ADC is ready to go, the controller then selects the channel it wishes to sample by setting adc_o.channel_sel. The controller holds this value until the ADC responds with adc_i.data_valid and adc_i.data.

Since there is no request sample signal between the controller and the ADC, the ADC takes a new sample when adc_o.channel_sel is changed from 0 to a valid channel. To take a new sample then, the controller actively sets adc_o.channel_sel to 0, before setting it to another valid channel.

Programmers Guide

Initialization

The controller should be initialized with the properties of the ADC and scan times.

Running in normal mode

If fast sampling is always required then the adc_pd_ctl.lp_mode bit should be clear. In this case the values in the adc_lp_sample_ctl are not used. The ADC will always be enabled and consuming power.

If power saving is required then the controller can be set to operate in low power mode by setting adc_pd_ctl.lp_mode. The adc_lp_sample_ctl must be programmed prior to setting this bit.

Running with the rest of the chip in sleep

Once programmed the controller and ADC can run when the rest of the chip is in low power state and the main clocks are stopped. This allows the chip to be woken when appropriate values are detected on the two ADC channels. The fast sampling mode can be used but will usually consume more power than desired when the chip is in sleep. So it is expected that adc_lp_sample_ctl is configured and low power mode enabled by setting adc_pd_ctl.lp_mode prior to the sleep being initiated.

If the ADC wakeup is not required then the controller and ADC should both be disabled by clearing adc_en_ctl prior to the sleep being initiated.

Use Case

While the ADC controller is meant to be used generically, it can be configured to satisfy more complex use cases. As an illustrative example, the programmers guide uses the Chrome OS Hardware Debug as an example of how the ADC controller can be used.

The debug setup referred to uses a USB-C debug accessory. This insertion of this debug accessory into a system, can be detected by the ADC controller.

The debug accessory voltage range of interest is shown in the diagram below:

The ADC can be used to detect debug cable connection / disconnection in the non-overlapping regions. As an example use case of the two channel filters they can be used for detection of a USB-C debug accessory. The ADC must meet some minimum specifications:

• Full scale range is 0.0V to 2.2V
• If the signal is below 0.0V the ADC value will be zero.
• If the signal is above 2.2V the ADC value will be maximum (i.e. same as 2.2V)
• Absolute maximum error +/- 15 mV in the 0.25 - 0.45 V range
• Absolute maximum error +/- 30 mV in the rest of the 0.0 - 2.2 V range

The following assumes:

• The slow clock runs at 200kHz or 5 us.
• The ADC requires 30 us to power on.
• The ADC takes a single sample in 44 clocks (220 us)

The controller should be initialized with the properties of the ADC and scan times.

• The ADC power up delay must be set in adc_pd_ctl.pwrup_time to 6 (30 us).

• The time to delay between samples in a slow scan should be set in adc_pd_ctl.wakeup_time to 1600 (8ms).

• The number of samples to cause transition from slow to fast scan should be set in adc_lp_sample_ctl to 4 (causing slow scan to be 4*8ms = 32ms of debounce time).

• The number of samples for debounce should be set in adc_sample_ctl to 155 (causing the total debounce time to be 32ms (slow scan) + 220us * 2 * 155 = 100ms, at the low end of the USB-C spec window).

• For the 10-bit ADC granularity, the filter registers adc_chnX_filter_ctlN should be programmed to:

Filter Ch0 Min Ch0 Max Ch1 Min Ch1 Max Device connected
0 IN 149 (0.32V) 279 (0.60V) 149 (0.32V) 279 (0.60V) Debug Sink (local RpUSB)
1 IN 391 (0.84V) 524 (1.125V) 391 (0.84V) 524 (1.125V) Debug Sink (local Rp1.5A)
2 IN 712 (1.53V) 931 (2.00V) 712 (1.53V) 931 (2.00V) Debug Sink (local Rp3A)
3 IN 712 (1.53V) 847 (1.82V) 405 (0.87V) 503 (1.08V) Debug Source with RpUSB
4 IN 349 (0.75V) 512 (1.12V) 186 (0.40V) 279 (0.60V) Debug Source with Rp1.5A
5 IN 405 (0.87V) 503 (1.08V) 712 (1.53V) 841 (1.82V) Debug Source RpUSB Flipped
6 IN 186 (0.40V) 279 (0.60V) 349 (0.75V) 521 (1.12V) Debug Source Rp1.5A Flipped
7 OUT 116 (0.25V) 954 (2.05V) 116 (0.25V) 954 (2.05V) Disconnect

Note that for the debug controller (DTS in USB-C specification) as a power source the filter that is hit will indicate the orientation of the connector. If the debug controller is acting as a power sink then the orientation cannot be known unless the debug controller supports the optional behavior of converting one of its pulldowns to an Ra (rather than Rp) to indicate CC2 (the CC that is not used for communication). This would not be detected by the filters since it happens later than connection detection and debounce in the USB-C protocol state machine, but could be detected by monitoring the current ADC value.

Device Interface Functions (DIFs)

To use this DIF, include the following C header:

#include "sw/device/lib/dif/dif_adc_ctrl.h"

This header provides the following device interface functions:

Registers

Summary
Name Offset Length Description

Interrupt State Register

Interrupt Enable Register

Interrupt Test Register

Enable filter matches as wakeups

Interrupt enable controls.

Debug cable internal status

Interrupt State Register

Reset default = 0x0, mask 0x1
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 match_done
BitsTypeResetNameDescription
0rw1c0x0match_done

ADC match or measurement event done

Interrupt Enable Register

Reset default = 0x0, mask 0x1
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 match_done
BitsTypeResetNameDescription
0rw0x0match_done

Enable interrupt when INTR_STATE.match_done is set.

Interrupt Test Register

Reset default = 0x0, mask 0x1
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 match_done
BitsTypeResetNameDescription
0wo0x0match_done

Write 1 to force INTR_STATE.match_done to 1.

Reset default = 0x0, mask 0x1
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 fatal_fault
BitsTypeResetNameDescription
0wo0x0fatal_fault

Write 1 to trigger one alert event of this kind.

Reset default = 0x0, mask 0x3
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 oneshot_mode adc_enable
BitsTypeResetNameDescription

1'b0: to power down ADC and ADC_CTRL FSM will enter the reset state; 1'b1: to power up ADC and ADC_CTRL FSM will start

1rw0x0oneshot_mode

Oneshot mode does not care about the filter value. 1'b0: disable; 1'b1: enable

Reset default = 0x64060, mask 0xfffffff1
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 wakeup_time... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...wakeup_time pwrup_time lp_mode
BitsTypeResetNameDescription
0rw0x0lp_mode

3:1Reserved
7:4rw0x6pwrup_time

ADC power up time, measured in always on clock cycles. After power up time is reached, the ADC controller needs one additional cycle before an ADC channel is selected for access.

31:8rw0x640wakeup_time

How often FSM wakes up from ADC PD mode to take a sample, measured in always on clock cycles.

Reset default = 0x4, mask 0xff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lp_sample_cnt
BitsTypeResetNameDescription
7:0rw0x4lp_sample_cnt

The number of samples in low-power mode when the low-power mode is enabled. After the programmed number is met, ADC won't be powered down any more. This value must be 1 or larger.

Reset default = 0x9b, mask 0xffff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 np_sample_cnt
BitsTypeResetNameDescription
15:0rw0x9bnp_sample_cnt

The number of samples in normal-power mode to meet the debounce spec. Used after the low-power mode condition is met or in the normal power mode. This value must be 1 or larger.

Reset default = 0x0, mask 0x1
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rst_en
BitsTypeResetNameDescription
0rw0x0rst_en

1'b0: Normal functional mode. 1'b1: SW to reset all the FSMs and timers

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN_0 max_v_0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cond_0 min_v_0
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_0

10-bit for chn0 filter min value

12rw0x0cond_0

17:13Reserved
27:18rw0x0max_v_0

10-bit for chn0 filter max value

30:28Reserved
31rw0x0EN_0

Enable for filter

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN_1 max_v_1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cond_1 min_v_1
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_1

12rw0x0cond_1

17:13Reserved
27:18rw0x0max_v_1

30:28Reserved
31rw0x0EN_1

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN_2 max_v_2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cond_2 min_v_2
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_2

12rw0x0cond_2

17:13Reserved
27:18rw0x0max_v_2

30:28Reserved
31rw0x0EN_2

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN_3 max_v_3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cond_3 min_v_3
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_3

12rw0x0cond_3

17:13Reserved
27:18rw0x0max_v_3

30:28Reserved
31rw0x0EN_3

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN_4 max_v_4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cond_4 min_v_4
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_4

12rw0x0cond_4

17:13Reserved
27:18rw0x0max_v_4

30:28Reserved
31rw0x0EN_4

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN_5 max_v_5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cond_5 min_v_5
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_5

12rw0x0cond_5

17:13Reserved
27:18rw0x0max_v_5

30:28Reserved
31rw0x0EN_5

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN_6 max_v_6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cond_6 min_v_6
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_6

12rw0x0cond_6

17:13Reserved
27:18rw0x0max_v_6

30:28Reserved
31rw0x0EN_6

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN_7 max_v_7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cond_7 min_v_7
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_7

12rw0x0cond_7

17:13Reserved
27:18rw0x0max_v_7

30:28Reserved
31rw0x0EN_7

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN_0 max_v_0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cond_0 min_v_0
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_0

10-bit for chn0 filter min value

12rw0x0cond_0

17:13Reserved
27:18rw0x0max_v_0

10-bit for chn0 filter max value

30:28Reserved
31rw0x0EN_0

Enable for filter

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN_1 max_v_1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cond_1 min_v_1
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_1

12rw0x0cond_1

17:13Reserved
27:18rw0x0max_v_1

30:28Reserved
31rw0x0EN_1

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN_2 max_v_2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cond_2 min_v_2
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_2

12rw0x0cond_2

17:13Reserved
27:18rw0x0max_v_2

30:28Reserved
31rw0x0EN_2

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN_3 max_v_3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cond_3 min_v_3
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_3

12rw0x0cond_3

17:13Reserved
27:18rw0x0max_v_3

30:28Reserved
31rw0x0EN_3

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN_4 max_v_4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cond_4 min_v_4
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_4

12rw0x0cond_4

17:13Reserved
27:18rw0x0max_v_4

30:28Reserved
31rw0x0EN_4

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN_5 max_v_5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cond_5 min_v_5
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_5

12rw0x0cond_5

17:13Reserved
27:18rw0x0max_v_5

30:28Reserved
31rw0x0EN_5

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN_6 max_v_6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cond_6 min_v_6
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_6

12rw0x0cond_6

17:13Reserved
27:18rw0x0max_v_6

30:28Reserved
31rw0x0EN_6

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN_7 max_v_7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cond_7 min_v_7
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_7

12rw0x0cond_7

17:13Reserved
27:18rw0x0max_v_7

30:28Reserved
31rw0x0EN_7

Reset default = 0x0, mask 0xfff0fff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 adc_chn_value_intr_0 adc_chn_value_intr_ext_0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 adc_chn_value_0 adc_chn_value_ext_0
BitsTypeResetNameDescription

2-bit extension; RO 0

Latest ADC value sampled on channel. each step is 2.148mV

15:12Reserved

2-bit extension; RO 0

ADC value sampled on channel when the interrupt is raised(debug cable is attached or disconnected), each step is 2.148mV

Reset default = 0x0, mask 0xfff0fff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 adc_chn_value_intr_1 adc_chn_value_intr_ext_1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 adc_chn_value_1 adc_chn_value_ext_1
BitsTypeResetNameDescription

15:12Reserved

Enable filter matches as wakeups

Reset default = 0x0, mask 0xff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EN
BitsTypeResetNameDescription
7:0rw0x0EN

0: filter match wil not generate wakeupe; 1: filter match will generate wakeup

Reset default = 0x0, mask 0xff

Indicates whether a particular filter has matched on all channels.

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COND
BitsTypeResetNameDescription
7:0rw1c0x0COND

0: filter condition is not met; 1: filter condition is met

Interrupt enable controls.

Reset default = 0x0, mask 0x1ff

adc_ctrl sends out only 1 interrupt, so this register controls which internal sources are actually registered.

This register uses the same bit enumeration as ADC_INTR_STATUS

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EN
BitsTypeResetNameDescription
8:0rw0x0EN

0: interrupt source is not enabled; 1: interrupt source is enabled