Analog to Digital Converter Control Interface

Overview

This document specifies the ADC controller IP functionality. This IP block implements control and filter logic for an analog block that implements a dual ADC. This module conforms to the Comportable guideline for peripheral functionality. See that document for integration overview within the broader top level system.

Features

The IP block implements the following features:

  • Register interface to dual ADC analog block
  • Support for 2 ADC channels
  • Support for 8 filters on the values from the channels
  • Support ADCs with 10-bit output (two reserved bits in CSR)
  • Support for debounce timers on the filter output
  • Run on a slow always-on clock to enable usage while the device is sleeping
  • Low power periodic scan mode for monitoring ADC channels

Description

The ADC controller is a simple front-end to an analog block that allows filtering and debouncing of the analog signals.

Compatibility

The ADC controller programming interface is not based on any existing interface.

Theory of Operation

The block diagram shows a conceptual view of the ADC controller state machine and filters.

Block Diagram

ADC_CTRL Block Diagram

Hardware Interface

Referring to the Comportable guideline for peripheral device functionality, the module adc_ctrl has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: clk_aon_i

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO: none

Interrupts:

Interrupt NameDescription
debug_cable

USB-C debug cable is attached or disconnected

Security Alerts: none

Design Details

Sampling state machine

The state machine that takes ADC samples follows a very simple pattern:

  1. Power up ADC: The controller issues the power up command to the ADC.

  2. Wait for ADC turn on: The controller waits for the number of clock cycles programmed in adc_pd_ctl.pwrup_time which should be set to match the ADC power up delay.

  3. Take sample Channel 0: The ADC is requested to sample channel 0. When the ADC signals complete the value is stored in adc_chn_val[0].adc_chn_value. Note that the time taken in this step depends on the properties of the ADC.

  4. Take sample Channel 1: The ADC is requested to sample channel 1. When the ADC signals complete the value is stored in adc_chn_val[1].adc_chn_value. Note that the time taken in this step depends on the properties of the ADC.

  5. Evaluate Filters: The filters are evaluated and debounce logic applied (see next section.

  6. Scan type check: At this point if the adc_pd_ctl.lp_mode bit is clear scanning continues at step (3). If the bit is set the next step depends on how many samples have hit the filters. If more than adc_lp_sample_ctl.lp_sample_cnt samples have hit then continuous scanning continues at step (3) else periodic scanning will continue at the next step (7).

  7. Power off ADC: The controller issues the power down command to the ADC.

  8. Wait sleep time: The controller will wait for the next sample timer to timeout before restarting at step (1).

In active operation the controller is in continuous scanning mode:

  • The ADC is continually powered on.
  • The sampling cycle time is the time taken for the ADC to take two samples (450us) plus NNN (fill in based on implementation but probably 4-10)) number of slow clock cycles x (5us; always-on clock frequency is 200KHz).
  • The debounce timer will trigger the filter status (and interrupt) after adc_sample_ctl multiplied by the continuous sampling cycle time.

For low power operation the periodic scanning mode can be used. In this mode samples are taken using a slower periodic sampling cycle time with the ADC powered down most of the time. Once a small number of cycles have hit the filter with periodic scanning then the controller switches to continuous scanning in order to more accurately debounce the signal. In low power mode:

  • The ADC is only powered up for adc_pd_ctl.pwrup_time slow clock cycles plus the time taken for the ADC to take two samples plus NNN slow clock cycles.
  • The total time between samples for a periodic scan is the time the ADC is powered up plus adc_pd_ctl.wakeup_time cycles of the slow clock.
  • The time taken to transition to the continuous scanning mode is the total time of a slow scan multiplied by the adc_lp_sample_ctl.
  • The debounce timer will trigger the filter status (and interrupt) after the time taken to transition to fast mode plus adc_sample_ctl multiplied by the fast sampling cycle time.

Although it can be used at any time, the periodic operation mode and use of the slow clock allows the ADC controller to continue to scan when most of the chip is in sleep or power-down modes. The controller can be configured to issue a wakeup to the rest of the chip. In this case if any filter enabled in the adc_wakeup_ctl register is hit then the wakeup will be issued. The filter that hit is recorded in the adc_wakeup_status register and the bit should be cleared to acknowledge the wake has happened (no further wake events will be issued until this is done).

Filters and debounce

There are two reserved bits in ADC filter control registers for future use. In the current implementation, ADC has 10-bit granularity. Each step is 2.148mV. It covers 0-2.2V.

The ADC controller implements eight pairs of filters that feed the debounce logic. Each pair has a filter for channel 0 and a filter for channel 1.

A filter consists of a max value, a min value and a cond flag indicating if the filter is hit by a sample inside or outside the range.

  • Inside the range: the filter is hit if minvaluemax.
  • Outside the range: inverse of inside, so the filter is hit if value < min or value > max.

Some example filters:

  • Inside min=7, max=23: any value between and including 7 and 23 will hit.
  • Outside min=7, max=23: any value less than 7 or greater than 23 will hit.
  • Inside min=7, max=7: the value must be exactly 7 to hit (sample noise may make an exact hit unlikely).
  • Inside min=0, max=7: the value must be less than 8 to hit.
  • Outside min=8, max=0xFFF: the value must be less than 8 to hit (alternate method).
  • Inside min=0, max=0xFFF: any value will hit. This may be useful to exclude one channel from the filter.
  • Outside min=0, max=0xFFF: no value will hit. If set for either channel the filter is effectively disabled.

All pairs of filters that are enabled in adc_chn0_filter_ctl[7:0] and adc_chn1_filter_ctl[7:0] are evaluated after each pair of samples has been taken. The filter result is passed to the periodic scan counter if enabled and not at its limit otherwise the result is passed to the debounce counter. The list below describes how the counters interpret the filter results:

  • If no filters are hit then the counter will reset to zero.
  • If one or more filters are hit but the set hit differs from the previous evaluation the counter resets to zero.
  • If one or more filters are hit and either none was hit in the previous evaluation or the same set was hit in the previous evaluation and the counter is not at its limit then the counter will increment.
  • If the counter is the periodic scan counter and it reaches its limit then continuous scanning is enabled and the debounce counter will be used for future evaluations.
  • If the counter is the debounce counter and it reaches its limit then:
    • If an interrupt is not already being raised then the current sample values are latched into adc_chn_val[0].adc_chn_value_intr and adc_chn_val[1].adc_chn_value_intr. i.e. these registers only record the value of the first debounced hit.
    • The adc_intr_status register is updated by setting the bits corresponding to filters that are hit (note that bits that are already set will not be cleared). This will cause the block to raise an interrupt if it was not already doing so.
    • If any filters are hit that are enabled in adc_wakeup_ctl the corresponding bits in the adc_wakeup_status register are set which may initiate a wakeup.
    • Note that the debounce counter will remain at its limit until the set of filters that are set changes when it will be reset to zero and start to debounce the next event.

Because scanning continues the adc_intr_status register will reflect any debounced events that are detected between the controller raising an interrupt and the status bits being cleared (by having 1 written to them). However, the adc_chn_val[0].adc_chn_value_intr and adc_chn_val[1].adc_chn_value_intrregisters record the value at the time the interrupt was first raised and thus reflect the filter state from that point.

Programmers Guide

Initialization

The controller should be initialized with the properties of the ADC and scan times.

Running in normal mode

If fast sampling is always required then the adc_pd_ctl.lp_mode bit should be clear. In this case the values in the adc_lp_sample_ctl are not used. The ADC will always be enabled and consuming power.

If power saving is required then the controller can be set to operate in low power mode by setting adc_pd_ctl.lp_mode. The adc_lp_sample_ctl must be programed prior to setting this bit.

Running with the rest of the chip in sleep

Once programmed the controller and ADC can run when the rest of the chip is in low power state and the main clocks are stopped. This allows the chip to be woken when appropriate values are detected on the two ADC channels. The fast sampling mode can be used but will usually consume more power than desired when the chip is in sleep. So it is expected that adc_lp_sample_ctl is configured and low power mode enabled by setting adc_pd_ctl.lp_mode prior to the sleep being initiated.

If the ADC wakeup is not required then the controller and ADC should both be disabled by clearing adc_en_ctl prior to the sleep being initiated.

Use for USB-C debug accessory detection.

As an example use case of the two channel filters they can be used for detection of a USB-C debug accessory. The ADC must meet some minimum specifications:

  • Full scale range is 0.0V to 2.2V
  • If the signal is below 0.0V the ADC value will be zero.
  • If the signal is above 2.2V the ADC value will be maximum (i.e. same as 2.2V)
  • Absolute maximum error +/- 15 mV in the 0.25 - 0.45 V range
  • Absolute maximum error +/- 30 mV in the rest of the 0.0 - 2.2 V range

The following assumes:

  • The slow clock runs at 200kHz or 5 Μs.
  • The ADC requires 30 Μs to power on.
  • The ADC takes a single sample in 44 clocks (220 Μs)

The controller should be initialized with the properties of the ADC and scan times.

  • The ADC power up delay must be set in adc_pd_ctl.pwrup_time to 6 (30 Μs).

  • The time to delay between samples in a slow scan should be set in adc_pd_ctl.wakeup_time to 1600 (8ms).

  • The number of samples to cause transition from slow to fast scan should be set in adc_lp_sample_ctl to 4 (causing slow scan to be 4*8ms = 32ms of debounce time).

  • The number of samples for debounce should be set in adc_sample_ctl to 155 (causing the total debounce time to be 32ms (slow scan) + 220Μs * 2 * 155 = 100ms, at the low end of the USB-C spec window).

  • For the 10-bit ADC granularity, the filter registers adc_chnX_filter_ctlN should be programmed to:

Filter Ch0 Min Ch0 Max Ch1 Min Ch1 Max Device connected
0 IN 149 (0.32V) 279 (0.60V) 149 (0.32V) 279 (0.60V) Debug Sink (local RpUSB)
1 IN 391 (0.84V) 524 (1.125V) 391 (0.84V) 524 (1.125V) Debug Sink (local Rp1.5A)
2 IN 712 (1.53V) 931 (2.00V) 712 (1.53V) 931 (2.00V) Debug Sink (local Rp3A)
3 IN 712 (1.53V) 847 (1.82V) 405 (0.87V) 503 (1.08V) Debug Source with RpUSB
4 IN 349 (0.75V) 512 (1.12V) 186 (0.40V) 279 (0.60V) Debug Source with Rp1.5A
5 IN 405 (0.87V) 503 (1.08V) 712 (1.53V) 841 (1.82V) Debug Source RpUSB Flipped
6 IN 186 (0.40V) 279 (0.60V) 349 (0.75V) 521 (1.12V) Debug Source Rp1.5A Flipped
7 OUT 116 (0.25V) 954 (2.05V) 116 (0.25V) 954 (2.05V) Disconnect

Note that for the debug controller (DTS in USB-C specification) as a power source the filter that is hit will indicate the orientation of the connector. If the debug controller is acting as a power sink then the orientation cannot be known unless the debug controller supports the optional behaviour of converting one of its pulldowns to an Ra (rather than Rp) to indicate CC2 (the CC that is not used for communication). This would not be detected by the filters since it happens later than connection detection and debounce in the USB-C protocol state machine, but could be detected by monitoring the current ADC value.

Registers

adc_ctrl.INTR_STATE @ 0x0

Interrupt State Register

Reset default = 0x0, mask 0x1
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  debug_cable
BitsTypeResetNameDescription
0rw1c0x0debug_cable

USB-C debug cable is attached or disconnected


adc_ctrl.INTR_ENABLE @ 0x4

Interrupt Enable Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  debug_cable
BitsTypeResetNameDescription
0rw0x0debug_cable

Enable interrupt when INTR_STATE.debug_cable is set.


adc_ctrl.INTR_TEST @ 0x8

Interrupt Test Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  debug_cable
BitsTypeResetNameDescription
0wo0x0debug_cable

Write 1 to force INTR_STATE.debug_cable to 1.


adc_ctrl.adc_en_ctl @ 0xc

ADC enable control register

Reset default = 0x0, mask 0x3
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1514131211109876543210
  oneshot_mode adc_enable
BitsTypeResetNameDescription
0rw0x0adc_enable

1'b0: to power down ADC and ADC_CTRL FSM will enter the reset state; 1'b1: to power up ADC and ADC_CTRL FSM will start

1rw0x0oneshot_mode

Oneshot mode does not care about the filter value. 1'b0: disable; 1'b1: enable


adc_ctrl.adc_pd_ctl @ 0x10

ADC PowerDown(PD) control register

Reset default = 0x64060, mask 0xfffffff1
31302928272625242322212019181716
wakeup_time...
1514131211109876543210
...wakeup_time pwrup_time   lp_mode
BitsTypeResetNameDescription
0rw0x0lp_mode

1'b0: adc_pd is disabled, use adc_sample_ctl. 1'b1: adc_pd is enabled, use both adc_lp_sample_ctl & adc_sample_ctl

3:1Reserved
7:4rw0x6pwrup_time

ADC power up time. unit in cycles, 200KHz(5us)

31:8rw0x640wakeup_time

How often FSM wakes up from ADC PD mode to take a sample. unit in cycles, 200KHz(5us)


adc_ctrl.adc_lp_sample_ctl @ 0x14

ADC Low-Power(LP) sample control register

Reset default = 0x4, mask 0xff
31302928272625242322212019181716
 
1514131211109876543210
  lp_sample_cnt
BitsTypeResetNameDescription
7:0rw0x4lp_sample_cnt

The number of samples in low-power mode when the low-power mode is enabled. After the programmed number is met, ADC won't be powered down any more.


adc_ctrl.adc_sample_ctl @ 0x18

ADC sample control register

Reset default = 0x9b, mask 0xffff
31302928272625242322212019181716
 
1514131211109876543210
np_sample_cnt
BitsTypeResetNameDescription
15:0rw0x9bnp_sample_cnt

The number of samples in normal-power mode to meet the debounce spec. used after the low-power mode condition is met or in the normal power mode


adc_ctrl.adc_fsm_rst @ 0x1c

ADC FSM reset control

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  rst_en
BitsTypeResetNameDescription
0rw0x0rst_en

1'b0: Normal functional mode. 1'b1: SW to reset all the FSMs and timers


adc_ctrl.adc_chn0_filter_ctl_0 @ 0x20

ADC channel0 filter range

Reset default = 0x0, mask 0xffc1ffc

There are 8 filters to define the potential range(min, max) [11:0]: min value [1:0] RO 0 [12]: condition(in the box or out of the box) [27:16]: max value [17:16] RO 0 each step is 2.148mV

31302928272625242322212019181716
  max_v_0  
1514131211109876543210
  cond_0 min_v_0  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_0

10-bit for chn0 filter min value

12rw0x0cond_0

1-bit for the condition; 1'b0 means min<=ADC<=max, 1'b1 means ADC>max or ADC

17:13Reserved
27:18rw0x0max_v_0

10-bit for chn0 filter max value


adc_ctrl.adc_chn0_filter_ctl_1 @ 0x24

ADC channel0 filter range

Reset default = 0x0, mask 0xffc1ffc

There are 8 filters to define the potential range(min, max) [11:0]: min value [1:0] RO 0 [12]: condition(in the box or out of the box) [27:16]: max value [17:16] RO 0 each step is 2.148mV

31302928272625242322212019181716
  max_v_1  
1514131211109876543210
  cond_1 min_v_1  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_1

For ADC_CTRL1

12rw0x0cond_1

For ADC_CTRL1

17:13Reserved
27:18rw0x0max_v_1

For ADC_CTRL1


adc_ctrl.adc_chn0_filter_ctl_2 @ 0x28

ADC channel0 filter range

Reset default = 0x0, mask 0xffc1ffc

There are 8 filters to define the potential range(min, max) [11:0]: min value [1:0] RO 0 [12]: condition(in the box or out of the box) [27:16]: max value [17:16] RO 0 each step is 2.148mV

31302928272625242322212019181716
  max_v_2  
1514131211109876543210
  cond_2 min_v_2  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_2

For ADC_CTRL2

12rw0x0cond_2

For ADC_CTRL2

17:13Reserved
27:18rw0x0max_v_2

For ADC_CTRL2


adc_ctrl.adc_chn0_filter_ctl_3 @ 0x2c

ADC channel0 filter range

Reset default = 0x0, mask 0xffc1ffc

There are 8 filters to define the potential range(min, max) [11:0]: min value [1:0] RO 0 [12]: condition(in the box or out of the box) [27:16]: max value [17:16] RO 0 each step is 2.148mV

31302928272625242322212019181716
  max_v_3  
1514131211109876543210
  cond_3 min_v_3  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_3

For ADC_CTRL3

12rw0x0cond_3

For ADC_CTRL3

17:13Reserved
27:18rw0x0max_v_3

For ADC_CTRL3


adc_ctrl.adc_chn0_filter_ctl_4 @ 0x30

ADC channel0 filter range

Reset default = 0x0, mask 0xffc1ffc

There are 8 filters to define the potential range(min, max) [11:0]: min value [1:0] RO 0 [12]: condition(in the box or out of the box) [27:16]: max value [17:16] RO 0 each step is 2.148mV

31302928272625242322212019181716
  max_v_4  
1514131211109876543210
  cond_4 min_v_4  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_4

For ADC_CTRL4

12rw0x0cond_4

For ADC_CTRL4

17:13Reserved
27:18rw0x0max_v_4

For ADC_CTRL4


adc_ctrl.adc_chn0_filter_ctl_5 @ 0x34

ADC channel0 filter range

Reset default = 0x0, mask 0xffc1ffc

There are 8 filters to define the potential range(min, max) [11:0]: min value [1:0] RO 0 [12]: condition(in the box or out of the box) [27:16]: max value [17:16] RO 0 each step is 2.148mV

31302928272625242322212019181716
  max_v_5  
1514131211109876543210
  cond_5 min_v_5  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_5

For ADC_CTRL5

12rw0x0cond_5

For ADC_CTRL5

17:13Reserved
27:18rw0x0max_v_5

For ADC_CTRL5


adc_ctrl.adc_chn0_filter_ctl_6 @ 0x38

ADC channel0 filter range

Reset default = 0x0, mask 0xffc1ffc

There are 8 filters to define the potential range(min, max) [11:0]: min value [1:0] RO 0 [12]: condition(in the box or out of the box) [27:16]: max value [17:16] RO 0 each step is 2.148mV

31302928272625242322212019181716
  max_v_6  
1514131211109876543210
  cond_6 min_v_6  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_6

For ADC_CTRL6

12rw0x0cond_6

For ADC_CTRL6

17:13Reserved
27:18rw0x0max_v_6

For ADC_CTRL6


adc_ctrl.adc_chn0_filter_ctl_7 @ 0x3c

ADC channel0 filter range

Reset default = 0x0, mask 0xffc1ffc

There are 8 filters to define the potential range(min, max) [11:0]: min value [1:0] RO 0 [12]: condition(in the box or out of the box) [27:16]: max value [17:16] RO 0 each step is 2.148mV

31302928272625242322212019181716
  max_v_7  
1514131211109876543210
  cond_7 min_v_7  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_7

For ADC_CTRL7

12rw0x0cond_7

For ADC_CTRL7

17:13Reserved
27:18rw0x0max_v_7

For ADC_CTRL7


adc_ctrl.adc_chn1_filter_ctl_0 @ 0x40

ADC channel1 filter range

Reset default = 0x0, mask 0xffc1ffc

There are 8 filters to define the potential range(min, max) [11:0]: min value [1:0] RO 0 [12]: condition(in the box or out of the box) [27:16]: max value [17:16] RO 0 each step is 2.148mV

31302928272625242322212019181716
  max_v_0  
1514131211109876543210
  cond_0 min_v_0  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_0

10-bit for chn0 filter min value

12rw0x0cond_0

1-bit for the condition; 1'b0 means min<=ADC<=max, 1'b1 means ADC>max or ADC

17:13Reserved
27:18rw0x0max_v_0

10-bit for chn0 filter max value


adc_ctrl.adc_chn1_filter_ctl_1 @ 0x44

ADC channel1 filter range

Reset default = 0x0, mask 0xffc1ffc

There are 8 filters to define the potential range(min, max) [11:0]: min value [1:0] RO 0 [12]: condition(in the box or out of the box) [27:16]: max value [17:16] RO 0 each step is 2.148mV

31302928272625242322212019181716
  max_v_1  
1514131211109876543210
  cond_1 min_v_1  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_1

For ADC_CTRL1

12rw0x0cond_1

For ADC_CTRL1

17:13Reserved
27:18rw0x0max_v_1

For ADC_CTRL1


adc_ctrl.adc_chn1_filter_ctl_2 @ 0x48

ADC channel1 filter range

Reset default = 0x0, mask 0xffc1ffc

There are 8 filters to define the potential range(min, max) [11:0]: min value [1:0] RO 0 [12]: condition(in the box or out of the box) [27:16]: max value [17:16] RO 0 each step is 2.148mV

31302928272625242322212019181716
  max_v_2  
1514131211109876543210
  cond_2 min_v_2  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_2

For ADC_CTRL2

12rw0x0cond_2

For ADC_CTRL2

17:13Reserved
27:18rw0x0max_v_2

For ADC_CTRL2


adc_ctrl.adc_chn1_filter_ctl_3 @ 0x4c

ADC channel1 filter range

Reset default = 0x0, mask 0xffc1ffc

There are 8 filters to define the potential range(min, max) [11:0]: min value [1:0] RO 0 [12]: condition(in the box or out of the box) [27:16]: max value [17:16] RO 0 each step is 2.148mV

31302928272625242322212019181716
  max_v_3  
1514131211109876543210
  cond_3 min_v_3  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_3

For ADC_CTRL3

12rw0x0cond_3

For ADC_CTRL3

17:13Reserved
27:18rw0x0max_v_3

For ADC_CTRL3


adc_ctrl.adc_chn1_filter_ctl_4 @ 0x50

ADC channel1 filter range

Reset default = 0x0, mask 0xffc1ffc

There are 8 filters to define the potential range(min, max) [11:0]: min value [1:0] RO 0 [12]: condition(in the box or out of the box) [27:16]: max value [17:16] RO 0 each step is 2.148mV

31302928272625242322212019181716
  max_v_4  
1514131211109876543210
  cond_4 min_v_4  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_4

For ADC_CTRL4

12rw0x0cond_4

For ADC_CTRL4

17:13Reserved
27:18rw0x0max_v_4

For ADC_CTRL4


adc_ctrl.adc_chn1_filter_ctl_5 @ 0x54

ADC channel1 filter range

Reset default = 0x0, mask 0xffc1ffc

There are 8 filters to define the potential range(min, max) [11:0]: min value [1:0] RO 0 [12]: condition(in the box or out of the box) [27:16]: max value [17:16] RO 0 each step is 2.148mV

31302928272625242322212019181716
  max_v_5  
1514131211109876543210
  cond_5 min_v_5  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_5

For ADC_CTRL5

12rw0x0cond_5

For ADC_CTRL5

17:13Reserved
27:18rw0x0max_v_5

For ADC_CTRL5


adc_ctrl.adc_chn1_filter_ctl_6 @ 0x58

ADC channel1 filter range

Reset default = 0x0, mask 0xffc1ffc

There are 8 filters to define the potential range(min, max) [11:0]: min value [1:0] RO 0 [12]: condition(in the box or out of the box) [27:16]: max value [17:16] RO 0 each step is 2.148mV

31302928272625242322212019181716
  max_v_6  
1514131211109876543210
  cond_6 min_v_6  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_6

For ADC_CTRL6

12rw0x0cond_6

For ADC_CTRL6

17:13Reserved
27:18rw0x0max_v_6

For ADC_CTRL6


adc_ctrl.adc_chn1_filter_ctl_7 @ 0x5c

ADC channel1 filter range

Reset default = 0x0, mask 0xffc1ffc

There are 8 filters to define the potential range(min, max) [11:0]: min value [1:0] RO 0 [12]: condition(in the box or out of the box) [27:16]: max value [17:16] RO 0 each step is 2.148mV

31302928272625242322212019181716
  max_v_7  
1514131211109876543210
  cond_7 min_v_7  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_7

For ADC_CTRL7

12rw0x0cond_7

For ADC_CTRL7

17:13Reserved
27:18rw0x0max_v_7

For ADC_CTRL7


adc_ctrl.adc_chn_val_0 @ 0x60

ADC value sampled on channel

Reset default = 0x0, mask 0xfff0fff
31302928272625242322212019181716
  adc_chn_value_intr_0 adc_chn_value_intr_ext_0
1514131211109876543210
  adc_chn_value_0 adc_chn_value_ext_0
BitsTypeResetNameDescription
1:0ro0x0adc_chn_value_ext_0

2-bit extension; RO 0

11:2ro0x0adc_chn_value_0

Latest ADC value sampled on channel. each step is 2.148mV

15:12Reserved
17:16ro0x0adc_chn_value_intr_ext_0

2-bit extension; RO 0

27:18ro0x0adc_chn_value_intr_0

ADC value sampled on channel when the interrupt is raised(debug cable is attached or disconnected)each step is 2.148mV


adc_ctrl.adc_chn_val_1 @ 0x64

ADC value sampled on channel

Reset default = 0x0, mask 0xfff0fff
31302928272625242322212019181716
  adc_chn_value_intr_1 adc_chn_value_intr_ext_1
1514131211109876543210
  adc_chn_value_1 adc_chn_value_ext_1
BitsTypeResetNameDescription
1:0ro0x0adc_chn_value_ext_1

For ADC_CTRL1

11:2ro0x0adc_chn_value_1

For ADC_CTRL1

15:12Reserved
17:16ro0x0adc_chn_value_intr_ext_1

For ADC_CTRL1

27:18ro0x0adc_chn_value_intr_1

For ADC_CTRL1


adc_ctrl.adc_wakeup_ctl @ 0x68

wakeup control

Reset default = 0x0, mask 0xff
31302928272625242322212019181716
 
1514131211109876543210
  chn0_1_filter7_en chn0_1_filter6_en chn0_1_filter5_en chn0_1_filter4_en chn0_1_filter3_en chn0_1_filter2_en chn0_1_filter1_en chn0_1_filter0_en
BitsTypeResetNameDescription
0rw0x0chn0_1_filter0_en

0: disable; 1: enable

1rw0x0chn0_1_filter1_en

0: disable; 1: enable

2rw0x0chn0_1_filter2_en

0: disable; 1: enable

3rw0x0chn0_1_filter3_en

0: disable; 1: enable

4rw0x0chn0_1_filter4_en

0: disable; 1: enable

5rw0x0chn0_1_filter5_en

0: disable; 1: enable

6rw0x0chn0_1_filter6_en

0: disable; 1: enable

7rw0x0chn0_1_filter7_en

0: disable; 1: enable


adc_ctrl.adc_wakeup_status @ 0x6c

Wakeup internal status

Reset default = 0x0, mask 0xff
31302928272625242322212019181716
 
1514131211109876543210
  cc_discon cc_1A5_src_det_flip cc_src_det_flip cc_1A5_src_det cc_src_det cc_3A0_sink_det cc_1A5_sink_det cc_sink_det
BitsTypeResetNameDescription
0rw1c0x0cc_sink_det

0: filter0 condition is not met; 1: filter0 condition is met

1rw1c0x0cc_1A5_sink_det

0: filter1 condition is not met; 1: filter1 condition is met

2rw1c0x0cc_3A0_sink_det

0: filter2 condition is not met; 1: filter2 condition is met

3rw1c0x0cc_src_det

0: filter3 condition is not met; 1: filter3 condition is met

4rw1c0x0cc_1A5_src_det

0: filter4 condition is not met; 1: filter4 condition is met

5rw1c0x0cc_src_det_flip

0: filter5 condition is not met; 1: filter5 condition is met

6rw1c0x0cc_1A5_src_det_flip

0: filter6 condition is not met; 1: filter6 condition is met

7rw1c0x0cc_discon

0: filter7 condition is not met; 1: filter7 condition is met


adc_ctrl.adc_intr_ctl @ 0x70

Debug cable internal control

Reset default = 0x0, mask 0x1ff
31302928272625242322212019181716
 
1514131211109876543210
  oneshot_intr_en chn0_1_filter7_en chn0_1_filter6_en chn0_1_filter5_en chn0_1_filter4_en chn0_1_filter3_en chn0_1_filter2_en chn0_1_filter1_en chn0_1_filter0_en
BitsTypeResetNameDescription
0rw0x0chn0_1_filter0_en

0: disable; 1: enable

1rw0x0chn0_1_filter1_en

0: disable; 1: enable

2rw0x0chn0_1_filter2_en

0: disable; 1: enable

3rw0x0chn0_1_filter3_en

0: disable; 1: enable

4rw0x0chn0_1_filter4_en

0: disable; 1: enable

5rw0x0chn0_1_filter5_en

0: disable; 1: enable

6rw0x0chn0_1_filter6_en

0: disable; 1: enable

7rw0x0chn0_1_filter7_en

0: disable; 1: enable

8rw0x0oneshot_intr_en

0: disable; 1: enable


adc_ctrl.adc_intr_status @ 0x74

Debug cable internal status

Reset default = 0x0, mask 0x1ff
31302928272625242322212019181716
 
1514131211109876543210
  oneshot cc_discon cc_1A5_src_det_flip cc_src_det_flip cc_1A5_src_det cc_src_det cc_3A0_sink_det cc_1A5_sink_det cc_sink_det
BitsTypeResetNameDescription
0rw1c0x0cc_sink_det

0: filter0 condition is not met; 1: filter0 condition is met

1rw1c0x0cc_1A5_sink_det

0: filter1 condition is not met; 1: filter1 condition is met

2rw1c0x0cc_3A0_sink_det

0: filter2 condition is not met; 1: filter2 condition is met

3rw1c0x0cc_src_det

0: filter3 condition is not met; 1: filter3 condition is met

4rw1c0x0cc_1A5_src_det

0: filter4 condition is not met; 1: filter4 condition is met

5rw1c0x0cc_src_det_flip

0: filter5 condition is not met; 1: filter5 condition is met

6rw1c0x0cc_1A5_src_det_flip

0: filter6 condition is not met; 1: filter6 condition is met

7rw1c0x0cc_discon

0: filter7 condition is not met; 1: filter7 condition is met

8rw1c0x0oneshot

0: oneshot sample is not done ; 1: oneshot sample is done