AES Checklist

This checklist is for Hardware Stage transitions for the AES peripheral. All checklist items refer to the content in the Checklist.

Design Checklist

D1

Type Item Resolution Note/Collaterals
Documentation SPEC_COMPLETE Done AES Design Spec
Documentation CSR_DEFINED Done
RTL CLKRST_CONNECTED Done
RTL IP_TOP Done
RTL IP_INSTANTIABLE Done
RTL MEM_INSTANCED_80 N/A
RTL FUNC_IMPLEMENTED Done
RTL ASSERT_KNOWN_ADDED Done
Code Quality LINT_SETUP Done
Review Signoff date Done 2019-11-05

D2

Type Item Resolution Note/Collaterals
Documentation NEW_FEATURES N/A
Documentation BLOCK_DIAGRAM N/A
Documentation DOC_INTERFACE N/A
Documentation MISSING_FUNC Done
Documentation FEATURE_FROZEN Done
RTL FEATURE_COMPLETE Done
RTL AREA_SANITY_CHECK Done
RTL PORT_FROZEN Done
RTL ARCHITECTURE_FROZEN Done
RTL REVIEW_TODO Done
RTL STYLE_X Done
Code Quality LINT_PASS Done
Code Quality CDC_SETUP N/A
Code Quality FPGA_TIMING Done
Code Quality CDC_SYNCMACRO N/A
Review Signoff date Done 2019-11-05

D3

Type Item Resolution Note/Collaterals
Documentation NEW_FEATURES_D3 Not Started
RTL TODO_COMPLETE Not Started
Code Quality LINT_COMPLETE Not Started
Code Quality CDC_COMPLETE Not Started
Review REVIEW_RTL Not Started
Review REVIEW_DELETED_FF Not Started
Review REVIEW_SW_CSR Not Started
Review REVIEW_SW_FATAL_ERR Not Started
Review REVIEW_SW_CHANGE Not Started
Review REVIEW_SW_ERRATA Not Started
Review Signoff date Not Started

Verification Checklist

V1

Type Item Resolution Note/Collaterals
Documentation DV_PLAN_DRAFT_COMPLETED Done AES DV Plan
Documentation TESTPLAN_COMPLETED Done AES Testplan
Testbench TB_TOP_CREATED Done
Testbench PRELIMINARY_ASSERTION_CHECKS_ADDED Done
Testbench SIM_TB_ENV_CREATED Done
Testbench SIM_RAL_MODEL_GEN_AUTOMATED Done
Testbench CSR_CHECK_GEN_AUTOMATED Done
Testbench TB_GEN_AUTOMATED N/A
Tests SIM_SANITY_TEST_PASSING Done
Tests SIM_CSR_MEM_TEST_SUITE_PASSING Done
Tests FPV_MAIN_ASSERTIONS_PROVEN N/A
Tool Setup SIM_ALT_TOOL_SETUP Done Xcelium (signoff), VCS (alt)
Regression SIM_SANITY_REGRESSION_SETUP Done
Regression SIM_NIGHTLY_REGRESSION_SETUP Done
Regression FPV_REGRESSION_SETUP N/A
Coverage SIM_COVERAGE_MODEL_ADDED Done
Integration PRE_VERIFIED_SUB_MODULES_V1 N/A
Review DESIGN_SPEC_REVIEWED Done
Review DV_PLAN_TESTPLAN_REVIEWED Done
Review STD_TEST_CATEGORIES_PLANNED Done Exception (Power)
Review V2_CHECKLIST_SCOPED Done
Review Reviewer(s) Done @sriyerg, @weicai, @eunchan
Review Signoff date Done 2020-03-17

V2

Type Item Resolution Note/Collaterals
Documentation DESIGN_DELTAS_CAPTURED_V2 Not started
Documentation DV_PLAN_COMPLETED Not started
Testbench ALL_INTERFACES_EXERCISED Not started
Testbench ALL_ASSERTION_CHECKS_ADDED Not started
Testbench SIM_TB_ENV_COMPLETED Not started
Tests SIM_ALL_TESTS_PASSING Not started
Tests FPV_ALL_ASSERTIONS_WRITTEN Not started
Tests FPV_ALL_ASSUMPTIONS_REVIEWED Not started
Tests SIM_FW_SIMULATED Not started
Regression SIM_NIGHTLY_REGRESSION_V2 Not started
Coverage SIM_CODE_COVERAGE_V2 Not started
Coverage SIM_FUNCTIONAL_COVERAGE_V2 Not started
Coverage FPV_CODE_COVERAGE_V2 Not started
Coverage FPV_COI_COVERAGE_V2 Not started
Issues NO_HIGH_PRIORITY_ISSUES_PENDING Not started
Issues ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED Not started
Integration PRE_VERIFIED_SUB_MODULES_V2 Not started
Review V3_CHECKLIST_SCOPED Not started
Review Reviewer(s) Not started
Review Signoff date Not started

V3

Type Item Resolution Note/Collaterals
Documentation DESIGN_DELTAS_CAPTURED_V3 Not started
Testbench ALL_TODOS_RESOLVED Not started
Tests X_PROP_ANALYSIS_COMPLETED Not started
Tests FPV_ASSERTIONS_PROVEN_AT_V3 Not started
Regression SIM_NIGHTLY_REGRESSION_AT_V3 Not started
Coverage SIM_CODE_COVERAGE_AT_100 Not started
Coverage SIM_FUNCTIONAL_COVERAGE_AT_100 Not started
Coverage FPV_CODE_COVERAGE_AT_100 Not started
Coverage FPV_COI_COVERAGE_AT_100 Not started
Issues NO_ISSUES_PENDING Not started
Code Quality NO_TOOL_WARNINGS_THROWN Not started
Integration PRE_VERIFIED_SUB_MODULES_V3 Not started
Review Reviewer(s) Not started
Review Signoff date Not started