AES DV Plan

Goals

  • DV
    • Verify all AES IP features by running dynamic simulations with a SV/UVM based testbench
    • Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP.
  • FPV
    • Verify TileLink device protocol compliance with an SVA based testbench

Current status

Design features

For detailed information on AES design features, please see the AES HWIP Technical Specification.

Testbench architecture

AES testbench has been constructed based on the CIP testbench architecture.

Block diagram

Block diagram

Top level testbench

Top level testbench is located at hw/ip/aes/dv/tb/tb.sv. It instantiates the AES DUT module hw/ip/aes/rtl/aes.sv. In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db:

Common DV utility components

The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

Global types & methods

All common types and methods defined at the package level can be found in aes_env_pkg. Some of them in use are:

parameter uint AES_ADDR_MAP_SIZE   = 2048;

TL_agent

AES instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into AES device.

RAL

The AES RAL model is constructed using the regtool.py script and is placed at env/aes_reg_block.sv.

Stimulus strategy

Test sequences

All test sequences reside in hw/ip/aes/dv/env/seq_lib. The aes_base_vseq virtual sequence is extended from cip_base_vseq and serves as a starting point. All test sequences are extended from aes_base_vseq. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. Some of the most commonly used tasks / functions are as follows:

  • aes_init: Configure aes control and can via a knob be set to randomize register content before starting a test.
  • set_op: Set AES operation to encrypt or decrypt.
  • write_key: Write initial key to aes init key registers.
  • add_data: Add the next 128 block to the input registers.
  • read_output: Poll the status reg for dataready bit and read the result from aes output regs

Functional coverage

To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met: *— Work in Progress —

Self-checking strategy

Scoreboard

The aes_scoreboard is primarily used for end to end checking. It creates the following analysis fifos to retrieve the data monitored by corresponding interface agent:

  • tl_a_chan_fifo, tl_d_chan_fifo: These 2 fifos provides transaction items at the end of address channel and data channel respectively

Assertions

  • TLUL assertions: The tb/aes_bind.sv binds the tlul_assert [assertions]/hw/ip/tlul/doc/TlulProtocolChecker/) to the IP to ensure TileLink interface protocol compliance.
  • Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.

Building and running tests

We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a basic sanity test:

$ cd hw/ip/aes/dv
$ make TEST_NAME=aes_sanity

Here’s how to run a basic test wihtout DPI calls:

$ cd hw/ip/aes/dv
$ make TEST_NAME=aes_wakeup_test

Testplan

Milestone Name Description Tests
V1 wake_up

Basic hello world, encrypt a plain text read it back - decrypt and compare to input

aes_wake_up
V1 sanity

Encrypt a plain text read it back - decrypt and compare to input but use reference model to compare after both encryption and decryption

aes_sanity
V1 csr_hw_reset

Verify the reset values as indicated in the RAL specification.

  • Write all CSRs with a random value.
  • Apply reset to the DUT as well as the RAL model.
  • Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
aes_csr_hw_reset
V1 csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

  • Loop through each CSR to write it with a random value.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
aes_csr_rw
V1 csr_bit_bash

Verify no aliasing within individual bits of a CSR.

  • Walk a 1 through each CSR by flipping 1 bit at a time.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • This verify that writing a specific bit within the CSR did not affect any of the other bits.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
aes_csr_bit_bash
V1 csr_aliasing

Verify no aliasing within the CSR address space.

  • Loop through each CSR to write it with a random value
  • Shuffle and read ALL CSRs back.
  • All CSRs except for the one that was written in this iteration should read back the previous value.
  • The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
aes_csr_aliasing
V2 algorithm

Compare cypher text from AWS module with the output of a C model using same key and data

aes_sanity
V2 key_size

Randomly select keysize to verify all supported keysizes are working

V2 failure_test
  • Tests what happens if a register is written a the wrong time?, if a key does not match the key setting etc. will module ignore or fail gracefully
  • enter a 256bit key but set AES to use 128 for encryption. then enter the 128bit of the key and use for decryption. will result match plain text and vice verca
V2 reset_recovery

Pull reset at random times make sure AES recover/resets correctly

V2 deinitialization

Make sure that there is no residual data from latest operation

V2 oob_addr_access

Access out of bounds address and verify correctness of response / behavior

aes_tl_errors
V2 illegal_access

Drive unsupported requests via TL interface and verify correctness of response / behavior

aes_tl_errors
V2 outstanding_access

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

aes_csr_hw_reset
aes_csr_rw
aes_csr_aliasing
aes_same_csr_outstanding
V2 partial_access

Do partial accesses.

aes_csr_hw_reset
aes_csr_rw
aes_csr_aliasing