AES DV Plan
- Verify all AES IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP.
- Verify TileLink device protocol compliance with an SVA based testbench
For detailed information on AES design features, please see the AES HWIP Technical Specification.
AES testbench has been constructed based on the CIP testbench architecture.
Top level testbench
Top level testbench is located at
It instantiates the AES DUT module
In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into
Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
Global types & methods
All common types and methods defined at the package level can be found in
Some of them in use are:
parameter uint NUM_ALERTS = 2;
AES instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into AES device.
UVM RAL model
The AES RAL model is created with the
ralgen FuseSoC generator script automatically when the simulation is at the build stage.
It can be created manually by invoking
All test sequences reside in
aes_base_vseq virtual sequence is extended from
cip_base_vseq and serves as a starting point.
All test sequences are extended from
aes_base_vseq provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:
- aes_init: Initialize the AES module from the randomized environment variables in the config.
- set_op: Set AES operation to encrypt or decrypt.
- write_key: Write initial key to AES init key registers.
- add_data: Add the next 128 block to the input registers.
- read_output: Poll the status register for data ready bit and read the result from AES output registers.
- clear_reg: Based on the input this function clears data input-, data output- or key-registers or any combination of these.
- set_manual_trigger: Chooses between AES auto start and manual start.
- trigger_start: Set the start bit to trigger a new encryption/decryption.
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following cover groups have been developed to prove that the test intent has been adequately met.
WORK IN PROGRESS WILL COME WITH V2.
aes_scoreboard is primarily used for end to end checking.
It creates the following analysis FIFOs to retrieve the data monitored by corresponding interface agents:
- tl_a_chan_fifo: tl address channel
- tl_d_chan_fifo: tl data channel
These 2 FIFOs provide transaction items at the end of the address channel and data channel respectively. Each FIFO is monitored and incoming transactions are stored. Whenever a transaction is finished the sequence item is handed over to a reference model that will generate the expected response. At the same time the scoreboard is waiting for the result of the AES module to compute. Once complete the result is scored against the prediction made by the reference model.
The reference model is selected to be either a C-implementation or an SSL-library selected on a random basis with the default distribution of 80% OpenSSL/BoringSSL and 20% C-model.
The default behavior for the verification is that the scoreboard wait until the complete message has been encrypted/decrypted before checking the result against the reference model.
The scoreboard has a step through mode where the scoring is done after each 128bit block. This setting is only available when using the C-model as reference and is controlled with a knob.
- TLUL assertions: The
tlul_assertassertions to the IP to ensure TileLink interface protocol compliance.
- Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
Building and running tests
We are using our in-house developed regression tool for both building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a basic sanity test:
$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/aes/dv/aes_sim_cfg.hjson -i aes_sanity
Here’s how to run a basic test without DPI calls:
$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/aes/dv/aes_sim_cfg.hjson -i aes_wakeup_test
Basic hello world, encrypt a plain text read it back - decrypt and compare to input.
Encrypt a plain text read it back - decrypt and compare to input but use reference model to compare after both encryption and decryption.
Verify the reset values as indicated in the RAL specification.
Verify accessibility of CSRs as indicated in the RAL specification.
Verify no aliasing within individual bits of a CSR.
Verify no aliasing within the CSR address space.
Verify random reset during CSR/memory access.
Verify shadow registers' update and storage errors.
Compare cypher text from DUT with the output of a C model using same key and data.
Randomly select key length to verify all supported key lengths are working.
Randomly select the spacing between consecutive messages and blocks from 0 - n clock cycles. The distribution will be weighted toward no and small gaps (0-10 cycles) but will also cover larger gaps.
Try to write data to registers without offloading the DUT output to verify Stall functionality.
Run multiple messages in a random mix of encryption / decryption. Each message should select its mode randomly.
Exercise trigger and clear registers at random times to make sure we handle the different cornercases correctly. Example of a cornercases clearing data input or data output before the data is consumed or the DUT finishes an operation.
Verify that the DUT handles the NIST test vectors correctly.
Verify that the DUT performs as specified for each key length in terms of latency and throughput. This testpoint will use automode (this will feed input data and offload output data as fast as the DUT can support it.)
Pull reset at random times, make sure DUT recover/resets correctly and there is no residual data left in the registers.
This will combine the other individual testpoints to ensure we stress test everything across the board.
Make sure that there is no residual data from latest operation.
Access out of bounds address and verify correctness of response / behavior
Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested
Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.
Access CSR with one or more bytes of data For read, expect to return all word value of the CSR For write, enabling bytes should cover all CSR valid fields