AES DV Plan
- Verify all AES IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP.
- Verify TileLink device protocol compliance with an SVA based testbench
For detailed information on AES design features, please see the AES HWIP Technical Specification.
AES testbench has been constructed based on the CIP testbench architecture.
Top level testbench
Top level testbench is located at
hw/ip/aes/dv/tb/tb.sv. It instantiates the AES DUT module
In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into
Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
Global types & methods
All common types and methods defined at the package level can be found in
Some of them in use are:
parameter uint AES_ADDR_MAP_SIZE = 2048;
AES instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into AES device.
The AES RAL model is constructed using the regtool.py script and is placed at
All test sequences reside in
aes_base_vseq virtual sequence is extended from
cip_base_vseq and serves as a starting point.
All test sequences are extended from
It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:
- aes_init: Configure aes control and can via a knob be set to randomize register content before starting a test.
- set_op: Set AES operation to encrypt or decrypt.
- write_key: Write initial key to aes init key registers.
- add_data: Add the next 128 block to the input registers.
- read_output: Poll the status reg for dataready bit and read the result from aes output regs
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met: *— Work in Progress —
aes_scoreboard is primarily used for end to end checking.
It creates the following analysis fifos to retrieve the data monitored by corresponding interface agent:
- tl_a_chan_fifo, tl_d_chan_fifo: These 2 fifos provides transaction items at the end of address channel and data channel respectively
- TLUL assertions: The
tlul_assert[assertions]/hw/ip/tlul/doc/TlulProtocolChecker/) to the IP to ensure TileLink interface protocol compliance.
- Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
Building and running tests
We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a basic sanity test:
$ cd hw/ip/aes/dv $ make TEST_NAME=aes_sanity
Here’s how to run a basic test wihtout DPI calls:
$ cd hw/ip/aes/dv $ make TEST_NAME=aes_wakeup_test
Basic hello world, encrypt a plain text read it back - decrypt and compare to input
Encrypt a plain text read it back - decrypt and compare to input but use reference model to compare after both encryption and decryption
Verify the reset values as indicated in the RAL specification.
Verify accessibility of CSRs as indicated in the RAL specification.
Verify no aliasing within individual bits of a CSR.
Verify no aliasing within the CSR address space.
Compare cypher text from AWS module with the output of a C model using same key and data
Randomly select keysize to verify all supported keysizes are working
Pull reset at random times make sure AES recover/resets correctly
Make sure that there is no residual data from latest operation
Access out of bounds address and verify correctness of response / behavior
Drive unsupported requests via TL interface and verify correctness of response / behavior
Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.
Do partial accesses.