• DV
    • Verify all AES IP features by running dynamic simulations with a SV/UVM based testbench
    • Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP.
  • FPV
    • Verify TileLink device protocol compliance with an SVA based testbench

Current status

Design features

For detailed information on AES design features, please see the AES HWIP Technical Specification.

Testbench architecture

AES testbench has been constructed based on the CIP testbench architecture.

Block diagram

Block diagram

Top level testbench

Top level testbench is located at hw/ip/aes/dv/tb/ It instantiates the AES DUT module hw/ip/aes/rtl/ In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db:

Common DV utility components

The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

Global types & methods

All common types and methods defined at the package level can be found in aes_env_pkg. Some of them in use are:

parameter uint NUM_ALERTS = 2;


AES instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into AES device.

UVM RAL model

The AES RAL model is created with the ralgen FuseSoC generator script automatically when the simulation is at the build stage.

It can be created manually by invoking regtool:

Stimulus strategy

Test sequences

All test sequences reside in hw/ip/aes/dv/env/seq_lib. The aes_base_vseq virtual sequence is extended from cip_base_vseq and serves as a starting point. All test sequences are extended from aes_base_vseq. aes_base_vseq provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. Some of the most commonly used tasks / functions are as follows:

  • aes_init: Initialize the AES module from the randomized environment variables in the config.
  • set_op: Set AES operation to encrypt or decrypt.
  • write_key: Write initial key to AES init key registers.
  • add_data: Add the next 128 block to the input registers.
  • read_output: Poll the status register for data ready bit and read the result from AES output registers.
  • clear_reg: Based on the input this function clears data input-, data output- or key-registers or any combination of these.
  • set_manual_trigger: Chooses between AES auto start and manual start.
  • trigger_start: Set the start bit to trigger a new encryption/decryption.

Functional coverage

To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following cover groups have been developed to prove that the test intent has been adequately met.


Self-checking strategy


The aes_scoreboard is primarily used for end to end checking. It creates the following analysis FIFOs to retrieve the data monitored by corresponding interface agents:

  • tl_a_chan_fifo: tl address channel
  • tl_d_chan_fifo: tl data channel

These 2 FIFOs provide transaction items at the end of the address channel and data channel respectively. Each FIFO is monitored and incoming transactions are stored. Whenever a transaction is finished the sequence item is handed over to a reference model that will generate the expected response. At the same time the scoreboard is waiting for the result of the AES module to compute. Once complete the result is scored against the prediction made by the reference model.

The reference model is selected to be either a C-implementation or an SSL-library selected on a random basis with the default distribution of 80% OpenSSL/BoringSSL and 20% C-model.

The default behavior for the verification is that the scoreboard wait until the complete message has been encrypted/decrypted before checking the result against the reference model.

The scoreboard has a step through mode where the scoring is done after each 128bit block. This setting is only available when using the C-model as reference and is controlled with a knob.


  • TLUL assertions: The tb/ binds the tlul_assert assertions to the IP to ensure TileLink interface protocol compliance.
  • Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.

Building and running tests

We are using our in-house developed regression tool for both building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a basic sanity test:

$ $REPO_TOP/util/dvsim/ $REPO_TOP/hw/ip/aes/dv/aes_sim_cfg.hjson -i aes_sanity

Here’s how to run a basic test without DPI calls:

$ $REPO_TOP/util/dvsim/ $REPO_TOP/hw/ip/aes/dv/aes_sim_cfg.hjson -i aes_wakeup_test


Milestone Name Description Tests
V1 wake_up

Basic hello world, encrypt a plain text read it back - decrypt and compare to input.

V1 sanity

Encrypt a plain text read it back - decrypt and compare to input but use reference model to compare after both encryption and decryption.

V1 csr_hw_reset

Verify the reset values as indicated in the RAL specification.

  • Write all CSRs with a random value.
  • Apply reset to the DUT as well as the RAL model.
  • Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

  • Loop through each CSR to write it with a random value.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_bit_bash

Verify no aliasing within individual bits of a CSR.

  • Walk a 1 through each CSR by flipping 1 bit at a time.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • This verify that writing a specific bit within the CSR did not affect any of the other bits.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_aliasing

Verify no aliasing within the CSR address space.

  • Loop through each CSR to write it with a random value
  • Shuffle and read ALL CSRs back.
  • All CSRs except for the one that was written in this iteration should read back the previous value.
  • The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_mem_rw_with_rand_reset

Verify random reset during CSR/memory access.

  • Run csr_rw sequence to randomly access CSRs
  • If memory exists, run mem_partial_access in parallel with csr_rw
  • Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
V1 shadow_reg_errors

Verify shadow registers' update and storage errors.

  • Issue reset at random to clear all the internal stored values and phases trackers in shadow registers.
  • Select all the shadow registers and a random amount of the rest of the non-excluded registers. Shuffle and write random values to the selected registers. For shadow registers, the second write is not enabled. There is a 50% possibility that the shadow register's write value is identical to its previous write value. If shadow register's second write value does not match the first write value, ensure that the update error alert is triggered.
  • Randomly inject storage errors by modifying the shadow register's staged or committed values via backdoor method. Ensure that the storage error alert is triggered.
  • Randomly decide to read all the non-excluded registers or fields. Then check the read values against predicted values. A read on a shadow register will clear its phase tracker.
  • Repeat the above steps a bunch of times.
V2 algorithm

Compare cypher text from DUT with the output of a C model using same key and data.

V2 key_length

Randomly select key length to verify all supported key lengths are working.

V2 back2back

Randomly select the spacing between consecutive messages and blocks from 0 - n clock cycles. The distribution will be weighted toward no and small gaps (0-10 cycles) but will also cover larger gaps.

V2 backpressure

Try to write data to registers without offloading the DUT output to verify Stall functionality.

V2 multi_message

Run multiple messages in a random mix of encryption / decryption. Each message should select its mode randomly.

V2 failure_test
  • Tests what happens if a register is written a the wrong time? If a key does not match the key setting etc. Will the DUT ignore or fail gracefully.
  • Enter a 256bit key but set DUT to use 128bit for encryption. Then enter the 128bit of the key and use for decryption. Will result match plain text and vice.
  • Write unsupported configurations (Key length and mode are 1 hot, what happens if more than one bit is set.)
V2 trigger_clear_test

Exercise trigger and clear registers at random times to make sure we handle the different cornercases correctly. Example of a cornercases clearing data input or data output before the data is consumed or the DUT finishes an operation.

V2 nist_test_vectors

Verify that the DUT handles the NIST test vectors correctly.

V2 performance

Verify that the DUT performs as specified for each key length in terms of latency and throughput. This testpoint will use automode (this will feed input data and offload output data as fast as the DUT can support it.)

V2 reset_recovery

Pull reset at random times, make sure DUT recover/resets correctly and there is no residual data left in the registers.

V2 stress

This will combine the other individual testpoints to ensure we stress test everything across the board.

V2 deinitialization

Make sure that there is no residual data from latest operation.

V2 tl_d_oob_addr_access

Access out of bounds address and verify correctness of response / behavior

V2 tl_d_illegal_access

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested

  • TL-UL protocol error cases
    • Unsupported opcode. e.g a_opcode isn't Get, PutPartialData or PutFullData
    • Mask isn't all active if opcode = PutFullData
    • Mask isn't in enabled lanes, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
    • Mask doesn't align with address, e.g. a_address = 0x01, a_mask = 'b0001
    • Address and size aren't aligned, e.g. a_address = 0x01, a_size != 0
    • Size is over 2.
  • OpenTitan defined error cases
    • Access unmapped address, return d_error = 1 when devmode_i == 1
    • Write CSR with unaligned address, e.g. a_address[1:0] != 0
    • Write CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
    • Write a memory without enabling all lanes (a_mask = '1) if memory doesn't support byte enabled write
    • Read a WO (write-only) memory
V2 tl_d_outstanding_access

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

V2 tl_d_partial_access

Access CSR with one or more bytes of data For read, expect to return all word value of the CSR For write, enabling bytes should cover all CSR valid fields