ALERT_HANDLER DV Plan
- Verify all ALERT_HANDLER IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
- Verify TileLink device protocol compliance with an SVA based testbench
- Verify transmitter and receiver pairs for alert and escalator
- Partially verify ping_timer
For detailed information on ALERT_HANDLER design features, please see the ALERT_HANDLER HWIP technical specification.
ALERT_HANDLER testbench has been constructed based on the CIP testbench architecture.
Top level testbench
Top level testbench is located at
hw/ip/alert_handler/dv/tb/tb.sv. It instantiates the ALERT_HANDLER DUT module
In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into
- Clock and reset interface
- TileLink host interface
- ALERT_HANDLER IOs
- Interrupts (
- Devmode (
Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
Global types & methods
All common types and methods defined at the package level can be found in
alert_handler_env_pkg. Some of them in use are:
parameter uint ALERT_HANDLER_ADDR_MAP_SIZE = 2048; parameter uint NUM_MAX_ESC_SEV = 8;
ALERT_HANDLER testbench instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into ALERT_HANDLER device.
[ALERT_HANDLER agent]:link WIP is used to drive and monitor transmitter and receiver pairs for the alerts and escalators.
UVM RAL Model
The ALERT_HANDLER RAL model is created with the
fusesoc generator script automatically when the simulation is at the build stage.
It can be created manually (separately) by running
make in the the
All test sequences reside in
alert_handler_base_vseq virtual sequence is extended from
cip_base_vseq and serves as a starting point.
All test sequences are extended from
It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:
// Work in Process:
- task 1:
- task 2:
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met: // Work in Process:
alert_handler_scoreboard is primarily used for end to end checking.
It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:
// Work in Process:
- tl_a_chan_fifo: tl address channel
- tl_d_chan_fifo: tl data channel
- TLUL assertions: The
tlul_assertassertions to the IP to ensure TileLink interface protocol compliance.
- Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
Building and running tests
We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here's how to run a basic sanity test:
$ cd hw/ip/alert_handler/dv $ make TEST_NAME=alert_handler_sanity
Verify the reset values as indicated in the RAL specification.
Verify accessibility of CSRs as indicated in the RAL specification.
Verify no aliasing within individual bits of a CSR.
Verify no aliasing within the CSR address space.
Based on the sanity test, this test will focus on testing the escalation accumulation feature. So all the escalations in the test will be triggered by alert accumulation.
Based on the sanity test, this test will focus on testing the escalation timeout feature. So all the escalations in the test will be triggered by interrupt timeout.
Based on the sanity test, this test enables ping testing, and check if the ping feature correctly pings all devices within certain period of time
This test will randomly inject differential pair failures on alert tx/rx pairs and the escalator tx/rx pairs. Then check if integrity failure alert is triggered and escalated
This test will randomly inject ping response failures on alert tx/rx pairs and the escalator tx/rx pairs. Then check if ping response failure alert is triggered and escalated
This test will randomly inject clock skew within the differential pairs. Then check no alert is raised
Input random alerts and randomly write phase cycles
Randomly enable classes and randomly write phase cycles
Have random reset in parallel with stress_all and tl_errors sequences
Verify common intr_test CSRs that allows SW to mock-inject interrupts.
The CSR test sequences will read and write accessible CSRs including the enable registers and their locked registers. The RAL model supports predicting the correct value of the locked registers based on their enable registers.
Access out of bounds address and verify correctness of response / behavior
Drive unsupported requests via TL interface and verify correctness of response / behavior
Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.
Do partial accesses.