ALERT_HANDLER DV Plan
- Verify all ALERT_HANDLER IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
- Verify TileLink device protocol compliance with an SVA based testbench
- Verify transmitter and receiver pairs for alert and escalator
- Partially verify ping_timer
For detailed information on ALERT_HANDLER design features, please see the ALERT_HANDLER HWIP technical specification.
ALERT_HANDLER testbench has been constructed based on the CIP testbench architecture.
Top level testbench
Top level testbench is located at
hw/ip/alert_handler/dv/tb/tb.sv. It instantiates the ALERT_HANDLER DUT module
In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into
- Clock and reset interface
- TileLink host interface
- ALERT_HANDLER IOs
- Interrupts (
- Devmode (
In chip level testing, alert_handler testbench environment can be reused with a chip-level paramter package located at
Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
Global types & methods
All common types and methods defined at the package level can be found in
alert_handler_env_pkg. Some of them in use are:
parameter uint NUM_MAX_ESC_SEV = 8;
ALERT_HANDLER testbench instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into ALERT_HANDLER device.
[ALERT_HANDLER agent]:link WIP is used to drive and monitor transmitter and receiver pairs for the alerts and escalators.
UVM RAL Model
The ALERT_HANDLER RAL model is created with the
fusesoc generator script automatically when the simulation is at the build stage.
It can be created manually by invoking
All test sequences reside in
alert_handler_base_vseq virtual sequence is extended from
cip_base_vseq and serves as a starting point.
All test sequences are extended from
It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:
- drive_alert: Drive alert_tx signal pairs through
- read_ecs_status: Readout registers that reflect escalation status, including
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:
- accum_cnt_cg: Cover number of alerts triggered under the same class
- esc_sig_length_cg: Cover signal length of each escalation pairs
alert_handler_scoreboard is primarily used for end to end checking.
It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:
- tl_a_chan_fifo: tl address channel
- tl_d_chan_fifo: tl data channel
- alert_fifo: An array of
alert_fifothat connects to corresponding alert_monitors
- esc_fifo: An array of
esc_fifothat connects to corresponding esc_monitors
Alert_handler scoreboard monitors all valid CSR registers, alert handshakes, and escalation handshakes. To ensure certain alert, interrupt, or escalation signals are triggered at the expected time, the alert_handler scoreboard implemented a few counters:
- intr_cnter_per_class[NUM_ALERT_HANDLER_CLASSES]: Count number of clock cycles that the interrupt bit stays high.
If the stored number is larger than the
timeout_cycregisters, the corresponding escalation is expected to be triggered
- accum_cnter_per_class[NUM_ALERT_HANDLER_CLASSES]: Count number of alerts triggered under the same class.
If the stored number is larger than the
accum_thresholdregisters, the corresponding escalation is expected to be triggered
- esc_cnter_per_signal[NUM_ESC_SIGNALS]: Count number of clock cycles that each escalation signal stays high.
Compare the counter against
The alert_handler scoreboard is parameterized to support different number of classes, alert pairs, and escalation pairs.
- TLUL assertions: The
tlul_assertassertions to the IP to ensure TileLink interface protocol compliance.
- Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
Building and running tests
We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:
$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/$CHIP/ip/alert_handler/dv/alert_handler_sim_cfg.hjson -i alert_handler_smoke
In this run command, $CHIP can be top_earlgrey, etc.
Verify the reset values as indicated in the RAL specification.
Verify accessibility of CSRs as indicated in the RAL specification.
Verify no aliasing within individual bits of a CSR.
Verify no aliasing within the CSR address space.
Verify random reset during CSR/memory access.
Based on the smoke test, this test will focus on testing the escalation accumulation feature. So all the escalations in the test will be triggered by alert accumulation.
Based on the smoke test, this test will focus on testing the escalation timeout feature. So all the escalations in the test will be triggered by interrupt timeout.
Based on the smoke test, this test enables ping testing, and check if the ping feature correctly pings all devices within certain period of time
This test will randomly inject differential pair failures on alert tx/rx pairs and the escalator tx/rx pairs. Then check if integrity failure alert is triggered and escalated
Based on the entropy test, this test will randomly inject ping timeout errors and ping signal integrity errors on alert tx/rx or escalator tx/rx pairs. Once a ping request is detected, the sequence will randomly execute one of the three tasks:
This test will randomly inject clock skew within the differential pairs. Then check no alert is raised
Input random alerts and randomly write phase cycles
Based on random_alerts test, this test will also randomly enable interrupt classes
Combine above sequences in one test to run sequentially with the following exclusions:
Verify common intr_test CSRs that allows SW to mock-inject interrupts.
The CSR test sequences will read and write accessible CSRs including the enable registers and their locked registers. The RAL model supports predicting the correct value of the locked registers based on their enable registers.
This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.
Access out of bounds address and verify correctness of response / behavior
Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested
Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.
Access CSR with one or more bytes of data For read, expect to return all word value of the CSR For write, enabling bytes should cover all CSR valid fields