# AON Timer DV Document

## Goals

• DV
• Verify the always-on timer (AON Timer) by running dynamic simulations with a SV/UVM based testbench
• Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
• FPV
• Verify TileLink device protocol compliance with an SVA based testbench

## Design features

The AON timer is documented in the AON Timer HWIP technical specification.

## Testbench architecture

The testbench is based on the CIP testbench architecture.

### Top-level testbench

The block’s testbench is located at hw/ip/aon_timer/dv/tb/tb.sv. It instantiates the aon_timer DUT module, defined at hw/ip/aon_timer/rtl/aon_timer.sv.

In addition, it instantiates the following interfaces, connects them to the DUT and registers their handles in uvm_config_db:

• A clock and reset interface for the fast clock
• A clock and reset interface for the AON clock
• A TileLink host interface The AON timer exposes a TL device. Here, the testbench is acting as the host CPU; in the OpenTitan SoC, this will be the Ibex core.
• Two interrupts (wakeup timer; watchdog bark) in the fast clock domain
• Two interrupts (wakeup timer; watchdog bite) in the AON clock domain
• The sleep mode input
• The core interface (see below).

The interrupts and sleep mode input are modelled with the basic pins_if interface.

The AON timer uses three clock domains (async, clk_i and clk_aon_i), with synchronisation logic between them. The following diagram shows the different inputs and outputs for the module and in which clock domain each resides.

To model this accurately without having to precisely model the timing of the synchronisation logic, the testbench is split into two pieces. The first piece has a precise model of the AON timer core and checks that the DUT respects it. The second piece has an approximate timing model and checks forwarding between the async, fast and slow clock domains. These pieces are connected through a bound-in interface, which observes signals on the aon_timer_core instance. This core interface is bound into the design as u_core_if and is used to passively monitor the signals coming in and out of the AON Timer Core block in this diagram.

In order to communicate through the register interface, the testbench uses the tl_agent that is instantiated in the CIP base environment. This is also used by generic test sequences to exercise the register interface.

### UVM RAL Model

The aon_timer RAL model is created with the ralgen FuseSoC generator script automatically when the simulation is at the build stage.

It can be created manually by invoking regtool. Running

util/regtool.py -s -t . hw/ip/aon_timer/data/aon_timer.hjson


will generate aon_timer_ral_pkg.core and aon_timer_ral_pkg.sv in the current directory.

### Stimulus strategy

We want to see timers expire without waiting too long, but we also want to check the counter for large values. To get this right, we normally set up tests as follows:

• Pick a threshold value
• Pick a start count slightly below the threshold value

Occasionally, we’ll pick a start count above the threshold value, to make sure nothing triggers when it shouldn’t. To ensure that we check wrap-around behaviour and see toggles on counter bits, we are careful to pick threshold values more often if they are near zero, the maximum value, or powers of two.

Since the two timers are essentially independent, we use two test sequences, driving them separately.

#### Test sequences

The test sequences can be found in hw/ip/aon_timer/dv/env/seq_lib. The basic test virtual sequence configures the block in a valid initial state, but doesn’t enable either timer. This is used as a base class for automated tests like the CSR tests.

TODO: Describe other test sequences here.

#### Functional coverage

TODO: Functional coverage points are not yet defined.

### Self-checking strategy

#### Scoreboard

As described earlier in this document, the self-checking strategy is in two parts. The first part of the strategy is to track the domain crossing logic and check that values propagate across unmodified and reasonably quickly. This does not include precise modelling for the CDC timing.

The second part of the self-checking logic looks at only the core interface. This is an interface of type aon_timer_core_if, that is bound into the aon_timer_core module. Here, there is a single clock domain (the AON clock) and easily predictable behaviour. The scoreboard contains an exact model of how the signals exposed by this interface will behave.

Putting the two parts of the scoreboard together gives a full checker for the block. An incoming configuration write will be tracked (with slightly flexible timing) through the CDC logic by the first part of the scoreboard. Once it takes effect in the core, the second part of the scoreboard will check that things behave correctly. Finally, outputs (in the form of configuration register updates or interrupts) will be tracked by the first part of the scoreboard as they go back through the CDC logic and, eventually, make it out to the top-level.

#### Assertions

TLUL protocol assertions are checked by binding the TL-UL protocol checker into the design.

Outputs are also checked for 'X values by assertions in the design RTL.

## Building and running tests

Tests can be run with dvsim.py. The link gives details of the tool’s features and command line arguments. To run a basic smoke test, go to the top of the repository and run:

\$ util/dvsim/dvsim.py hw/ip/aon_timer/dv/aon_timer_sim_cfg.hjson -i aon_timer_smoke


## Testplan

### Testpoints

Milestone Name Tests Description
V1 smoke aon_timer_smoke

Smoke test accessing a major datapath within the aon_timer.

Stimulus:

• TBD

Checks:

• TBD
V1 feature1

Add more test entries here like above.

V1 csr_hw_reset aon_timer_csr_hw_reset

Verify the reset values as indicated in the RAL specification.

• Write all CSRs with a random value.
• Apply reset to the DUT as well as the RAL model.
• Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_rw aon_timer_csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

• Loop through each CSR to write it with a random value.
• Read the CSR back and check for correctness while adhering to its access policies.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_bit_bash aon_timer_csr_bit_bash

Verify no aliasing within individual bits of a CSR.

• Walk a 1 through each CSR by flipping 1 bit at a time.
• Read the CSR back and check for correctness while adhering to its access policies.
• This verify that writing a specific bit within the CSR did not affect any of the other bits.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_aliasing aon_timer_csr_aliasing

Verify no aliasing within the CSR address space.

• Loop through each CSR to write it with a random value
• Shuffle and read ALL CSRs back.
• All CSRs except for the one that was written in this iteration should read back the previous value.
• The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_mem_rw_with_rand_resetaon_timer_csr_mem_rw_with_rand_reset

Verify random reset during CSR/memory access.

• Run csr_rw sequence to randomly access CSRs
• If memory exists, run mem_partial_access in parallel with csr_rw
• Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
V1 mem_walk aon_timer_mem_walk

Verify accessibility of all memories in the design.

• Run the standard UVM mem walk sequence on all memories in the RAL model.
• It is mandatory to run this test from all available interfaces the memories are accessible from.
V1 mem_partial_access aon_timer_mem_partial_access

Verify partial-accessibility of all memories in the design.

• Do partial reads and writes into the memories and verify the outcome for correctness.
• Also test outstanding access on memories
V2 intr_test aon_timer_intr_test

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

• Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
• Randomly &quot;turn on&quot; interrupts by writing random value(s) to intr_test CSR(s).
• Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
• Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
• Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
• Repeat the above steps a bunch of times.

Access out of bounds address and verify correctness of response / behavior

V2 tl_d_illegal_access aon_timer_tl_errors

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the [TLUL spec]({{&lt; relref &quot;hw/ip/tlul/doc/_index.md#explicit-error-cases&quot; &gt;}})

• TL-UL protocol error cases
• invalid opcode
• some mask bits not set when opcode is PutFullData
• mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = &#x27;b0010
• mask and address misaligned, e.g. a_address = 0x01, a_mask = &#x27;b0001
• address and size aren't aligned, e.g. a_address = 0x01, a_size != 0
• size is greater than 2
• OpenTitan defined error cases
• access unmapped address, expect d_error = 1 when devmode_i == 1
• write a CSR with unaligned address, e.g. a_address[1:0] != 0
• write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
• write a memory with a_mask != &#x27;1 when it doesn't support partial accesses
• read a WO (write-only) memory
• write a RO (read-only) memory
V2 tl_d_outstanding_access aon_timer_csr_hw_reset
aon_timer_csr_rw
aon_timer_csr_aliasing
aon_timer_same_csr_outstanding

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

V2 tl_d_partial_access aon_timer_csr_hw_reset
aon_timer_csr_rw
aon_timer_csr_aliasing
aon_timer_same_csr_outstanding

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

V3 tl_intg_err aon_timer_tl_intg_err

Verify that the data integrity check violation generates an alert.

Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.

### Covergroups

Name Description
tl_errors_cg

Cover the following error cases on TL-UL bus:

• TL-UL protocol error cases.
• OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.
tl_intg_err_cg

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

tl_intg_err_mem_subword_cg

Cover the kinds of integrity errors with byte enabled write on memory.

Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.