CSRNG DV document
- Verify all CSRNG IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the DV plan below towards closing code and functional coverage on the IP and all of its sub-modules
- Verify TileLink device protocol compliance with an SVA based testbench
For detailed information on CSRNG design features, please see the CSRNG HWIP technical specification.
CSRNG testbench has been constructed based on the CIP testbench architecture.
Top level testbench
Top level testbench is located at
hw/ip/csrng/dv/tb/tb.sv. It instantiates the CSRNG DUT module
In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into
- Clock and reset interface
- TileLink host interface
- CSRNG IOs
- Interrupts (
- Alerts (
- Devmode (
Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
Global types & methods
All common types and methods defined at the package level can be found in
csrng_env_pkg. Some of them in use are:
CSRNG testbench instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into CSRNG device.
CSRNG testbench instantiates this push_pull_agent(/hw/dv/sv/push_pull_agent/README/) which models the ENTROPY_SRC module.
UVM RAL Model
The CSRNG RAL model is created with the
ralgen FuseSoC generator script automatically when the simulation is at the build stage.
It can be created manually by invoking
All test sequences reside in
csrng_base_vseq virtual sequence is extended from
cip_base_vseq and serves as a starting point.
All test sequences are extended from
It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:
- csrng_init: Initialize the CSRNG module from the randomized environment variables in the config.
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:
- common covergroup for interrupts
hw/dv/sv/cip_lib/cip_base_env_cov.sv: Cover interrupt value, interrupt enable, intr_test, interrupt pin
csrng_scoreboard is primarily used for end to end checking.
It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:
- tl_a_chan_fifo, tl_d_chan_fifo: These 2 fifos provide transaction items at the end of Tilelink address channel and data channel respectively
- entropy_src_fifo, genbits_fifo: The entropy_src_fifo provides transaction items from the predictor and the genbits_fifo provide actual post-entropy_src transaction items to compare
- TLUL assertions: The
tlul_assertassertions to the IP to ensure TileLink interface protocol compliance.
- Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
Building and running tests
We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:
$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/csrng/dv/csrng_sim_cfg.hjson -i csrng_smoke
Enable csrng, send instantiate/generate cmds, verify 0-seed genbits/interrupt.
Verify the reset values as indicated in the RAL specification.
Verify accessibility of CSRs as indicated in the RAL specification.
Verify no aliasing within individual bits of a CSR.
Verify no aliasing within the CSR address space.
Verify random reset during CSR/memory access.
Verify ability to access genbits register based on value of efuse input. Verify regen bit disables write access of control registers. Verify registers at End-Of-Test.
Verify cs_cmd_req_done interrupt asserts/clears as predicted. Verify cs_entropy_req interrupt asserts/clears as predicted. Verify cs_hw_inst_exc interrupt asserts/clears as predicted. Verify cs_fifo_err interrupt asserts/clears as predicted. Verify fifo error status bits are set as predicted.
Verify all SW app csrng commands req/status behave as predicted. Verify all HW app csrng commands req/status behave as predicted. Verify above for all valid values of acmd, clen, flags, glen. Verify for multiple hw app interfaces running in parallel. Verify sw/hw app interfaces running in parallel.
Verify lifecycle hardware debug mode enables AES bypass, reading CSRNG internal state. Verify CSRNG internal state for all csrng/genbits operations.
Verify genbits generated as predicted. Verify fips bits is passed through properly. Verify for multiple hw app interfaces running in parallel.
Combine the other individual testpoints while injecting TL errors and running CSR tests in parallel.
Verify common intr_test CSRs that allows SW to mock-inject interrupts.
Access out of bounds address and verify correctness of response / behavior
Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested
Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.
Access CSR with one or more bytes of data For read, expect to return all word value of the CSR For write, enabling bytes should cover all CSR valid fields
This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.