EDN DV document

Goals

DV
- Verify all EDN IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
FPV
- Verify TileLink device protocol compliance with an SVA based testbench

Current status

Design features

For detailed information on EDN design features, please see the EDN HWIP technical specification.

Testbench architecture

EDN testbench has been constructed based on the CIP testbench architecture.

Block diagram

Top level testbench

Top level testbench is located at hw/ip/edn/dv/tb.sv. It instantiates the EDN DUT module hw/ip/edn/rtl/edn.sv. In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db:

Common DV utility components

The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

Global types & methods

All common types and methods defined at the package level can be found in edn_env_pkg. Some of them in use are:

parameter uint MIN_NUM_ENDPOINTS = 1;
parameter uint MAX_NUM_ENDPOINTS = 7;

TL_agent

EDN testbench instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into EDN device.

Endpoint_agent

EDN testbench instantiates this push_pull_agent(/hw/dv/sv/push_pull_agent/doc/) which models an endpoint module.

Csrng_agent

EDN testbench instantiates this agent(/hw/dv/sv/csrng_agent/doc/) which models the csrng module.

UVM RAL Model

The EDN RAL model is created with the ralgen FuseSoC generator script automatically when the simulation is at the build stage.

It can be created manually by invoking regtool:

Stimulus strategy

Test sequences

All test sequences reside in hw/ip/edn/dv/env/seq_lib. The edn_base_vseq virtual sequence is extended from cip_base_vseq and serves as a starting point. All test sequences are extended from edn_base_vseq. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. Some of the most commonly used tasks / functions are as follows:

edn_init: Initialize the EDN module from the randomized environment variables in the config.

Functional coverage

To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:

common covergroup for interrupts hw/dv/sv/cip_lib/cip_base_env_cov.sv: Cover interrupt value, interrupt enable, intr_test, interrupt pin

Self-checking strategy

Scoreboard

The edn_scoreboard is primarily used for end to end checking. It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:

tl_a_chan_fifo, tl_d_chan_fifo: These 2 fifos provide transaction items at the end of Tilelink address channel and data channel respectively

Assertions

TLUL assertions: The tb/edn_bind.sv binds the tlul_assert assertions to the IP to ensure TileLink interface protocol compliance.
Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.

Building and running tests

We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:

$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/edn/dv/edn_sim_cfg.hjson -i edn_smoke

Testplan

Testpoints

Milestone	Name	Tests	Description
V1	smoke	edn_smoke	Verify send instantiate/generate command Verify single endpoint requests Verify endpoint data = genbits data
V1	csr_hw_reset	edn_csr_hw_reset	Verify the reset values as indicated in the RAL specification. Write all CSRs with a random value. Apply reset to the DUT as well as the RAL model. Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.
V1	csr_rw	edn_csr_rw	Verify accessibility of CSRs as indicated in the RAL specification. Loop through each CSR to write it with a random value. Read the CSR back and check for correctness while adhering to its access policies. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.
V1	csr_bit_bash	edn_csr_bit_bash	Verify no aliasing within individual bits of a CSR. Walk a 1 through each CSR by flipping 1 bit at a time. Read the CSR back and check for correctness while adhering to its access policies. This verify that writing a specific bit within the CSR did not affect any of the other bits. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.
V1	csr_aliasing	edn_csr_aliasing	Verify no aliasing within the CSR address space. Loop through each CSR to write it with a random value Shuffle and read ALL CSRs back. All CSRs except for the one that was written in this iteration should read back the previous value. The CSR that was written in this iteration is checked for correctness while adhering to its access policies. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	Verify random reset during CSR/memory access. Run csr_rw sequence to randomly access CSRs If memory exists, run mem_partial_access in parallel with csr_rw Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value It is mandatory to run this test for all available interfaces the CSRs are accessible from.
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw edn_csr_aliasing	Verify regwen CSR and its corresponding lockable CSRs. Randomly access all CSRs Test when regwen CSR is set, its corresponding lockable CSRs become read-only registers Note: If regwen CSR is HW read-only, this feature can be fully tested by common CSR tests - csr_rw and csr_aliasing. If regwen CSR is HW updated, a separate test should be created to test it. This is only applicable if the block contains regwen and locakable CSRs.
V2	firmware	edn_genbits	Verify SW_CMD_REQ/SW_CMD_STS registers/bits behave as predicted. Verify software mode behaves as predicted. Verify INSTANTIATE/GENERATE software cmds. Verify cmd_fifo_reset bit causes fifos to reset.
V2	csrng_commands	edn_genbits	Verify when no/some/all endpoints requesting (test arbiter). Verify boot request mode behaves as predicted. Verify BOOT_INS_CMD/BOOT_GEN_CMD registers. Verify auto request mode behaves as predicted. Verify RESEED_CMD/GENERATE_CMD/MAX_NUM_REQS_BETWEEN_RESEEDS registers. Verify SUM_STS register bits behave as predicted. Verify all csrng commands (clen = 0-12, sw_mode, boot/auto_req_mode). Verify with ready randomly asserting/deasserting
V2	genbits	edn_genbits	Verify genbits input is transferred to endpoint(s) as predicted. Verify fips bit(s) are properly transferred to endpoint.
V2	interrupts	edn_intr	Verify intr_edn_cmd_req_done interrupt asserts/clears as predicted. Verify intr_edn_fatal_err interrupt asserts/clears as predicted.
V2	alerts	edn_alert	Verify recov_alert_sts asserts/clears as predicted.
V2	errs	edn_err	Verify ERR_CODE asserts as predicted. Verify ERR_CODE all reg bits via ERR_CODE_TEST.
V2	stress_all	edn_stress_all	Combine the other individual testpoints while injecting TL errors and running CSR tests in parallel.
V2	intr_test	edn_intr_test	Verify common intr_test CSRs that allows SW to mock-inject interrupts. Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s). Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s). Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR. Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set. Clear a random set of interrupts by writing a randomly value to intr_state CSR(s). Repeat the above steps a bunch of times.
V2	alert_test	edn_alert_test	Verify common `alert_test` CSR that allows SW to mock-inject alert requests. Enable a random set of alert requests by writing random value to alert_test CSR. Check each `alert_tx.alert_p` pin to verify that only the requested alerts are triggered. During alert_handshakes, write `alert_test` CSR again to verify that: If `alert_test` writes to current ongoing alert handshake, the `alert_test` request will be ignored. If `alert_test` writes to current idle alert handshake, a new alert_handshake should be triggered. Wait for the alert handshakes to finish and verify `alert_tx.alert_p` pins all sets back to 0. Repeat the above steps a bunch of times.
V2	tl_d_oob_addr_access	edn_tl_errors	Access out of bounds address and verify correctness of response / behavior
V2	tl_d_illegal_access	edn_tl_errors	Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the [TLUL spec]({{< relref "hw/ip/tlul/doc/_index.md#explicit-error-cases" >}}) TL-UL protocol error cases invalid opcode some mask bits not set when opcode is `PutFullData` mask does not match the transfer size, e.g. `a_address = 0x00`, `a_size = 0`, `a_mask = 'b0010` mask and address misaligned, e.g. `a_address = 0x01`, `a_mask = 'b0001` address and size aren't aligned, e.g. `a_address = 0x01`, `a_size != 0` size is greater than 2 OpenTitan defined error cases access unmapped address, expect `d_error = 1` when `devmode_i == 1` write a CSR with unaligned address, e.g. `a_address[1:0] != 0` write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte write a memory with `a_mask != '1` when it doesn't support partial accesses read a WO (write-only) memory write a RO (read-only) memory write with `instr_type = True`
V2	tl_d_outstanding_access	edn_csr_hw_reset edn_csr_rw edn_csr_aliasing edn_same_csr_outstanding	Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.
V2	tl_d_partial_access	edn_csr_hw_reset edn_csr_rw edn_csr_aliasing edn_same_csr_outstanding	Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.
V2S	tl_intg_err	edn_tl_intg_err edn_sec_cm	Verify that the data integrity check violation generates an alert. Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert. Inject a fault at the onehot check in `u_reg.u_prim_reg_we_check` and verify the corresponding fatal alert occurs
V2S	sec_cm_config_regwen		Verify the countermeasure(s) CONFIG.REGWEN.
V2S	sec_cm_config_mubi		Verify the countermeasure(s) CONFIG.MUBI.
V2S	sec_cm_main_sm_fsm_sparse		Verify the countermeasure(s) MAIN_SM.FSM.SPARSE.
V2S	sec_cm_ack_sm_fsm_sparse		Verify the countermeasure(s) ACK_SM.FSM.SPARSE.
V2S	sec_cm_ctr_redun		Verify the countermeasure(s) CTR.REDUN.
V2S	sec_cm_main_sm_ctr_local_esc		Verify the countermeasure(s) MAIN_SM.CTR.LOCAL_ESC.
V2S	sec_cm_cs_rdata_bus_consistency		Verify the countermeasure(s) CS_RDATA.BUS.CONSISTENCY.
V2S	sec_cm_tile_link_bus_integrity		Verify the countermeasure(s) TILE_LINK.BUS.INTEGRITY.
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.

Covergroups

Name	Description
cs_cmds_cg	Covers the following: csrng_commands vs clen, flags, glen sw, auto_req_mode commands (boot_req_mode cmds have no additional data) ready deasserts during command Crosses between above coverpoints
edn_cfg_cg	Covers that all edn configuration options have been tested. Individual config settings that will be covered include: boot_req_mode auto_req_mode sw_mode (neither boot_req_mode/auto_req_mode) num_endpoints num_boot_reqs Cross between num_endpoints and mode.
edn_endpoints_cg	Covers none/some/all endpoints requesting
err_test_cg	Covers that all fatal errors, all fifo errors and all error codes of edn have been tested. Individual config settings that will be covered include: which_fatal_err (0 to 4), 5 possible fatal errors including rescmd, gencmd fifo error, ack_sm_err, main_sm_err and cntr_err which_fifo (0 to 1), 2 differnt fifos, rescmd fifo and gencmd fifo which_err_code (0 to 15), 8 ERR_CODE errors, plus 8 ERR_CODE_TEST bits test which_fifo_err (0 to 2), fifo write/read/state errors which_invalid_mubi (0 to 3), 4 possible invalid mubi4 value fields
regwen_val_when_new_value_written_cg	Cover each lockable reg field with these 2 cases: When regwen = 1, a different value is written to the lockable CSR field, and a read occurs after that. When regwen = 0, a different value is written to the lockable CSR field, and a read occurs after that. This is only applicable if the block contains regwen and locakable CSRs.
tl_errors_cg	Cover the following error cases on TL-UL bus: TL-UL protocol error cases. OpenTitan defined error cases, refer to testpoint `tl_d_illegal_access`.
tl_intg_err_cg	Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check. Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.