EDN DV document
- Verify all EDN IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the DV plan below towards closing code and functional coverage on the IP and all of its sub-modules
- Verify TileLink device protocol compliance with an SVA based testbench
For detailed information on EDN design features, please see the EDN HWIP technical specification.
EDN testbench has been constructed based on the CIP testbench architecture.
Top level testbench
Top level testbench is located at
hw/ip/edn/dv/tb.sv. It instantiates the EDN DUT module
In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into
- Clock and reset interface
- TileLink host interface
- EDN IOs
- Interrupts (
- Alerts (
- Devmode (
Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
Global types & methods
All common types and methods defined at the package level can be found in
edn_env_pkg. Some of them in use are:
### TL_agent EDN testbench instantiates (already handled in CIP base env) [tl_agent]() which provides the ability to drive and independently monitor random traffic via TL host interface into EDN device. ### Endpoint_agent EDN testbench instantiates this push_pull_agent() which models an endpoint module. ### Csrng_agent EDN testbench instantiates this agent() which models the csrng module. ### UVM RAL Model The EDN RAL model is created with the [`ralgen`]() FuseSoC generator script automatically when the simulation is at the build stage. It can be created manually by invoking [`regtool`](): ### Stimulus strategy #### Test sequences All test sequences reside in `hw/ip/edn/dv/env/seq_lib`. The `edn_base_vseq` virtual sequence is extended from `cip_base_vseq` and serves as a starting point. All test sequences are extended from `edn_base_vseq`. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. Some of the most commonly used tasks / functions are as follows: * edn_init: Initialize the EDN module from the randomized environment variables in the config. #### Functional coverage To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met: * common covergroup for interrupts `hw/dv/sv/cip_lib/cip_base_env_cov.sv`: Cover interrupt value, interrupt enable, intr_test, interrupt pin ### Self-checking strategy #### Scoreboard The `edn_scoreboard` is primarily used for end to end checking. It creates the following analysis ports to retrieve the data monitored by corresponding interface agents: * tl_a_chan_fifo, tl_d_chan_fifo: These 2 fifos provide transaction items at the end of Tilelink address channel and data channel respectively <!-- * analysis port1: * analysis port2: explain inputs monitored, flow of data and outputs checked --> #### Assertions * TLUL assertions: The `tb/edn_bind.sv` binds the `tlul_assert` [assertions]() to the IP to ensure TileLink interface protocol compliance. * Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset. ## Building and running tests We are using our in-house developed [regression tool]() for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here's how to run a smoke test: ```console $ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/edn/dv/edn_sim_cfg.hjson -i edn_smoke
Enable edn, let edn boot mode generate csrng instantiate/generate commands, endpoint requests genbits, compare csrng/endpoint genbits.
Verify the reset values as indicated in the RAL specification.
Verify accessibility of CSRs as indicated in the RAL specification.
Verify no aliasing within individual bits of a CSR.
Verify no aliasing within the CSR address space.
Verify random reset during CSR/memory access.
Verify SW_CMD_REQ/SW_CMD_STS registers/bits behave as predicted. Verify RESEED/GENERATE software cmds work with 0 and 12 32-bit words of additional data. Verify cmd_fifo_reset bit causes fifos to reset. Verify boot_req_dis bit disables boot_req mode. Verify registers at End-Of-Test.
Verify endpoint agent reqs generate csrng commands for both fifo full/empty conditions. Verify when no/some/all endpoints requesting (test arbiter). Verify auto-request mode (RESEED_CMD/GENERATE_CMD registers) behaves as predicted. Verify max_num_reqs_between_reseeds in auto-generate mode. Verify boot-time request mode behaves as predicted. Verify SUM_STS register bits behave as predicted.
Verify genbits input is transferred to endpoint(s) as predicted. Verify fips bit(s) are properly transferred to endpoint.
Verify intr_edn_cmd_req_done interrupt asserts/clears as predicted. Verify intr_edn_fatal_err interrupt asserts/clears as predicted. Verify ERR_CODE all reg bits via ERR_CODE_TEST.
Combine the other individual testpoints while injecting TL errors and running CSR tests in parallel.
Verify common intr_test CSRs that allows SW to mock-inject interrupts.
Access out of bounds address and verify correctness of response / behavior
Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested
Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.
Access CSR with one or more bytes of data For read, expect to return all word value of the CSR For write, enabling bytes should cover all CSR valid fields
This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.