EDN DV document
Goals
- DV
- Verify all EDN IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
- FPV
- Verify TileLink device protocol compliance with an SVA based testbench
Current status
Design features
For detailed information on EDN design features, please see the EDN HWIP technical specification.
Testbench architecture
EDN testbench has been constructed based on the CIP testbench architecture.
Block diagram
Top level testbench
Top level testbench is located at hw/ip/edn/dv/tb.sv
. It instantiates the EDN DUT module hw/ip/edn/rtl/edn.sv
.
In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db
:
- Clock and reset interface
- TileLink host interface
- EDN IOs
- Interrupts (
pins_if
- Alerts (
pins_if
- Devmode (
pins_if
Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
Global types & methods
All common types and methods defined at the package level can be found in
edn_env_pkg
. Some of them in use are:
parameter uint MIN_NUM_ENDPOINTS = 1;
parameter uint MAX_NUM_ENDPOINTS = 7;
TL_agent
EDN testbench instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into EDN device.
Endpoint_agent
EDN testbench instantiates this push_pull_agent(/hw/dv/sv/push_pull_agent/doc/) which models an endpoint module.
Csrng_agent
EDN testbench instantiates this agent(/hw/dv/sv/csrng_agent/doc/) which models the csrng module.
UVM RAL Model
The EDN RAL model is created with the ralgen
FuseSoC generator script automatically when the simulation is at the build stage.
It can be created manually by invoking regtool
:
Stimulus strategy
Test sequences
All test sequences reside in hw/ip/edn/dv/env/seq_lib
.
The edn_base_vseq
virtual sequence is extended from cip_base_vseq
and serves as a starting point.
All test sequences are extended from edn_base_vseq
.
It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:
- edn_init: Initialize the EDN module from the randomized environment variables in the config.
Functional coverage
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:
- common covergroup for interrupts
hw/dv/sv/cip_lib/cip_base_env_cov.sv
: Cover interrupt value, interrupt enable, intr_test, interrupt pin
Self-checking strategy
Scoreboard
The edn_scoreboard
is primarily used for end to end checking.
It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:
- tl_a_chan_fifo, tl_d_chan_fifo: These 2 fifos provide transaction items at the end of Tilelink address channel and data channel respectively
Assertions
- TLUL assertions: The
tb/edn_bind.sv
binds thetlul_assert
assertions to the IP to ensure TileLink interface protocol compliance. - Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
Building and running tests
We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:
$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/edn/dv/edn_sim_cfg.hjson -i edn_smoke
Testplan
Testpoints
Milestone | Name | Tests | Description |
---|---|---|---|
V1 | smoke | edn_smoke | Verify send instantiate/generate command Verify single endpoint requests Verify endpoint data = genbits data |
V1 | csr_hw_reset | edn_csr_hw_reset | Verify the reset values as indicated in the RAL specification.
|
V1 | csr_rw | edn_csr_rw | Verify accessibility of CSRs as indicated in the RAL specification.
|
V1 | csr_bit_bash | edn_csr_bit_bash | Verify no aliasing within individual bits of a CSR.
|
V1 | csr_aliasing | edn_csr_aliasing | Verify no aliasing within the CSR address space.
|
V1 | csr_mem_rw_with_rand_reset | edn_csr_mem_rw_with_rand_reset | Verify random reset during CSR/memory access.
|
V1 | regwen_csr_and_corresponding_lockable_csr | edn_csr_rw edn_csr_aliasing | Verify regwen CSR and its corresponding lockable CSRs.
Note:
This is only applicable if the block contains regwen and locakable CSRs. |
V2 | firmware | edn_genbits | Verify SW_CMD_REQ/SW_CMD_STS registers/bits behave as predicted. Verify software mode behaves as predicted. Verify INSTANTIATE/GENERATE software cmds. Verify cmd_fifo_reset bit causes fifos to reset. |
V2 | csrng_commands | edn_genbits | Verify when no/some/all endpoints requesting (test arbiter). Verify boot request mode behaves as predicted. Verify BOOT_INS_CMD/BOOT_GEN_CMD registers. Verify auto request mode behaves as predicted. Verify RESEED_CMD/GENERATE_CMD/MAX_NUM_REQS_BETWEEN_RESEEDS registers. Verify SUM_STS register bits behave as predicted. Verify all csrng commands (clen = 0-12, sw_mode, boot/auto_req_mode). Verify with ready randomly asserting/deasserting |
V2 | genbits | edn_genbits | Verify genbits input is transferred to endpoint(s) as predicted. Verify fips bit(s) are properly transferred to endpoint. |
V2 | interrupts | edn_intr | Verify intr_edn_cmd_req_done interrupt asserts/clears as predicted. Verify intr_edn_fatal_err interrupt asserts/clears as predicted. |
V2 | alerts | edn_alert | Verify recov_alert_sts asserts/clears as predicted. |
V2 | errs | edn_err | Verify ERR_CODE asserts as predicted. Verify ERR_CODE all reg bits via ERR_CODE_TEST. |
V2 | stress_all | edn_stress_all | Combine the other individual testpoints while injecting TL errors and running CSR tests in parallel. |
V2 | intr_test | edn_intr_test | Verify common intr_test CSRs that allows SW to mock-inject interrupts.
|
V2 | alert_test | edn_alert_test | Verify common
|
V2 | tl_d_oob_addr_access | edn_tl_errors | Access out of bounds address and verify correctness of response / behavior |
V2 | tl_d_illegal_access | edn_tl_errors | Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the [TLUL spec]({{< relref "hw/ip/tlul/doc/_index.md#explicit-error-cases" >}})
|
V2 | tl_d_outstanding_access | edn_csr_hw_reset edn_csr_rw edn_csr_aliasing edn_same_csr_outstanding | Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address. |
V2 | tl_d_partial_access | edn_csr_hw_reset edn_csr_rw edn_csr_aliasing edn_same_csr_outstanding | Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields. |
V2S | tl_intg_err | edn_tl_intg_err edn_sec_cm | Verify that the data integrity check violation generates an alert.
|
V2S | sec_cm_config_regwen | Verify the countermeasure(s) CONFIG.REGWEN. | |
V2S | sec_cm_config_mubi | Verify the countermeasure(s) CONFIG.MUBI. | |
V2S | sec_cm_main_sm_fsm_sparse | Verify the countermeasure(s) MAIN_SM.FSM.SPARSE. | |
V2S | sec_cm_ack_sm_fsm_sparse | Verify the countermeasure(s) ACK_SM.FSM.SPARSE. | |
V2S | sec_cm_ctr_redun | Verify the countermeasure(s) CTR.REDUN. | |
V2S | sec_cm_main_sm_ctr_local_esc | Verify the countermeasure(s) MAIN_SM.CTR.LOCAL_ESC. | |
V2S | sec_cm_cs_rdata_bus_consistency | Verify the countermeasure(s) CS_RDATA.BUS.CONSISTENCY. | |
V2S | sec_cm_tile_link_bus_integrity | Verify the countermeasure(s) TILE_LINK.BUS.INTEGRITY. | |
V3 | stress_all_with_rand_reset | edn_stress_all_with_rand_reset | This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers. |
Covergroups
Name | Description |
---|---|
cs_cmds_cg | Covers the following:
|
edn_cfg_cg | Covers that all edn configuration options have been tested. Individual config settings that will be covered include:
|
edn_endpoints_cg | Covers none/some/all endpoints requesting |
err_test_cg | Covers that all fatal errors, all fifo errors and all error codes of edn have been tested. Individual config settings that will be covered include:
|
regwen_val_when_new_value_written_cg | Cover each lockable reg field with these 2 cases:
This is only applicable if the block contains regwen and locakable CSRs. |
tl_errors_cg | Cover the following error cases on TL-UL bus:
|
tl_intg_err_cg | Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check. Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied. |