ENTROPY_SRC HWIP Technical Specification
Overview
This document specifies ENTROPY_SRC hardware IP functionality. This module conforms to the Comportable guideline for peripheral functionality.
Features
- This revision provides an interface to an external physical random noise generator (also referred to as a physical true random number generator or PTRNG) source, and an LFSR (linear feedback shift register) digital source. The LFSR is used as a digital, pseudo-random type of entropy source, while the PTRNG external source is a physical true random noise source. A noise source and its relation to an entropy source are defined by SP 800-90B.
- A set of registers is provided for firmware to obtain entropy bits.
- The set of registers is designed such that firmware can select between an LFSR or a PTRNG noise source.
- Interrupts are supported:
- Entropy bits are available for firmware consumption.
- The internal health tests have detected a test failure.
- An internal FIFO error has occurred.
- Two health checks that are defined by SP 800-90B are performed by this revision: Repetition Count and Adaptive Proportion tests.
- Two additional hardware health checks are performed by this revision: Bucket and Markov tests.
- Firmware-defined (mailbox-based) and vendor-defined health checks are also supported.
- A health check failure alert is supported by this revision.
Description
This IP block provides an entropy source that is capable of using a PTRNG noise source to generate random values in a manner that is compliant both with FIPS (though NIST SP 800-90B) and CC (AIS31) recommendations.
The random values generated by this block serve as non-deterministic seeds for the CSRNG block. The outputs of the CSRNG are then used either directly by firmware or are distributed to other hardware blocks through the Entropy Distribution Network.
In the terms of AIS31 classes, this block is meant to satisfy the requirements for a PTG.2 class physical entropy source, with “internal” entropy (an AIS31 term, meaning the min-entropy as measured just before the output pins) exceeding 0.997 entropy-bits/output-bit. In NIST terms, this block satisfies the requirements for a “full-entropy” source, which requires even smaller deviations from ideal entropy, at the level of less than one part in 264. When operating in full-compliance mode, raw outputs from a PTRNG noise source (external to this block) are passed through a conditioning function based on a suitable secure hash function (SHA-2 or SHA-3) which has been vetted by NIST to meet these stringent requirements.
These raw noise bits are subjected to a sequence of health-checks to screen the raw signals for statistical defects which would cause any significant deviations from ideal entropy at the output of the conditioning block. These tests include:
- The Repetition Count test, which screens for stuck-bits, or a complete failure of the PTRNG noise source,
- The Adaptive Proportion test, which screens for statistical bias in the number of 1’s or 0’s output by the noise source,
- The “Bucket Test”, which looks for correlations between the individual noise channels that the external noise source concatenates together to produce the raw noise sequence,
- The “Markov Test”, which looks for unexpected first-order temporal correlations between bits output by the individual noise channels,
- The “Mailbox Test”, in which raw-noise data is transferred to firmware in contiguous 2kbit-blocks, so that firmware can perform custom tests, and signal a failure through the same path as the other tests, and
- Optional Vendor Specific tests, which allow silicon creators to extend the health checks by adding a top-level block external to this IP.
The Repetition Count and Adaptive Proportion test are specifically recommended by SP 800-90B, and are implemented in accordance with those recommendations. In FIPS/CC-compliance mode, all checks except the Repetition Count test are performed on fixed window of data, typically consisting of 1024 bits each. Per the definition in SP 800-90B, the Repetition Count test does not operate on a fixed window. The repetition count test fails if any sequence of bits continuously asserts the same value for too many samples, as determined by the programmable threshold, regardless of whether that sequence crosses any window boundaries. The thresholds for these tests should be chosen to achieve a low false-positive rate (α) given a conservative estimate of the manufacturing tolerances of the PTRNG noise source. The combined choice of threshold and window size then determine the false-negative rate (β), or the probability of missing statistical defects at any particular magnitude.
When the IP is disabled by clearing the ENABLE
bit in CONF, all heath checks are disabled and all counters internal to the health checks are reset.
In order to compensate for the fact our tests (like all realistic statistical tests) have finite resolution for detecting defects, we conservatively use 1024 bits of PTRNG noise source to construct each 384 bit conditioned entropy sample. When passed through the conditioning block, the resultant entropy stream will be full entropy unless the PTRNG noise source has encountered some statistical defect serious enough to reduce the raw min-entropy to a level below 0.375 bits of entropy per output bit. We choose this level as our definition of “non-tolerable statistical defects” for the purposes of evaluating this system under AIS31. Given this definition of “non-tolerable defects”, the health-checks as implemented for this block will almost certainly detect any of the previously mentioned defects in a single iteration of the health checks (i.e. such serious defects will be detected with very low β).
In addition to the brief, low-latency health checks, various long-term statistics are accumulated in registers for additional diagnostic purposes or for in-depth analysis. For the hardware interface, entropy bits will be transferred whenever the downstream consumer is ready to receive them.
At a high-level, this ENTROPY_SRC block, when enabled, will continuously collect entropy bits from the entropy source into a FIFO that can be read from the TL-UL bus, or sent out through a hardware interface. The PTRNG noise source will generate a relatively slow set of bit streams, with a total bit rate on the order of 50 kbps. The digital source can be programmed to be faster, or much slower if desired. A digital source rate of flexible speed might be useful in demonstrating how the downstream applications use the entropy.
Once a noise source has been selected through configuration, the raw noise data processing begins. This ENTROPY_SRC block will do health checks, collect and pack bits, and finally send them through a conditioning unit. There are two modes in which entropy bits are delivered, boot-time and FIPS/CC mode. Boot-time mode will deliver bits sooner for specific on-boot obfuscation applications, though the bits may not yet have been subjected to the same level of startup health checks required for FIPS or CC compliance.
In boot-time mode health checks only operate on a window of 384 bits. The boot-time health checks are the same as the FIPS/CC health-checks, though with different thresholds. They are sensitive to the same types of statistical defects, though at reduced statistical resolution. With suitable thresholds, the boot-time health checks can be operate both with low false-alarm rates (low α), while still confirming with low β that the total entropy of the first seed contains at least 80 bits of total entropy. During start up the initial 384 bits are held in a buffer until the boot-time start-up health checks are performed. Storing the seed in this buffer, allows this seed to released to the CSRNG immediately after the entropy has been confirmed.
Boot-time mode also has the feature that it bypasses the SHA conditioning function, as only 384 bits are used in the initial boot-time seed.
For maximal flexibility in normal operation, the conditioning function can also be implemented by firmware. When this firmware conditioning feature is activated, data read directly out of the noise source can be reinjected into the entropy pipeline via a TL-UL register after it has been processed by firmware. It should be noted that this firmware algorithm must be vetted by NIST to satisfy the requirements for a full-entropy source. This feature can also be disabled for security purposes, either by locking the feature via the REGEN register at boot, or by a write to one-time programmable (OTP) memory.
Compatibility
This IP block does not have any direct hardware compatibility requirements. However, the general design of this block follows the overall NIST recommendations, as described by SP 800-90B.
Theory of Operations
As already described, this IP block will collect bits of entropy for firmware or hardware consumption. This revision supports both an LFSR for the pseudo-random digital implementation, and an external interface for the PTRNG noise source implementation.
The first step is initialization and enabling.
Normally PTRNG noise source mode is selected, and the ENABLE
field will be set to enable PTRNG noise source mode.
If using LFSR mode, before setting the ENABLE
field, the LFSR seed input should be initialized, using the SEED register.
The ENTROPY_RATE register will default to a sample rate of 20 microseconds, assuming a system clock rate of 100 nanoseconds.
The SEED register will transfer its value to the LFSR block, but the LFSR block is locked once the ENABLE
field is set.
After the block is enabled and initialized, entropy bits will be collected up indefinitely until disabled.
After a reset, the ENTROPY_SRC block will start up in boot-time mode by default. This feature is designed to provide an initial seed’s worth of entropy with lower latency than the normal FIPS/CC compliant health check process. Health testing will still be performed on boot-time mode entropy, but the window of checking is, by default, 384 bits instead of 1024 bits. When entropy is delivered to the downstream hardware block, a signal will indicate what type of entropy it is - FIPS compliant or not. Boot-time mode can be completely disabled in the CONF register.
Once the initial boot-time mode phase has completed, the ENTROPY_SRC block will switch to FIPS compliant mode. In this mode, once the raw entropy has been health checked, it will be passed into a conditioner block. This block will compress the bits such that the entropy bits/physical bits, or min-entropy value, should be improved over the raw data source min-entropy value. The compression operation, by default, will compress every 1024 tested bits into 384 full-entropy bits.
The hardware conditioning can also be bypassed and replaced in normal operation with a firmware-defined conditioning algorithm. This firmware conditioning algorithm, can be disabled on boot for security purposes. The exact mechanism for this functionality will be described in a future update to this document (TBD).
Health checks are performed on the input raw data from the PTRNG noise source when in that mode. There are four health tests that will be performed: repetitive count, adaptive proportion, bucket, and Markov tests. Each test has a pair of threshold values that determine that pass/fail of the test, one threshold for boot-time mode, and one for normal mode. By default, all tests are enabled, but can be turn off in the CONF register. Because of the variability of the PTRNG noise source, there are several registers that log statistics associated with the health tests. For example, the adaptive proportion test has a high watermark register that logs the highest measured number of ones. The ADAPTP_HI_WATERMARKS register has an entry for both normal and boot-time modes. This register allows for determining how close the threshold value should be set to the fail over value. Specific to the adaptive proportion test, there is also the ADAPTP_LO_WATERMARKS register, which will hold the lowest number of ones measured. To help understand how well the thresholds work through time, a running count of test fails is kept in the ADAPTP_HI_TOTAL_FAILS register. The above example for the adaptive proportion test also applies to the other health tests, with the exception of the low watermark registers. See the timing diagrams below for more details on how the health tests work. It should be noted that for all error counter registers, they are sized for 16 bits, which prevents any case where counters might wrap.
The firmware override function has the capability to completely override the hardware health tests and the conditioner paths. In the case of health tests, firwmare can turn off one or all of the health tests and perform the tests in firmware. A data path is provided in the hardware such that the inbound entropy can be trapped in the pre-conditioner FIFO. Once a pre-determined threshold of entropy has been reached in this FIFO, the firmware can then read the entropy bits out of the FIFO. At this point, firmware can do additional health checks on the entropy. Optionally, firmware can do the conditioning function, assuming the the hardware is configured to bypass the conditioner block. Once firmware has processed the entropy, it will write the entropy back into the pre-conditioner FIFO. The firmware override control bits will be set such that the new entropy will resume normal flow operation.
Vendor-specific tests are supported through an external health test interface (xht). This is the same interface that is used for the internal health tests. Below is a description of this interface:
- entropy_bit: 4-bit wide bus of entropy to be tested.
- entropy_bit_valid: indication of when the entropy is valid.
- clear: signal to clear counters, and is register driven.
- active: signal to indicate when the test should run, and is register driven.
- thresh_hi: field to indicate what high threshold the test should use, and is register driven.
- thresh_lo: field to indicate what low threshold the test should use, and is register driven.
- window: field to indicate what the size of the test window is, and is register driven.
- test_cnt: generic test count result, to be read from a register.
- test_fail_hi_pulse: indication that a high threshold comparison failed, to be read from a register.
- test_fail_lo_pulse: indication that a low threshold comparison failed, to be read from a register.
The ALERT_THRESHOLD register determines how many fails can occur before an alert is issued. By default, the current threshold is set to two, such that the occurrence of two failing test cycles back-to-back would provide a very low α value. The ALERT_FAIL_COUNTS register holds the total number of fails, plus all of the individual contributing failing tests. Setting the ALERT_THRESHOLD register to zero will disable alert generation.
Firmware has a path to read entropy from the ENTROPY_SRC block.
The ENTROPY_CONTROL register allows firmware to set the internal multiplexers to steer entropy data to the ENTROPY_DATA register.
The control bit ES_TYPE
sets whether the entropy will come from the conditioning block or be sourced through the bypass path.
A status bit will be set that can either be polled or generate an interrupt when the entropy bits are available to be read from the ENTROPY_DATA register.
The firmware needs to read the ENTROPY_DATA register twelve times in order to cleanly evacuate the 384-bit seed from the hardware path (12*32bits=384bits total).
The firmware will directly read out of the main entropy FIFO, and when the control bit ES_ROUTE
is set, no entropy is being passed to the block hardware interface.
If the main entropy FIFO fills up, additional entropy that has been health checked and conditioned will be dropped at that point.
The above process will be repeated for as long as entropy bits are to be collected and processed.
At any time, the ENABLE
field can be cleared to halt the entropy generation (and health check testing) immediately.
Block Diagram
Hardware Interfaces
Referring to the
Comportable guideline for peripheral device functionality,
the module entropy_src
has
the following hardware interfaces defined.
Primary Clock: clk_i
Other Clocks: none
Bus Device Interface: tlul
Bus Host Interface: none
Peripheral Pins for Chip IO: none
Interrupts:
Interrupt Name | Description |
---|---|
es_entropy_valid | Asserted when entropy source bits are available. |
es_health_test_failed | Asserted when the alert count has been met. |
es_fatal_err | Asserted when a FIFO error occurs, or if an illegal state machine state is reached. |
Security Alerts:
Alert Name | Description |
---|---|
recov_alert | This alert is triggered upon the alert health test threshold criteria not met. |
fatal_alert | This alert triggers if an illegal state machine state is reached. |
Design Details
Initialization
After power-up, the ENTROPY_SRC block is disabled. In this state, the seed register will continuously be loaded into the LFSR. The seed register can be written without restriction, regardless of any state of any control bits.
For simplicity of initialization, only a single register write is needed to start functional operation of the ENTROPY_SRC block. This assumes that proper defaults are chosen for thresholds, sampling rate, and other registers.
For security reasons, a configuration and control register locking function is performed by the REGEN register. Clearing the bit in this register will prevent future modification of the CONF register or other writeable registers by firmware.
Entropy Processing
When enabled, the ENTROPY_SRC block will generate entropy bits continuously.
The es_entropy_valid
bit in the ENTROPY_SRC_INTR_STATE
register will indicate to the firmware when entropy bits can read from the ENTROPY_DATA register.
The firmware will do 32-bit register reads of the ENTROPY_DATA register to retrieve the entropy bits.
Each read will automatically pop an entry from the entropy unpacker block.
A full twelve 32-bit words need to be read at a time.
The hardware entropy interface will move entropy bits out of the ENTROPY FIFO when it is not empty, and the downstream hardware is ready. If firmware is not currently reading entropy bits, all processed entropy bits will flow to the hardware entropy interface.
An additional feature is the RATE register. The purpose of this register is to simulate faster or slower entropy generation sources than when the digital source is selected. This will aid firmware design and debug when trying to handle all entropy source types and rates. When in PTRNG mode, this register must exactly match the sample rate required by the PTRNG source, expected to be in the range of about 25 to 50 kilohertz.
Interrupts
The ENTROPY_SRC module has several interrupts: es_entropy_valid
, es_health_test_failed
, and es_fifo_err
.
The es_entropy_valid
interrupt should be asserted when an entropy source has been implemented that is relatively slow.
The es_health_test_failed
interrupt will trigger when the internal health test fails and exceeds the alert threshold.
The es_fifo_err
interrupt will fire when an internal FIFO has a malfunction.
The conditions that cause this to happen are either when there is a push to a full FIFO or a pull from an empty FIFO.
Future Features
- Timer to pace health checks only when there is no demand for entropy seeds
- One-way threshold values if regen register cannot be used
- Support for golden test pattern
Entropy Source Hardware Interface
The following waveform shows an example of how the entropy source hardware interface works, which is much like a FIFO.
PTRNG Hardware Interface
The following waveform shows an example of what the PTRNG timing looks like.
Repetition Count Test
The following waveform shows how a sampling of the LFSR data pattern will be tested by the Repetition Count test. Operating on each bit stream, this test will count when a signal is at a stuck level. This NIST test is intended to signal a catastrophic failure with the PTRNG noise source.
Adaptive Proportion Test
The following waveform shows how a sampling of the LFSR data pattern will be tested by the Adaptive Proportion test. Operating on all four bit streams, this test will count how many ones are present in the full sample period. This NIST test is intended to find bias when either too many or too few ones are present.
Bucket Test
The following waveform shows how a sampling of the LFSR data pattern will be tested by the Bucket test. Operating on all four bit streams, this test will identify the symbol and sort it into bin counters, or “buckets”. This test is intended to find bias with a symbol or symbols.
Markov Test
The following waveform shows how a sampling of the LFSR data pattern will be tested by the Markov test.
Operating on all four bit streams, this test will identify pairs of transitions in time per bit stream.
Specifically, only pairs of 0b01
and 0b10
will be counted.
Programmers Guide
Initialization
The following code snippet demonstrates initializing the ENTROPY_SRC block for entropy bit generation.
void entropy_src_init(unsigned int rate) {
// set the rate value (optional)
*SEED_REG = rate;
// set the configuration enable bits (rng mode, all health tests enabled)
*CONF_REG = 0x1;
// the ENTROPY_SRC interrupts can optionally be enabled
}
Entropy Processing
The following code snippet demonstrates reading entropy bits from the ENTROPY_SRC block.
int entropy_src_entropy(unsigned int numEntropyBits) {
// read numEntropyBits, check for ENTROPY_SRC_INTR_STATE bit 0
return *ENTROPY_DATA_REG;
}
Error conditions
Need to alert the system of a FIFO overflow condition.
Register Table
entropy_src.INTR_STATE @ 0x0
Interrupt State Register Reset default = 0x0, mask 0x7
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw1c | 0x0 | es_entropy_valid | Asserted when entropy source bits are available. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw1c | 0x0 | es_health_test_failed | Asserted when the alert count has been met. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw1c | 0x0 | es_fatal_err | Asserted when a FIFO error occurs, or if an illegal state machine state is reached. |
entropy_src.INTR_ENABLE @ 0x4
Interrupt Enable Register Reset default = 0x0, mask 0x7
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x0 | es_entropy_valid | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw | 0x0 | es_health_test_failed | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw | 0x0 | es_fatal_err | Enable interrupt when |
entropy_src.INTR_TEST @ 0x8
Interrupt Test Register Reset default = 0x0, mask 0x7
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | wo | 0x0 | es_entropy_valid | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | wo | 0x0 | es_health_test_failed | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | wo | 0x0 | es_fatal_err | Write 1 to force |
entropy_src.ALERT_TEST @ 0xc
Alert Test Register Reset default = 0x0, mask 0x3
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | wo | 0x0 | recov_alert | Write 1 to trigger one alert event of this kind. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | wo | 0x0 | fatal_alert | Write 1 to trigger one alert event of this kind. |
entropy_src.REGWEN @ 0x10
Register write enable for all control registers Reset default = 0x1, mask 0x1
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw0c | 0x1 | REGWEN | When true, all writeable registers can be modified. When false, they become read-only. Defaults true, write one to clear. Note that this needs to be cleared after initial configuration at boot in order to lock in the listed register settings. |
entropy_src.REV @ 0x14
Revision register Reset default = 0x10303, mask 0xffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:0 | ro | 0x3 | ABI_REVISION | Read of this register shows the ABI of this block. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:8 | ro | 0x3 | HW_REVISION | Read of this register shows the revision of this block. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
23:16 | ro | 0x1 | CHIP_TYPE | Read of this register shows the type of chip using this block. |
entropy_src.CONF @ 0x18
Configuration register Reset default = 0x0, mask 0x1ffb
Register enable = REGWEN
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1:0 | rw | x | ENABLE | This field is the module enable for the ENTROPY_SRC entropy generation function. This two bit field determines what source will be used for all processing: 0b00: Disabled 0b01: PTRNG mode enabled 0b10: LFSR mode enabled 0b11: Reserved | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | rw | x | BOOT_BYPASS_DISABLE | Setting this bit disables the initial generation of non-FIPS entropy. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4 | rw | x | REPCNT_DISABLE | Setting this bit disables the health test called Repetition Count test. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | rw | x | ADAPTP_DISABLE | Setting this bit disables the health test called Adaptive Proportion test. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | rw | x | BUCKET_DISABLE | Setting this bit disables the health test called Bucket test. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | rw | x | MARKOV_DISABLE | Setting this bit disables the health test called Markov test. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | rw | x | HEALTH_TEST_CLR | Setting this bit will clear all registers related to the health test operations. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | rw | x | RNG_BIT_EN | Setting this bit enables the single RNG bit mode, where only one bit is sampled. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11:10 | rw | x | RNG_BIT_SEL | When the above bit iset, this field selects which bit from the RNG bus will be processed when in single RNG bit mode. This two bit field selects the RNG bit stream: 0b00: RNG bit 0 0b01: RNG bit 1 0b10: RNG bit 2 0b11: RNG bit 3 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
12 | rw | x | EXTHT_ENABLE | Setting this bit enables the hardware-based health test that is external to ENTROPY_SRC." |
entropy_src.RATE @ 0x1c
Entropy rate register Reset default = 0x8, mask 0xffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | rw | 0x8 | ENTROPY_RATE | This register determines the rate that entropy bits will be supplied. In LFSR mode, this is the rate that the LFSR value will be advanced. The number in this register represents how many clocks there are between each newLFSR value generation. |
entropy_src.ENTROPY_CONTROL @ 0x20
Entropy control register Reset default = 0x0, mask 0x3
Register enable = REGWEN
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | x | ES_ROUTE | Setting this bit routes the generated entropy value to the ENTROPY_DATA register to be read by firmware. When this bit is zero, the generated entropy will be forwarded out of this module to the hardware interface. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw | x | ES_TYPE | Setting this bit will bypass the conditioning logic and bring raw entropy data to the ENTROPY_DATA register. When zero, FIPS compliant entropy will be brought the ENTROPY_DATA register, after being conditioned. |
entropy_src.ENTROPY_DATA @ 0x24
Entropy data bits Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | ENTROPY_DATA | A read of this register provides generated entropy bits to firmware. |
entropy_src.HEALTH_TEST_WINDOWS @ 0x28
Health test windows register Reset default = 0x600100, mask 0xffffffff
Register enable = REGWEN
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | rw | 0x100 | FIPS_WINDOW | This is the window size for all health tests. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. The default value is (1024 bits * 1 clock/4 bits); | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | rw | 0x60 | BYPASS_WINDOW | This is the window size for all health tests when running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. The default value is (384 bits * 1 clock/4 bits); |
entropy_src.REPCNT_THRESHOLDS @ 0x2c
Repetition count test thresholds register Reset default = 0x200020, mask 0xffffffff
Register enable = REGWEN
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | rw | 0x20 | FIPS_REPCNT_THRESH | This is the threshold size for the repetition count health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. The default value is 32 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | rw | 0x20 | BYPASS_REPCNT_THRESH | This is the threshold size for the repetition count health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. The default value is 32 |
entropy_src.ADAPTP_HI_THRESHOLDS @ 0x30
Adaptive proportion test high thresholds register Reset default = 0xe00256, mask 0xffffffff
Register enable = REGWEN
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | rw | 0x256 | FIPS_ADAPTP_HI_THRESH | This is the threshold size for the adaptive proportion health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. The default value is 598. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | rw | 0xe0 | BYPASS_ADAPTP_HI_THRESH | This is the threshold size for the adaptive proportion health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. The default value is .375 of the FIPS threshold. |
entropy_src.ADAPTP_LO_THRESHOLDS @ 0x34
Adaptive proportion test low thresholds register Reset default = 0xa001aa, mask 0xffffffff
Register enable = REGWEN
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | rw | 0x1aa | FIPS_ADAPTP_LO_THRESH | This is the threshold size for the adaptive proportion health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. The default value is 426. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | rw | 0xa0 | BYPASS_ADAPTP_LO_THRESH | This is the threshold size for the adaptive proportion health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. The default value is .375 of the FIPS threshold. |
entropy_src.BUCKET_THRESHOLDS @ 0x38
Bucket test thresholds register Reset default = 0x200020, mask 0xffffffff
Register enable = REGWEN
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | rw | 0x20 | FIPS_BUCKET_THRESH | This is the threshold size for the bucket health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. The default value is 32. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | rw | 0x20 | BYPASS_BUCKET_THRESH | This is the threshold size for the bucket health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. The default value is 32. |
entropy_src.MARKOV_HI_THRESHOLDS @ 0x3c
Markov test high thresholds register Reset default = 0x600100, mask 0xffffffff
Register enable = REGWEN
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | rw | 0x100 | FIPS_MARKOV_HI_THRESH | This is the threshold size for the Markov health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. The default value is 256. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | rw | 0x60 | BYPASS_MARKOV_HI_THRESH | This is the threshold size for the Markov health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. The default value is .375 of the FIPS threshold. |
entropy_src.MARKOV_LO_THRESHOLDS @ 0x40
Markov test low thresholds register Reset default = 0x60010, mask 0xffffffff
Register enable = REGWEN
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | rw | 0x10 | FIPS_MARKOV_LO_THRESH | This is the threshold size for the Markov health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. The default value is 16. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | rw | 0x6 | BYPASS_MARKOV_LO_THRESH | This is the threshold size for the Markov health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. The default value is .375 of the FIPS threshold. |
entropy_src.EXTHT_HI_THRESHOLDS @ 0x44
External health test high thresholds register Reset default = 0x0, mask 0xffffffff
Register enable = REGWEN
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | rw | 0x0 | FIPS_EXTHT_HI_THRESH | This is the threshold size for the external health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. The default value is 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | rw | 0x0 | BYPASS_EXTHT_HI_THRESH | This is the threshold size for the external health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. The default value is 0. |
entropy_src.EXTHT_LO_THRESHOLDS @ 0x48
External health test low thresholds register Reset default = 0x0, mask 0xffffffff
Register enable = REGWEN
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | rw | 0x0 | FIPS_EXTHT_LO_THRESH | This is the threshold size for the external health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. The default value is 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | rw | 0x0 | BYPASS_EXTHT_LO_THRESH | This is the threshold size for the external health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. The default value is 0. |
entropy_src.REPCNT_HI_WATERMARKS @ 0x4c
Repetition count test high watermarks register Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | ro | x | FIPS_REPCNT_HI_WATERMARK | High watermark value of the REPCNT test in FIPS mode. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | ro | x | BYPASS_REPCNT_HI_WATERMARK | High watermark value of the REPCNT test in bypass mode. |
entropy_src.ADAPTP_HI_WATERMARKS @ 0x50
Adaptive proportion test high watermarks register Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | ro | x | FIPS_ADAPTP_HI_WATERMARK | High watermark value of the adaptive proportion test in FIPS mode. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | ro | x | BYPASS_ADAPTP_HI_WATERMARK | High watermark value of the adaptive proportion test in bypass mode. |
entropy_src.ADAPTP_LO_WATERMARKS @ 0x54
Adaptive proportion test low watermarks register Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | ro | x | FIPS_ADAPTP_LO_WATERMARK | Low watermark value of the adaptive proportion test in FIPS mode. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | ro | x | BYPASS_ADAPTP_LO_WATERMARK | Low watermark value of the adaptive proportion test in bypass mode. |
entropy_src.EXTHT_HI_WATERMARKS @ 0x58
External health test high watermarks register Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | ro | x | FIPS_EXTHT_HI_WATERMARK | High watermark value of the external health test in FIPS mode. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | ro | x | BYPASS_EXTHT_HI_WATERMARK | High watermark value of the external health test in bypass mode. |
entropy_src.EXTHT_LO_WATERMARKS @ 0x5c
External health test low watermarks register Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | ro | x | FIPS_EXTHT_LO_WATERMARK | Low watermark value of the external health test in FIPS mode. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | ro | x | BYPASS_EXTHT_LO_WATERMARK | Low watermark value of the external health test in bypass mode. |
entropy_src.BUCKET_HI_WATERMARKS @ 0x60
Bucket test high watermarks register Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | ro | x | FIPS_BUCKET_HI_WATERMARK | High watermark value of the bucket test in FIPS mode. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | ro | x | BYPASS_BUCKET_HI_WATERMARK | High watermark value of the bucket test in bypass mode. |
entropy_src.MARKOV_HI_WATERMARKS @ 0x64
Markov test high watermarks register Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | ro | x | FIPS_MARKOV_HI_WATERMARK | High watermark value of the Markov test in FIPS mode. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | ro | x | BYPASS_MARKOV_HI_WATERMARK | High watermark value of the Markov test in bypass mode. |
entropy_src.MARKOV_LO_WATERMARKS @ 0x68
Markov test low watermarks register Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | ro | x | FIPS_MARKOV_LO_WATERMARK | Low watermark value of the Markov test in FIPS mode. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | ro | x | BYPASS_MARKOV_LO_WATERMARK | Low watermark value of the Markov test in bypass mode. |
entropy_src.REPCNT_TOTAL_FAILS @ 0x6c
Repetition count test failure counter register Reset default = 0x0, mask 0xffffffff
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | REPCNT_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |
entropy_src.ADAPTP_HI_TOTAL_FAILS @ 0x70
Adaptive proportion high test failure counter register Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | ADAPTP_HI_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |
entropy_src.ADAPTP_LO_TOTAL_FAILS @ 0x74
Adaptive proportion low test failure counter register Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | ADAPTP_LO_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |
entropy_src.BUCKET_TOTAL_FAILS @ 0x78
Bucket test failure counter register Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | BUCKET_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |
entropy_src.MARKOV_HI_TOTAL_FAILS @ 0x7c
Markov high test failure counter register Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | MARKOV_HI_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |
entropy_src.MARKOV_LO_TOTAL_FAILS @ 0x80
Markov low test failure counter register Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | MARKOV_LO_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |
entropy_src.EXTHT_HI_TOTAL_FAILS @ 0x84
External health test high threshold failure counter register Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | EXTHT_HI_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |
entropy_src.EXTHT_LO_TOTAL_FAILS @ 0x88
External health test low threshold failure counter register Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | EXTHT_LO_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |
entropy_src.ALERT_THRESHOLD @ 0x8c
Alert threshold register Reset default = 0x2, mask 0xf
Register enable = REGWEN
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 | rw | 0x2 | ALERT_THRESHOLD | This is the threshold size that will signal an alert when value is reached. A value of zero will disable alerts. The default value is 2. |
entropy_src.ALERT_FAIL_COUNTS @ 0x90
Alert failure counts register Reset default = 0x0, mask 0xfffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 | ro | x | ANY_FAIL_COUNT | This field will hold a running count of the total alert count, which is a sum of all of the other counters in this register. It is intended to only hold a maximum count of 16 fails, even though the addition of all possible fails will easily overflow this field. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:4 | ro | x | REPCNT_FAIL_COUNT | This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11:8 | ro | x | ADAPTP_HI_FAIL_COUNT | This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:12 | ro | x | ADAPTP_LO_FAIL_COUNT | This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
19:16 | ro | x | BUCKET_FAIL_COUNT | This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
23:20 | ro | x | MARKOV_HI_FAIL_COUNT | This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
27:24 | ro | x | MARKOV_LO_FAIL_COUNT | This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared. |
entropy_src.EXTHT_FAIL_COUNTS @ 0x94
External health test alert failure counts register Reset default = 0x0, mask 0xff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 | ro | x | EXTHT_HI_FAIL_COUNT | This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:4 | ro | x | EXTHT_LO_FAIL_COUNT | This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared. |
entropy_src.FW_OV_CONTROL @ 0x98
Firmware override control register Reset default = 0x0, mask 0x7
Register enable = REGWEN
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | x | FW_OV_MODE | Setting this bit will put the entropy flow in firmware override mode. In this mode, firmware can explicitly control the flow in and out of the pre-conditioner FIFO. Once data has been written or read out of the FIFO to the extent that the override function has been completed, this bit can be cleared and normal entropy flow will resume. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw | x | FW_OV_FIFO_REG_RD | Setting this bit will prevent entropy flow out of the pre-conditioner FIFO and into the normal downstream stages, either the conditioner stage or the bypass path. Register reads of the FIFO output will be done in this mode. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw | x | FW_OV_FIFO_REG_WR | Setting this bit will switch the input into the pre-conditioner FIFO. Firmware can directly write into the FIFO, up to the full size of the FIFO. |
entropy_src.FW_OV_RD_DATA @ 0x9c
Firwware override FIFO read register Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | FW_OV_RD_DATA | A read of this register pops the top entry off of the pre-conditioner FIFO. The result is transfered to this register for firmware operations. |
entropy_src.FW_OV_WR_DATA @ 0xa0
Firwware override FIFO write register Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | FW_OV_WR_DATA | A read of this register pops the top entry off of the pre-conditioner FIFO. The result is transfered to this register for firmware operations. |
entropy_src.FW_OV_FIFO_STS @ 0xa4
Firwware override FIFO status register Reset default = 0x0, mask 0x7f
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:0 | ro | x | FW_OV_FIFO_STS | A read of this register will show what the current depth of the
pre-conditioner FIFO. Firmware can use this value when updated the
contents of the FIFO. The physical maximum depth is 64 entries, the
maximum value of this register is also 64, or 0x40. This depth can
be logically lowered by the |
entropy_src.PRE_COND_FIFO_DEPTH @ 0xa8
Pre-conditioner FIFO depth control register Reset default = 0x40, mask 0x7f
Register enable = REGWEN
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:0 | rw | 0x40 | PRE_COND_FIFO_DEPTH | This field to set the logical depth of the pre-conditioner FIFO. Firmware can set this value to be less (a logical depth) than the actual physical size of the FIFO. This field with be compared with the actual size of the FIFO and indicate full to the upstream entropy flow. The default value of this register is 64, or 0x40. |
entropy_src.DEBUG_STATUS @ 0xac
Debug status register Reset default = 0x0, mask 0x80000003
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1:0 | ro | x | ENTROPY_FIFO_DEPTH | This is the depth of the entropy source FIFO. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
30:2 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31 | ro | x | DIAG | This bit is for internal debug only. |
entropy_src.SEED @ 0xb0
ENTROPY_SRC seed register Reset default = 0xb, mask 0xf
Register enable = REGWEN
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 | rw | 0xb | LFSR_SEED | Seed used to load into the LFSR for the initial state. This field will not update if the REGWEN bit 0 is cleared. |
entropy_src.ERR_CODE @ 0xb4
Hardware detection of error conditions status register Reset default = 0x0, mask 0x70300007
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | ro | x | SFIFO_ESRNG_ERR | This bit will be set to one when an error has been detected for the esrng FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until firmware clears it. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | ro | x | SFIFO_PRECON_ERR | This bit will be set to one when an error has been detected for the precon FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until firmware clears it. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | ro | x | SFIFO_ESFINAL_ERR | This bit will be set to one when an error has been detected for the esfinal FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until firmware clears it. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
19:3 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
20 | ro | x | ES_ACK_SM_ERR | This bit will be set to one when an illegal state has been detected for the ES ack stage state machine. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until firmware clears it. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
21 | ro | x | ES_MAIN_SM_ERR | This bit will be set to one when an illegal state has been detected for the ES main stage state machine. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until firmware clears it. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
27:22 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
28 | ro | x | FIFO_WRITE_ERR | This bit will be set to one when any of the source bits (bits 0 through 1 of this this register) are asserted as a result of an error pulse generated from any full FIFO that has been recieved a write pulse. This bit will stay set until firmware clears it. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
29 | ro | x | FIFO_READ_ERR | This bit will be set to one when any of the source bits (bits 0 through 1 of this this register) are asserted as a result of an error pulse generated from any empty FIFO that has recieved a read pulse. This bit will stay set until firmware clears it. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
30 | ro | x | FIFO_STATE_ERR | This bit will be set to one when any of the source bits (bits 0 through 1 of this this register) are asserted as a result of an error pulse generated from any FIFO where both the empty and full status bits are set. This bit will stay set until firmware clears it. |
entropy_src.ERR_CODE_TEST @ 0xb8
Test error conditions register Reset default = 0x0, mask 0x1f
Register enable = REGWEN
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | rw | x | ERR_CODE_TEST | Setting this field will set the bit number for which an error
will be forced in the hardware. This bit number is that same one
found in the |