ENTROPY_SRC HWIP Technical Specification

Overview

This document specifies ENTROPY_SRC hardware IP functionality. This module conforms to the Comportable guideline for peripheral functionality.

Features

  • This revision provides an interface to an external physical random noise generator (also referred to as a physical true random number generator or PTRNG) source, and an LFSR (linear feedback shift register) digital source. The LFSR is used as a digital, pseudo-random type of entropy source, while the PTRNG external source is a physical true random noise source. A noise source and its relation to an entropy source are defined by SP 800-90B.
  • A set of registers is provided for firmware to obtain entropy bits.
  • The set of registers is designed such that firmware can select between an LFSR or a PTRNG noise source.
  • Interrupts are supported:
    • Entropy bits are available for firmware consumption.
    • The internal health tests have detected a test failure.
    • An internal FIFO error has occurred.
  • Two health checks that are defined by SP 800-90B are performed by this revision: Repetition Count and Adaptive Proportion tests.
  • Two additional hardware health checks are performed by this revision: Bucket and Markov tests.
  • Firmware-defined (mailbox-based) and vendor-defined health checks are also supported.
  • A health check failure alert is supported by this revision.

Description

This IP block provides an entropy source that is capable of using a PTRNG noise source to generate random values in a manner that is compliant both with FIPS (though NIST SP 800-90B) and CC (AIS31) recommendations.

The random values generated by this block serve as non-deterministic seeds for the CSRNG block. The outputs of the CSRNG are then used either directly by firmware or are distributed to other hardware blocks through the Entropy Distribution Network.

In the terms of AIS31 classes, this block is meant to satisfy the requirements for a PTG.2 class physical entropy source, with “internal” entropy (an AIS31 term, meaning the min-entropy as measured just before the output pins) exceeding 0.997 entropy-bits/output-bit. In NIST terms, this block satisfies the requirements for a “full-entropy” source, which requires even smaller deviations from ideal entropy, at the level of less than one part in 264. When operating in full-compliance mode, raw outputs from a PTRNG noise source (external to this block) are passed through a conditioning function based on a suitable secure hash function (SHA-2 or SHA-3) which has been vetted by NIST to meet these stringent requirements.

These raw noise bits are subjected to a sequence of health-checks to screen the raw signals for statistical defects which would cause any significant deviations from ideal entropy at the output of the conditioning block. These tests include:

  • The Repetition Count test, which screens for stuck-bits, or a complete failure of the PTRNG noise source,
  • The Adaptive Proportion test, which screens for statistical bias in the number of 1’s or 0’s output by the noise source,
  • The “Bucket Test”, which looks for correlations between the individual noise channels that the external noise source concatenates together to produce the raw noise sequence,
  • The “Markov Test”, which looks for unexpected first-order temporal correlations between bits output by the individual noise channels,
  • The “Mailbox Test”, in which raw-noise data is transferred to firmware in contiguous 2kbit-blocks, so that firmware can perform custom tests, and signal a failure through the same path as the other tests, and
  • Optional Vendor Specific tests, which allow silicon creators to extend the health checks by adding a top-level block external to this IP.

The Repetition Count and Adaptive Proportion test are specifically recommended by SP 800-90B, and are implemented in accordance with those recommendations. In FIPS/CC-compliance mode, all checks except the Repetition Count test are performed on fixed window of data, typically consisting of 1024 bits each. Per the definition in SP 800-90B, the Repetition Count test does not operate on a fixed window. The repetition count test fails if any sequence of bits continuously asserts the same value for too many samples, as determined by the programmable threshold, regardless of whether that sequence crosses any window boundaries. The thresholds for these tests should be chosen to achieve a low false-positive rate (α) given a conservative estimate of the manufacturing tolerances of the PTRNG noise source. The combined choice of threshold and window size then determine the false-negative rate (β), or the probability of missing statistical defects at any particular magnitude.

When the IP is disabled by clearing the ENABLE bit in CONF, all heath checks are disabled and all counters internal to the health checks are reset.

In order to compensate for the fact our tests (like all realistic statistical tests) have finite resolution for detecting defects, we conservatively use 1024 bits of PTRNG noise source to construct each 384 bit conditioned entropy sample. When passed through the conditioning block, the resultant entropy stream will be full entropy unless the PTRNG noise source has encountered some statistical defect serious enough to reduce the raw min-entropy to a level below 0.375 bits of entropy per output bit. We choose this level as our definition of “non-tolerable statistical defects” for the purposes of evaluating this system under AIS31. Given this definition of “non-tolerable defects”, the health-checks as implemented for this block will almost certainly detect any of the previously mentioned defects in a single iteration of the health checks (i.e. such serious defects will be detected with very low β).

In addition to the brief, low-latency health checks, various long-term statistics are accumulated in registers for additional diagnostic purposes or for in-depth analysis. For the hardware interface, entropy bits will be transferred whenever the downstream consumer is ready to receive them.

At a high-level, this ENTROPY_SRC block, when enabled, will continuously collect entropy bits from the entropy source into a FIFO that can be read from the TL-UL bus, or sent out through a hardware interface. The PTRNG noise source will generate a relatively slow set of bit streams, with a total bit rate on the order of 50 kbps. The digital source can be programmed to be faster, or much slower if desired. A digital source rate of flexible speed might be useful in demonstrating how the downstream applications use the entropy.

Once a noise source has been selected through configuration, the raw noise data processing begins. This ENTROPY_SRC block will do health checks, collect and pack bits, and finally send them through a conditioning unit. There are two modes in which entropy bits are delivered, boot-time and FIPS/CC mode. Boot-time mode will deliver bits sooner for specific on-boot obfuscation applications, though the bits may not yet have been subjected to the same level of startup health checks required for FIPS or CC compliance.

In boot-time mode health checks only operate on a window of 384 bits. The boot-time health checks are the same as the FIPS/CC health-checks, though with different thresholds. They are sensitive to the same types of statistical defects, though at reduced statistical resolution. With suitable thresholds, the boot-time health checks can be operate both with low false-alarm rates (low α), while still confirming with low β that the total entropy of the first seed contains at least 80 bits of total entropy. During start up the initial 384 bits are held in a buffer until the boot-time start-up health checks are performed. Storing the seed in this buffer, allows this seed to released to the CSRNG immediately after the entropy has been confirmed.

Boot-time mode also has the feature that it bypasses the SHA conditioning function, as only 384 bits are used in the initial boot-time seed.

For maximal flexibility in normal operation, the conditioning function can also be implemented by firmware. When this firmware conditioning feature is activated, data read directly out of the noise source can be reinjected into the entropy pipeline via a TL-UL register after it has been processed by firmware. It should be noted that this firmware algorithm must be vetted by NIST to satisfy the requirements for a full-entropy source. This feature can also be disabled for security purposes, either by locking the feature via the REGEN register at boot, or by a write to one-time programmable (OTP) memory.

Compatibility

This IP block does not have any direct hardware compatibility requirements. However, the general design of this block follows the overall NIST recommendations, as described by SP 800-90B.

Theory of Operations

As already described, this IP block will collect bits of entropy for firmware or hardware consumption. This revision supports both an LFSR for the pseudo-random digital implementation, and an external interface for the PTRNG noise source implementation.

The first step is initialization and enabling. Normally PTRNG noise source mode is selected, and the ENABLE field will be set to enable PTRNG noise source mode. If using LFSR mode, before setting the ENABLE field, the LFSR seed input should be initialized, using the SEED register. The ENTROPY_RATE register will default to a sample rate of 20 microseconds, assuming a system clock rate of 100 nanoseconds. The SEED register will transfer its value to the LFSR block, but the LFSR block is locked once the ENABLE field is set. After the block is enabled and initialized, entropy bits will be collected up indefinitely until disabled.

After a reset, the ENTROPY_SRC block will start up in boot-time mode by default. This feature is designed to provide an initial seed’s worth of entropy with lower latency than the normal FIPS/CC compliant health check process. Health testing will still be performed on boot-time mode entropy, but the window of checking is, by default, 384 bits instead of 1024 bits. When entropy is delivered to the downstream hardware block, a signal will indicate what type of entropy it is - FIPS compliant or not. Boot-time mode can be completely disabled in the CONF register.

Once the initial boot-time mode phase has completed, the ENTROPY_SRC block will switch to FIPS compliant mode. In this mode, once the raw entropy has been health checked, it will be passed into a conditioner block. This block will compress the bits such that the entropy bits/physical bits, or min-entropy value, should be improved over the raw data source min-entropy value. The compression operation, by default, will compress every 1024 tested bits into 384 full-entropy bits.

The hardware conditioning can also be bypassed and replaced in normal operation with a firmware-defined conditioning algorithm. This firmware conditioning algorithm, can be disabled on boot for security purposes. The exact mechanism for this functionality will be described in a future update to this document (TBD).

Health checks are performed on the input raw data from the PTRNG noise source when in that mode. There are four health tests that will be performed: repetitive count, adaptive proportion, bucket, and Markov tests. Each test has a pair of threshold values that determine that pass/fail of the test, one threshold for boot-time mode, and one for normal mode. By default, all tests are enabled, but can be turn off in the CONF register. Because of the variability of the PTRNG noise source, there are several registers that log statistics associated with the health tests. For example, the adaptive proportion test has a high watermark register that logs the highest measured number of ones. The ADAPTP_HI_WATERMARKS register has an entry for both normal and boot-time modes. This register allows for determining how close the threshold value should be set to the fail over value. Specific to the adaptive proportion test, there is also the ADAPTP_LO_WATERMARKS register, which will hold the lowest number of ones measured. To help understand how well the thresholds work through time, a running count of test fails is kept in the ADAPTP_HI_TOTAL_FAILS register. The above example for the adaptive proportion test also applies to the other health tests, with the exception of the low watermark registers. See the timing diagrams below for more details on how the health tests work. It should be noted that for all error counter registers, they are sized for 16 bits, which prevents any case where counters might wrap.

The Mailbox test and Vendor-specific tests are planned, but not yet implemented. The theory of operation for these tests will therefore be described in a future update.

The ALERT_THRESHOLD register determines how many fails can occur before an alert is issued. By default, the current threshold is set to two, such that the occurrence of two failing test cycles back-to-back would provide a very low α value. The ALERT_FAIL_COUNTS register holds the total number of fails, plus all of the individual contributing failing tests. Setting the ALERT_THRESHOLD register to zero will disable alert generation.

Firmware has a path to read entropy from the ENTROPY_SRC block. The ENTROPY_CONTROL register allows firmware to set the internal multiplexers to steer entropy data to the ENTROPY_DATA register. The control bit ES_TYPE sets whether the entropy will come from the conditioning block or be sourced through the bypass path. A status bit will be set that can either be polled or generate an interrupt when the entropy bits are available to be read from the ENTROPY_DATA register. The firmware needs to read the ENTROPY_DATA register twelve times in order to cleanly evacuate the 384-bit seed from the hardware path (12*32bits=384bits total). The firmware will directly read out of the main entropy FIFO, and when the control bit ES_ROUTE is set, no entropy is being passed to the block hardware interface. If the main entropy FIFO fills up, additional entropy that has been health checked and conditioned will be dropped at that point.

The above process will be repeated for as long as entropy bits are to be collected and processed.

At any time, the ENABLE field can be cleared to halt the entropy generation (and health check testing) immediately.

Block Diagram

ENTROPY_SRC Block Diagram

Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module entropy_src has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: none

Bus Device Interface: tlul

Bus Host Interface: none

Peripheral Pins for Chip IO: none

Interrupts:

Interrupt NameDescription
es_entropy_validAsserted when entropy source bits are available.
es_health_test_failedAsserted when the alert count has been met.
es_fifo_errAsserted when a FIFO error occurs.

Security Alerts:

Alert NameDescription
es_alert_count_metThis alert is triggered upon the alert count being met.

Design Details

Initialization

After power-up, the ENTROPY_SRC block is disabled. In this state, the seed register will continuously be loaded into the LFSR. The seed register can be written without restriction, regardless of any state of any control bits.

For simplicity of initialization, only a single register write is needed to start functional operation of the ENTROPY_SRC block. This assumes that proper defaults are chosen for thresholds, sampling rate, and other registers.

For security reasons, a configuration and control register locking function is performed by the REGEN register. Clearing the bit in this register will prevent future modification of the CONF register or other writeable registers by firmware.

Entropy Processing

When enabled, the ENTROPY_SRC block will generate entropy bits continuously. The es_entropy_valid bit in the ENTROPY_SRC_INTR_STATE register will indicate to the firmware when entropy bits can read from the ENTROPY_DATA register. The firmware will do 32-bit register reads of the ENTROPY_DATA register to retrieve the entropy bits. Each read will automatically pop an entry from the entropy unpacker block. A full twelve 32-bit words need to be read at a time.

The hardware entropy interface will move entropy bits out of the ENTROPY FIFO when it is not empty, and the downstream hardware is ready. If firmware is not currently reading entropy bits, all processed entropy bits will flow to the hardware entropy interface.

An additional feature is the RATE register. The purpose of this register is to simulate faster or slower entropy generation sources than when the digital source is selected. This will aid firmware design and debug when trying to handle all entropy source types and rates. When in PTRNG mode, this register must exactly match the sample rate required by the PTRNG source, expected to be in the range of about 25 to 50 kilohertz.

Interrupts

The ENTROPY_SRC module has several interrupts: es_entropy_valid, es_health_test_failed, and es_fifo_err`.

The es_entropy_valid interrupt should be asserted when an entropy source has been implemented that is relatively slow.

The es_health_test_failed interrupt will trigger when the internal health test fails and exceeds the alert threshold.

The es_fifo_err interrupt will fire when an internal FIFO has a malfunction. The conditions that cause this to happen are either when there is a push to a full FIFO or a pull from an empty FIFO.

Future Features

  • Timer to pace health checks only when there is no demand for entropy seeds
  • One-way threshold values if regen register cannot be used
  • Support for golden test pattern

Entropy Source Hardware Interface

The following waveform shows an example of how the entropy source hardware interface works, which is much like a FIFO.

PTRNG Hardware Interface

The following waveform shows an example of what the PTRNG timing looks like.

Repetition Count Test

The following waveform shows how a sampling of the LFSR data pattern will be tested by the Repetition Count test. Operating on each bit stream, this test will count when a signal is at a stuck level. This NIST test is intended to signal a catastrophic failure with the PTRNG noise source.

Adaptive Proportion Test

The following waveform shows how a sampling of the LFSR data pattern will be tested by the Adaptive Proportion test. Operating on all four bit streams, this test will count how many ones are present in the full sample period. This NIST test is intended to find bias when either too many or too few ones are present.

Bucket Test

The following waveform shows how a sampling of the LFSR data pattern will be tested by the Bucket test. Operating on all four bit streams, this test will identify the symbol and sort it into bin counters, or “buckets”. This test is intended to find bias with a symbol or symbols.

Markov Test

The following waveform shows how a sampling of the LFSR data pattern will be tested by the Markov test. Operating on all four bit streams, this test will identify pairs of transitions in time per bit stream. Specifically, only pairs of 0b01 and 0b10 will be counted.

Programmers Guide

Initialization

The following code snippet demonstrates initializing the ENTROPY_SRC block for entropy bit generation.


void entropy_src_init(unsigned int rate) {

  // set the rate value (optional)
  *SEED_REG = rate;

  // set the configuration enable bits (rng mode, all health tests enabled)
  *CONF_REG = 0x1;

  // the ENTROPY_SRC interrupts can optionally be enabled
}

Entropy Processing

The following code snippet demonstrates reading entropy bits from the ENTROPY_SRC block.


int entropy_src_entropy(unsigned int numEntropyBits) {

  // read numEntropyBits, check for ENTROPY_SRC_INTR_STATE bit 0
  return *ENTROPY_DATA_REG;

}

Error conditions

Need to alert the system of a FIFO overflow condition.

Register Table

entropy_src.INTR_STATE @ + 0x0
Interrupt State Register
Reset default = 0x0, mask 0x7
31302928272625242322212019181716
 
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  es_fifo_err es_health_test_failed es_entropy_valid
BitsTypeResetNameDescription
0rw1c0x0es_entropy_validAsserted when entropy source bits are available.
1rw1c0x0es_health_test_failedAsserted when the alert count has been met.
2rw1c0x0es_fifo_errAsserted when a FIFO error occurs.


entropy_src.INTR_ENABLE @ + 0x4
Interrupt Enable Register
Reset default = 0x0, mask 0x7
31302928272625242322212019181716
 
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  es_fifo_err es_health_test_failed es_entropy_valid
BitsTypeResetNameDescription
0rw0x0es_entropy_validEnable interrupt when INTR_STATE.es_entropy_valid is set
1rw0x0es_health_test_failedEnable interrupt when INTR_STATE.es_health_test_failed is set
2rw0x0es_fifo_errEnable interrupt when INTR_STATE.es_fifo_err is set


entropy_src.INTR_TEST @ + 0x8
Interrupt Test Register
Reset default = 0x0, mask 0x7
31302928272625242322212019181716
 
1514131211109876543210
  es_fifo_err es_health_test_failed es_entropy_valid
BitsTypeResetNameDescription
0wo0x0es_entropy_validWrite 1 to force INTR_STATE.es_entropy_valid to 1
1wo0x0es_health_test_failedWrite 1 to force INTR_STATE.es_health_test_failed to 1
2wo0x0es_fifo_errWrite 1 to force INTR_STATE.es_fifo_err to 1


entropy_src.ALERT_TEST @ + 0xc
Alert Test Register
Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  es_alert_count_met
BitsTypeResetNameDescription
0wo0x0es_alert_count_metWrite 1 to trigger one alert event of this kind.


entropy_src.REGEN @ + 0x10
Register write enable for all control registers
Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  REGEN
BitsTypeResetNameDescription
0rw1c0x1REGENWhen true, all writeable registers can be modified. When false, they become read-only. Defaults true, write one to clear. Note that this needs to be cleared after initial configuration at boot in order to lock in the listed register settings.


entropy_src.REV @ + 0x14
Revision register
Reset default = 0x10303, mask 0xffffff
31302928272625242322212019181716
  CHIP_TYPE
1514131211109876543210
HW_REVISION ABI_REVISION
BitsTypeResetNameDescription
7:0ro0x3ABI_REVISIONRead of this register shows the ABI of this block.
15:8ro0x3HW_REVISIONRead of this register shows the revision of this block.
23:16ro0x1CHIP_TYPERead of this register shows the type of chip using this block.


entropy_src.CONF @ + 0x18
Configuration register
Reset default = 0x0, mask 0x1ffb
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  EXTHT_ENABLE RNG_BIT_SEL RNG_BIT_EN HEALTH_TEST_CLR MARKOV_DISABLE BUCKET_DISABLE ADAPTP_DISABLE REPCNT_DISABLE BOOT_BYPASS_DISABLE   ENABLE
BitsTypeResetNameDescription
1:0rw0x0ENABLEThis field is the module enable for the ENTROPY_SRC entropy generation function. This two bit field determines what source will be used for all processing: 0b00: Disabled 0b01: PTRNG mode enabled 0b10: LFSR mode enabled 0b11: Reserved
2Reserved
3rw0x0BOOT_BYPASS_DISABLESetting this bit disables the initial generation of non-FIPS entropy.
4rw0x0REPCNT_DISABLESetting this bit disables the health test called Repetition Count test.
5rw0x0ADAPTP_DISABLESetting this bit disables the health test called Adaptive Proportion test.
6rw0x0BUCKET_DISABLESetting this bit disables the health test called Bucket test.
7rw0x0MARKOV_DISABLESetting this bit disables the health test called Markov test.
8rw0x0HEALTH_TEST_CLRSetting this bit will clear all registers related to the health test operations.
9rw0x0RNG_BIT_ENSetting this bit enables the single RNG bit mode, where only one bit is sampled.
11:10rw0x0RNG_BIT_SELWhen the above bit iset, this field selects which bit from the RNG bus will be processed when in single RNG bit mode. This two bit field selects the RNG bit stream: 0b00: RNG bit 0 0b01: RNG bit 1 0b10: RNG bit 2 0b11: RNG bit 3
12rw0x0EXTHT_ENABLESetting this bit enables the hardware-based health test that is external to ENTROPY_SRC."


entropy_src.RATE @ + 0x1c
Entropy rate register
Reset default = 0x7d0, mask 0xffff
31302928272625242322212019181716
 
1514131211109876543210
ENTROPY_RATE
BitsTypeResetNameDescription
15:0rw0x7d0ENTROPY_RATEThis register determines the rate that entropy bits will be supplied. In LFSR mode, this is the rate that the LFSR value will be advanced. In PTRNG mode, this is the rate that the raw entropy source will be sampled at. The default rate is 50 KHz, or 4 physcial bits per 20 micro-seconds.


entropy_src.ENTROPY_CONTROL @ + 0x20
Entropy control register
Reset default = 0x0, mask 0x3
Register enable = REGEN
31302928272625242322212019181716
 
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  ES_TYPE ES_ROUTE
BitsTypeResetNameDescription
0rw0x0ES_ROUTESetting this bit routes the generated entropy value to the ENTROPY_DATA register to be read by firmware. When this bit is zero, the generated entropy will be forwarded out of this module to the hardware interface.
1rw0x0ES_TYPESetting this bit will bypass the conditioning logic and bring raw entropy data to the ENTROPY_DATA register. When zero, FIPS compliant entropy will be brought the ENTROPY_DATA register, after being conditioned.


entropy_src.ENTROPY_DATA @ + 0x24
Entropy data bits
Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
ENTROPY_DATA...
1514131211109876543210
...ENTROPY_DATA
BitsTypeResetNameDescription
31:0ro0x0ENTROPY_DATAA read of this register provides generated entropy bits to firmware.


entropy_src.HEALTH_TEST_WINDOWS @ + 0x28
Health test windows register
Reset default = 0x600100, mask 0xffffffff
Register enable = REGEN
31302928272625242322212019181716
BYPASS_WINDOW
1514131211109876543210
FIPS_WINDOW
BitsTypeResetNameDescription
15:0rw0x100FIPS_WINDOWThis is the window size for all health tests. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. The default value is (1024 bits * 1 clock/4 bits);
31:16rw0x60BYPASS_WINDOWThis is the window size for all health tests when running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. The default value is (384 bits * 1 clock/4 bits);


entropy_src.REPCNT_THRESHOLDS @ + 0x2c
Repetition count test thresholds register
Reset default = 0x200020, mask 0xffffffff
Register enable = REGEN
31302928272625242322212019181716
BYPASS_REPCNT_THRESH
1514131211109876543210
FIPS_REPCNT_THRESH
BitsTypeResetNameDescription
15:0rw0x20FIPS_REPCNT_THRESHThis is the threshold size for the repetition count health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. The default value is 32
31:16rw0x20BYPASS_REPCNT_THRESHThis is the threshold size for the repetition count health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. The default value is 32


entropy_src.ADAPTP_HI_THRESHOLDS @ + 0x30
Adaptive proportion test high thresholds register
Reset default = 0xe00256, mask 0xffffffff
Register enable = REGEN
31302928272625242322212019181716
BYPASS_ADAPTP_HI_THRESH
1514131211109876543210
FIPS_ADAPTP_HI_THRESH
BitsTypeResetNameDescription
15:0rw0x256FIPS_ADAPTP_HI_THRESHThis is the threshold size for the adaptive proportion health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. The default value is 598.
31:16rw0xe0BYPASS_ADAPTP_HI_THRESHThis is the threshold size for the adaptive proportion health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. The default value is .375 of the FIPS threshold.


entropy_src.ADAPTP_LO_THRESHOLDS @ + 0x34
Adaptive proportion test low thresholds register
Reset default = 0xa001aa, mask 0xffffffff
Register enable = REGEN
31302928272625242322212019181716
BYPASS_ADAPTP_LO_THRESH
1514131211109876543210
FIPS_ADAPTP_LO_THRESH
BitsTypeResetNameDescription
15:0rw0x1aaFIPS_ADAPTP_LO_THRESHThis is the threshold size for the adaptive proportion health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. The default value is 426.
31:16rw0xa0BYPASS_ADAPTP_LO_THRESHThis is the threshold size for the adaptive proportion health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. The default value is .375 of the FIPS threshold.


entropy_src.BUCKET_THRESHOLDS @ + 0x38
Bucket test thresholds register
Reset default = 0x200020, mask 0xffffffff
Register enable = REGEN
31302928272625242322212019181716
BYPASS_BUCKET_THRESH
1514131211109876543210
FIPS_BUCKET_THRESH
BitsTypeResetNameDescription
15:0rw0x20FIPS_BUCKET_THRESHThis is the threshold size for the bucket health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. The default value is 32.
31:16rw0x20BYPASS_BUCKET_THRESHThis is the threshold size for the bucket health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. The default value is 32.


entropy_src.MARKOV_THRESHOLDS @ + 0x3c
Markov test thresholds register
Reset default = 0x600100, mask 0xffffffff
Register enable = REGEN
31302928272625242322212019181716
BYPASS_MARKOV_THRESH
1514131211109876543210
FIPS_MARKOV_THRESH
BitsTypeResetNameDescription
15:0rw0x100FIPS_MARKOV_THRESHThis is the threshold size for the Markov health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. The default value is 256.
31:16rw0x60BYPASS_MARKOV_THRESHThis is the threshold size for the Markov health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. The default value is .375 of the FIPS threshold.


entropy_src.EXTHT_HI_THRESHOLDS @ + 0x40
External health test high thresholds register
Reset default = 0x0, mask 0xffffffff
Register enable = REGEN
31302928272625242322212019181716
BYPASS_EXTHT_HI_THRESH
1514131211109876543210
FIPS_EXTHT_HI_THRESH
BitsTypeResetNameDescription
15:0rw0x0FIPS_EXTHT_HI_THRESHThis is the threshold size for the external health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. The default value is 0.
31:16rw0x0BYPASS_EXTHT_HI_THRESHThis is the threshold size for the external health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. The default value is 0.


entropy_src.EXTHT_LO_THRESHOLDS @ + 0x44
External health test low thresholds register
Reset default = 0x0, mask 0xffffffff
Register enable = REGEN
31302928272625242322212019181716
BYPASS_EXTHT_LO_THRESH
1514131211109876543210
FIPS_EXTHT_LO_THRESH
BitsTypeResetNameDescription
15:0rw0x0FIPS_EXTHT_LO_THRESHThis is the threshold size for the external health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. The default value is 0.
31:16rw0x0BYPASS_EXTHT_LO_THRESHThis is the threshold size for the external health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. The default value is 0.


entropy_src.REPCNT_HI_WATERMARKS @ + 0x48
Repetition count test high watermarks register
Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
BYPASS_REPCNT_HI_WATERMARK
1514131211109876543210
FIPS_REPCNT_HI_WATERMARK
BitsTypeResetNameDescription
15:0ro0x0FIPS_REPCNT_HI_WATERMARKHigh watermark value of the REPCNT test in FIPS mode.
31:16ro0x0BYPASS_REPCNT_HI_WATERMARKHigh watermark value of the REPCNT test in bypass mode.


entropy_src.ADAPTP_HI_WATERMARKS @ + 0x4c
Adaptive proportion test high watermarks register
Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
BYPASS_ADAPTP_HI_WATERMARK
1514131211109876543210
FIPS_ADAPTP_HI_WATERMARK
BitsTypeResetNameDescription
15:0ro0x0FIPS_ADAPTP_HI_WATERMARKHigh watermark value of the adaptive proportion test in FIPS mode.
31:16ro0x0BYPASS_ADAPTP_HI_WATERMARKHigh watermark value of the adaptive proportion test in bypass mode.


entropy_src.ADAPTP_LO_WATERMARKS @ + 0x50
Adaptive proportion test low watermarks register
Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
BYPASS_ADAPTP_LO_WATERMARK
1514131211109876543210
FIPS_ADAPTP_LO_WATERMARK
BitsTypeResetNameDescription
15:0ro0x0FIPS_ADAPTP_LO_WATERMARKLow watermark value of the adaptive proportion test in FIPS mode.
31:16ro0x0BYPASS_ADAPTP_LO_WATERMARKLow watermark value of the adaptive proportion test in bypass mode.


entropy_src.EXTHT_HI_WATERMARKS @ + 0x54
External health test high watermarks register
Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
BYPASS_EXTHT_HI_WATERMARK
1514131211109876543210
FIPS_EXTHT_HI_WATERMARK
BitsTypeResetNameDescription
15:0ro0x0FIPS_EXTHT_HI_WATERMARKHigh watermark value of the external health test in FIPS mode.
31:16ro0x0BYPASS_EXTHT_HI_WATERMARKHigh watermark value of the external health test in bypass mode.


entropy_src.EXTHT_LO_WATERMARKS @ + 0x58
External health test low watermarks register
Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
BYPASS_EXTHT_LO_WATERMARK
1514131211109876543210
FIPS_EXTHT_LO_WATERMARK
BitsTypeResetNameDescription
15:0ro0x0FIPS_EXTHT_LO_WATERMARKLow watermark value of the external health test in FIPS mode.
31:16ro0x0BYPASS_EXTHT_LO_WATERMARKLow watermark value of the external health test in bypass mode.


entropy_src.BUCKET_HI_WATERMARKS @ + 0x5c
Bucket test high watermarks register
Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
BYPASS_BUCKET_HI_WATERMARK
1514131211109876543210
FIPS_BUCKET_HI_WATERMARK
BitsTypeResetNameDescription
15:0ro0x0FIPS_BUCKET_HI_WATERMARKHigh watermark value of the bucket test in FIPS mode.
31:16ro0x0BYPASS_BUCKET_HI_WATERMARKHigh watermark value of the bucket test in bypass mode.


entropy_src.MARKOV_HI_WATERMARKS @ + 0x60
Markov test high watermarks register
Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
BYPASS_MARKOV_HI_WATERMARK
1514131211109876543210
FIPS_MARKOV_HI_WATERMARK
BitsTypeResetNameDescription
15:0ro0x0FIPS_MARKOV_HI_WATERMARKHigh watermark value of the Markov test in FIPS mode.
31:16ro0x0BYPASS_MARKOV_HI_WATERMARKHigh watermark value of the Markov test in bypass mode.


entropy_src.REPCNT_TOTAL_FAILS @ + 0x64
Repetition count test failure counter register
Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
REPCNT_TOTAL_FAILS...
1514131211109876543210
...REPCNT_TOTAL_FAILS
BitsTypeResetNameDescription
31:0ro0x0REPCNT_TOTAL_FAILSThis register will hold a running count of test failures observed during normal operation. It will persist until cleared.


entropy_src.ADAPTP_HI_TOTAL_FAILS @ + 0x68
Adaptive proportion high test failure counter register
Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
ADAPTP_HI_TOTAL_FAILS...
1514131211109876543210
...ADAPTP_HI_TOTAL_FAILS
BitsTypeResetNameDescription
31:0ro0x0ADAPTP_HI_TOTAL_FAILSThis register will hold a running count of test failures observed during normal operation. It will persist until cleared.


entropy_src.ADAPTP_LO_TOTAL_FAILS @ + 0x6c
Adaptive proportion low test failure counter register
Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
ADAPTP_LO_TOTAL_FAILS...
1514131211109876543210
...ADAPTP_LO_TOTAL_FAILS
BitsTypeResetNameDescription
31:0ro0x0ADAPTP_LO_TOTAL_FAILSThis register will hold a running count of test failures observed during normal operation. It will persist until cleared.


entropy_src.BUCKET_TOTAL_FAILS @ + 0x70
Bucket test failure counter register
Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
BUCKET_TOTAL_FAILS...
1514131211109876543210
...BUCKET_TOTAL_FAILS
BitsTypeResetNameDescription
31:0ro0x0BUCKET_TOTAL_FAILSThis register will hold a running count of test failures observed during normal operation. It will persist until cleared.


entropy_src.MARKOV_TOTAL_FAILS @ + 0x74
Markov test failure counter register
Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
MARKOV_TOTAL_FAILS...
1514131211109876543210
...MARKOV_TOTAL_FAILS
BitsTypeResetNameDescription
31:0ro0x0MARKOV_TOTAL_FAILSThis register will hold a running count of test failures observed during normal operation. It will persist until cleared.


entropy_src.EXTHT_HI_TOTAL_FAILS @ + 0x78
External health test high threshold failure counter register
Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
EXTHT_HI_TOTAL_FAILS...
1514131211109876543210
...EXTHT_HI_TOTAL_FAILS
BitsTypeResetNameDescription
31:0ro0x0EXTHT_HI_TOTAL_FAILSThis register will hold a running count of test failures observed during normal operation. It will persist until cleared.


entropy_src.EXTHT_LO_TOTAL_FAILS @ + 0x7c
External health test low threshold failure counter register
Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
EXTHT_LO_TOTAL_FAILS...
1514131211109876543210
...EXTHT_LO_TOTAL_FAILS
BitsTypeResetNameDescription
31:0ro0x0EXTHT_LO_TOTAL_FAILSThis register will hold a running count of test failures observed during normal operation. It will persist until cleared.


entropy_src.ALERT_THRESHOLD @ + 0x80
Alert threshold register
Reset default = 0x2, mask 0xf
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  ALERT_THRESHOLD
BitsTypeResetNameDescription
3:0rw0x2ALERT_THRESHOLDThis is the threshold size that will signal an alert when value is reached. A value of zero will disable alerts. The default value is 2.


entropy_src.ALERT_FAIL_COUNTS @ + 0x84
Alert failure counts register
Reset default = 0x0, mask 0xffffff
31302928272625242322212019181716
  MARKOV_FAIL_COUNT BUCKET_FAIL_COUNT
1514131211109876543210
ADAPTP_LO_FAIL_COUNT ADAPTP_HI_FAIL_COUNT REPCNT_FAIL_COUNT ANY_FAIL_COUNT
BitsTypeResetNameDescription
3:0ro0x0ANY_FAIL_COUNTThis field will hold a running count of the total alert count, which is a sum of all of the other counters in this register. It is intended to only hold a maximum count of 16 fails, even though the addition of all possible fails will easily overflow this field. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared.
7:4ro0x0REPCNT_FAIL_COUNTThis field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared.
11:8ro0x0ADAPTP_HI_FAIL_COUNTThis field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared.
15:12ro0x0ADAPTP_LO_FAIL_COUNTThis field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared.
19:16ro0x0BUCKET_FAIL_COUNTThis field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared.
23:20ro0x0MARKOV_FAIL_COUNTThis field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared.


entropy_src.EXTHT_FAIL_COUNTS @ + 0x88
External health test alert failure counts register
Reset default = 0x0, mask 0xff
31302928272625242322212019181716
 
1514131211109876543210
  EXTHT_LO_FAIL_COUNT EXTHT_HI_FAIL_COUNT
BitsTypeResetNameDescription
3:0ro0x0EXTHT_HI_FAIL_COUNTThis field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared.
7:4ro0x0EXTHT_LO_FAIL_COUNTThis field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared.


entropy_src.DEBUG_STATUS @ + 0x8c
Debug status register
Reset default = 0x0, mask 0x80000003
31302928272625242322212019181716
DIAG  
1514131211109876543210
  ENTROPY_FIFO_DEPTH
BitsTypeResetNameDescription
1:0ro0x0ENTROPY_FIFO_DEPTHThis is the depth of the entropy source FIFO.
30:2Reserved
31ro0x0DIAGThis bit is for internal debug only.


entropy_src.SEED @ + 0x90
ENTROPY_SRC seed register
Reset default = 0xb, mask 0xf
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  LFSR_SEED
BitsTypeResetNameDescription
3:0rw0xbLFSR_SEEDSeed used to load into the LFSR for the initial state. This field will not update if the REGEN bit 0 is cleared.