ENTROPY_SRC DV document

Goals

DV
- Verify all ENTROPY_SRC IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
FPV
- Verify TileLink device protocol compliance with an SVA based testbench

Current status

Design features

For detailed information on ENTROPY_SRC design features, please see the ENTROPY_SRC HWIP technical specification.

Testbench architecture

ENTROPY_SRC testbench has been constructed based on the CIP testbench architecture.

Block diagram

Top level testbench

Top level testbench is located at hw/ip/entropy_src/dv/tb/tb.sv. It instantiates the ENTROPY_SRC DUT module hw/ip/entropy_src/rtl/entropy_src.sv. In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db:

Clock and reset interface
TileLink host interface
ENTROPY_SRC IOs
Interrupts (pins_if
Alerts (pins_if
Devmode (pins_if

Common DV utility components

The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

Global types & methods

All common types and methods defined at the package level can be found in entropy_src_env_pkg. Some of them in use are:

TL_agent

ENTROPY_SRC testbench instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into ENTROPY_SRC device.

Rng_agent

Entropy_src testbench instantiates this PUSH_pull_agent(/hw/dv/sv/push_pull_agent/README/) which models the rng source.

Csrng_agent

Entropy_src testbench instantiates this push_PULL_agent(/hw/dv/sv/push_pull_agent/README/) which models the csrng module.

UVM RAL Model

The ENTROPY_SRC RAL model is created with the ralgen FuseSoC generator script automatically when the simulation is at the build stage.

It can be created manually (separately) by running make in the hw/ area.

Stimulus strategy

Test sequences

All test sequences reside in hw/ip/entropy_src/dv/env/seq_lib. The entropy_src_base_vseq virtual sequence is extended from cip_base_vseq and serves as a starting point. All test sequences are extended from entropy_src_base_vseq. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. Some of the most commonly used tasks / functions are as follows:

entropy_src_init: Initialize the ENTROPY_SRC module from the randomized environment variables in the config.

Functional coverage

To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:

common covergroup for interrupts hw/dv/sv/cip_lib/cip_base_env_cov.sv: Cover interrupt value, interrupt enable, intr_test, interrupt pin

Self-checking strategy

Scoreboard

The entropy_src_scoreboard is primarily used for end to end checking. It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:

tl_a_chan_fifo, tl_d_chan_fifo: These 2 fifos provide transaction items at the end of Tilelink address channel and data channel respectively
rng_fifo, csrng_fifo: The rng_fifo provides transaction items from the predictor and the csrng_fifo provide actual post-entropy_src transaction items to compare

Assertions

TLUL assertions: The tb/entropy_src_bind.sv binds the tlul_assert assertions to the IP to ensure TileLink interface protocol compliance.
Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.

Building and running tests

We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:

$ cd hw/ip/entropy_src/dv
$ make TEST_NAME=entropy_src_smoke

Testplan

Testpoints

Milestone	Name	Tests	Description
V1	smoke	entropy_src_smoke	Enable entropy_src, wait for interrupt, verify entropy.
V1	csr_hw_reset	entropy_src_csr_hw_reset	Verify the reset values as indicated in the RAL specification. Write all CSRs with a random value. Apply reset to the DUT as well as the RAL model. Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.
V1	csr_rw	entropy_src_csr_rw	Verify accessibility of CSRs as indicated in the RAL specification. Loop through each CSR to write it with a random value. Read the CSR back and check for correctness while adhering to its access policies. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.
V1	csr_bit_bash	entropy_src_csr_bit_bash	Verify no aliasing within individual bits of a CSR. Walk a 1 through each CSR by flipping 1 bit at a time. Read the CSR back and check for correctness while adhering to its access policies. This verify that writing a specific bit within the CSR did not affect any of the other bits. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.
V1	csr_aliasing	entropy_src_csr_aliasing	Verify no aliasing within the CSR address space. Loop through each CSR to write it with a random value Shuffle and read ALL CSRs back. All CSRs except for the one that was written in this iteration should read back the previous value. The CSR that was written in this iteration is checked for correctness while adhering to its access policies. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.
V1	csr_mem_rw_with_rand_reset	entropy_src_csr_mem_rw_with_rand_reset	Verify random reset during CSR/memory access. Run csr_rw sequence to randomly access CSRs If memory exists, run mem_partial_access in parallel with csr_rw Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value It is mandatory to run this test for all available interfaces the CSRs are accessible from.
V2	firmware		Verify ability to access entropy register based on value of efuse input Verify es_regen bit enables/disables write access to control registers Verify registers at End-Of-Test
V2	firmware_mode		Verify health_checks aren't active Verify bypass active Verify read FIFO Random FIFO depths
V2	rng_mode	entropy_src_rng	Verify rng entropy Random FIFO depths Random rates Verify single_bit_mode for all bit_selector values Verify FIPS bits match predicted
V2	health_checks		Verify AdaptProp, RepCnt, RepCntSym, Bucket, Markov health check results match predicted. Generate passing and failing raw entropy streams Random window sizes Default and random hi/lo bypass/fips thresholds Enables/fail counts/clears Verify hi/lo bypass/fips watermarks Verify External health check behaves as predicted Verify outputs match internal reg values/entropy bus Pulse inputs and verify captured Verify health testing stops when no demand for entropy
V2	conditioning		Verify genbits seeds in bypass mode as predicted. Verify genbits seeds after shah3 conditioning as predicted.
V2	interrupts		Verify es_entropy_valid interrupt asserts as predicted. Verify es_health_test_failed interrupt asserts as predicted. Verify es_fifo_err interrupt asserts as predicted.
V2	alerts		Verify es_alert_count_met asserts as expected.
V2	stress_all	entropy_src_stress_all	Combine the individual test points while injecting TL errors and running CSR tests in parallel.
V2	fifo_errs		Verify they never occur with asserts
V2	intr_test	entropy_src_intr_test	Verify common intr_test CSRs that allows SW to mock-inject interrupts. Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s). Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s). Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR. Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set. Clear a random set of interrupts by writing a randomly value to intr_state CSR(s). Repeat the above steps a bunch of times.
V2	alert_test	entropy_src_alert_test	Verify common `alert_test` CSR that allows SW to mock-inject alert requests. Enable a random set of alert requests by writing random value to alert_test CSR. Check each `alert_tx.alert_p` pin to verify that only the requested alerts are triggered. During alert_handshakes, write `alert_test` CSR again to verify that: If `alert_test` writes to current ongoing alert handshake, the `alert_test` request will be ignored. If `alert_test` writes to current idle alert handshake, a new alert_handshake should be triggered. Wait for the alert handshakes to finish and verify `alert_tx.alert_p` pins all sets back to 0. Repeat the above steps a bunch of times.
V2	tl_d_oob_addr_access	entropy_src_tl_errors	Access out of bounds address and verify correctness of response / behavior
V2	tl_d_illegal_access	entropy_src_tl_errors	Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the [TLUL spec]({{< relref "hw/ip/tlul/doc/_index.md#explicit-error-cases" >}}) TL-UL protocol error cases invalid opcode some mask bits not set when opcode is `PutFullData` mask does not match the transfer size, e.g. `a_address = 0x00`, `a_size = 0`, `a_mask = 'b0010` mask and address misaligned, e.g. `a_address = 0x01`, `a_mask = 'b0001` address and size aren't aligned, e.g. `a_address = 0x01`, `a_size != 0` size is greater than 2 OpenTitan defined error cases access unmapped address, expect `d_error = 1` when `devmode_i == 1` write a CSR with unaligned address, e.g. `a_address[1:0] != 0` write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte write a memory with `a_mask != '1` when it doesn't support partial accesses read a WO (write-only) memory write a RO (read-only) memory
V2	tl_d_outstanding_access	entropy_src_csr_hw_reset entropy_src_csr_rw entropy_src_csr_aliasing entropy_src_same_csr_outstanding	Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.
V2	tl_d_partial_access	entropy_src_csr_hw_reset entropy_src_csr_rw entropy_src_csr_aliasing entropy_src_same_csr_outstanding	Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.
V3	tl_intg_err	entropy_src_tl_intg_err	Verify that the data integrity check violation generates an alert. Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.
V3	stress_all_with_rand_reset	entropy_src_stress_all_with_rand_reset	This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.

Covergroups

Name Description

tl_errors_cg

Name	Description
tl_errors_cg	Cover the following error cases on TL-UL bus: TL-UL protocol error cases. OpenTitan defined error cases, refer to testpoint `tl_d_illegal_access`.
tl_intg_err_cg	Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.
tl_intg_err_mem_subword_cg	Cover the kinds of integrity errors with byte enabled write on memory. Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.

Cover the following error cases on TL-UL bus:

TL-UL protocol error cases.
OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.

tl_intg_err_cg

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

tl_intg_err_mem_subword_cg

Cover the kinds of integrity errors with byte enabled write on memory.

Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.