ENTROPY_SRC DV Plan
- Verify all ENTROPY_SRC IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
- Verify TileLink device protocol compliance with an SVA based testbench
For detailed information on ENTROPY_SRC design features, please see the ENTROPY_SRC HWIP technical specification.
ENTROPY_SRC testbench has been constructed based on the CIP testbench architecture.
Top level testbench
Top level testbench is located at
hw/ip/entropy_src/dv/tb/tb.sv. It instantiates the ENTROPY_SRC DUT module
In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into
Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
Global types & methods
All common types and methods defined at the package level can be found in
entropy_src_env_pkg. Some of them in use are:
ENTROPY_SRC testbench instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into ENTROPY_SRC device.
UVM RAL Model
The ENTROPY_SRC RAL model is created with the
ralgen FuseSoC generator script automatically when the simulation is at the build stage.
It can be created manually (separately) by running
make in the
All test sequences reside in
entropy_src_base_vseq virtual sequence is extended from
cip_base_vseq and serves as a starting point.
All test sequences are extended from
It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:
- entropy_src_init: Initialize the ENTROPY_SRC module from the randomized environment variables in the config.
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:
- common covergroup for interrupts
hw/dv/sv/cip_lib/cip_base_env_cov.sv: Cover interrupt value, interrupt enable, intr_test, interrupt pin
entropy_src_scoreboard is primarily used for end to end checking.
It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:
- tl_a_chan_fifo, tl_d_chan_fifo: These 2 fifos provide transaction items at the end of Tilelink address channel and data channel respectively
- TLUL assertions: The
tlul_assertassertions to the IP to ensure TileLink interface protocol compliance.
- Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
Building and running tests
We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here's how to run a basic sanity test:
$ cd hw/ip/entropy_src/dv $ make TEST_NAME=entropy_src_sanity
Enable entropy_src in LFSR mode, wait for interrupt, verify entropy.
Verify the reset values as indicated in the RAL specification.
Verify accessibility of CSRs as indicated in the RAL specification.
Verify no aliasing within individual bits of a CSR.
Verify no aliasing within the CSR address space.
Verify random reset during CSR/memory access.
Verify entropy is not available via register if efuse input is 0.
Verify different seeds produce different entropy.
Verify rng activity does not affect lfsr operation.
Verify digital entropy for all fifo depths.
Verify rng entropy for various clk speeds, fifo_depths.
Verify rng single_bit_mode for all bit_selector values.
Verify es_regen bit enables/disables write access to control registers.
Verify entropy for various entropy_rate values.
Verify APT health check for various cutoff/window values.
Verify RCT health check for various cutoff values.
Verify correct conditions cause proper interrupts for all fifo depths.
This will combine the other individual testpoints while injecting TL errors and running CSR tests in parallel.
This will combine the other individual testpoints while injecting TL errors and running CSR tests in parallel and asserting reset in the middle of test.
Verify common intr_test CSRs that allows SW to mock-inject interrupts.
Access out of bounds address and verify correctness of response / behavior
Drive unsupported requests via TL interface and verify correctness of response / behavior
Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.
Do partial accesses.