Flash Controller HWIP Technical Specification

Overview

This document describes the flash controller functionality. The flash controller is broken down into 3 major components

  • Open source flash controller
  • Closed source vendor flash wrapper
  • Closed source vendor flash module

A breakdown of the 3 can be seen below Flash High Level Boundaries

This open source flash controller is divided into two partitions.

  • Flash protocol controller
  • Flash physical controller

The remaining document focuses primarily on the function of these blocks.

This module conforms to the Comportable guideline for peripheral functionality. See that document for integration overview within the broader top level system.

Features

Flash Protocol Controller Features

The flash protocol controller interfaces with software and other hardware components in the system (such as life cycle, key manager and OTP). Regardless of the flash size underneath, the flash controller maintains the same data resolution as the bus and processor (default 4B). The flash physical controller (see section below) is then responsible for bridging that size gap between the default data resolution and the actual flash memory.

The protocol controller currently supports the following features:

  • Controller initiated read, program and erase of flash.
    • Erase can be either of a page, or an entire bank.
  • Support for differentiation between informational and data flash partitions.
  • Support for accessing multiple types of information partition.
    • Some flash storage support multiple types of information storage for each information partition.
  • Parameterized support for burst program / read, up to 64B.
    • Longer programs / reads are supported, however the protocol controller will directly back-pressure the bus if software supplies more data than can be consumed, or if software reads more than there is data available.
    • Software can also choose to operate by polling the current state of the FIFO or through FIFO interrupts (empty / full / level).
  • Flash memory protection at page boundaries.
  • Life cycle RMA entry.
  • Key manager secret seeds that are inaccessible to software.
  • Support vendor flash module erase suspend.
  • Provisioning of flash specific attributes:
    • High endurance.
  • Idle indication to external power managers.
  • Software control of flash code fetch.

Flash Physical Controller Features

The flash physical controller wraps the actual flash memory and translates both host and controller initiated requests into low level flash transactions.

The physical controller supports the following features

  • Multiple banks of flash memory.
  • For each flash bank, parameterized support for number of flash pages (default to 256).
  • For each flash page, parameterized support for number of words and word size (default to 256 words of 8-bytes each).
  • Data and informational partitions within each bank of flash memory.
  • Arbitration between host requests and controller requests at the bank level.
    • Host requests are always favored, however the controller priority can escalate if it repeatedly loses arbitration.
    • Since banks are arbitrated independently and transactions may take different amounts of times to complete, the physical controller is also responsible for ensuring in-order response to both the controller and host.
  • Flash read stage.
    • Each bank maintains a parameterizable number of read buffers in front of the flash memory (default to 4).
    • The read buffers behave as miniature read-only-caches to store flash data when flash words are greater than bus words.
    • When a program or erase collides with an entry already stored in the read buffer, the buffer contents are invalidated.
      • This situation may arise if a read is followed by a program or erase.
  • Flash program stage
    • Flash data word packing when flash word size is an integer multiple of bus word size.
  • Flash scrambling
    • Flash supports XEX scrambling using the PRINCE cipher.
    • Scrambling is optional based on page boundaries and is configurable by software.
  • Two types of Flash ECC support.
    • A pre-scramble ICV (integrity check value) used for integrity verification implemented as ECC.
    • A post-scramble ECC used for reliability detection, this is configurable on a page boundary.
  • Life cycle modulated JTAG connection to the vendor flash module.

Flash Memory Overview

Unlike sram, flash memory is not typically organized as a contiguous block of generic storage. Instead it is organized into data partitions and information partitions.

The data partition holds generic data like a generic memory would. The information partition holds metadata about the data partition as well as design specific secret data. This includes but is not limited to:

  • Redundancy information.
  • Manufacturer specific information.
  • Manufacturer flash timing information.
  • Design specific unique seeds.
  • The redundancy pages themselves, which are not accessible directly as data partitions.

Note, there can be more than one information partition, and none of them are required to be the same size as the data partition. See the diagram below for an illustrative example. Flash Example Partition

Which type of partition is accessed is controlled through the CONTROL.PARTITION_SEL field. The current flash controller implements one type of information partition and thus is controlled by 1 bit only. This may change in the future.

Lastly, while the different partitions may be identical in some attributes, they are different in others.

  • All types of partitions must have the same page size and word size; however they are not required to have the same number of pages, thus some partitions may be larger and others smaller.
  • All types of partitions obey the same program and erase rules :
    • A bit cannot be programmed back to 1 once it has been programmed to 0.
    • Only erase can restore a bit to 1 under normal circumstances.
  • All partitions (data and information) can be read, programmed and erased by the flash protocol controller, subject to memory protection and life cycle qualification .
  • System hosts (processor and other entities) can only directly read the data partition, they do not have any kind of access to information partitions.
    • System hosts are also not subject to memory protection rules, as those apply to the flash protocol controller only.

For default assumptions of the design, see the default configuration.

Addresses Map

Bank Address

The flash address map is built upon the bank base address. The bank size is based upon the number of pages in the data partition. The first bank’s address is always 0x0. The second bank’s address is 0x0 + size_of_bank_in_bytes.

For example: Assume each bank is 512KB in size. The address of bank 0 is 0x0. The address of bank 1 is 0x80000

Page Address

The address of a particular page is calculated based on the page size and the index number of the page.

For example: Assume each page is 2KB in size.

To access page 0 in bank 1, the address would be the base address of bank 1 plus the base address of page 0. This would still be 0x80000 in this case.

To access page 4 in bank 1, the address would then be 0x80000 + 2KB * 4 = 0x82000.

Partition Access

All partitions share the same addressing scheme. For example, the page 0 address of any kind of partition is always the same.

To distinguish which partition is accessed, use the configuration in CONTROL.PARTITION_SEL and CONTROL.INFO_SEL Note however, the system host is only able to access the data partitions.

Default Address Map

Based on the default configuration, the following would be the default address map for each partition / page.

Location Address
Bank 0 Page 0 0x0
Bank 0 Page 1 0x800
Bank 0 Page 2 0x1000
Bank 0 Page 255 0x7F800
Bank 1 Page 0 0x80000
Bank 1 Page 1 0x80800
Bank 1 Page 2 0x81000
Bank 1 Page 255 0xFF800

Note when accessing from host, the system memory address for flash should be added to this offset.

Secret Information Partitions

Two information partition pages (one for creator and one for owner) in the design hold secret seeds for the key manager. These pages, when enabled by life cycle and OTP, are read upon flash controller initialization (no software configuration is required). The read values are then fed to the key manager for later processing. There is a page for creator and a page for the owner.

The seed pages can be programmed/erased/read by software when the following are set:

  • lc_creator_seed_sw_rw_en - allows software access to creator seed partition.
  • lc_owner_seed_sw_rw_en - allows software access to owner seed partition.

The seed pages are read under the following initialization conditions:

  • life cycle sets provision enable - lc_seed_hw_rd_en is set.

See life cycle for more details on when this partition is allowed to be populated.

Isolated Information Partitions

One information partition page in the design is used for manufacturing time authentication. The accessibility of this page is controlled by life cycle and OTP.

During TEST states, the isolated page is only programmable.

  • lc_iso_part_sw_wr_en is set, but lc_iso_part_sw_rd_en is not.

During production and RMA states, the isolated page is also readable.

  • Both lc_iso_part_sw_wr_en and lc_iso_part_sw_rd_en are set.

See life cycle for more details

Theory of Operation

Block Diagram

Flash Block Diagram

Flash Protocol Controller

The Flash Protocol Controller sits between the host software interface, other hardware components and the flash physical controller. Its primary functions are two fold

  • Translate software program, erase and read requests into a high level protocol for the actual flash physical controller
  • Act as communication interface between flash and other components in the system, such as life cycle and key manager.

The flash protocol controller is not responsible for the detailed timing and waveform control of the flash, nor is it responsible for data scrambling and reliability metadata such as ICV and ECC. Instead, it maintains FIFOs / interrupts for the software to process data, as well as high level abstraction of region protection controls and error handling.

The flash controller selects requests between the software and hardware interfaces. By default, the hardware interfaces have precedence and are used to read out seed materials from flash. The seed material is read twice to confirm the values are consistent. They are then forwarded to the key manager for processing. During this seed phase, software initiated activities are back-pressured until the seed reading is complete. It is recommended that instead of blindly issuing transactions to the flash controller, the software polls STATUS.INIT_WIP until it is 0.

Once the seed phase is complete, the flash controller switches to the software interface. Software can then read / program / erase the flash as needed.

RMA Entry Handling

When an RMA entry request is received from the life cycle manager, the flash controller waits for any pending flash transaction to complete, then switches priority to the hardware interface. The flash controller then initiates RMA entry process and notifies the life cycle controller when it is complete. The RMA entry process wipes out all data, creator, owner and isolated partitions.

After RMA completes, the flash controller is disabled. When disabled the flash protocol controller registers can still be accessed. However, flash memory access are not allowed, either directly by the host or indirectly through flash protocol controller initiated transactions. It is expected that after an RMA transition, the entire system will be rebooted.

Initialization

The flash protocol controller is initialized through INIT. When initialization is invoked, the flash controller requests the address and data scrambling keys from an external entity, otp_ctrl in this case.

After the scrambling keys are requested, the flash protocol controller reads the root seeds out of the secret partitions and sends them to the key manager. Once the above steps are completed, the read buffers in the flash physical controller are enabled for operation.

RMA Entry

During RMA entry, the flash controller “wipes” the contents of the following:

  • Creator partition
  • Owner partition
  • Isolated partition
  • All data partitions

This process ensures that after RMA there is no sensitive information left that can be made use on the tester. As stated previously, once RMA entry completes, the flash memory can no longer be accessed, either directly or indirectly. The flash controller registers however, remain accessible for status reads and so forth, although new operations cannot be issued.

Memory Protection

Flash memory protection is handled differently depending on what type of partition is accessed.

For data partitions, software can configure a number of memory protection regions such as MP_REGION_CFG_0. For each region, software specifies both the beginning page and the number of pages that belong to that region. Software then configures the access privileges for that region. Finally, each region can be activated or de-activated from matching through MP_REGION_CFG_0.EN.

Subsequent accesses are then allowed or denied based on the defined rule set. Similar to RISCV pmp, if two region overlaps, the lower region index has higher priority.

For information partitions, the protection is done per individual page. Each page can be configured with access privileges. As a result, software does not need to define a start and end page for information partitions. See BANK0_INFO0_PAGE_CFG_0 as an example.

Bank Erase Protection

Unlike read, program and page erase operations, the bank erase command is the only one that can be issued at a bank level. Because of this, bank erase commands are not guarded by the typical memory protection mechanisms.

Instead, whether bank erase is allowed is controlled by MP_BANK_CFG_SHADOWED, where there is a separate configuration bit per bank. When the corresponding bit is set, that particular bank is permitted to have bank level operations.

The specific behavior of what is erased when bank erase is issued is flash memory dependent and thus can vary by vendor and technology. This section describes the general behavior and how open source modeling is done.

Memory Protection for Key Manager and Life Cycle

While memory protection is largely under software control, certain behavior is hardwired to support key manager secret partitions and life cycle functions.

Software can only control the accessibility of the creator secret seed page under the following condition(s):

  • life cycle sets provision enable.
  • OTP indicates the seeds are not locked.

Software can only control the accessibility of the owner secret seed page under the following condition(s):

  • life cycle sets provision enable.

During life cycle RMA transition, the software configured memory protection for both data and information partitions is ignored. Instead, the flash controller assumes a default accessibility setting that allows it to secure the chip and transition to RMA.

Program Resolution

Certain flash memories place restrictions on the program window. This means the flash accepts program beats only if all beats belong to the same address window. Typically, this boundary is nicely aligned (for example, 16 words, 32 words) and is related to how the flash memory amortizes the program operation over nearby words.

To support this function, the flash controller errors back anytime the start of the program beat is in a different window from the end of the program beat. The valid program range is thus the valid program resolution for a particular memory.

This information is not configurable but instead decided at design time and is exposed as a readable status.

Erase Suspend

The flash controller supports erase suspend through ERASE_SUSPEND. This allows the software to interrupt an ongoing erase operation.

The behavior of what happens to flash contents when erase is suspended is vendor defined; however, generally it can be assumed that the erase would be incomplete. It is then up to the controlling software to take appropriate steps to erase again at a later time.

Additional Flash Attributes

There are certain attributes provisioned in MP_REGION_CFG_0 that are not directly used by the open source protocol or physical controllers.

Instead, these attributes are fed to the vendor flash module on a per-page or defined boundary basis. Currently there is only one such attribute MP_REGION_CFG_0.HE.

Idle Indication to External Power Manager

The flash controller provides an idle indication to an external power manager. This idle indication does not mean the controller is doing “nothing”, but rather the controller is not doing anything “stateful”, e.g. program or erase.

This is because an external power manager event (such as shutting off power) while a flash stateful transaction is ongoing may be damaging to the vendor flash module.

Flash Code Execution Handling

Flash can be used to store both data and code. To support separate access privileges between data and code, the flash protocol controller provides EXEC for software control.

If software programs EXEC to 0xa26a38f7, code fetch from flash is allowed. If software programs EXEC to any other value, code fetch from flash results in an error.

The flash protocol controller distinguishes code / data transactions through the instruction type attribute of the TL-UL interface.

Flash Errors and Faults

The flash protocol controller maintains 3 different categories of observed errors and faults. In general, errors are considered recoverable and primarily geared towards problems that could have been caused by software or that occurred during a software initiated operation. Errors can be found in ERR_CODE.

Faults, on the other hand, represent error events that are unlikely to have been caused by software and represent a major malfunction of the system.

Faults are further divided into two categories:

  • Standard faults
  • Custom faults

Standard faults represent errors that occur in the standard structures of the design, for example sparsely encoded FSMs, duplicated counters and the bus transmission integrity scheme.

Custom faults represent custom errors, primarily errors generated by the life cycle management interface, the flash storage integrity interface and the flash macro itself.

See (#flash-escalation) for further differentiation between standard and custom faults.

Transmission Integrity Faults

Since the flash controller has multiple interfaces for access, transmission integrity failures can manifest in different ways.

There are 4 interfaces:

The impact of transmission integrity of each interface is described below.

Host Direct Access to Flash Controller Register Files

This category of transmission integrity behaves identically to other modules. A bus transaction, when received, is checked for command and data payload integrity. If an integrity error is seen, the issuing bus host receives an in-band error response and a fault is registered in STD_FAULT_STATUS.REG_INTG_ERR.

Host Direct Access to Flash Macro

Flash can only be read by the host. The transmission integrity scheme used is end-to-end, so integrity generated inside the flash is fed directly to the host. It is the host’s responsibility to check for integrity correctness and react accordingly.

Host / Software Initiated Access to Flash Macro

Since controller operations are initiated through writes to the register file, the command check is identical to host direct access to regfiles. Controller reads behave similarly to host direct access to macro, the read data and its associated integrity are returned through the controller read FIFO for the initiating host to handle.

For program operations, the write data and its associated integrity are stored and propagated through the flash protocol and physical controllers. Prior to packing the data for final flash program, the data is then checked for integrity correctness. If the data integrity is incorrect, an in-band error response is returned to the initiating host and an error is registered in ERR_CODE.PROG_INTG_ERR. An error is also registered in STD_FAULT_STATUS.PROG_INTG_ERR to indicate that a fatal fault has occurred.

The reasons a program error is registered in two locations are two-fold:

  • It is registered in ERR_CODE so software can discover during operation status that a program has failed.
  • It is registered in STD_FAULT_STATUS because transmission integrity failures represent a fatal failure in the standard structure of the design, something that should never happen.
Life Cycle Management Interface / Hardware Initiated Access to Flash Macro

The life cycle management interface issues transactions directly to the flash controller and does not perform a command payload integrity check.

For read operations, the read data and its associated integrity are directly checked by the life cycle management interface. If an integrity error is seen, it is registered in FAULT_STATUS.LCMGR_INTG_ERR.

For program operations, the program data and its associated integrity are propagated into the flash controller. If an integrity error is seen, an error is registered in FAULT_STATUS.PROG_INTG_ERR.

In addition to transmission integrity errors described above, the flash can also emit read errors based on ECC and ICV checks.

Flash reliability ECC errors (multi-bit errors) and integrity check errors (integrity check errors) are both reflected as in-band errors to the entity that issued the transaction. That means if a host direct read, controller initiated read or hardware initiated read encounters one of these errors, the error is directly reflected in the operation status.

Further, reliability ECC / integrity check errors are also captured in FAULT_STATUS and can be used to generate fatal alerts. The reason these are not captured in STD_FAULT_STATUS is because 1 or 2 bit errors can occur in real usage due to environmental conditions, thus they do not belong to the standard group of structural errors. If we assume 2-bit errors can occur, then software must have a mechanism to recover from the error instead of escalation.

Flash Escalation

Flash has two sources of escalation - global and local.

Global escalation is triggered by the life cycle controller through lc_escalate_en. Local escalation is triggered by a standard faults of flash, seen in STD_FAULT_STATUS. Local escalation is not configurable and automatically triggers when this subset of faults are seen.

For the escalation behavior, see flash access disable .

Flash Access Disable

Flash access can be disabled through global escalation trigger, local escalation trigger, rma process completion or software command. The escalation triggers are described here. The software command to disable flash can be found in DIS. The description for rma entry can be found here.

When disabled, the flash has a two layered response:

  • The flash protocol controller memory protection errors back all controller initiated operations.
  • The host-facing tlul adapter errors back all host initiated operations.
  • The flash physical controller completes any existing stateful operations (program or erase) and drops all future flash transactions.
  • The flash protocol controller arbiter completes any existing software issued commands and enters a disabled state where no new transactions can be issued.

Flash Physical Controller

The Flash Physical Controller is the wrapper module that contains the actual flash memory instantiation. It is responsible for arbitrating high level protocol commands (such as read, program, erase) as well as any additional security (scrambling) and reliability (ECC) features. The contained vendor wrapper module is then responsible for converting high level commands into low level signaling and timing specific to a particular flash vendor. The vendor wrapper module is also responsible for any BIST, redundancy handling, remapping features or custom configurations required for the flash.

The scramble keys are provided by an external static block such as the OTP.

Host and Protocol Controller Handling

Both the protocol controller and the system host converge on the physical controller. The protocol controller has read access to all partitions as well as program and erase privileges. The host on the other hand, can only read the data partitions.

Even though the host has less access to flash, it is prioritized when competing against the protocol controller for access. When a host request and a protocol controller request arrive at the same time, the host is favored and granted. Every time the protocol controller loses such an arbitration, it increases an arbitration lost count. Once this lost count reaches 5, the protocol controller is favored. This ensures a stream of host activity cannot deny protocol controller access (for example a tight polling loop).

Flash Bank Erase Behavior

This section describes the open source modeling of flash memory. The actual flash memory behavior may differ, and should consult the specific vendor or technology specification.

When a bank erase command is issued and allowed, see bank erase protection, the erase behavior is dependent on CONTROL.PARTITION_SEL.

  • If data partition is selected, all data in the data partition is erased.
  • If info partition is selected, all data in the data partition is erased AND all data in the info partitions (including all info types) is also erased.

Flash Scrambling

Flash scrambling is built using the XEX tweakable block cipher.

When a read transaction is sent to flash, the following steps are taken:

  • The tweak is calculated using the transaction address and a secret address key through a Galois multiplier.
  • The data content is read out of flash.
  • If the data content is scrambled, the tweak is XOR’d with the scrambled text and then decrypted through the PRINCE block cipher using a secret data key.
  • The output of the PRINCE cipher is XOR’d again with the tweak and the final results are presented.
  • If the data content is not scrambled, the PRINCE cipher and XOR steps are skipped and data provided directly back to the requestor.

When a program transaction is sent to flash, the same steps are taken if the address in question has scrambling enabled. During a program, the text is scrambled through the PRINCE block cipher.

Scramble enablement is done differently depending on the type of partitions.

  • For data partitions, the scramble enablement is done on contiguous page boundaries.
    • Software has the ability to configure these regions and whether scramble is enabled.
  • For information partitions, the scramble enablement is done on a per page basis.
    • Software can configure for each page whether scramble is enabled.

Flash ECC and ICV

Flash supports both ECC (error correction) and ICV (integrity check value). While the two are used for different functions, they are implemented as two separate ECCs, thus flash supports two types of ECC.

ICV is an integrity check, implemented as an ECC, used to detect whether the de-scrambled data has been modified. The other is a reliability ECC used for error detection and correction on the whole flash word.

The key differentiation here is that ICV is used only for detection, while the real error correction can correct single bit errors. Both ICV and ECC are configurable based on the various page and memory property configurations.

Overall ICV and ECC Application

The following diagram shows how the various ICV / ECC tags are applied and used through the life of a transactions. Flash ECC_LIFE.

Note that the ICV (integrity ECC) is calculated over the descrambled data and is only 4-bits, while the reliability ECC is calculated over both the scrambled data and the ICV.

ICV

The purpose of the ICV (integrity check value, implemented as an ECC) is to emulate end-to-end integrity like the other memories. This is why the data is calculated over the descrambled data as it can be stored alongside for continuous checks. When descrambled data is returned to the host, the ICV is used to validate the data is correct.

The flash may not always have the capacity to store both the ICV and reliability ECC, the ICV is thus truncated since it is not used for error correction.

Reliability ECC

Similar to scrambling, the reliability ECC is enabled based on an address decode. The ECC for flash is chosen such that a fully erased flash word has valid ECC. Likewise a flash word that is completely 0 is also valid ECC.

Unlike the integrity ECC, the reliability ECC is actually used for error correction if an accidental bit-flip is seen, it is thus fully stored and not truncated.

ECC enablement is done differently depending on the type of partitions.

  • For data partitions, the ECC enablement is done on contiguous page boundaries.
    • Software has the ability to configure these regions and whether ECC is enabled.
  • For information partitions,the ECC enablement is done on a per page basis.
    • Software can configure for each page whether ECC is enabled.
Scrambling Consistency

The flash physical controller does not keep a history of when a particular memory location has scrambling enabled or disabled. This means if a memory location was programmed while scrambled, disabling scrambling and then reading it back will result in garbage. Similarly, if a location was programmed while non-scrambled, enabling scrambling and then reading it back will also result in garbage.

It it thus the programmer’s responsibility to maintain a consistent definition of whether a location is scrambled. It is also highly recommended in a normal use case to setup up scramble and non-scramble regions and not change it further.

Flash Read Pipeline

Since the system host reads directly from the flash for instructions, it is critical to not add significant latency during read, especially if de-scrambling is required. As such, the flash read is actually a two stage pipeline, where each stage can take multiple cycles.

Additionally, since the flash word size is typically larger than the bus word, recently read flash entries are locally cached. The cache behaves as a highly simplified read-only-cache and holds by default 4 flash words per flash bank.

When a read transaction is sent to flash, the following steps are taken:

  • A check is performed against the local cache
    • If there is a hit (either the entry is already in cache, or the entry is currently being processed), the transaction is immediately forwarded to the response queue.
    • If there is not a hit, an entry in the local cache is selected for allocation (round robin arbitration) and a flash read is issued.
  • When the flash read completes, its descrambling attributes are checked:
    • If descrambling is required, the read data begins the descrambling phase - at this time, a new flash read can be issued for the following transaction.
    • if descrambling is not required, the descrambling phase is skipped and the transaction is pushed to the response queue.
  • When the descrambling is complete, the descrambled text is pushed to the response queue.

The following diagram shows how the flash read pipeline timing works. Flash Read Pipeline

In this example, the first two host requests trigger a full sequence. The third host requests immediately hits in the local cache and responds in order after the first two.

Flash Buffer

The flash buffer is a small read-only memory that holds multiple entries of recently read flash words. This is needed when the flash word is wider than a bus word. The flash access time is amortized across the the entire flash word if software accesses in a mostly linear sequence.

The flash buffer has a round robin replacement policy when more flash words are read. When an erase / program is issued to the flash, the entries are evicted to ensure new words are fetched.

When a page erase / program is issued to a flash bank, only entries that fall into that address range are evicted. When a bank erase is issued, then all entries are evicted.

The flash buffer is only enabled after INIT is invoked. When an RMA entry sequence is received, the flash buffers are disabled.

As an example, assume a flash word is made up of 2 bus words. Assume also the following address to word mapping:

  • Address 0 - flash word 0, bus word 0 / bus word 1
  • Address 2 - flash word 1, bus word 2 / bus word 3

When software reads bus word 1, the entire flash word 0 is captured into the flash buffer. When software comes back to read bus word 0, instead of accessing the flash again, the data is retrieved directly from the buffer.

The recently read entries store both the de-scrambled data and the integrity ECC. The reliability ECC is not stored because the small buffer is purely flip-flop based and does not have storage reliability concerns like the main flash macro.

When a read hits in the flash buffer, the integrity ECC is checked against the de-scrambled data and an error is returned to the initiating entity, whether it is a the controller itself or a host.

Accessing Information Partition

The information partition uses the same address scheme as the data partition - which is directly accessible by software. This means the address of page{N}.word{M} is the same no matter which type of partition is accessed.

Which partition a specific transaction accesses is denoted through a separate field CONTROL.PARTITION_SEL in the CONTROL register. If CONTROL.PARTITION_SEL is set, then the information partition is accessed. If CONTROL.PARTITION_SEL is not set, then the corresponding word in the data partition is accessed.

Flash scrambling, if enabled, also applies to information partitions. It may be required for manufacturers to directly inject data into specific pages flash information partitions via die contacts. For these pages, scramble shall be permanently disabled as the manufacturer should not be aware of scrambling functions.

JTAG Connection

The flash physical controller provides a JTAG connection to the vendor flash module. The vendor flash module can use this interface to build a testing setup or to provide backdoor access for debug.

Due to the ability of this connection to bypass access controls, this connection is modulated by life cycle and only enabled when non-volatile debug, or lc_nvm_debug_en is allowed in the system.

Flash Default Configuration

Since the flash controller is highly dependent on the specific flavor of flash memory chosen underneath, its configuration can vary widely between different integrations.

This sections details the default settings used by the flash controller:

  • Number of banks: 2
  • Number of data partition pages per bank: 256
  • Program resolution: 8 flash words
  • Flash word data bits: 64
  • Flash word metadata bits: 8
  • ECC choice: Hamming code SECDED
  • Information partition types: 3
  • Number of information partition type 0 pages per bank: 10
  • Number of information partition type 1 pages per bank: 1
  • Number of information partition type 2 pages per bank: 2
  • Secret partition 0 (used for creator): Bank 0, information partition 0, page 1
  • Secret partition 1 (used for owner): Bank 0, information partition 0, page 2
  • Isolated partition: Bank 0, information partition 0, page 3

Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module flash_ctrl has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: clk_otp_i

Bus Device Interfaces (TL-UL): core_tl, prim_tl, mem_tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO:

Pin namedirectionDescription
tckinput

jtag clock

tmsinput

jtag tms

tdiinput

jtag input

tdooutput

jtag output

Inter-Module Signals: Reference

Inter-Module Signals
Port Name Package::Struct Type Act Width Description
otp otp_ctrl_pkg::flash_otp_key req_rsp req 1
lc_nvm_debug_en lc_ctrl_pkg::lc_tx uni rcv 1
flash_bist_enable prim_mubi_pkg::mubi4 uni rcv 1
flash_power_down_h logic uni rcv 1
flash_power_ready_h logic uni rcv 1
flash_test_mode_a io none 2
flash_test_voltage_h io none 1
lc_creator_seed_sw_rw_en lc_ctrl_pkg::lc_tx uni rcv 1
lc_owner_seed_sw_rw_en lc_ctrl_pkg::lc_tx uni rcv 1
lc_iso_part_sw_rd_en lc_ctrl_pkg::lc_tx uni rcv 1
lc_iso_part_sw_wr_en lc_ctrl_pkg::lc_tx uni rcv 1
lc_seed_hw_rd_en lc_ctrl_pkg::lc_tx uni rcv 1
lc_escalate_en lc_ctrl_pkg::lc_tx uni rcv 1
rma_req lc_ctrl_pkg::lc_tx uni rcv 1
rma_ack lc_ctrl_pkg::lc_tx uni req 1
rma_seed lc_ctrl_pkg::lc_flash_rma_seed uni rcv 1
pwrmgr pwrmgr_pkg::pwr_flash uni req 1
keymgr flash_ctrl_pkg::keymgr_flash uni req 1
obs_ctrl ast_pkg::ast_obs_ctrl uni rcv 1
fla_obs logic uni req 8
core_tl tlul_pkg::tl req_rsp rsp 1
prim_tl tlul_pkg::tl req_rsp rsp 1
mem_tl tlul_pkg::tl req_rsp rsp 1

Interrupts:

Interrupt NameTypeDescription
prog_emptyEvent

Program FIFO empty

prog_lvlEvent

Program FIFO drained to level

rd_fullEvent

Read FIFO full

rd_lvlEvent

Read FIFO filled to level

op_doneEvent

Operation complete

corr_errEvent

Correctable error encountered

Security Alerts:

Alert NameDescription
recov_err

flash recoverable errors

fatal_std_err

flash standard fatal errors

fatal_err

flash fatal errors

fatal_prim_flash_alert

Fatal alert triggered inside the flash primitive, including fatal TL-UL bus integrity faults of the test interface.

recov_prim_flash_alert

Recoverable alert triggered inside the flash primitive.

Security Countermeasures:

Countermeasure IDDescription
FLASH_CTRL.REG.BUS.INTEGRITY

End-to-end bus integrity scheme. Since there are multiple access points for flash, please see Transmission Integrity Faults in the documentation for more details.

The bus integrity scheme for flash is different from other comportable modules.

FLASH_CTRL.HOST.BUS.INTEGRITY

End-to-end bus integrity scheme. Since there are multiple access points for flash, please see Transmission Integrity Faults in the documentation for more details.

The bus integrity scheme for flash is different from other comportable modules.

FLASH_CTRL.MEM.BUS.INTEGRITY

End-to-end bus integrity scheme. Since there are multiple access points for flash, please see Transmission Integrity Faults in the documentation for more details.

The bus integrity scheme for flash is different from other comportable modules.

FLASH_CTRL.SCRAMBLE.KEY.SIDELOAD

The scrambling key is sideloaded from OTP and thus unreadable by SW.

FLASH_CTRL.LC_CTRL.INTERSIG.MUBI

Life cycle control signals are used control information partition access and flash debug access. See secret information partition, isolated information partitions and jtag connection in documentation for more details.

FLASH_CTRL.CTRL.CONFIG.REGWEN

Configurations cannot be changed when an operation is ongoing.

FLASH_CTRL.DATA_REGIONS.CONFIG.REGWEN

Each data region has a configurable regwen.

FLASH_CTRL.DATA_REGIONS.CONFIG.SHADOW

Data region configuration is shadowed.

FLASH_CTRL.INFO_REGIONS.CONFIG.REGWEN

Each info page of each type in each bank has separate regwen.

FLASH_CTRL.INFO_REGIONS.CONFIG.SHADOW

Each info page is shadowed.

FLASH_CTRL.BANK.CONFIG.REGWEN

Each bank has separate regwen for bank erase.

FLASH_CTRL.BANK.CONFIG.SHADOW

Each bank has separate regwen for bank erase.

FLASH_CTRL.MEM.CTRL.GLOBAL_ESC

Global escalation causes memory to no longer be accessible.

FLASH_CTRL.MEM.CTRL.LOCAL_ESC

A subset of fatal errors cause memory to no longer be accessible. This subset is defined in STD_FAULT_STATUS.

FLASH_CTRL.MEM_DISABLE.CONFIG.MUBI

Software control for flash disable is multibit. The register is DIS.

FLASH_CTRL.EXEC.CONFIG.REDUN

Software control for flash enable is 32-bit constant. The register is EXEC.

FLASH_CTRL.MEM.SCRAMBLE

The flash supports XEX scrambling. The cipher used is PRINCE. The scrambling scheme is enabled by software, please see flash scrambling in documentation for more details.

FLASH_CTRL.MEM.INTEGRITY

The flash supports two layers of ECC integrity: one layer is for integrity, and the other layer is for reliability. These ECCs are enabled and disabled together by software. Please see Flash ECC in the documentation for more details.

FLASH_CTRL.RMA_ENTRY.MEM.SEC_WIPE

RMA entry entry wipes flash memory with random data.

FLASH_CTRL.CTRL.FSM.SPARSE

RMA handling FSMs in flash_ctrl_lcmgr are sparsely encoded. FSM in flash_ctrl_arb is sparsely encoded.

FLASH_CTRL.PHY.FSM.SPARSE

PHY FSMs are sparsely encoded.

FLASH_CTRL.PHY_PROG.FSM.SPARSE

PHY program FSMs are sparsely encoded.

FLASH_CTRL.CTR.REDUN

flash_ctrl_lcmgr handling counters are redundantly encoded. This includes seed count and address count used during seed reading phase, as well as word count, page count and wipe index in RMA entry phase.

FLASH_CTRL.PHY_ARBITER.CTRL.REDUN

The phy arbiter for controller and host is redundant. The arbiter has two instance underneath that are constantly compared to each other.

FLASH_CTRL.PHY_HOST_GRANT.CTRL.CONSISTENCY

The host grant is consistency checked. If the host is ever granted with info partition access, it is an error. If the host is ever granted at the same time as a program/erase operation, it is an error.

FLASH_CTRL.PHY_ACK.CTRL.CONSISTENCY

If the host or controller ever receive an unexpeced transaction acknowledge, it is an error.

FLASH_CTRL.FIFO.CTR.REDUN

The FIFO pointers of several FIFOs are implemented with duplicate counters.

Signals

In addition to the interrupts and bus signals, the tables below lists the flash controller functional I/Os.

Signal Direction Description
lc_creator_seed_sw_rw_en input Indication from lc_ctrl that software is allowed to read/write creator seed.
lc_owner_seed_sw_rw_en input Indication from lc_ctrl that software is allowed to read/write owner seed.
lc_seed_hw_rd_en input Indication from lc_ctrl that hardware is allowed to read creator / owner seeds.
lc_iso_part_sw_rd_en input Indication from lc_ctrl that software is allowed to read the isolated partition.
lc_iso_part_sw_wr_en input Indication from lc_ctrl that software is allowed to write the isolated partition.
lc_escalate_en input Escalation indication from lc_ctrl.
lc_nvm_debug_en input Indication from lc_ctrl that non-volatile memory debug is allowed.
core_tl input/output TL-UL interface used to access flash_ctrl registers for activating program / erase and reads to information partitions/
prim_tl input/output TL-UL interface used to access the vendor flash memory proprietary registers.
mem_tl input/output TL-UL interface used by host to access the vendor flash memory directly.
OTP input/output Interface used to request scrambling keys from otp_ctrl.
rma_req input rma entry request from lc_ctrl.
rma_ack output rma entry acknowlegement to lc_ctrl.
rma_seed input rma entry seed.
pwrmgr output Idle indication to pwrmgr.
keymgr output Secret seed bus to keymgr.

In addition to the functional IOs, there are a set of signals that are directly connected to vendor flash module.

Signal Direction Description
scan_en input scan enable
scanmode input scan mode
scan_rst_n input scan reset
flash_bist_enable input enable flash built-in-self-test
flash_power_down_h input flash power down indication, note this is NOT a core level signal
flash_power_ready_h input flash power ready indication, note this is NOT a core level signal
flash_test_mode_a input/output flash test mode io, note this is NOT a core level signal
flash_test_voltage_h input/output flash test voltage, note this is NOT a core level signal
flash_alert output flash alert outputs directly to AST

Design Details

Flash Protocol Controller Description

The flash protocol controller uses a simple FIFO interface to communicate between the software and flash physical controller. There is a read FIFO for read operations, and a program FIFO for program operations. Note, this means flash can be read both through the controller and the main bus interface. This may prove useful if the controller wishes to allocate specific regions to HW FSMs only, but is not a necessary feature.

When software initiates a read transaction of a programmable number of flash words, the flash controller will fill up the read FIFO for software to consume. Likewise, when software initiates a program transaction, software will fill up the program FIFO for the controller to consume.

The controller is designed such that the overall number of words in a transaction can significantly exceed the FIFO depth. In the case of read, once the FIFO is full, the controller will cease writing more entries and wait for software to consume the contents (an interrupt will be triggered to the software to alert it to such an event). In the case of program, the controller will stop writing to flash once all existing data is consumed - it will likewise trigger an interrupt to software to prepare more data. See detailed steps in theory of operation. The following is a diagram of the controller construction as well as its over connectivity with the flash module.

Flash Protocol Controller

Host Read

Unlike controller initiated reads, host reads have separate rdy / done signals to ensure transactions can be properly pipelined. As host reads are usually tied to host execution upstream, additional latency can severely harm performance and is not desired. The expected waveform from the perspective of the physical controller is shown below.

The host_req_done_o is always single cycle pulsed and upstream logic is expected to always accept and correctly handle the return. The same cycle the return data is posted a new command / address can be accepted. While the example shows flash reads completing in back to back cycles, this is typically not the case.

Controller Read

Unlike host reads, controller reads are not as performance critical and do not have command / data pipeline requirements. Instead, the protocol controller will hold the read request and address lines until the done is seen. Once the done is seen, the controller then transitions to the next read operation. The expected waveform from the perspective of the physical controller is shown below.

Controller Program

Program behavior is similar to reads. The protocol controller will hold the request, address and data lines until the programming is complete. The expected waveform from the perspective of the physical controller is shown below.

Programmers Guide

Issuing a Controller Read

To issue a flash read, the programmer must

  • Specify the address of the first flash word to read
  • Specify the number of total flash words to read, beginning at the supplied address
  • Specify the operation to be ‘READ’ type
  • Set the ‘START’ bit for the operation to begin

The above fields can be set in the CONTROL and ADDR registers. See library code for implementation.

It is acceptable for total number of flash words to be significantly greater than the depth of the read FIFO. In this situation, the read FIFO will fill up (or hit programmable fill value), pause the flash read and trigger an interrupt to software. Once there is space inside the FIFO, the controller will resume reading until the appropriate number of words have been read. Once the total count has been reached, the flash controller will post OP_DONE in the OP_STATUS register.

Issuing a Controller Program

To program flash, the same procedure as read is followed. However, instead of setting the CONTROL register for read operation, a program operation is selected instead. Software will then fill the program FIFO and wait for the controller to consume this data. Similar to the read case, the controller will automatically stall when there is insufficient data in the FIFO. When all desired words have been programmed, the controller will post OP_DONE in the OP_STATUS register.

Debugging a Read Error

Since flash has multiple access modes, debugging read errors can be complicated. The following lays out the expected cases.

Error Encountered by Software Direct Read

If software reads the flash directly, it may encounter a variety of errors (read data integrity / ECC failures, both reliability and integrity). ECC failures create in-band error responses and should be recognized as a bus exception. Read data integrity failures also create exceptions directly inside the processor as part of end-to-end transmission integrity.

From these exceptions, software should be able to determine the error address through processor specific means. Once the address is discovered, further steps can be taken to triage the issue.

Error Encountered by Software Initiated Controller Operations

A controller operation can encounter a much greater variety of errors, see ERR_CODE. When such an error is encountered, as reflected by OP_STATUS when the operation is complete, software can examine the ERR_ADDR to determine the error location. Once the address is discovered, further steps can be taken to triage the issue.

Correctable ECC Errors

Correctable ECC errors are by nature not fatal errors and do not stop operation. Instead, if the error is correctable, the flash controller fixes the issue and registers the last address where a single bit error was seen. See ECC_SINGLE_ERR_CNT and ECC_SINGLE_ERR_ADDR

Device Interface Functions (DIFs)

To use this DIF, include the following C header:

#include "sw/device/lib/dif/dif_flash_ctrl.h"

This header provides the following device interface functions:

Register Table

The flash protocol controller maintains two separate access windows for the FIFO. It is implemented this way because the access window supports transaction back-pressure should the FIFO become full (in case of write) or empty (in case of read).

Registers visible under device interface core

Summary
Name Offset Length Description
flash_ctrl.INTR_STATE 0x0 4

Interrupt State Register

flash_ctrl.INTR_ENABLE 0x4 4

Interrupt Enable Register

flash_ctrl.INTR_TEST 0x8 4

Interrupt Test Register

flash_ctrl.ALERT_TEST 0xc 4

Alert Test Register

flash_ctrl.DIS 0x10 4

Disable flash functionality

flash_ctrl.EXEC 0x14 4

Controls whether flash can be used for code execution fetches

flash_ctrl.INIT 0x18 4

Controller init register

flash_ctrl.CTRL_REGWEN 0x1c 4

Controls the configurability of the CONTROL register.

flash_ctrl.CONTROL 0x20 4

Control register

flash_ctrl.ADDR 0x24 4

Address for flash operation

flash_ctrl.PROG_TYPE_EN 0x28 4

Enable different program types

flash_ctrl.ERASE_SUSPEND 0x2c 4

Suspend erase

flash_ctrl.REGION_CFG_REGWEN_0 0x30 4

Memory region registers configuration enable.

flash_ctrl.REGION_CFG_REGWEN_1 0x34 4

Memory region registers configuration enable.

flash_ctrl.REGION_CFG_REGWEN_2 0x38 4

Memory region registers configuration enable.

flash_ctrl.REGION_CFG_REGWEN_3 0x3c 4

Memory region registers configuration enable.

flash_ctrl.REGION_CFG_REGWEN_4 0x40 4

Memory region registers configuration enable.

flash_ctrl.REGION_CFG_REGWEN_5 0x44 4

Memory region registers configuration enable.

flash_ctrl.REGION_CFG_REGWEN_6 0x48 4

Memory region registers configuration enable.

flash_ctrl.REGION_CFG_REGWEN_7 0x4c 4

Memory region registers configuration enable.

flash_ctrl.MP_REGION_CFG_0 0x50 4

Memory property configuration for data partition

flash_ctrl.MP_REGION_CFG_1 0x54 4

Memory property configuration for data partition

flash_ctrl.MP_REGION_CFG_2 0x58 4

Memory property configuration for data partition

flash_ctrl.MP_REGION_CFG_3 0x5c 4

Memory property configuration for data partition

flash_ctrl.MP_REGION_CFG_4 0x60 4

Memory property configuration for data partition

flash_ctrl.MP_REGION_CFG_5 0x64 4

Memory property configuration for data partition

flash_ctrl.MP_REGION_CFG_6 0x68 4

Memory property configuration for data partition

flash_ctrl.MP_REGION_CFG_7 0x6c 4

Memory property configuration for data partition

flash_ctrl.MP_REGION_0 0x70 4

Memory base and size configuration for data partition

flash_ctrl.MP_REGION_1 0x74 4

Memory base and size configuration for data partition

flash_ctrl.MP_REGION_2 0x78 4

Memory base and size configuration for data partition

flash_ctrl.MP_REGION_3 0x7c 4

Memory base and size configuration for data partition

flash_ctrl.MP_REGION_4 0x80 4

Memory base and size configuration for data partition

flash_ctrl.MP_REGION_5 0x84 4

Memory base and size configuration for data partition

flash_ctrl.MP_REGION_6 0x88 4

Memory base and size configuration for data partition

flash_ctrl.MP_REGION_7 0x8c 4

Memory base and size configuration for data partition

flash_ctrl.DEFAULT_REGION 0x90 4

Default region properties

flash_ctrl.BANK0_INFO0_REGWEN_0 0x94 4

Memory region registers configuration enable.

flash_ctrl.BANK0_INFO0_REGWEN_1 0x98 4

Memory region registers configuration enable.

flash_ctrl.BANK0_INFO0_REGWEN_2 0x9c 4

Memory region registers configuration enable.

flash_ctrl.BANK0_INFO0_REGWEN_3 0xa0 4

Memory region registers configuration enable.

flash_ctrl.BANK0_INFO0_REGWEN_4 0xa4 4

Memory region registers configuration enable.

flash_ctrl.BANK0_INFO0_REGWEN_5 0xa8 4

Memory region registers configuration enable.

flash_ctrl.BANK0_INFO0_REGWEN_6 0xac 4

Memory region registers configuration enable.

flash_ctrl.BANK0_INFO0_REGWEN_7 0xb0 4

Memory region registers configuration enable.

flash_ctrl.BANK0_INFO0_REGWEN_8 0xb4 4

Memory region registers configuration enable.

flash_ctrl.BANK0_INFO0_REGWEN_9 0xb8 4

Memory region registers configuration enable.

flash_ctrl.BANK0_INFO0_PAGE_CFG_0 0xbc 4

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

flash_ctrl.BANK0_INFO0_PAGE_CFG_1 0xc0 4

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

flash_ctrl.BANK0_INFO0_PAGE_CFG_2 0xc4 4

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

flash_ctrl.BANK0_INFO0_PAGE_CFG_3 0xc8 4

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

flash_ctrl.BANK0_INFO0_PAGE_CFG_4 0xcc 4

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

flash_ctrl.BANK0_INFO0_PAGE_CFG_5 0xd0 4

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

flash_ctrl.BANK0_INFO0_PAGE_CFG_6 0xd4 4

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

flash_ctrl.BANK0_INFO0_PAGE_CFG_7 0xd8 4

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

flash_ctrl.BANK0_INFO0_PAGE_CFG_8 0xdc 4

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

flash_ctrl.BANK0_INFO0_PAGE_CFG_9 0xe0 4

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

flash_ctrl.BANK0_INFO1_REGWEN 0xe4 4

Memory region registers configuration enable.

flash_ctrl.BANK0_INFO1_PAGE_CFG 0xe8 4

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

flash_ctrl.BANK0_INFO2_REGWEN_0 0xec 4

Memory region registers configuration enable.

flash_ctrl.BANK0_INFO2_REGWEN_1 0xf0 4

Memory region registers configuration enable.

flash_ctrl.BANK0_INFO2_PAGE_CFG_0 0xf4 4

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

flash_ctrl.BANK0_INFO2_PAGE_CFG_1 0xf8 4

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

flash_ctrl.BANK1_INFO0_REGWEN_0 0xfc 4

Memory region registers configuration enable.

flash_ctrl.BANK1_INFO0_REGWEN_1 0x100 4

Memory region registers configuration enable.

flash_ctrl.BANK1_INFO0_REGWEN_2 0x104 4

Memory region registers configuration enable.

flash_ctrl.BANK1_INFO0_REGWEN_3 0x108 4

Memory region registers configuration enable.

flash_ctrl.BANK1_INFO0_REGWEN_4 0x10c 4

Memory region registers configuration enable.

flash_ctrl.BANK1_INFO0_REGWEN_5 0x110 4

Memory region registers configuration enable.

flash_ctrl.BANK1_INFO0_REGWEN_6 0x114 4

Memory region registers configuration enable.

flash_ctrl.BANK1_INFO0_REGWEN_7 0x118 4

Memory region registers configuration enable.

flash_ctrl.BANK1_INFO0_REGWEN_8 0x11c 4

Memory region registers configuration enable.

flash_ctrl.BANK1_INFO0_REGWEN_9 0x120 4

Memory region registers configuration enable.

flash_ctrl.BANK1_INFO0_PAGE_CFG_0 0x124 4

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

flash_ctrl.BANK1_INFO0_PAGE_CFG_1 0x128 4

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

flash_ctrl.BANK1_INFO0_PAGE_CFG_2 0x12c 4

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

flash_ctrl.BANK1_INFO0_PAGE_CFG_3 0x130 4

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

flash_ctrl.BANK1_INFO0_PAGE_CFG_4 0x134 4

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

flash_ctrl.BANK1_INFO0_PAGE_CFG_5 0x138 4

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

flash_ctrl.BANK1_INFO0_PAGE_CFG_6 0x13c 4

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

flash_ctrl.BANK1_INFO0_PAGE_CFG_7 0x140 4

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

flash_ctrl.BANK1_INFO0_PAGE_CFG_8 0x144 4

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

flash_ctrl.BANK1_INFO0_PAGE_CFG_9 0x148 4

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

flash_ctrl.BANK1_INFO1_REGWEN 0x14c 4

Memory region registers configuration enable.

flash_ctrl.BANK1_INFO1_PAGE_CFG 0x150 4

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

flash_ctrl.BANK1_INFO2_REGWEN_0 0x154 4

Memory region registers configuration enable.

flash_ctrl.BANK1_INFO2_REGWEN_1 0x158 4

Memory region registers configuration enable.

flash_ctrl.BANK1_INFO2_PAGE_CFG_0 0x15c 4

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

flash_ctrl.BANK1_INFO2_PAGE_CFG_1 0x160 4

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

flash_ctrl.BANK_CFG_REGWEN 0x164 4

Bank configuration registers configuration enable.

flash_ctrl.MP_BANK_CFG_SHADOWED 0x168 4

Memory properties bank configuration

flash_ctrl.OP_STATUS 0x16c 4

Flash Operation Status

flash_ctrl.STATUS 0x170 4

Flash Controller Status

flash_ctrl.DEBUG_STATE 0x174 4

Current flash fsm state

flash_ctrl.ERR_CODE 0x178 4

Flash error code register. This register tabulates detailed error status of the flash. This is separate from OP_STATUS, which is used to indicate the current state of the software initiated flash operation.

flash_ctrl.STD_FAULT_STATUS 0x17c 4

This register tabulates standard fault status of the flash.

flash_ctrl.FAULT_STATUS 0x180 4

This register tabulates customized fault status of the flash.

flash_ctrl.ERR_ADDR 0x184 4

Synchronous error address

flash_ctrl.ECC_SINGLE_ERR_CNT 0x188 4

Total number of single bit ECC error count

flash_ctrl.ECC_SINGLE_ERR_ADDR_0 0x18c 4

Latest address of ECC single err

flash_ctrl.ECC_SINGLE_ERR_ADDR_1 0x190 4

Latest address of ECC single err

flash_ctrl.PHY_ALERT_CFG 0x194 4

Phy alert configuration

flash_ctrl.PHY_STATUS 0x198 4

Flash Phy Status

flash_ctrl.Scratch 0x19c 4

Flash Controller Scratch

flash_ctrl.FIFO_LVL 0x1a0 4

Programmable depth where FIFOs should generate interrupts

flash_ctrl.FIFO_RST 0x1a4 4

Reset for flash controller FIFOs

flash_ctrl.CURR_FIFO_LVL 0x1a8 4

Current program and read fifo depth

flash_ctrl.prog_fifo 0x1ac 4

Flash program FIFO.

flash_ctrl.rd_fifo 0x1b0 4

Flash read FIFO.

flash_ctrl.INTR_STATE @ 0x0

Interrupt State Register

Reset default = 0x0, mask 0x3f
31302928272625242322212019181716
 
1514131211109876543210
  corr_err op_done rd_lvl rd_full prog_lvl prog_empty
BitsTypeResetNameDescription
0rw1c0x0prog_empty

Program FIFO empty

1rw1c0x0prog_lvl

Program FIFO drained to level

2rw1c0x0rd_full

Read FIFO full

3rw1c0x0rd_lvl

Read FIFO filled to level

4rw1c0x0op_done

Operation complete

5rw1c0x0corr_err

Correctable error encountered


flash_ctrl.INTR_ENABLE @ 0x4

Interrupt Enable Register

Reset default = 0x0, mask 0x3f
31302928272625242322212019181716
 
1514131211109876543210
  corr_err op_done rd_lvl rd_full prog_lvl prog_empty
BitsTypeResetNameDescription
0rw0x0prog_empty

Enable interrupt when INTR_STATE.prog_empty is set.

1rw0x0prog_lvl

Enable interrupt when INTR_STATE.prog_lvl is set.

2rw0x0rd_full

Enable interrupt when INTR_STATE.rd_full is set.

3rw0x0rd_lvl

Enable interrupt when INTR_STATE.rd_lvl is set.

4rw0x0op_done

Enable interrupt when INTR_STATE.op_done is set.

5rw0x0corr_err

Enable interrupt when INTR_STATE.corr_err is set.


flash_ctrl.INTR_TEST @ 0x8

Interrupt Test Register

Reset default = 0x0, mask 0x3f
31302928272625242322212019181716
 
1514131211109876543210
  corr_err op_done rd_lvl rd_full prog_lvl prog_empty
BitsTypeResetNameDescription
0wo0x0prog_empty

Write 1 to force INTR_STATE.prog_empty to 1.

1wo0x0prog_lvl

Write 1 to force INTR_STATE.prog_lvl to 1.

2wo0x0rd_full

Write 1 to force INTR_STATE.rd_full to 1.

3wo0x0rd_lvl

Write 1 to force INTR_STATE.rd_lvl to 1.

4wo0x0op_done

Write 1 to force INTR_STATE.op_done to 1.

5wo0x0corr_err

Write 1 to force INTR_STATE.corr_err to 1.


flash_ctrl.ALERT_TEST @ 0xc

Alert Test Register

Reset default = 0x0, mask 0x1f
31302928272625242322212019181716
 
1514131211109876543210
  recov_prim_flash_alert fatal_prim_flash_alert fatal_err fatal_std_err recov_err
BitsTypeResetNameDescription
0wo0x0recov_err

Write 1 to trigger one alert event of this kind.

1wo0x0fatal_std_err

Write 1 to trigger one alert event of this kind.

2wo0x0fatal_err

Write 1 to trigger one alert event of this kind.

3wo0x0fatal_prim_flash_alert

Write 1 to trigger one alert event of this kind.

4wo0x0recov_prim_flash_alert

Write 1 to trigger one alert event of this kind.


flash_ctrl.DIS @ 0x10

Disable flash functionality

Reset default = 0x9, mask 0xf
31302928272625242322212019181716
 
1514131211109876543210
  VAL
BitsTypeResetNameDescription
3:0rw0c0x9VAL

Disables flash functionality completely. This is a shortcut mechanism used by the software to completely kill flash in case of emergency.

Since this register is rw0c instead of rw, to disable, write any value in the form of 0xxx or xxx0, where x could be either 0 or 1.


flash_ctrl.EXEC @ 0x14

Controls whether flash can be used for code execution fetches

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
EN...
1514131211109876543210
...EN
BitsTypeResetNameDescription
31:0rw0x0EN

A value of 0xa26a38f7 allows flash to be used for code execution. Any other value prevents code execution.


flash_ctrl.INIT @ 0x18

Controller init register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  VAL
BitsTypeResetNameDescription
0rw1s0x0VAL

Initializes the flash controller.

During the initialization process, the flash controller requests the address and data scramble keys and reads out the root seeds stored in flash before allowing other usage of the flash controller.

When the initialization sequence is complete, the flash read buffers are enabled and turned on.


flash_ctrl.CTRL_REGWEN @ 0x1c

Controls the configurability of the CONTROL register.

Reset default = 0x1, mask 0x1

This register ensures the contents of CONTROL cannot be changed by software once a flash operation has begun.

It unlocks whenever the existing flash operation completes, regardless of success or error.

31302928272625242322212019181716
 
1514131211109876543210
  EN
BitsTypeResetNameDescription
0ro0x1EN

Configuration enable.

This bit defaults to 1 and is set to 0 by hardware when flash operation is initiated. When the controller completes the flash operation, this bit is set back to 1 to allow software configuration of CONTROL


flash_ctrl.CONTROL @ 0x20

Control register

Reset default = 0x0, mask 0xfff07f1
Register enable = CTRL_REGWEN
31302928272625242322212019181716
  NUM
1514131211109876543210
  INFO_SEL PARTITION_SEL ERASE_SEL PROG_SEL OP   START
BitsTypeResetNameDescription
0rw0x0START

Start flash transaction. This bit shall only be set at the same time or after the other fields of the CONTROL register and ADDR have been programmed.

3:1Reserved
5:4rw0x0OP

Flash operation selection

0x0Read

Flash Read.

Read desired number of flash words

0x1Prog

Flash Program.

Program desired number of flash words

0x2Erase

Flash Erase Operation.

See ERASE_SEL for details on erase operation

Other values are reserved.

6rw0x0PROG_SEL

Flash program operation type selection

0x0Normal program

Normal program operation to the flash

0x1Program repair

Repair program operation to the flash. Whether this is actually supported depends on the underlying flash memory.

7rw0x0ERASE_SEL

Flash erase operation type selection

0x0Page Erase

Erase 1 page of flash

0x1Bank Erase

Erase 1 bank of flash

8rw0x0PARTITION_SEL

When doing a read, program or page erase operation, selects either info or data partition for operation. When 0, select data partition - this is the portion of flash that is accessible both by the host and by the controller. When 1, select info partition - this is the portion of flash that is only accessible by the controller.

When doing a bank erase operation, selects info partition also for erase. When 0, bank erase only erases data partition. When 1, bank erase erases data partition and info partition.

10:9rw0x0INFO_SEL

Informational partions can have multiple types.

This field selects the info type to be accessed.

15:11Reserved
27:16rw0x0NUM

One fewer than the number of bus words the flash operation should read or program. For example, to read 10 words, software should program this field with the value 9.


flash_ctrl.ADDR @ 0x24

Address for flash operation

Reset default = 0x0, mask 0xfffff
Register enable = CTRL_REGWEN
31302928272625242322212019181716
  START...
1514131211109876543210
...START
BitsTypeResetNameDescription
19:0rw0x0START

Start address of a flash transaction. This is a byte address relative to the flash only. Ie, an address of 0 will access address 0 of the requested partition.

For read operations, the flash controller will truncate to the closest, lower word aligned address. For example, if 0x13 is supplied, the controller will perform a read at address 0x10.

Program operations behave similarly, the controller does not have read modified write support.

For page erases, the controller will truncate to the closest lower page aligned address. Similarly for bank erases, the controller will truncate to the closest lower bank aligned address.


flash_ctrl.PROG_TYPE_EN @ 0x28

Enable different program types

Reset default = 0x3, mask 0x3
Register enable = CTRL_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  REPAIR NORMAL
BitsTypeResetNameDescription
0rw0c0x1NORMAL

Normal prog type available

1rw0c0x1REPAIR

Repair prog type available


flash_ctrl.ERASE_SUSPEND @ 0x2c

Suspend erase

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REQ
BitsTypeResetNameDescription
0rw0x0REQ

When 1, request erase suspend. If no erase ongoing, the request is immediately cleared by hardware If erase ongoing, the request is fed to the flash_phy and cleared when the suspend is handled.


flash_ctrl.REGION_CFG_REGWEN_0 @ 0x30

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_0
BitsTypeResetNameDescription
0rw0c0x1REGION_0

Region register write enable. Once set to 0, it can longer be configured to 1

0x0Region locked

Region can no longer be configured until next reset

0x1Region enabled

Region can be configured


flash_ctrl.REGION_CFG_REGWEN_1 @ 0x34

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_1
BitsTypeResetNameDescription
0rw0c0x1REGION_1

For FLASH_CTRL1


flash_ctrl.REGION_CFG_REGWEN_2 @ 0x38

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_2
BitsTypeResetNameDescription
0rw0c0x1REGION_2

For FLASH_CTRL2


flash_ctrl.REGION_CFG_REGWEN_3 @ 0x3c

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_3
BitsTypeResetNameDescription
0rw0c0x1REGION_3

For FLASH_CTRL3


flash_ctrl.REGION_CFG_REGWEN_4 @ 0x40

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_4
BitsTypeResetNameDescription
0rw0c0x1REGION_4

For FLASH_CTRL4


flash_ctrl.REGION_CFG_REGWEN_5 @ 0x44

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_5
BitsTypeResetNameDescription
0rw0c0x1REGION_5

For FLASH_CTRL5


flash_ctrl.REGION_CFG_REGWEN_6 @ 0x48

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_6
BitsTypeResetNameDescription
0rw0c0x1REGION_6

For FLASH_CTRL6


flash_ctrl.REGION_CFG_REGWEN_7 @ 0x4c

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_7
BitsTypeResetNameDescription
0rw0c0x1REGION_7

For FLASH_CTRL7


flash_ctrl.MP_REGION_CFG_0 @ 0x50

Memory property configuration for data partition

Reset default = 0x9999999, mask 0xfffffff
Register enable = REGION_CFG_REGWEN_0
31302928272625242322212019181716
  HE_EN_0 ECC_EN_0 SCRAMBLE_EN_0
1514131211109876543210
ERASE_EN_0 PROG_EN_0 RD_EN_0 EN_0
BitsTypeResetNameDescription
3:0rw0x9EN_0

Region enabled, following fields apply. If region is disabled, it is not matched against any incoming transaction.

7:4rw0x9RD_EN_0

Region can be read

11:8rw0x9PROG_EN_0

Region can be programmed

15:12rw0x9ERASE_EN_0

Region can be erased

19:16rw0x9SCRAMBLE_EN_0

Region is scramble enabled.

23:20rw0x9ECC_EN_0

Region is integrity checked and reliability ECC enabled.

27:24rw0x9HE_EN_0

Region is high endurance enabled.


flash_ctrl.MP_REGION_CFG_1 @ 0x54

Memory property configuration for data partition

Reset default = 0x9999999, mask 0xfffffff
Register enable = REGION_CFG_REGWEN_1
31302928272625242322212019181716
  HE_EN_1 ECC_EN_1 SCRAMBLE_EN_1
1514131211109876543210
ERASE_EN_1 PROG_EN_1 RD_EN_1 EN_1
BitsTypeResetNameDescription
3:0rw0x9EN_1

For FLASH_CTRL1

7:4rw0x9RD_EN_1

For FLASH_CTRL1

11:8rw0x9PROG_EN_1

For FLASH_CTRL1

15:12rw0x9ERASE_EN_1

For FLASH_CTRL1

19:16rw0x9SCRAMBLE_EN_1

For FLASH_CTRL1

23:20rw0x9ECC_EN_1

For FLASH_CTRL1

27:24rw0x9HE_EN_1

For FLASH_CTRL1


flash_ctrl.MP_REGION_CFG_2 @ 0x58

Memory property configuration for data partition

Reset default = 0x9999999, mask 0xfffffff
Register enable = REGION_CFG_REGWEN_2
31302928272625242322212019181716
  HE_EN_2 ECC_EN_2 SCRAMBLE_EN_2
1514131211109876543210
ERASE_EN_2 PROG_EN_2 RD_EN_2 EN_2
BitsTypeResetNameDescription
3:0rw0x9EN_2

For FLASH_CTRL2

7:4rw0x9RD_EN_2

For FLASH_CTRL2

11:8rw0x9PROG_EN_2

For FLASH_CTRL2

15:12rw0x9ERASE_EN_2

For FLASH_CTRL2

19:16rw0x9SCRAMBLE_EN_2

For FLASH_CTRL2

23:20rw0x9ECC_EN_2

For FLASH_CTRL2

27:24rw0x9HE_EN_2

For FLASH_CTRL2


flash_ctrl.MP_REGION_CFG_3 @ 0x5c

Memory property configuration for data partition

Reset default = 0x9999999, mask 0xfffffff
Register enable = REGION_CFG_REGWEN_3
31302928272625242322212019181716
  HE_EN_3 ECC_EN_3 SCRAMBLE_EN_3
1514131211109876543210
ERASE_EN_3 PROG_EN_3 RD_EN_3 EN_3
BitsTypeResetNameDescription
3:0rw0x9EN_3

For FLASH_CTRL3

7:4rw0x9RD_EN_3

For FLASH_CTRL3

11:8rw0x9PROG_EN_3

For FLASH_CTRL3

15:12rw0x9ERASE_EN_3

For FLASH_CTRL3

19:16rw0x9SCRAMBLE_EN_3

For FLASH_CTRL3

23:20rw0x9ECC_EN_3

For FLASH_CTRL3

27:24rw0x9HE_EN_3

For FLASH_CTRL3


flash_ctrl.MP_REGION_CFG_4 @ 0x60

Memory property configuration for data partition

Reset default = 0x9999999, mask 0xfffffff
Register enable = REGION_CFG_REGWEN_4
31302928272625242322212019181716
  HE_EN_4 ECC_EN_4 SCRAMBLE_EN_4
1514131211109876543210
ERASE_EN_4 PROG_EN_4 RD_EN_4 EN_4
BitsTypeResetNameDescription
3:0rw0x9EN_4

For FLASH_CTRL4

7:4rw0x9RD_EN_4

For FLASH_CTRL4

11:8rw0x9PROG_EN_4

For FLASH_CTRL4

15:12rw0x9ERASE_EN_4

For FLASH_CTRL4

19:16rw0x9SCRAMBLE_EN_4

For FLASH_CTRL4

23:20rw0x9ECC_EN_4

For FLASH_CTRL4

27:24rw0x9HE_EN_4

For FLASH_CTRL4


flash_ctrl.MP_REGION_CFG_5 @ 0x64

Memory property configuration for data partition

Reset default = 0x9999999, mask 0xfffffff
Register enable = REGION_CFG_REGWEN_5
31302928272625242322212019181716
  HE_EN_5 ECC_EN_5 SCRAMBLE_EN_5
1514131211109876543210
ERASE_EN_5 PROG_EN_5 RD_EN_5 EN_5
BitsTypeResetNameDescription
3:0rw0x9EN_5

For FLASH_CTRL5

7:4rw0x9RD_EN_5

For FLASH_CTRL5

11:8rw0x9PROG_EN_5

For FLASH_CTRL5

15:12rw0x9ERASE_EN_5

For FLASH_CTRL5

19:16rw0x9SCRAMBLE_EN_5

For FLASH_CTRL5

23:20rw0x9ECC_EN_5

For FLASH_CTRL5

27:24rw0x9HE_EN_5

For FLASH_CTRL5


flash_ctrl.MP_REGION_CFG_6 @ 0x68

Memory property configuration for data partition

Reset default = 0x9999999, mask 0xfffffff
Register enable = REGION_CFG_REGWEN_6
31302928272625242322212019181716
  HE_EN_6 ECC_EN_6 SCRAMBLE_EN_6
1514131211109876543210
ERASE_EN_6 PROG_EN_6 RD_EN_6 EN_6
BitsTypeResetNameDescription
3:0rw0x9EN_6

For FLASH_CTRL6

7:4rw0x9RD_EN_6

For FLASH_CTRL6

11:8rw0x9PROG_EN_6

For FLASH_CTRL6

15:12rw0x9ERASE_EN_6

For FLASH_CTRL6

19:16rw0x9SCRAMBLE_EN_6

For FLASH_CTRL6

23:20rw0x9ECC_EN_6

For FLASH_CTRL6

27:24rw0x9HE_EN_6

For FLASH_CTRL6


flash_ctrl.MP_REGION_CFG_7 @ 0x6c

Memory property configuration for data partition

Reset default = 0x9999999, mask 0xfffffff
Register enable = REGION_CFG_REGWEN_7
31302928272625242322212019181716
  HE_EN_7 ECC_EN_7 SCRAMBLE_EN_7
1514131211109876543210
ERASE_EN_7 PROG_EN_7 RD_EN_7 EN_7
BitsTypeResetNameDescription
3:0rw0x9EN_7

For FLASH_CTRL7

7:4rw0x9RD_EN_7

For FLASH_CTRL7

11:8rw0x9PROG_EN_7

For FLASH_CTRL7

15:12rw0x9ERASE_EN_7

For FLASH_CTRL7

19:16rw0x9SCRAMBLE_EN_7

For FLASH_CTRL7

23:20rw0x9ECC_EN_7

For FLASH_CTRL7

27:24rw0x9HE_EN_7

For FLASH_CTRL7


flash_ctrl.MP_REGION_0 @ 0x70

Memory base and size configuration for data partition

Reset default = 0x0, mask 0x7ffff
Register enable = REGION_CFG_REGWEN_0
31302928272625242322212019181716
  SIZE_0...
1514131211109876543210
...SIZE_0 BASE_0
BitsTypeResetNameDescription
8:0rw0x0BASE_0

Region base page. Note the granularity is page, not byte or word

18:9rw0x0SIZE_0

Region size in number of pages. For example, if base is 0 and size is 1, then the region is defined by page 0. If base is 0 and size is 2, then the region is defined by pages 0 and 1.


flash_ctrl.MP_REGION_1 @ 0x74

Memory base and size configuration for data partition

Reset default = 0x0, mask 0x7ffff
Register enable = REGION_CFG_REGWEN_1
31302928272625242322212019181716
  SIZE_1...
1514131211109876543210
...SIZE_1 BASE_1
BitsTypeResetNameDescription
8:0rw0x0BASE_1

For FLASH_CTRL1

18:9rw0x0SIZE_1

For FLASH_CTRL1


flash_ctrl.MP_REGION_2 @ 0x78

Memory base and size configuration for data partition

Reset default = 0x0, mask 0x7ffff
Register enable = REGION_CFG_REGWEN_2
31302928272625242322212019181716
  SIZE_2...
1514131211109876543210
...SIZE_2 BASE_2
BitsTypeResetNameDescription
8:0rw0x0BASE_2

For FLASH_CTRL2

18:9rw0x0SIZE_2

For FLASH_CTRL2


flash_ctrl.MP_REGION_3 @ 0x7c

Memory base and size configuration for data partition

Reset default = 0x0, mask 0x7ffff
Register enable = REGION_CFG_REGWEN_3
31302928272625242322212019181716
  SIZE_3...
1514131211109876543210
...SIZE_3 BASE_3
BitsTypeResetNameDescription
8:0rw0x0BASE_3

For FLASH_CTRL3

18:9rw0x0SIZE_3

For FLASH_CTRL3


flash_ctrl.MP_REGION_4 @ 0x80

Memory base and size configuration for data partition

Reset default = 0x0, mask 0x7ffff
Register enable = REGION_CFG_REGWEN_4
31302928272625242322212019181716
  SIZE_4...
1514131211109876543210
...SIZE_4 BASE_4
BitsTypeResetNameDescription
8:0rw0x0BASE_4

For FLASH_CTRL4

18:9rw0x0SIZE_4

For FLASH_CTRL4


flash_ctrl.MP_REGION_5 @ 0x84

Memory base and size configuration for data partition

Reset default = 0x0, mask 0x7ffff
Register enable = REGION_CFG_REGWEN_5
31302928272625242322212019181716
  SIZE_5...
1514131211109876543210
...SIZE_5 BASE_5
BitsTypeResetNameDescription
8:0rw0x0BASE_5

For FLASH_CTRL5

18:9rw0x0SIZE_5

For FLASH_CTRL5


flash_ctrl.MP_REGION_6 @ 0x88

Memory base and size configuration for data partition

Reset default = 0x0, mask 0x7ffff
Register enable = REGION_CFG_REGWEN_6
31302928272625242322212019181716
  SIZE_6...
1514131211109876543210
...SIZE_6 BASE_6
BitsTypeResetNameDescription
8:0rw0x0BASE_6

For FLASH_CTRL6

18:9rw0x0SIZE_6

For FLASH_CTRL6


flash_ctrl.MP_REGION_7 @ 0x8c

Memory base and size configuration for data partition

Reset default = 0x0, mask 0x7ffff
Register enable = REGION_CFG_REGWEN_7
31302928272625242322212019181716
  SIZE_7...
1514131211109876543210
...SIZE_7 BASE_7
BitsTypeResetNameDescription
8:0rw0x0BASE_7

For FLASH_CTRL7

18:9rw0x0SIZE_7

For FLASH_CTRL7


flash_ctrl.DEFAULT_REGION @ 0x90

Default region properties

Reset default = 0x999999, mask 0xffffff
31302928272625242322212019181716
  HE_EN ECC_EN
1514131211109876543210
SCRAMBLE_EN ERASE_EN PROG_EN RD_EN
BitsTypeResetNameDescription
3:0rw0x9RD_EN

Region can be read

7:4rw0x9PROG_EN

Region can be programmed

11:8rw0x9ERASE_EN

Region can be erased

15:12rw0x9SCRAMBLE_EN

Region is scramble enabled.

19:16rw0x9ECC_EN

Region is ECC enabled (both integrity and reliability ECC).

23:20rw0x9HE_EN

Region is high endurance enabled.


flash_ctrl.BANK0_INFO0_REGWEN_0 @ 0x94

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_0
BitsTypeResetNameDescription
0rw0c0x1REGION_0

Info0 page write enable. Once set to 0, it can longer be configured to 1

0x0Page locked

Region can no longer be configured until next reset

0x1Page enabled

Region can be configured


flash_ctrl.BANK0_INFO0_REGWEN_1 @ 0x98

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_1
BitsTypeResetNameDescription
0rw0c0x1REGION_1

For FLASH_CTRL1


flash_ctrl.BANK0_INFO0_REGWEN_2 @ 0x9c

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_2
BitsTypeResetNameDescription
0rw0c0x1REGION_2

For FLASH_CTRL2


flash_ctrl.BANK0_INFO0_REGWEN_3 @ 0xa0

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_3
BitsTypeResetNameDescription
0rw0c0x1REGION_3

For FLASH_CTRL3


flash_ctrl.BANK0_INFO0_REGWEN_4 @ 0xa4

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_4
BitsTypeResetNameDescription
0rw0c0x1REGION_4

For FLASH_CTRL4


flash_ctrl.BANK0_INFO0_REGWEN_5 @ 0xa8

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_5
BitsTypeResetNameDescription
0rw0c0x1REGION_5

For FLASH_CTRL5


flash_ctrl.BANK0_INFO0_REGWEN_6 @ 0xac

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_6
BitsTypeResetNameDescription
0rw0c0x1REGION_6

For FLASH_CTRL6


flash_ctrl.BANK0_INFO0_REGWEN_7 @ 0xb0

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_7
BitsTypeResetNameDescription
0rw0c0x1REGION_7

For FLASH_CTRL7


flash_ctrl.BANK0_INFO0_REGWEN_8 @ 0xb4

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_8
BitsTypeResetNameDescription
0rw0c0x1REGION_8

For FLASH_CTRL8


flash_ctrl.BANK0_INFO0_REGWEN_9 @ 0xb8

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_9
BitsTypeResetNameDescription
0rw0c0x1REGION_9

For FLASH_CTRL9


flash_ctrl.BANK0_INFO0_PAGE_CFG_0 @ 0xbc

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff
Register enable = BANK0_INFO0_REGWEN_0
31302928272625242322212019181716
  HE_EN_0 ECC_EN_0 SCRAMBLE_EN_0
1514131211109876543210
ERASE_EN_0 PROG_EN_0 RD_EN_0 EN_0
BitsTypeResetNameDescription
3:0rw0x9EN_0

Region enabled, following fields apply

7:4rw0x9RD_EN_0

Region can be read

11:8rw0x9PROG_EN_0

Region can be programmed

15:12rw0x9ERASE_EN_0

Region can be erased

19:16rw0x9SCRAMBLE_EN_0

Region is scramble enabled.

23:20rw0x9ECC_EN_0

Region is ECC enabled (both integrity and reliability ECC).

27:24rw0x9HE_EN_0

Region is high endurance enabled.


flash_ctrl.BANK0_INFO0_PAGE_CFG_1 @ 0xc0

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff
Register enable = BANK0_INFO0_REGWEN_1
31302928272625242322212019181716
  HE_EN_1 ECC_EN_1 SCRAMBLE_EN_1
1514131211109876543210
ERASE_EN_1 PROG_EN_1 RD_EN_1 EN_1
BitsTypeResetNameDescription
3:0rw0x9EN_1

For FLASH_CTRL1

7:4rw0x9RD_EN_1

For FLASH_CTRL1

11:8rw0x9PROG_EN_1

For FLASH_CTRL1

15:12rw0x9ERASE_EN_1

For FLASH_CTRL1

19:16rw0x9SCRAMBLE_EN_1

For FLASH_CTRL1

23:20rw0x9ECC_EN_1

For FLASH_CTRL1

27:24rw0x9HE_EN_1

For FLASH_CTRL1


flash_ctrl.BANK0_INFO0_PAGE_CFG_2 @ 0xc4

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff
Register enable = BANK0_INFO0_REGWEN_2
31302928272625242322212019181716
  HE_EN_2 ECC_EN_2 SCRAMBLE_EN_2
1514131211109876543210
ERASE_EN_2 PROG_EN_2 RD_EN_2 EN_2
BitsTypeResetNameDescription
3:0rw0x9EN_2

For FLASH_CTRL2

7:4rw0x9RD_EN_2

For FLASH_CTRL2

11:8rw0x9PROG_EN_2

For FLASH_CTRL2

15:12rw0x9ERASE_EN_2

For FLASH_CTRL2

19:16rw0x9SCRAMBLE_EN_2

For FLASH_CTRL2

23:20rw0x9ECC_EN_2

For FLASH_CTRL2

27:24rw0x9HE_EN_2

For FLASH_CTRL2


flash_ctrl.BANK0_INFO0_PAGE_CFG_3 @ 0xc8

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff
Register enable = BANK0_INFO0_REGWEN_3
31302928272625242322212019181716
  HE_EN_3 ECC_EN_3 SCRAMBLE_EN_3
1514131211109876543210
ERASE_EN_3 PROG_EN_3 RD_EN_3 EN_3
BitsTypeResetNameDescription
3:0rw0x9EN_3

For FLASH_CTRL3

7:4rw0x9RD_EN_3

For FLASH_CTRL3

11:8rw0x9PROG_EN_3

For FLASH_CTRL3

15:12rw0x9ERASE_EN_3

For FLASH_CTRL3

19:16rw0x9SCRAMBLE_EN_3

For FLASH_CTRL3

23:20rw0x9ECC_EN_3

For FLASH_CTRL3

27:24rw0x9HE_EN_3

For FLASH_CTRL3


flash_ctrl.BANK0_INFO0_PAGE_CFG_4 @ 0xcc

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff
Register enable = BANK0_INFO0_REGWEN_4
31302928272625242322212019181716
  HE_EN_4 ECC_EN_4 SCRAMBLE_EN_4
1514131211109876543210
ERASE_EN_4 PROG_EN_4 RD_EN_4 EN_4
BitsTypeResetNameDescription
3:0rw0x9EN_4

For FLASH_CTRL4

7:4rw0x9RD_EN_4

For FLASH_CTRL4

11:8rw0x9PROG_EN_4

For FLASH_CTRL4

15:12rw0x9ERASE_EN_4

For FLASH_CTRL4

19:16rw0x9SCRAMBLE_EN_4

For FLASH_CTRL4

23:20rw0x9ECC_EN_4

For FLASH_CTRL4

27:24rw0x9HE_EN_4

For FLASH_CTRL4


flash_ctrl.BANK0_INFO0_PAGE_CFG_5 @ 0xd0

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff
Register enable = BANK0_INFO0_REGWEN_5
31302928272625242322212019181716
  HE_EN_5 ECC_EN_5 SCRAMBLE_EN_5
1514131211109876543210
ERASE_EN_5 PROG_EN_5 RD_EN_5 EN_5
BitsTypeResetNameDescription
3:0rw0x9EN_5

For FLASH_CTRL5

7:4rw0x9RD_EN_5

For FLASH_CTRL5

11:8rw0x9PROG_EN_5

For FLASH_CTRL5

15:12rw0x9ERASE_EN_5

For FLASH_CTRL5

19:16rw0x9SCRAMBLE_EN_5

For FLASH_CTRL5

23:20rw0x9ECC_EN_5

For FLASH_CTRL5

27:24rw0x9HE_EN_5

For FLASH_CTRL5


flash_ctrl.BANK0_INFO0_PAGE_CFG_6 @ 0xd4

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff
Register enable = BANK0_INFO0_REGWEN_6
31302928272625242322212019181716
  HE_EN_6 ECC_EN_6 SCRAMBLE_EN_6
1514131211109876543210
ERASE_EN_6 PROG_EN_6 RD_EN_6 EN_6
BitsTypeResetNameDescription
3:0rw0x9EN_6

For FLASH_CTRL6

7:4rw0x9RD_EN_6

For FLASH_CTRL6

11:8rw0x9PROG_EN_6

For FLASH_CTRL6

15:12rw0x9ERASE_EN_6

For FLASH_CTRL6

19:16rw0x9SCRAMBLE_EN_6

For FLASH_CTRL6

23:20rw0x9ECC_EN_6

For FLASH_CTRL6

27:24rw0x9HE_EN_6

For FLASH_CTRL6


flash_ctrl.BANK0_INFO0_PAGE_CFG_7 @ 0xd8

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff
Register enable = BANK0_INFO0_REGWEN_7
31302928272625242322212019181716
  HE_EN_7 ECC_EN_7 SCRAMBLE_EN_7
1514131211109876543210
ERASE_EN_7 PROG_EN_7 RD_EN_7 EN_7
BitsTypeResetNameDescription
3:0rw0x9EN_7

For FLASH_CTRL7

7:4rw0x9RD_EN_7

For FLASH_CTRL7

11:8rw0x9PROG_EN_7

For FLASH_CTRL7

15:12rw0x9ERASE_EN_7

For FLASH_CTRL7

19:16rw0x9SCRAMBLE_EN_7

For FLASH_CTRL7

23:20rw0x9ECC_EN_7

For FLASH_CTRL7

27:24rw0x9HE_EN_7

For FLASH_CTRL7


flash_ctrl.BANK0_INFO0_PAGE_CFG_8 @ 0xdc

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff
Register enable = BANK0_INFO0_REGWEN_8
31302928272625242322212019181716
  HE_EN_8 ECC_EN_8 SCRAMBLE_EN_8
1514131211109876543210
ERASE_EN_8 PROG_EN_8 RD_EN_8 EN_8
BitsTypeResetNameDescription
3:0rw0x9EN_8

For FLASH_CTRL8

7:4rw0x9RD_EN_8

For FLASH_CTRL8

11:8rw0x9PROG_EN_8

For FLASH_CTRL8

15:12rw0x9ERASE_EN_8

For FLASH_CTRL8

19:16rw0x9SCRAMBLE_EN_8

For FLASH_CTRL8

23:20rw0x9ECC_EN_8

For FLASH_CTRL8

27:24rw0x9HE_EN_8

For FLASH_CTRL8


flash_ctrl.BANK0_INFO0_PAGE_CFG_9 @ 0xe0

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff
Register enable = BANK0_INFO0_REGWEN_9
31302928272625242322212019181716
  HE_EN_9 ECC_EN_9 SCRAMBLE_EN_9
1514131211109876543210
ERASE_EN_9 PROG_EN_9 RD_EN_9 EN_9
BitsTypeResetNameDescription
3:0rw0x9EN_9

For FLASH_CTRL9

7:4rw0x9RD_EN_9

For FLASH_CTRL9

11:8rw0x9PROG_EN_9

For FLASH_CTRL9

15:12rw0x9ERASE_EN_9

For FLASH_CTRL9

19:16rw0x9SCRAMBLE_EN_9

For FLASH_CTRL9

23:20rw0x9ECC_EN_9

For FLASH_CTRL9

27:24rw0x9HE_EN_9

For FLASH_CTRL9


flash_ctrl.BANK0_INFO1_REGWEN @ 0xe4

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_0
BitsTypeResetNameDescription
0rw0c0x1REGION_0

Info1 page write enable. Once set to 0, it can longer be configured to 1

0x0Page locked

Region can no longer be configured until next reset

0x1Page enabled

Region can be configured


flash_ctrl.BANK0_INFO1_PAGE_CFG @ 0xe8

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff
Register enable = BANK0_INFO1_REGWEN
31302928272625242322212019181716
  HE_EN_0 ECC_EN_0 SCRAMBLE_EN_0
1514131211109876543210
ERASE_EN_0 PROG_EN_0 RD_EN_0 EN_0
BitsTypeResetNameDescription
3:0rw0x9EN_0

Region enabled, following fields apply

7:4rw0x9RD_EN_0

Region can be read

11:8rw0x9PROG_EN_0

Region can be programmed

15:12rw0x9ERASE_EN_0

Region can be erased

19:16rw0x9SCRAMBLE_EN_0

Region is scramble enabled.

23:20rw0x9ECC_EN_0

Region is ECC enabled (both integrity and reliability ECC).

27:24rw0x9HE_EN_0

Region is high endurance enabled.


flash_ctrl.BANK0_INFO2_REGWEN_0 @ 0xec

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_0
BitsTypeResetNameDescription
0rw0c0x1REGION_0

Info2 page write enable. Once set to 0, it can longer be configured to 1

0x0Page locked

Region can no longer be configured until next reset

0x1Page enabled

Region can be configured


flash_ctrl.BANK0_INFO2_REGWEN_1 @ 0xf0

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_1
BitsTypeResetNameDescription
0rw0c0x1REGION_1

For FLASH_CTRL1


flash_ctrl.BANK0_INFO2_PAGE_CFG_0 @ 0xf4

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff
Register enable = BANK0_INFO2_REGWEN_0
31302928272625242322212019181716
  HE_EN_0 ECC_EN_0 SCRAMBLE_EN_0
1514131211109876543210
ERASE_EN_0 PROG_EN_0 RD_EN_0 EN_0
BitsTypeResetNameDescription
3:0rw0x9EN_0

Region enabled, following fields apply

7:4rw0x9RD_EN_0

Region can be read

11:8rw0x9PROG_EN_0

Region can be programmed

15:12rw0x9ERASE_EN_0

Region can be erased

19:16rw0x9SCRAMBLE_EN_0

Region is scramble enabled.

23:20rw0x9ECC_EN_0

Region is ECC enabled (both integrity and reliability ECC).

27:24rw0x9HE_EN_0

Region is high endurance enabled.


flash_ctrl.BANK0_INFO2_PAGE_CFG_1 @ 0xf8

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff
Register enable = BANK0_INFO2_REGWEN_1
31302928272625242322212019181716
  HE_EN_1 ECC_EN_1 SCRAMBLE_EN_1
1514131211109876543210
ERASE_EN_1 PROG_EN_1 RD_EN_1 EN_1
BitsTypeResetNameDescription
3:0rw0x9EN_1

For FLASH_CTRL1

7:4rw0x9RD_EN_1

For FLASH_CTRL1

11:8rw0x9PROG_EN_1

For FLASH_CTRL1

15:12rw0x9ERASE_EN_1

For FLASH_CTRL1

19:16rw0x9SCRAMBLE_EN_1

For FLASH_CTRL1

23:20rw0x9ECC_EN_1

For FLASH_CTRL1

27:24rw0x9HE_EN_1

For FLASH_CTRL1


flash_ctrl.BANK1_INFO0_REGWEN_0 @ 0xfc

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_0
BitsTypeResetNameDescription
0rw0c0x1REGION_0

Info0 page write enable. Once set to 0, it can longer be configured to 1

0x0Page locked

Region can no longer be configured until next reset

0x1Page enabled

Region can be configured


flash_ctrl.BANK1_INFO0_REGWEN_1 @ 0x100

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_1
BitsTypeResetNameDescription
0rw0c0x1REGION_1

For FLASH_CTRL1


flash_ctrl.BANK1_INFO0_REGWEN_2 @ 0x104

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_2
BitsTypeResetNameDescription
0rw0c0x1REGION_2

For FLASH_CTRL2


flash_ctrl.BANK1_INFO0_REGWEN_3 @ 0x108

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_3
BitsTypeResetNameDescription
0rw0c0x1REGION_3

For FLASH_CTRL3


flash_ctrl.BANK1_INFO0_REGWEN_4 @ 0x10c

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_4
BitsTypeResetNameDescription
0rw0c0x1REGION_4

For FLASH_CTRL4


flash_ctrl.BANK1_INFO0_REGWEN_5 @ 0x110

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_5
BitsTypeResetNameDescription
0rw0c0x1REGION_5

For FLASH_CTRL5


flash_ctrl.BANK1_INFO0_REGWEN_6 @ 0x114

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_6
BitsTypeResetNameDescription
0rw0c0x1REGION_6

For FLASH_CTRL6


flash_ctrl.BANK1_INFO0_REGWEN_7 @ 0x118

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_7
BitsTypeResetNameDescription
0rw0c0x1REGION_7

For FLASH_CTRL7


flash_ctrl.BANK1_INFO0_REGWEN_8 @ 0x11c

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_8
BitsTypeResetNameDescription
0rw0c0x1REGION_8

For FLASH_CTRL8


flash_ctrl.BANK1_INFO0_REGWEN_9 @ 0x120

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_9
BitsTypeResetNameDescription
0rw0c0x1REGION_9

For FLASH_CTRL9


flash_ctrl.BANK1_INFO0_PAGE_CFG_0 @ 0x124

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff
Register enable = BANK1_INFO0_REGWEN_0
31302928272625242322212019181716
  HE_EN_0 ECC_EN_0 SCRAMBLE_EN_0
1514131211109876543210
ERASE_EN_0 PROG_EN_0 RD_EN_0 EN_0
BitsTypeResetNameDescription
3:0rw0x9EN_0

Region enabled, following fields apply

7:4rw0x9RD_EN_0

Region can be read

11:8rw0x9PROG_EN_0

Region can be programmed

15:12rw0x9ERASE_EN_0

Region can be erased

19:16rw0x9SCRAMBLE_EN_0

Region is scramble enabled.

23:20rw0x9ECC_EN_0

Region is ECC enabled (both integrity and reliability ECC).

27:24rw0x9HE_EN_0

Region is high endurance enabled.


flash_ctrl.BANK1_INFO0_PAGE_CFG_1 @ 0x128

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff
Register enable = BANK1_INFO0_REGWEN_1
31302928272625242322212019181716
  HE_EN_1 ECC_EN_1 SCRAMBLE_EN_1
1514131211109876543210
ERASE_EN_1 PROG_EN_1 RD_EN_1 EN_1
BitsTypeResetNameDescription
3:0rw0x9EN_1

For FLASH_CTRL1

7:4rw0x9RD_EN_1

For FLASH_CTRL1

11:8rw0x9PROG_EN_1

For FLASH_CTRL1

15:12rw0x9ERASE_EN_1

For FLASH_CTRL1

19:16rw0x9SCRAMBLE_EN_1

For FLASH_CTRL1

23:20rw0x9ECC_EN_1

For FLASH_CTRL1

27:24rw0x9HE_EN_1

For FLASH_CTRL1


flash_ctrl.BANK1_INFO0_PAGE_CFG_2 @ 0x12c

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff
Register enable = BANK1_INFO0_REGWEN_2
31302928272625242322212019181716
  HE_EN_2 ECC_EN_2 SCRAMBLE_EN_2
1514131211109876543210
ERASE_EN_2 PROG_EN_2 RD_EN_2 EN_2
BitsTypeResetNameDescription
3:0rw0x9EN_2

For FLASH_CTRL2

7:4rw0x9RD_EN_2

For FLASH_CTRL2

11:8rw0x9PROG_EN_2

For FLASH_CTRL2

15:12rw0x9ERASE_EN_2

For FLASH_CTRL2

19:16rw0x9SCRAMBLE_EN_2

For FLASH_CTRL2

23:20rw0x9ECC_EN_2

For FLASH_CTRL2

27:24rw0x9HE_EN_2

For FLASH_CTRL2


flash_ctrl.BANK1_INFO0_PAGE_CFG_3 @ 0x130

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff
Register enable = BANK1_INFO0_REGWEN_3
31302928272625242322212019181716
  HE_EN_3 ECC_EN_3 SCRAMBLE_EN_3
1514131211109876543210
ERASE_EN_3 PROG_EN_3 RD_EN_3 EN_3
BitsTypeResetNameDescription
3:0rw0x9EN_3

For FLASH_CTRL3

7:4rw0x9RD_EN_3

For FLASH_CTRL3

11:8rw0x9PROG_EN_3

For FLASH_CTRL3

15:12rw0x9ERASE_EN_3

For FLASH_CTRL3

19:16rw0x9SCRAMBLE_EN_3

For FLASH_CTRL3

23:20rw0x9ECC_EN_3

For FLASH_CTRL3

27:24rw0x9HE_EN_3

For FLASH_CTRL3


flash_ctrl.BANK1_INFO0_PAGE_CFG_4 @ 0x134

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff
Register enable = BANK1_INFO0_REGWEN_4
31302928272625242322212019181716
  HE_EN_4 ECC_EN_4 SCRAMBLE_EN_4
1514131211109876543210
ERASE_EN_4 PROG_EN_4 RD_EN_4 EN_4
BitsTypeResetNameDescription
3:0rw0x9EN_4

For FLASH_CTRL4

7:4rw0x9RD_EN_4

For FLASH_CTRL4

11:8rw0x9PROG_EN_4

For FLASH_CTRL4

15:12rw0x9ERASE_EN_4

For FLASH_CTRL4

19:16rw0x9SCRAMBLE_EN_4

For FLASH_CTRL4

23:20rw0x9ECC_EN_4

For FLASH_CTRL4

27:24rw0x9HE_EN_4

For FLASH_CTRL4


flash_ctrl.BANK1_INFO0_PAGE_CFG_5 @ 0x138

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff
Register enable = BANK1_INFO0_REGWEN_5
31302928272625242322212019181716
  HE_EN_5 ECC_EN_5 SCRAMBLE_EN_5
1514131211109876543210
ERASE_EN_5 PROG_EN_5 RD_EN_5 EN_5
BitsTypeResetNameDescription
3:0rw0x9EN_5

For FLASH_CTRL5

7:4rw0x9RD_EN_5

For FLASH_CTRL5

11:8rw0x9PROG_EN_5

For FLASH_CTRL5

15:12rw0x9ERASE_EN_5

For FLASH_CTRL5

19:16rw0x9SCRAMBLE_EN_5

For FLASH_CTRL5

23:20rw0x9ECC_EN_5

For FLASH_CTRL5

27:24rw0x9HE_EN_5

For FLASH_CTRL5


flash_ctrl.BANK1_INFO0_PAGE_CFG_6 @ 0x13c

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff
Register enable = BANK1_INFO0_REGWEN_6
31302928272625242322212019181716
  HE_EN_6 ECC_EN_6 SCRAMBLE_EN_6
1514131211109876543210
ERASE_EN_6 PROG_EN_6 RD_EN_6 EN_6
BitsTypeResetNameDescription
3:0rw0x9EN_6

For FLASH_CTRL6

7:4rw0x9RD_EN_6

For FLASH_CTRL6

11:8rw0x9PROG_EN_6

For FLASH_CTRL6

15:12rw0x9ERASE_EN_6

For FLASH_CTRL6

19:16rw0x9SCRAMBLE_EN_6

For FLASH_CTRL6

23:20rw0x9ECC_EN_6

For FLASH_CTRL6

27:24rw0x9HE_EN_6

For FLASH_CTRL6


flash_ctrl.BANK1_INFO0_PAGE_CFG_7 @ 0x140

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff
Register enable = BANK1_INFO0_REGWEN_7
31302928272625242322212019181716
  HE_EN_7 ECC_EN_7 SCRAMBLE_EN_7
1514131211109876543210
ERASE_EN_7 PROG_EN_7 RD_EN_7 EN_7
BitsTypeResetNameDescription
3:0rw0x9EN_7

For FLASH_CTRL7

7:4rw0x9RD_EN_7

For FLASH_CTRL7

11:8rw0x9PROG_EN_7

For FLASH_CTRL7

15:12rw0x9ERASE_EN_7

For FLASH_CTRL7

19:16rw0x9SCRAMBLE_EN_7

For FLASH_CTRL7

23:20rw0x9ECC_EN_7

For FLASH_CTRL7

27:24rw0x9HE_EN_7

For FLASH_CTRL7


flash_ctrl.BANK1_INFO0_PAGE_CFG_8 @ 0x144

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff
Register enable = BANK1_INFO0_REGWEN_8
31302928272625242322212019181716
  HE_EN_8 ECC_EN_8 SCRAMBLE_EN_8
1514131211109876543210
ERASE_EN_8 PROG_EN_8 RD_EN_8 EN_8
BitsTypeResetNameDescription
3:0rw0x9EN_8

For FLASH_CTRL8

7:4rw0x9RD_EN_8

For FLASH_CTRL8

11:8rw0x9PROG_EN_8

For FLASH_CTRL8

15:12rw0x9ERASE_EN_8

For FLASH_CTRL8

19:16rw0x9SCRAMBLE_EN_8

For FLASH_CTRL8

23:20rw0x9ECC_EN_8

For FLASH_CTRL8

27:24rw0x9HE_EN_8

For FLASH_CTRL8


flash_ctrl.BANK1_INFO0_PAGE_CFG_9 @ 0x148

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff
Register enable = BANK1_INFO0_REGWEN_9
31302928272625242322212019181716
  HE_EN_9 ECC_EN_9 SCRAMBLE_EN_9
1514131211109876543210
ERASE_EN_9 PROG_EN_9 RD_EN_9 EN_9
BitsTypeResetNameDescription
3:0rw0x9EN_9

For FLASH_CTRL9

7:4rw0x9RD_EN_9

For FLASH_CTRL9

11:8rw0x9PROG_EN_9

For FLASH_CTRL9

15:12rw0x9ERASE_EN_9

For FLASH_CTRL9

19:16rw0x9SCRAMBLE_EN_9

For FLASH_CTRL9

23:20rw0x9ECC_EN_9

For FLASH_CTRL9

27:24rw0x9HE_EN_9

For FLASH_CTRL9


flash_ctrl.BANK1_INFO1_REGWEN @ 0x14c

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_0
BitsTypeResetNameDescription
0rw0c0x1REGION_0

Info1 page write enable. Once set to 0, it can longer be configured to 1

0x0Page locked

Region can no longer be configured until next reset

0x1Page enabled

Region can be configured


flash_ctrl.BANK1_INFO1_PAGE_CFG @ 0x150

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff
Register enable = BANK1_INFO1_REGWEN
31302928272625242322212019181716
  HE_EN_0 ECC_EN_0 SCRAMBLE_EN_0
1514131211109876543210
ERASE_EN_0 PROG_EN_0 RD_EN_0 EN_0
BitsTypeResetNameDescription
3:0rw0x9EN_0

Region enabled, following fields apply

7:4rw0x9RD_EN_0

Region can be read

11:8rw0x9PROG_EN_0

Region can be programmed

15:12rw0x9ERASE_EN_0

Region can be erased

19:16rw0x9SCRAMBLE_EN_0

Region is scramble enabled.

23:20rw0x9ECC_EN_0

Region is ECC enabled (both integrity and reliability ECC).

27:24rw0x9HE_EN_0

Region is high endurance enabled.


flash_ctrl.BANK1_INFO2_REGWEN_0 @ 0x154

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_0
BitsTypeResetNameDescription
0rw0c0x1REGION_0

Info2 page write enable. Once set to 0, it can longer be configured to 1

0x0Page locked

Region can no longer be configured until next reset

0x1Page enabled

Region can be configured


flash_ctrl.BANK1_INFO2_REGWEN_1 @ 0x158

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_1
BitsTypeResetNameDescription
0rw0c0x1REGION_1

For FLASH_CTRL1


flash_ctrl.BANK1_INFO2_PAGE_CFG_0 @ 0x15c

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff
Register enable = BANK1_INFO2_REGWEN_0
31302928272625242322212019181716
  HE_EN_0 ECC_EN_0 SCRAMBLE_EN_0
1514131211109876543210
ERASE_EN_0 PROG_EN_0 RD_EN_0 EN_0
BitsTypeResetNameDescription
3:0rw0x9EN_0

Region enabled, following fields apply

7:4rw0x9RD_EN_0

Region can be read

11:8rw0x9PROG_EN_0

Region can be programmed

15:12rw0x9ERASE_EN_0

Region can be erased

19:16rw0x9SCRAMBLE_EN_0

Region is scramble enabled.

23:20rw0x9ECC_EN_0

Region is ECC enabled (both integrity and reliability ECC).

27:24rw0x9HE_EN_0

Region is high endurance enabled.


flash_ctrl.BANK1_INFO2_PAGE_CFG_1 @ 0x160

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff
Register enable = BANK1_INFO2_REGWEN_1
31302928272625242322212019181716
  HE_EN_1 ECC_EN_1 SCRAMBLE_EN_1
1514131211109876543210
ERASE_EN_1 PROG_EN_1 RD_EN_1 EN_1
BitsTypeResetNameDescription
3:0rw0x9EN_1

For FLASH_CTRL1

7:4rw0x9RD_EN_1

For FLASH_CTRL1

11:8rw0x9PROG_EN_1

For FLASH_CTRL1

15:12rw0x9ERASE_EN_1

For FLASH_CTRL1

19:16rw0x9SCRAMBLE_EN_1

For FLASH_CTRL1

23:20rw0x9ECC_EN_1

For FLASH_CTRL1

27:24rw0x9HE_EN_1

For FLASH_CTRL1


flash_ctrl.BANK_CFG_REGWEN @ 0x164

Bank configuration registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  BANK
BitsTypeResetNameDescription
0rw0c0x1BANK

Bank register write enable. Once set to 0, it can longer be configured to 1

0x0Bank locked

Bank can no longer be configured until next reset

0x1Bank enabled

Bank can be configured


flash_ctrl.MP_BANK_CFG_SHADOWED @ 0x168

Memory properties bank configuration

Reset default = 0x0, mask 0x3
Register enable = BANK_CFG_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  ERASE_EN_1 ERASE_EN_0
BitsTypeResetNameDescription
0rw0x0ERASE_EN_0

Bank wide erase enable

1rw0x0ERASE_EN_1

Bank wide erase enable


flash_ctrl.OP_STATUS @ 0x16c

Flash Operation Status

Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  err done
BitsTypeResetNameDescription
0rw0x0done

Flash operation done. Set by HW, cleared by SW

1rw0x0err

Flash operation error. Set by HW, cleared by SW. See ERR_CODE for more details.


flash_ctrl.STATUS @ 0x170

Flash Controller Status

Reset default = 0xa, mask 0x1f
31302928272625242322212019181716
 
1514131211109876543210
  init_wip prog_empty prog_full rd_empty rd_full
BitsTypeResetNameDescription
0ro0x0rd_full

Flash read FIFO full, software must consume data

1ro0x1rd_empty

Flash read FIFO empty

2ro0x0prog_full

Flash program FIFO full

3ro0x1prog_empty

Flash program FIFO empty, software must provide data

4ro0x0init_wip

Flash controller undergoing init, inclusive of phy init


flash_ctrl.DEBUG_STATE @ 0x174

Current flash fsm state

Reset default = 0x0, mask 0x7ff
31302928272625242322212019181716
 
1514131211109876543210
  lcmgr_state
BitsTypeResetNameDescription
10:0roxlcmgr_state

Current lcmgr interface staet


flash_ctrl.ERR_CODE @ 0x178

Flash error code register. This register tabulates detailed error status of the flash. This is separate from OP_STATUS, which is used to indicate the current state of the software initiated flash operation.

Reset default = 0x0, mask 0xff

Note, all errors in this register are considered recoverable errors, ie, errors that could have been generated by software.

31302928272625242322212019181716
 
1514131211109876543210
  macro_err update_err prog_type_err prog_win_err prog_err rd_err mp_err op_err
BitsTypeResetNameDescription
0rw1c0x0op_err

Software has supplied an undefined operation. See CONTROL.OP for list of valid operations.

1rw1c0x0mp_err

Flash access has encountered an access permission error. Please see ERR_ADDR for exact address. This is a synchronous error.

2rw1c0x0rd_err

Flash read has an error. This could be a reliability ECC error or an storage integrity error encountered during a software issued controller read, see STD_FAULT_STATUS. See ERR_ADDR for exact address. This is a synchronous error.

3rw1c0x0prog_err

Flash program has an error. This could be a program integrity error, see STD_FAULT_STATUS. This is a synchronous error.

4rw1c0x0prog_win_err

Flash program has a window resolution error. Ie, the start of program and end of program are in different windows. Please check ERR_ADDR. This is a synchronous error.

5rw1c0x0prog_type_err

Flash program selected unavailable type, see PROG_TYPE_EN. This is a synchronous error.

6rw1c0x0update_err

A shadow register encountered an update error. This is an asynchronous error.

7rw1c0x0macro_err

A recoverable error has been encountered in the flash macro. Please read the flash macro status registers for more details.


flash_ctrl.STD_FAULT_STATUS @ 0x17c

This register tabulates standard fault status of the flash.

Reset default = 0x0, mask 0x1ff

These represent errors that occur in the standard structures of the design. For example fsm integrity, counter integrity and tlul integrity.

31302928272625242322212019181716
 
1514131211109876543210
  fifo_err ctrl_cnt_err phy_fsm_err storage_err arb_fsm_err lcmgr_intg_err lcmgr_err prog_intg_err reg_intg_err
BitsTypeResetNameDescription
0ro0x0reg_intg_err

The flash controller encountered a register integrity error.

1ro0x0prog_intg_err

The flash controller encountered a program data transmission integrity error.

2ro0x0lcmgr_err

The life cycle management interface has encountered a fatal error. The error is either an FSM sparse encoding error or a count error.

3ro0x0lcmgr_intg_err

The life cycle management interface has encountered a transmission integrity error. This is an integrity error on the generated integrity during a life cycle management interface read.

4ro0x0arb_fsm_err

The arbiter fsm has encountered a sparse encoding error.

5ro0x0storage_err

A shadow register encountered a storage error.

6ro0x0phy_fsm_err

A flash phy fsm has encountered a sparse encoding error.

7ro0x0ctrl_cnt_err

Flash ctrl read/prog has encountered a count error.

8ro0x0fifo_err

Flash primitive fifo's have encountered a count error.


flash_ctrl.FAULT_STATUS @ 0x180

This register tabulates customized fault status of the flash.

Reset default = 0x0, mask 0xfff

These are errors that are impossible to have been caused by software or unrecoverable in nature.

31302928272625242322212019181716
 
1514131211109876543210
  host_gnt_err arb_err spurious_ack phy_storage_err phy_relbl_err seed_err prog_type_err prog_win_err prog_err rd_err mp_err op_err
BitsTypeResetNameDescription
0ro0x0op_err

The flash life cycle management interface has supplied an undefined operation. See CONTROL.OP for list of valid operations.

1ro0x0mp_err

The flash life cycle management interface encountered a memory permission error.

2ro0x0rd_err

The flash life cycle management interface encountered a read error. This could be a reliability ECC error or an integrity ECC error encountered during a read, see STD_FAULT_STATUS for more details.

3ro0x0prog_err

The flash life cycle management interface encountered a program error. This could be a program integirty eror, see STD_FAULT_STATUS for more details.

4ro0x0prog_win_err

The flash life cycle management interface encountered a program resolution error.

5ro0x0prog_type_err

The flash life cycle management interface encountered a program type error. A program type not supported by the flash macro was issued.

6ro0x0seed_err

The seed reading process encountered an unexpected error.

7ro0x0phy_relbl_err

The flash macro encountered a storage reliability ECC error.

8ro0x0phy_storage_err

The flash macro encountered a storage integrity ECC error.

9ro0x0spurious_ack

The flash emitted an unexpected acknowledgement.

10ro0x0arb_err

The phy arbiter encountered inconsistent results.

11ro0x0host_gnt_err

A host transaction was granted with illegal properties.


flash_ctrl.ERR_ADDR @ 0x184

Synchronous error address

Reset default = 0x0, mask 0xfffff
31302928272625242322212019181716
  ERR_ADDR...
1514131211109876543210
...ERR_ADDR
BitsTypeResetNameDescription
19:0ro0x0ERR_ADDR

flash_ctrl.ECC_SINGLE_ERR_CNT @ 0x188

Total number of single bit ECC error count

Reset default = 0x0, mask 0xffff
31302928272625242322212019181716
 
1514131211109876543210
ECC_SINGLE_ERR_CNT_1 ECC_SINGLE_ERR_CNT_0
BitsTypeResetNameDescription
7:0rw0x0ECC_SINGLE_ERR_CNT_0

This count will not wrap when saturated

15:8rw0x0ECC_SINGLE_ERR_CNT_1

This count will not wrap when saturated


flash_ctrl.ECC_SINGLE_ERR_ADDR_0 @ 0x18c

Latest address of ECC single err

Reset default = 0x0, mask 0xfffff
31302928272625242322212019181716
  ECC_SINGLE_ERR_ADDR_0...
1514131211109876543210
...ECC_SINGLE_ERR_ADDR_0
BitsTypeResetNameDescription
19:0ro0x0ECC_SINGLE_ERR_ADDR_0

Latest single error address for this bank


flash_ctrl.ECC_SINGLE_ERR_ADDR_1 @ 0x190

Latest address of ECC single err

Reset default = 0x0, mask 0xfffff
31302928272625242322212019181716
  ECC_SINGLE_ERR_ADDR_1...
1514131211109876543210
...ECC_SINGLE_ERR_ADDR_1
BitsTypeResetNameDescription
19:0ro0x0ECC_SINGLE_ERR_ADDR_1

For ECC_SINGLE_ERR1


flash_ctrl.PHY_ALERT_CFG @ 0x194

Phy alert configuration

Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  alert_trig alert_ack
BitsTypeResetNameDescription
0rw0x0alert_ack

Acknowledge flash phy alert

1rw0x0alert_trig

Trigger flash phy alert


flash_ctrl.PHY_STATUS @ 0x198

Flash Phy Status

Reset default = 0x6, mask 0x7
31302928272625242322212019181716
 
1514131211109876543210
  prog_repair_avail prog_normal_avail init_wip
BitsTypeResetNameDescription
0ro0x0init_wip

Flash phy controller initializing

1ro0x1prog_normal_avail

Normal program supported

2ro0x1prog_repair_avail

Program repair supported


flash_ctrl.Scratch @ 0x19c

Flash Controller Scratch

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
data...
1514131211109876543210
...data
BitsTypeResetNameDescription
31:0rw0x0data

Flash ctrl scratch register


flash_ctrl.FIFO_LVL @ 0x1a0

Programmable depth where FIFOs should generate interrupts

Reset default = 0xf0f, mask 0x1f1f
31302928272625242322212019181716
 
1514131211109876543210
  RD   PROG
BitsTypeResetNameDescription
4:0rw0xfPROG

When the program FIFO drains to this level, trigger an interrupt. Default value is set such that interrupt does not trigger at reset.

7:5Reserved
12:8rw0xfRD

When the read FIFO fills to this level, trigger an interrupt. Default value is set such that interrupt does not trigger at reset.


flash_ctrl.FIFO_RST @ 0x1a4

Reset for flash controller FIFOs

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN
BitsTypeResetNameDescription
0rw0x0EN

Active high resets for both program and read FIFOs. This is especially useful after the controller encounters an error of some kind. This bit will hold the FIFO in reset as long as it is set.


flash_ctrl.CURR_FIFO_LVL @ 0x1a8

Current program and read fifo depth

Reset default = 0x0, mask 0x1f1f
31302928272625242322212019181716
 
1514131211109876543210
  RD   PROG
BitsTypeResetNameDescription
4:0ro0x0PROG

Current program fifo depth

7:5Reserved
12:8ro0x0RD

Current read fifo depth


flash_ctrl.prog_fifo @ + 0x1ac
1 item wo window
Byte writes are not supported
310
+0x1ac 

Flash program FIFO.

The FIFO is 16 entries of 4B flash words. This FIFO can only be programmed by software after a program operation has been initiated via the CONTROL register. This ensures accidental programming of the program FIFO cannot lock up the system.


flash_ctrl.rd_fifo @ + 0x1b0
1 item ro window
Byte writes are not supported
310
+0x1b0 

Flash read FIFO.

The FIFO is 16 entries of 4B flash words


Registers visible under device interface prim

Summary
Name Offset Length Description
flash_ctrl.CSR0_REGWEN 0x0 4

flash_ctrl.CSR1 0x4 4

flash_ctrl.CSR2 0x8 4

flash_ctrl.CSR3 0xc 4

flash_ctrl.CSR4 0x10 4

flash_ctrl.CSR5 0x14 4

flash_ctrl.CSR6 0x18 4

flash_ctrl.CSR7 0x1c 4

flash_ctrl.CSR8 0x20 4

flash_ctrl.CSR9 0x24 4

flash_ctrl.CSR10 0x28 4

flash_ctrl.CSR11 0x2c 4

flash_ctrl.CSR12 0x30 4

flash_ctrl.CSR13 0x34 4

flash_ctrl.CSR14 0x38 4

flash_ctrl.CSR15 0x3c 4

flash_ctrl.CSR16 0x40 4

flash_ctrl.CSR17 0x44 4

flash_ctrl.CSR18 0x48 4

flash_ctrl.CSR19 0x4c 4

flash_ctrl.CSR20 0x50 4

flash_ctrl.CSR0_REGWEN @ 0x0

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  field0
BitsTypeResetNameDescription
0rw0c0x1field0

Other values are reserved.


flash_ctrl.CSR1 @ 0x4

Reset default = 0x0, mask 0x1fff
Register enable = CSR0_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  field1 field0
BitsTypeResetNameDescription
7:0rw0x0field0

Other values are reserved.

12:8rw0x0field1

Other values are reserved.


flash_ctrl.CSR2 @ 0x8

Reset default = 0x0, mask 0xff
31302928272625242322212019181716
 
1514131211109876543210
  field7 field6 field5 field4 field3 field2 field1 field0
BitsTypeResetNameDescription
0rw1c0x0field0

Other values are reserved.

1rw1c0x0field1

Other values are reserved.

2rw1c0x0field2

Other values are reserved.

3rw0x0field3

Other values are reserved.

4rw1c0x0field4

Other values are reserved.

5rw1c0x0field5

Other values are reserved.

6rw1c0x0field6

Other values are reserved.

7rw0x0field7

Other values are reserved.


flash_ctrl.CSR3 @ 0xc

Reset default = 0x0, mask 0xfffffff
Register enable = CSR0_REGWEN
31302928272625242322212019181716
  field9 field8 field7 field6 field5 field4...
1514131211109876543210
...field4 field3 field2 field1 field0
BitsTypeResetNameDescription
3:0rw0x0field0

Other values are reserved.

7:4rw0x0field1

Other values are reserved.

10:8rw0x0field2

Other values are reserved.

13:11rw0x0field3

Other values are reserved.

16:14rw0x0field4

Other values are reserved.

19:17rw0x0field5

Other values are reserved.

20rw0x0field6

Other values are reserved.

23:21rw0x0field7

Other values are reserved.

25:24rw0x0field8

Other values are reserved.

27:26rw0x0field9

Other values are reserved.


flash_ctrl.CSR4 @ 0x10

Reset default = 0x0, mask 0xfff
Register enable = CSR0_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  field3 field2 field1 field0
BitsTypeResetNameDescription
2:0rw0x0field0

Other values are reserved.

5:3rw0x0field1

Other values are reserved.

8:6rw0x0field2

Other values are reserved.

11:9rw0x0field3

Other values are reserved.


flash_ctrl.CSR5 @ 0x14

Reset default = 0x0, mask 0x7fffff
Register enable = CSR0_REGWEN
31302928272625242322212019181716
  field4 field3...
1514131211109876543210
...field3 field2 field1 field0
BitsTypeResetNameDescription
2:0rw0x0field0

Other values are reserved.

4:3rw0x0field1

Other values are reserved.

13:5rw0x0field2

Other values are reserved.

18:14rw0x0field3

Other values are reserved.

22:19rw0x0field4

Other values are reserved.


flash_ctrl.CSR6 @ 0x18

Reset default = 0x0, mask 0x1ffffff
Register enable = CSR0_REGWEN
31302928272625242322212019181716
  field8 field7 field6 field5 field4 field3...
1514131211109876543210
...field3 field2 field1 field0
BitsTypeResetNameDescription
2:0rw0x0field0

Other values are reserved.

5:3rw0x0field1

Other values are reserved.

13:6rw0x0field2

Other values are reserved.

16:14rw0x0field3

Other values are reserved.

18:17rw0x0field4

Other values are reserved.

20:19rw0x0field5

Other values are reserved.

22:21rw0x0field6

Other values are reserved.

23rw0x0field7

Other values are reserved.

24rw0x0field8

Other values are reserved.


flash_ctrl.CSR7 @ 0x1c

Reset default = 0x0, mask 0x1ffff
Register enable = CSR0_REGWEN
31302928272625242322212019181716
  field1...
1514131211109876543210
...field1 field0
BitsTypeResetNameDescription
7:0rw0x0field0

Other values are reserved.

16:8rw0x0field1

Other values are reserved.


flash_ctrl.CSR8 @ 0x20

Reset default = 0x0, mask 0xffffffff
Register enable = CSR0_REGWEN
31302928272625242322212019181716
field0...
1514131211109876543210
...field0
BitsTypeResetNameDescription
31:0rw0x0field0

Other values are reserved.


flash_ctrl.CSR9 @ 0x24

Reset default = 0x0, mask 0xffffffff
Register enable = CSR0_REGWEN
31302928272625242322212019181716
field0...
1514131211109876543210
...field0
BitsTypeResetNameDescription
31:0rw0x0field0

Other values are reserved.


flash_ctrl.CSR10 @ 0x28

Reset default = 0x0, mask 0xffffffff
Register enable = CSR0_REGWEN
31302928272625242322212019181716
field0...
1514131211109876543210
...field0
BitsTypeResetNameDescription
31:0rw0x0field0

Other values are reserved.


flash_ctrl.CSR11 @ 0x2c

Reset default = 0x0, mask 0xffffffff
Register enable = CSR0_REGWEN
31302928272625242322212019181716
field0...
1514131211109876543210
...field0
BitsTypeResetNameDescription
31:0rw0x0field0

Other values are reserved.


flash_ctrl.CSR12 @ 0x30

Reset default = 0x0, mask 0x3ff
Register enable = CSR0_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  field0
BitsTypeResetNameDescription
9:0rw0x0field0

Other values are reserved.


flash_ctrl.CSR13 @ 0x34

Reset default = 0x0, mask 0x1fffff
Register enable = CSR0_REGWEN
31302928272625242322212019181716
  field1 field0...
1514131211109876543210
...field0
BitsTypeResetNameDescription
19:0rw0x0field0

Other values are reserved.

20rw0x0field1

Other values are reserved.


flash_ctrl.CSR14 @ 0x38

Reset default = 0x0, mask 0x1ff
Register enable = CSR0_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  field1 field0
BitsTypeResetNameDescription
7:0rw0x0field0

Other values are reserved.

8rw0x0field1

Other values are reserved.


flash_ctrl.CSR15 @ 0x3c

Reset default = 0x0, mask 0x1ff
Register enable = CSR0_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  field1 field0
BitsTypeResetNameDescription
7:0rw0x0field0

Other values are reserved.

8rw0x0field1

Other values are reserved.


flash_ctrl.CSR16 @ 0x40

Reset default = 0x0, mask 0x1ff
Register enable = CSR0_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  field1 field0
BitsTypeResetNameDescription
7:0rw0x0field0

Other values are reserved.

8rw0x0field1

Other values are reserved.


flash_ctrl.CSR17 @ 0x44

Reset default = 0x0, mask 0x1ff
Register enable = CSR0_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  field1 field0
BitsTypeResetNameDescription
7:0rw0x0field0

Other values are reserved.

8rw0x0field1

Other values are reserved.


flash_ctrl.CSR18 @ 0x48

Reset default = 0x0, mask 0x1
Register enable = CSR0_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  field0
BitsTypeResetNameDescription
0rw0x0field0

Other values are reserved.


flash_ctrl.CSR19 @ 0x4c

Reset default = 0x0, mask 0x1
Register enable = CSR0_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  field0
BitsTypeResetNameDescription
0rw0x0field0

Other values are reserved.


flash_ctrl.CSR20 @ 0x50

Reset default = 0x0, mask 0x7
31302928272625242322212019181716
 
1514131211109876543210
  field2 field1 field0
BitsTypeResetNameDescription
0rw1c0x0field0

Other values are reserved.

1rw1c0x0field1

Other values are reserved.

2ro0x0field2

Other values are reserved.


Registers visible under device interface mem

This interface does not expose any registers.