Flash Controller HWIP Technical Specification

Overview

This document describes the flash controller functionality. The flash controller is broken down into 3 major components

  • Open source flash controller
  • Closed source vendor flash wrapper
  • Closed source vendor flash module

A breakdown of the 3 can be seen below Flash High Level Boundaries

This open source flash controller is divided into two partitions.

  • Flash protocol controller
  • Flash physical controller

The remaining document focuses primarily on the function of these blocks.

This module conforms to the Comportable guideline for peripheral functionality. See that document for integration overview within the broader top level system.

Features

Flash Protocol Controller Features

The flash protocol controller interfaces with software and other hardware components in the system (such as life cycle, key manager and OTP). Regardless of the flash size underneath, the flash controller maintains the same data resolution as the bus and processor (default 4B). The flash physical controller (see section below) is then responsible for bridging that size gap between the default data resolution and the actual flash memory.

The protocol controller currently supports the following features:

  • Controller initiated read, program and erase of flash.
    • Erase can be either of a page, or an entire bank.
  • Support for differentiation between informational and data flash partitions.
  • Support for accessing multiple types of information partition.
    • Some flash storage support multiple types of information storage for each information partition.
  • Parameterized support for burst program / read, up to 64B.
    • Longer programs / reads are supported, however the protocol controller will directly back-pressure the bus if software supplies more data than can be consumed, or if software reads more than there is data available.
    • Software can also choose to operate by polling the current state of the FIFO or through FIFO interrupts (empty / full / level).
  • Flash memory protection at page boundaries.
  • Life cycle RMA entry.
  • Key manager secret seeds that are inaccessible to software.
  • Features to be added if required
    • Program verification
      • may not be required if flash memory supports alternative mechanisms of verification.
    • Erase verification
      • may not be required if flash memory supports alternative mechanisms of verification.
    • Flash redundant pages
      • Flash may contain additional pages used to remap broken pages for yield recovery.
      • The storage, loading and security of redundant pages may also be implemented in the physical controller or flash memory.

Features under consideration

  • Ability to access flash metadata bits (see flash ECC)
    • This feature is pending software discussions and actual usecase need.

Flash Physical Controller Features

The flash physical controller wraps the actual flash memory and translates both host and controller initiated requests into low level flash transactions.

The physical controller supports the following features

  • Multiple banks of flash memory
  • For each flash bank, parameterized support for number of flash pages (default to 256)
  • For each flash page, parameterized support for number of words and word size (default to 128 words of 8-bytes each)
  • Data and informational partitions within each bank of flash memory
  • Arbitration between host requests and controller requests at the bank level
    • Host requests are always favored, however the controller priority can escalate if it repeatedly loses arbitration
    • Since banks are arbitrated independently and transactions may take different amounts of times to complete, the physical controller is also responsible for ensuring in-order response to both the controller and host.
  • Flash read stage
    • Each bank maintains a parameterizable number of read buffers in front of the flash memory (default to 4).
    • The read buffers behave as miniature read-only-caches to store flash data when flash words are greater than bus words.
    • When a program or erase collides with an entry already stored in the read buffer, the buffer contents are invalidated.
      • This situation may arise if a read is followed by a program or erase.
  • Flash program stage
    • Flash data word packing when flash word size is an integer multiple of bus word size.
  • Flash scrambling
    • Flash supports XEX scrambling using the prince cipher

Features to be implemented

  • Flash scrambling
    • Scrambling is optional based on page boundaries and is configurable by software
  • Flash ECC
    • Flash supports SECDED on the flash word boundary, the ECC bits are stored in the metadata bits and are not normally visible to software.
    • A feature is under consideration to expose the metadata bits to the flash protocol controller.
    • ECC is optional based on page boudaries and is configurable by software

Flash Memory Overview

Unlike sram, flash memory is not typically organized as a contiguous block of generic storage. Instead it is organized into data partitions and information partitions.

The data partition holds generic data like a generic memory would. The information partition holds metadata about the data partition as well as design specific secret data. This includes but is not limited to:

  • Redundancy information.
  • Manufacturer specific information.
  • Manufacturer flash timing information.
  • Design specific unique seeds.
  • The redundancy pages themselves, which are not accessible directly as data partitions.

Note, there can be more than one information partition, and none of them are required to be the same size as the data partition. See the diagram below for an illustrative example. Flash Example Partition

Which type of partition is accessed is controlled through the CONTROL.PARTITION_SEL field. The current flash controller implements one type of information partition and thus is controlled by 1 bit only. This may change in the future.

Lastly, while the different partitions may be identical in some attributes, they are different in others.

  • All types of partitions must have the same page size and word size; however they are not required to have the same number of pages, thus some partitions may be larger and others smaller.
  • All types of partitions obey the same program and erase rules :
    • A bit cannot be programmed back to 1 once it has been programmed to 0.
    • Only erase can restore a bit to 1 under normal circumstances.
  • Data partitions can be directly read by software and other hardware hosts, while information partitions can only be read by the flash controller

By default, this design assumes 1 type of information partition and 4 pages per type of information partition.

Secret Information Partitions

Two information partition pages in the design hold secret seeds for the key manager. These pages, when enabled by life cycle and otp, are read upon flash controller initialization (no software configuration is required). The read values are then fed to the key manager for later processing. There is a page for creator and a page for the owner.

The seed pages are read under the following initialization conditions:

  • life cycle sets provision enable

See life cycle for more details.

Isolated Information Partitions

One information partition page in the design is used for manufacturing time authentication. The accessibility of this page is controlled by life cycle and otp.

During TEST states, the isolated page is only progrmmable. During production and RMA states, the isolated page is also readable.

See life cycle for more details

Theory of Operation

Block Diagram

Flash Block Diagram

Flash Protocol Controller

The Flash Protocol Controller sits between the host software interface, other hardware components and the flash physical controller. Its primary functions are two fold

  • Translate software program, erase and read requests into a high level protocol for the actual flash physical controller
  • Act as communication interface between flash and other components in the system, such as life cycle and key manager.

The flash protocol controller is not responsible for the detailed timing and waveform control of the flash, nor is it responsible for data scrambling and reliability metadata such as parity and ECC. Instead, it maintains FIFOs / interrupts for the software to process data, as well as high level abstraction of region protection controls and error handling.

The flash controller selects requests between the software and hardware interfaces. By default, the hardware interfaces have precendence and are used to read out seed materials from flash. The seed material is read twice to confirm the values are consistent. They are then forwarded to the key manager for processing. During this seed phase, software initiated activities are back-pressured until the seed reading is complete. It is recommended that instead of blindly issuing transactions to the flash controller, the software polls STATUS.INIT_WIP until it is 0.

Once the seed phase is complete, the flash controller switches to the software interface. Software can then read / program / erase the flash as needed.

When an RMA entry request is received from the life cycle manager, the flash controller waits for any pending flash transaction to complete, then switches priority to the hardware interface. The flash controller then initiates RMA entry process and notifies the life cycle controller when it is complete. Unlike the seed phase, after the RMA phase, the flash controller does not grant control back to software as the system is expected to reboot after an RMA attempt.

RMA Entry

During RMA entry, the flash controller “wipes” the contents of the following

  • Creator partition
  • Owner partition
  • Isolated partition
  • All data partitions

This process ensures that after RMA there is no sensitive information left that can be made use on the tester.

Memory Protection

Flash memory protection is handled differently depending on what type of partition is accessed.

For data partitions, software can configure a number of memory protection regions such as MP_REGION_CFG0. For each region, software specifies both the beginning page and the number of pages that belong to that region. Software then configures the access privileges for that region. Subsequent accesses are then allowed or denied based on the defined rule set. Similar to RISCV pmp, if two region overlaps, the lower region index has higher priority.

For information partitions, the protection is done per indvidual page. Each page can be configured with access privileges. As a result, software does not need to define a start and end page for information partitions. See BANK0_INFO_PAGE_CFG0 as an example.

Memory Protection for Key Manager and Life Cycle

While memory protection is largely under software control, certain behavior is hardwired to support key manager secret partitions and life cycle functions.

Software can only control the accessibility of the creator secret seed page under the following condition(s):

  • life cycle sets provision enable.
  • otp indicates the seeds are not locked.

Software can only control the accessibility of the owner secret seed page under the following condition(s):

  • life cycle sets provision enable.

During life cycle RMA transition, the software configured memory protection for both data and information partitions is ignored. Instead, the flash controller assumes a default accessibility setting that allows it to secure the chip and transition to RMA.

Program Resolution

Certain flash memories place restrictions on the program window. This means the flash accepts program beats only if all beats belong to the same address window. Typically, this boundary is nicely aligned (for example, 16 words, 32 words) and is related to how the flash memory amortizes the program operation over nearby words.

To support this function, the flash controller errors back anytime the start of the program beat is in a different window from the end of the program beat. The valid program range is thus the valid program resolution for a particular memory.

This information is not configurable but instead decided at design time and is exposed as a readable status.

Flash Physical Controller

The Flash Physical Controller is the wrapper module that contains the actual flash memory instantiation. It is responsible for arbitrating high level protocol commands (such as read, program, erase) as well as any additional security (scrambling) and reliability (ECC) features. The contained vendor wrapper module is then responsible for converting high level commands into low level signaling and timing specific to a particular flash vendor. The vendor wrapper module is also responsible for any BIST, redundancy handling, remapping features or custom configurations required for the flash.

The scramble keys are provided by an external static block such as the OTP.

Flash Scrambling

Flash scrambling is built using the XEX tweakable block cipher.

When a read transaction is sent to flash, the following steps are taken:

  • The tweak is calculated using the transaction address and a secret address key through a galois multiplier.
  • The data content is read out of flash.
  • If the data content is scrambled, the tweak is XOR’d with the scrambled text and then decrypted through the prince block cipher using a secret data key.
  • The output of the prince cipher is XOR’d again with the tweak and the final results are presented
  • If the data content is not scrambled, the prince and XOR steps are skipped and data provided directly back to the requestor.

When a program transaction is sent to flash, the same steps are taken if the address in question has scrambling enabled. During a program, the text is scrambled through the prince block cipher.

Scramble enablement is done differently depending on the type of partitions.

  • For data partitions, the scramble enablement is done on contiugous page boundaries.
    • Software has the ability to configure these regions and whether scramble is enabled.
  • For information partitions,the scramble enablement is done on a per page basis.
    • Software can configure for each page whether scramble is enabled.

Flash ECC

Similar to scrambling, flash ECC is enabled based on an address decode. The ECC for flash is chosen such that a fully erased flash word has valid ECC. Likewise a flash word that is completely 0 is also valid ECC.

ECC enablement is done differently depending on the type of partitions.

  • For data partitions, the ECC enablement is done on contiugous page boundaries.
    • Software has the ability to configure these regions and whether ECC is enabled.
  • For information partitions,the ECC enablement is done on a per page basis.
    • Software can configure for each page whether ECC is enabled.

Scrambling Consistency

The flash physical controller does not keep a history of when a particular memory location has scrambling enabled or disabled. This means if a memory locaiton was programmed while scrambled, disabling scrambling and then reading it back will result in garbage. Similarly, if a location was programmed while non-scrambled, enabling scrambling and then reading it back will also result in gargabe.

It it thus the programmer’s responsibility to maintain a consistent definition of whether a location is scrambled. It is also highly recommended in a normal use case to setup up scramble and non-scramble regions and not change it further.

Flash Read Pipeline

Since the system host reads directly from the flash for instructions, it is critical to not add significant latency during read, especially if de-scrambling is required. As such, the flash read is actually a two stage pipeline, where each stage can take multiple cycles.

Additionally, since the flash word size is typically larger than the bus word, recently read flash entries are locally cached. The cache behaves as a highly simplified read-only-cache and holds by default 4 flash words per flash bank.

When a read transaction is sent to flash, the following steps are taken:

  • A check is performed against the local cache
    • If there is a hit (either the entry is already in cache, or the entry is currently being processed), the transacton is immediately forwarded to the response queue.
    • If there is not a hit, an entry in the local cache is selected for allocation (round robin arbitration) and a flash read is issued.
  • When the flash read completes, its descrambling attributes are checked:
    • If descrambling is required, the read data begins the descrambling phase - at this time, a new flash read can be issued for the following transaction.
    • if descrambling is not required, the descrambling phase is skipped and the transaction is pushed to the response queue.
  • When the descrambling is complete, the descrambled text is pushed to the response queue.

The following diagram shows how the flash read pipeline timing works. Flash Read Pipeline

In this example, the first two host requests trigger a full sequence. The third host requests immediately hits in the local cache and responds in order after the first two.

Accessing Information Partition

The information partition uses the same address scheme as the data partition - which is directly accessible by software. This means the address of page{N}.word{M} is the same no matter which type of partition is accessed.

Which partition a specific transaction accesses is denoted through a separate field CONTROL.PARTITION_SEL in the CONTROL register. If CONTROL.PARTITION_SEL is set, then the information partition is accessed. If CONTROL.PARTITION_SEL is not set, then the corresponding word in the data partition is accessed.

Flash scrambling, if enabled, also applies to information partitions. However, one TBD feature is related to flash support of life cycle and manufacturing. It may be required for manufacturers to directly inject data into specific pages flash information partitions via die contacts. For these pages, scramble shall be permanently disabled as the manufacturer should not be aware of scrambling functions.

Flash Default Configuration

Since the flash controller is highly dependent on the specific flavor of flash memory chosen underneath, its configuration can vary widely between different integrations.

This sections details the default settings used by the flash controller:

  • Number of banks: 2
  • Number of pages per bank: 256
  • Program resolution: 8 flash words
  • Flash word data bits: 64
  • Flash word metadata bits: 8
  • ECC choice: Hamming code SECDED
  • Information partition types: 3
  • Size of information partition type 0: 10 pages
  • Size of information partition type 1: 1 page
  • Size of information partition type 2: 2 pages
  • Secret partition 0 (used for creator): Bank 0, information partition 0, page 1
  • Secret partition 1 (used for owner): Bank 0, information partition 0, page 2
  • Isolated partition: Bank 0, information partition 0, page 3

Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module FLASH_CTRL has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: clk_otp_i

Bus Device Interfaces (TL-UL): core_tl, prim_tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO:

Pin namedirectionDescription
tckinput

jtag clock

tmsinput

jtag tms

tdiinput

jtag input

tdooutput

jtag output

Interrupts:

Interrupt NameDescription
prog_empty

Program FIFO empty

prog_lvl

Program FIFO drained to level

rd_full

Read FIFO full

rd_lvl

Read FIFO filled to level

op_done

Operation complete

err

Error encountered

Security Alerts:

Alert NameDescription
recov_err

flash alerts directly from prim_flash

recov_mp_err

recoverable flash alert for permission error

recov_ecc_err

recoverable flash alert for ecc error

fatal_intg_err

Fatal integrity error

Signals

In addition to the interrupts and bus signals, the tables below lists the flash protocol controller I/Os.

Signal Direction Description
flash_i input Inputs from physical controller, connects to flash_ctrl_o of physical controller.
flash_o output Outputs to physical controller, connects to flash_ctrl_i of physical controller.
otp_i input Inputs from OTP, indicates the locked state of the creator seed page.
lc_i input Inputs from life cycle, indicates RMA intent and provisioning enable.
pwrmgr_i input Inputs from power manager, flash controller initialization request.

Each of flash_i and flash_o is a struct that packs together additional signals, as shown below

Signal Source Destination Description
req protocol controller physical controller Protocol controller initiated transaction
addr protocol controller physical controller Protocol controller initiated transaction address
part protocol controller physical controller Protocol controller initiated transaction partition type - data or informational
info_sel protocol controller physical controller Protocol controller initiated transaction information partition select - 0 ~ N
scramble_en protocol controller physical controller Protocol controller initiated transaction address is scramble enabled
ecc_en protocol controller physical controller Protocol controller initiated transaction address is ecc enabled
he_en protocol controller physical controller Protocol controller initiated transaction address is high endurance enabled
rd protocol controller physical controller Protocol controller initiated read
prog protocol controller physical controller Protocol controller initiated program
pg_erase protocol controller physical controller Protocol controller initiated page erase
prog_data protocol controller physical controller Protocol controller initiated program data, 1 flash word wide
prog_type protocol controller physical controller Protocol controller initiated program type, normal program or repair program
prog_last protocol controller physical controller Protocol controller last program beat
bk_erase protocol controller physical controller Protocol controller initiated bank erase
addr_key protocol controller physical controller Physical controller address scramble key
data_key protocol controller physical controller Physical controller data scramble key
rd_done physical controller protocol controller Physical controller read done
prog_done physical controller protocol controller Physical controller program done
erase_done physical controller protocol controller Physical controller erase done
init_busy physical controller protocol controller Physical controller reset release initialization in progress
rd_data physical controller protocol controller Physical Controller read data, 1 flash word wide

The physical controller IOs are listed and described below.

Signal Direction Description
host_req_i input Host initiated direct read, should always be highest priority. Host is only able to perform direct reads
host_addr_i input Address of host initiated direct read
host_req_rdy_o output Host request ready, ‘1’ implies transaction has been accepted, but not necessarily finished
host_req_done_o output Host request completed
host_rdata_o output Host read data, 1 flash word wide
flash_ctrl_i input Inputs from protocol controller, connects to flash_o of protocol controller
flash_ctrl_o output Outputs to protocol controller, connects to flash_i of protcol controller

Design Detials

Flash Protocol Controller Description

The flash protocol controller uses a simple FIFO interface to communicate between the software and flash physical controller. There is a read fifo for read operations, and a program fifo for program operations. Note, this means flash can be read both through the controller and the main bus interface. This may prove useful if the controller wishes to allocate specific regions to HW FSMs only, but is not a necessary feature.

When software initiates a read transaction of a programmable number of flash words, the flash controller will fill up the read FIFO for software to consume. Likewise, when software initiates a program transaction, software will fill up the program FIFO for the controller to consume.

The controller is designed such that the overall number of words in a transaction can significantly exceed the FIFO depth. In the case of read, once the FIFO is full, the controller will cease writing more entries and wait for software to consume the contents (an interrupt will be triggered to the software to alert it to such an event). In the case of program, the controller will stop writing to flash once all existing data is consumed - it will likewise trigger an interrupt to software to prepare more data. See detailed steps in theory of operation. The following is a diagram of the controller construction as well as its over connectivity with the flash module.

Flash Protocol Controller

Host Read

Unlike controller initiated reads, host reads have separate rdy / done signals to ensure transactions can be properly pipelined. As host reads are usually tied to host execution upstream, additional latency can severely harm performance and is not desired. The expected waveform from the perspective of the physical controller is shown below.

The host_req_done_o is always single cycle pulsed and upstream logic is expected to always accept and correctly handle the return. The same cycle the return data is posted a new command / address can be accepted. While the example shows flash reads completing in back to back cycles, this is typically not the case.

Controller Read

Unlike host reads, controller reads are not as performance critical and do not have command / data pipeline requirements. Instead, the protocol controller will hold the read request and address lines until the done is seen. Once the done is seen, the controller then transitions to the next read operation. The expected waveform from the perspective of the physical controller is shown below.

Controller Program

Program behavior is similar to reads. The protocol controller will hold the request, address and data lines until the programming is complete. The expected waveform from the perspective of the physical controller is shown below.

Programmers Guide

Issuing a Controller Read

To issue a flash read, the programmer must

  • Specify the address of the first flash word to read
  • Specify the number of total flash words to read, beginning at the supplied address
  • Specify the operation to be ‘READ’ type
  • Set the ‘START’ bit for the operation to begin

The above fields can be set in the CONTROL and ADDR registers. See library code for implementation.

It is acceptable for total number of flash words to be significantly greater than the depth of the read FIFO. In this situation, the read FIFO will fill up (or hit programmable fill value), pause the flash read and trigger an interrupt to software. Once there is space inside the FIFO, the controller will resume reading until the appropriate number of words have been read. Once the total count has been reached, the flash controller will post OP_DONE in the OP_STATUS register.

Issuing a Controller Program

To program flash, the same procedure as read is followed. However, instead of setting the CONTROL register for read operation, a program operation is selected instead. Software will then fill the program FIFO and wait for the controller to consume this data. Similar to the read case, the controller will automatically stall when there is insufficient data in the FIFO. When all desired words have been programmed, the controller will post OP_DONE in the OP_STATUS register.

Register Table

The flash protocol controller maintains two separate access windows for the FIFO. It is implemented this way because the access window supports transaction back-pressure should the FIFO become full (in case of write) or empty (in case of read).

Registers visible under device interface core

FLASH_CTRL.INTR_STATE @ 0x0

Interrupt State Register

Reset default = 0x0, mask 0x3f
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  err op_done rd_lvl rd_full prog_lvl prog_empty
BitsTypeResetNameDescription
0rw1c0x0prog_empty

Program FIFO empty

1rw1c0x0prog_lvl

Program FIFO drained to level

2rw1c0x0rd_full

Read FIFO full

3rw1c0x0rd_lvl

Read FIFO filled to level

4rw1c0x0op_done

Operation complete

5rw1c0x0err

Error encountered


FLASH_CTRL.INTR_ENABLE @ 0x4

Interrupt Enable Register

Reset default = 0x0, mask 0x3f
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  err op_done rd_lvl rd_full prog_lvl prog_empty
BitsTypeResetNameDescription
0rw0x0prog_empty

Enable interrupt when INTR_STATE.prog_empty is set.

1rw0x0prog_lvl

Enable interrupt when INTR_STATE.prog_lvl is set.

2rw0x0rd_full

Enable interrupt when INTR_STATE.rd_full is set.

3rw0x0rd_lvl

Enable interrupt when INTR_STATE.rd_lvl is set.

4rw0x0op_done

Enable interrupt when INTR_STATE.op_done is set.

5rw0x0err

Enable interrupt when INTR_STATE.err is set.


FLASH_CTRL.INTR_TEST @ 0x8

Interrupt Test Register

Reset default = 0x0, mask 0x3f
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  err op_done rd_lvl rd_full prog_lvl prog_empty
BitsTypeResetNameDescription
0wo0x0prog_empty

Write 1 to force INTR_STATE.prog_empty to 1.

1wo0x0prog_lvl

Write 1 to force INTR_STATE.prog_lvl to 1.

2wo0x0rd_full

Write 1 to force INTR_STATE.rd_full to 1.

3wo0x0rd_lvl

Write 1 to force INTR_STATE.rd_lvl to 1.

4wo0x0op_done

Write 1 to force INTR_STATE.op_done to 1.

5wo0x0err

Write 1 to force INTR_STATE.err to 1.


FLASH_CTRL.ALERT_TEST @ 0xc

Alert Test Register

Reset default = 0x0, mask 0xf
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  fatal_intg_err recov_ecc_err recov_mp_err recov_err
BitsTypeResetNameDescription
0wo0x0recov_err

Write 1 to trigger one alert event of this kind.

1wo0x0recov_mp_err

Write 1 to trigger one alert event of this kind.

2wo0x0recov_ecc_err

Write 1 to trigger one alert event of this kind.

3wo0x0fatal_intg_err

Write 1 to trigger one alert event of this kind.


FLASH_CTRL.FLASH_DISABLE @ 0x10

Disable flash functionality

Reset default = 0x0, mask 0x1
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  VAL
BitsTypeResetNameDescription
0rw1s0x0VAL

Disables flash functionality completely. This is a shortcut mechanism used by the software to completely kill flash in case of emergency.


FLASH_CTRL.INIT @ 0x14

Controller init register

Reset default = 0x0, mask 0x1
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  VAL
BitsTypeResetNameDescription
0rw1s0x0VAL

Initializes the flash controller. During the initialization process, the flash controller reads out the root seeds before allowing other usage of the flash controller.


FLASH_CTRL.CTRL_REGWEN @ 0x18

Controls the configurability of the CONTROL register.

Reset default = 0x1, mask 0x1

This register ensures the contents of CONTROL cannot be changed by software once a flash operation has begun.

It unlocks whenever the existing flash operation completes, regardless of success or error.

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  EN
BitsTypeResetNameDescription
0ro0x1EN

Configuration enable.

This bit defaults to 1 and is set to 0 by hardware when flash operation is initiated. When the controller completes the flash operation, this bit is set back to 1 to allow software configuration of CONTROL


FLASH_CTRL.CONTROL @ 0x1c

Control register

Reset default = 0x0, mask 0xfff07f1
Register enable = CTRL_REGWEN
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  NUM
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  INFO_SEL PARTITION_SEL ERASE_SEL PROG_SEL OP   START
BitsTypeResetNameDescription
0rw0x0START

Start flash transaction. This bit shall only be set after the other fields of the CONTROL register and ADDR have been programmed

3:1Reserved
5:4rw0x0OP

Flash operation selection

0Read

Flash Read.

Read desired number of flash words

1Prog

Flash Program.

Program desired number of flash words

2Erase

Flash Erase Operation.

See ERASE_SEL for details on erase operation

Other values are reserved.

6rw0x0PROG_SEL

Flash program operation type selection

0Normal program

Normal program operation to the flash

1Program repair

Repair program operation to the flash. Whether this is actually supported depends on the underlying flash memory.

7rw0x0ERASE_SEL

Flash erase operation type selection

0Page Erase

Erase 1 page of flash

1Bank Erase

Erase 1 bank of flash

8rw0x0PARTITION_SEL

Selects either info or data partition for operation.

When 0, select data partition - this is the portion of flash that is accessible both by the host and by the controller.

When 1, select info partition - this is the portion of flash that is only accessible by the controller.

10:9rw0x0INFO_SEL

Informational partions can have multiple types.

This field selects the info type to be accessed.

15:11Reserved
27:16rw0x0NUM

Number of bus words the flash operation should read or program.


FLASH_CTRL.ADDR @ 0x20

Address for flash operation

Reset default = 0x0, mask 0xffffffff
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START...
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...START
BitsTypeResetNameDescription
31:0rw0x0START

Start address of a flash transaction. Software should supply the full byte address. The flash controller will then truncate the address as needed. For read operations, the flash controller will truncate to the closest, lower word aligned address. For example, if 0x13 is supplied, the controller will perform a read at address 0x10.

Program operations behave similarly, the controller does not have read modified write support.

For page erases, the controller will truncate to the closest lower page aligned address. Similarly for bank erases, the controller will truncate to the closest lower bank aligned address.


FLASH_CTRL.PROG_TYPE_EN @ 0x24

Enable different program types

Reset default = 0x3, mask 0x3
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  REPAIR NORMAL
BitsTypeResetNameDescription
0rw0c0x1NORMAL

Normal prog type available

1rw0c0x1REPAIR

Repair prog type available


FLASH_CTRL.ERASE_SUSPEND @ 0x28

Suspend erase

Reset default = 0x0, mask 0x1
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  REQ
BitsTypeResetNameDescription
0rw0x0REQ

When 1, request erase suspend. If no erase ongoing, the request is immediately cleared by hardware If erase ongoing, the request is fed to the flash_phy and cleared when the suspend is handled.


FLASH_CTRL.REGION_CFG_REGWEN_0 @ 0x2c

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_0
BitsTypeResetNameDescription
0rw0c0x1REGION_0

Region register write enable. Once set to 0, it can longer be configured to 1

0Region locked

Region can no longer be configured until next reset

1Region enabled

Region can be configured


FLASH_CTRL.REGION_CFG_REGWEN_1 @ 0x30

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  REGION_1
BitsTypeResetNameDescription
0rw0c0x1REGION_1

For FLASH_CTRL1


FLASH_CTRL.REGION_CFG_REGWEN_2 @ 0x34

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  REGION_2
BitsTypeResetNameDescription
0rw0c0x1REGION_2

For FLASH_CTRL2


FLASH_CTRL.REGION_CFG_REGWEN_3 @ 0x38

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  REGION_3
BitsTypeResetNameDescription
0rw0c0x1REGION_3

For FLASH_CTRL3


FLASH_CTRL.REGION_CFG_REGWEN_4 @ 0x3c

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  REGION_4
BitsTypeResetNameDescription
0rw0c0x1REGION_4

For FLASH_CTRL4


FLASH_CTRL.REGION_CFG_REGWEN_5 @ 0x40

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_5
BitsTypeResetNameDescription
0rw0c0x1REGION_5

For FLASH_CTRL5


FLASH_CTRL.REGION_CFG_REGWEN_6 @ 0x44

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  REGION_6
BitsTypeResetNameDescription
0rw0c0x1REGION_6

For FLASH_CTRL6


FLASH_CTRL.REGION_CFG_REGWEN_7 @ 0x48

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  REGION_7
BitsTypeResetNameDescription
0rw0c0x1REGION_7

For FLASH_CTRL7


FLASH_CTRL.MP_REGION_CFG_0 @ 0x4c

Memory property configuration for data partition

Reset default = 0x0, mask 0x7ffff7f
Register enable = REGION_CFG_REGWEN_0
31302928272625242322212019181716
  SIZE_0 BASE_0...
1514131211109876543210
...BASE_0   HE_EN_0 ECC_EN_0 SCRAMBLE_EN_0 ERASE_EN_0 PROG_EN_0 RD_EN_0 EN_0
BitsTypeResetNameDescription
0rw0x0EN_0

Region enabled, following fields apply

1rw0x0RD_EN_0

Region can be read

2rw0x0PROG_EN_0

Region can be programmed

3rw0x0ERASE_EN_0

Region can be erased

4rw0x0SCRAMBLE_EN_0

Region is scramble enabled.

5rw0x0ECC_EN_0

Region is ECC enabled.

6rw0x0HE_EN_0

Region is high endurance enabled.

7Reserved
16:8rw0x0BASE_0

Region base page. Note the granularity is page, not byte or word

26:17rw0x0SIZE_0

Region size in number of pages


FLASH_CTRL.MP_REGION_CFG_1 @ 0x50

Memory property configuration for data partition

Reset default = 0x0, mask 0x7ffff7f
Register enable = REGION_CFG_REGWEN_1
31302928272625242322212019181716
  SIZE_1 BASE_1...
1514131211109876543210
...BASE_1   HE_EN_1 ECC_EN_1 SCRAMBLE_EN_1 ERASE_EN_1 PROG_EN_1 RD_EN_1 EN_1
BitsTypeResetNameDescription
0rw0x0EN_1

For FLASH_CTRL1

1rw0x0RD_EN_1

For FLASH_CTRL1

2rw0x0PROG_EN_1

For FLASH_CTRL1

3rw0x0ERASE_EN_1

For FLASH_CTRL1

4rw0x0SCRAMBLE_EN_1

For FLASH_CTRL1

5rw0x0ECC_EN_1

For FLASH_CTRL1

6rw0x0HE_EN_1

For FLASH_CTRL1

7Reserved
16:8rw0x0BASE_1

For FLASH_CTRL1

26:17rw0x0SIZE_1

For FLASH_CTRL1


FLASH_CTRL.MP_REGION_CFG_2 @ 0x54

Memory property configuration for data partition

Reset default = 0x0, mask 0x7ffff7f
Register enable = REGION_CFG_REGWEN_2
31302928272625242322212019181716
  SIZE_2 BASE_2...
1514131211109876543210
...BASE_2   HE_EN_2 ECC_EN_2 SCRAMBLE_EN_2 ERASE_EN_2 PROG_EN_2 RD_EN_2 EN_2
BitsTypeResetNameDescription
0rw0x0EN_2

For FLASH_CTRL2

1rw0x0RD_EN_2

For FLASH_CTRL2

2rw0x0PROG_EN_2

For FLASH_CTRL2

3rw0x0ERASE_EN_2

For FLASH_CTRL2

4rw0x0SCRAMBLE_EN_2

For FLASH_CTRL2

5rw0x0ECC_EN_2

For FLASH_CTRL2

6rw0x0HE_EN_2

For FLASH_CTRL2

7Reserved
16:8rw0x0BASE_2

For FLASH_CTRL2

26:17rw0x0SIZE_2

For FLASH_CTRL2


FLASH_CTRL.MP_REGION_CFG_3 @ 0x58

Memory property configuration for data partition

Reset default = 0x0, mask 0x7ffff7f
Register enable = REGION_CFG_REGWEN_3
31302928272625242322212019181716
  SIZE_3 BASE_3...
1514131211109876543210
...BASE_3   HE_EN_3 ECC_EN_3 SCRAMBLE_EN_3 ERASE_EN_3 PROG_EN_3 RD_EN_3 EN_3
BitsTypeResetNameDescription
0rw0x0EN_3

For FLASH_CTRL3

1rw0x0RD_EN_3

For FLASH_CTRL3

2rw0x0PROG_EN_3

For FLASH_CTRL3

3rw0x0ERASE_EN_3

For FLASH_CTRL3

4rw0x0SCRAMBLE_EN_3

For FLASH_CTRL3

5rw0x0ECC_EN_3

For FLASH_CTRL3

6rw0x0HE_EN_3

For FLASH_CTRL3

7Reserved
16:8rw0x0BASE_3

For FLASH_CTRL3

26:17rw0x0SIZE_3

For FLASH_CTRL3


FLASH_CTRL.MP_REGION_CFG_4 @ 0x5c

Memory property configuration for data partition

Reset default = 0x0, mask 0x7ffff7f
Register enable = REGION_CFG_REGWEN_4
31302928272625242322212019181716
  SIZE_4 BASE_4...
1514131211109876543210
...BASE_4   HE_EN_4 ECC_EN_4 SCRAMBLE_EN_4 ERASE_EN_4 PROG_EN_4 RD_EN_4 EN_4
BitsTypeResetNameDescription
0rw0x0EN_4

For FLASH_CTRL4

1rw0x0RD_EN_4

For FLASH_CTRL4

2rw0x0PROG_EN_4

For FLASH_CTRL4

3rw0x0ERASE_EN_4

For FLASH_CTRL4

4rw0x0SCRAMBLE_EN_4

For FLASH_CTRL4

5rw0x0ECC_EN_4

For FLASH_CTRL4

6rw0x0HE_EN_4

For FLASH_CTRL4

7Reserved
16:8rw0x0BASE_4

For FLASH_CTRL4

26:17rw0x0SIZE_4

For FLASH_CTRL4


FLASH_CTRL.MP_REGION_CFG_5 @ 0x60

Memory property configuration for data partition

Reset default = 0x0, mask 0x7ffff7f
Register enable = REGION_CFG_REGWEN_5
31302928272625242322212019181716
  SIZE_5 BASE_5...
1514131211109876543210
...BASE_5   HE_EN_5 ECC_EN_5 SCRAMBLE_EN_5 ERASE_EN_5 PROG_EN_5 RD_EN_5 EN_5
BitsTypeResetNameDescription
0rw0x0EN_5

For FLASH_CTRL5

1rw0x0RD_EN_5

For FLASH_CTRL5

2rw0x0PROG_EN_5

For FLASH_CTRL5

3rw0x0ERASE_EN_5

For FLASH_CTRL5

4rw0x0SCRAMBLE_EN_5

For FLASH_CTRL5

5rw0x0ECC_EN_5

For FLASH_CTRL5

6rw0x0HE_EN_5

For FLASH_CTRL5

7Reserved
16:8rw0x0BASE_5

For FLASH_CTRL5

26:17rw0x0SIZE_5

For FLASH_CTRL5


FLASH_CTRL.MP_REGION_CFG_6 @ 0x64

Memory property configuration for data partition

Reset default = 0x0, mask 0x7ffff7f
Register enable = REGION_CFG_REGWEN_6
31302928272625242322212019181716
  SIZE_6 BASE_6...
1514131211109876543210
...BASE_6   HE_EN_6 ECC_EN_6 SCRAMBLE_EN_6 ERASE_EN_6 PROG_EN_6 RD_EN_6 EN_6
BitsTypeResetNameDescription
0rw0x0EN_6

For FLASH_CTRL6

1rw0x0RD_EN_6

For FLASH_CTRL6

2rw0x0PROG_EN_6

For FLASH_CTRL6

3rw0x0ERASE_EN_6

For FLASH_CTRL6

4rw0x0SCRAMBLE_EN_6

For FLASH_CTRL6

5rw0x0ECC_EN_6

For FLASH_CTRL6

6rw0x0HE_EN_6

For FLASH_CTRL6

7Reserved
16:8rw0x0BASE_6

For FLASH_CTRL6

26:17rw0x0SIZE_6

For FLASH_CTRL6


FLASH_CTRL.MP_REGION_CFG_7 @ 0x68

Memory property configuration for data partition

Reset default = 0x0, mask 0x7ffff7f
Register enable = REGION_CFG_REGWEN_7
31302928272625242322212019181716
  SIZE_7 BASE_7...
1514131211109876543210
...BASE_7   HE_EN_7 ECC_EN_7 SCRAMBLE_EN_7 ERASE_EN_7 PROG_EN_7 RD_EN_7 EN_7
BitsTypeResetNameDescription
0rw0x0EN_7

For FLASH_CTRL7

1rw0x0RD_EN_7

For FLASH_CTRL7

2rw0x0PROG_EN_7

For FLASH_CTRL7

3rw0x0ERASE_EN_7

For FLASH_CTRL7

4rw0x0SCRAMBLE_EN_7

For FLASH_CTRL7

5rw0x0ECC_EN_7

For FLASH_CTRL7

6rw0x0HE_EN_7

For FLASH_CTRL7

7Reserved
16:8rw0x0BASE_7

For FLASH_CTRL7

26:17rw0x0SIZE_7

For FLASH_CTRL7


FLASH_CTRL.DEFAULT_REGION @ 0x6c

Default region properties

Reset default = 0x0, mask 0x3f
31302928272625242322212019181716
 
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  HE_EN ECC_EN SCRAMBLE_EN ERASE_EN PROG_EN RD_EN
BitsTypeResetNameDescription
0rw0x0RD_EN

Region can be read

1rw0x0PROG_EN

Region can be programmed

2rw0x0ERASE_EN

Region can be erased

3rw0x0SCRAMBLE_EN

Region is scrambleenabled

4rw0x0ECC_EN

Region is ECC enabled

5rw0x0HE_EN

Region is high endurance enabled


FLASH_CTRL.BANK0_INFO0_REGWEN_0 @ 0x70

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  REGION_0
BitsTypeResetNameDescription
0rw0c0x1REGION_0

Info0 page write enable. Once set to 0, it can longer be configured to 1

0Page locked

Region can no longer be configured until next reset

1Page enabled

Region can be configured


FLASH_CTRL.BANK0_INFO0_REGWEN_1 @ 0x74

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_1
BitsTypeResetNameDescription
0rw0c0x1REGION_1

For FLASH_CTRL1


FLASH_CTRL.BANK0_INFO0_REGWEN_2 @ 0x78

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_2
BitsTypeResetNameDescription
0rw0c0x1REGION_2

For FLASH_CTRL2


FLASH_CTRL.BANK0_INFO0_REGWEN_3 @ 0x7c

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_3
BitsTypeResetNameDescription
0rw0c0x1REGION_3

For FLASH_CTRL3


FLASH_CTRL.BANK0_INFO0_REGWEN_4 @ 0x80

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_4
BitsTypeResetNameDescription
0rw0c0x1REGION_4

For FLASH_CTRL4


FLASH_CTRL.BANK0_INFO0_REGWEN_5 @ 0x84

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_5
BitsTypeResetNameDescription
0rw0c0x1REGION_5

For FLASH_CTRL5


FLASH_CTRL.BANK0_INFO0_REGWEN_6 @ 0x88

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_6
BitsTypeResetNameDescription
0rw0c0x1REGION_6

For FLASH_CTRL6


FLASH_CTRL.BANK0_INFO0_REGWEN_7 @ 0x8c

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_7
BitsTypeResetNameDescription
0rw0c0x1REGION_7

For FLASH_CTRL7


FLASH_CTRL.BANK0_INFO0_REGWEN_8 @ 0x90

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_8
BitsTypeResetNameDescription
0rw0c0x1REGION_8

For FLASH_CTRL8


FLASH_CTRL.BANK0_INFO0_REGWEN_9 @ 0x94

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_9
BitsTypeResetNameDescription
0rw0c0x1REGION_9

For FLASH_CTRL9


FLASH_CTRL.BANK0_INFO0_PAGE_CFG_0 @ 0x98

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x0, mask 0x7f
Register enable = BANK0_INFO0_REGWEN_0
31302928272625242322212019181716
 
1514131211109876543210
  HE_EN_0 ECC_EN_0 SCRAMBLE_EN_0 ERASE_EN_0 PROG_EN_0 RD_EN_0 EN_0
BitsTypeResetNameDescription
0rw0x0EN_0

Region enabled, following fields apply

1rw0x0RD_EN_0

Region can be read

2rw0x0PROG_EN_0

Region can be programmed

3rw0x0ERASE_EN_0

Region can be erased

4rw0x0SCRAMBLE_EN_0

Region is scramble enabled.

5rw0x0ECC_EN_0

Region is ECC enabled.

6rw0x0HE_EN_0

Region is high endurance enabled.


FLASH_CTRL.BANK0_INFO0_PAGE_CFG_1 @ 0x9c

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x0, mask 0x7f
Register enable = BANK0_INFO0_REGWEN_1
31302928272625242322212019181716
 
1514131211109876543210
  HE_EN_1 ECC_EN_1 SCRAMBLE_EN_1 ERASE_EN_1 PROG_EN_1 RD_EN_1 EN_1
BitsTypeResetNameDescription
0rw0x0EN_1

For FLASH_CTRL1

1rw0x0RD_EN_1

For FLASH_CTRL1

2rw0x0PROG_EN_1

For FLASH_CTRL1

3rw0x0ERASE_EN_1

For FLASH_CTRL1

4rw0x0SCRAMBLE_EN_1

For FLASH_CTRL1

5rw0x0ECC_EN_1

For FLASH_CTRL1

6rw0x0HE_EN_1

For FLASH_CTRL1


FLASH_CTRL.BANK0_INFO0_PAGE_CFG_2 @ 0xa0

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x0, mask 0x7f
Register enable = BANK0_INFO0_REGWEN_2
31302928272625242322212019181716
 
1514131211109876543210
  HE_EN_2 ECC_EN_2 SCRAMBLE_EN_2 ERASE_EN_2 PROG_EN_2 RD_EN_2 EN_2
BitsTypeResetNameDescription
0rw0x0EN_2

For FLASH_CTRL2

1rw0x0RD_EN_2

For FLASH_CTRL2

2rw0x0PROG_EN_2

For FLASH_CTRL2

3rw0x0ERASE_EN_2

For FLASH_CTRL2

4rw0x0SCRAMBLE_EN_2

For FLASH_CTRL2

5rw0x0ECC_EN_2

For FLASH_CTRL2

6rw0x0HE_EN_2

For FLASH_CTRL2


FLASH_CTRL.BANK0_INFO0_PAGE_CFG_3 @ 0xa4

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x0, mask 0x7f
Register enable = BANK0_INFO0_REGWEN_3
31302928272625242322212019181716
 
1514131211109876543210
  HE_EN_3 ECC_EN_3 SCRAMBLE_EN_3 ERASE_EN_3 PROG_EN_3 RD_EN_3 EN_3
BitsTypeResetNameDescription
0rw0x0EN_3

For FLASH_CTRL3

1rw0x0RD_EN_3

For FLASH_CTRL3

2rw0x0PROG_EN_3

For FLASH_CTRL3

3rw0x0ERASE_EN_3

For FLASH_CTRL3

4rw0x0SCRAMBLE_EN_3

For FLASH_CTRL3

5rw0x0ECC_EN_3

For FLASH_CTRL3

6rw0x0HE_EN_3

For FLASH_CTRL3


FLASH_CTRL.BANK0_INFO0_PAGE_CFG_4 @ 0xa8

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x0, mask 0x7f
Register enable = BANK0_INFO0_REGWEN_4
31302928272625242322212019181716
 
1514131211109876543210
  HE_EN_4 ECC_EN_4 SCRAMBLE_EN_4 ERASE_EN_4 PROG_EN_4 RD_EN_4 EN_4
BitsTypeResetNameDescription
0rw0x0EN_4

For FLASH_CTRL4

1rw0x0RD_EN_4

For FLASH_CTRL4

2rw0x0PROG_EN_4

For FLASH_CTRL4

3rw0x0ERASE_EN_4

For FLASH_CTRL4

4rw0x0SCRAMBLE_EN_4

For FLASH_CTRL4

5rw0x0ECC_EN_4

For FLASH_CTRL4

6rw0x0HE_EN_4

For FLASH_CTRL4


FLASH_CTRL.BANK0_INFO0_PAGE_CFG_5 @ 0xac

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x0, mask 0x7f
Register enable = BANK0_INFO0_REGWEN_5
31302928272625242322212019181716
 
1514131211109876543210
  HE_EN_5 ECC_EN_5 SCRAMBLE_EN_5 ERASE_EN_5 PROG_EN_5 RD_EN_5 EN_5
BitsTypeResetNameDescription
0rw0x0EN_5

For FLASH_CTRL5

1rw0x0RD_EN_5

For FLASH_CTRL5

2rw0x0PROG_EN_5

For FLASH_CTRL5

3rw0x0ERASE_EN_5

For FLASH_CTRL5

4rw0x0SCRAMBLE_EN_5

For FLASH_CTRL5

5rw0x0ECC_EN_5

For FLASH_CTRL5

6rw0x0HE_EN_5

For FLASH_CTRL5


FLASH_CTRL.BANK0_INFO0_PAGE_CFG_6 @ 0xb0

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x0, mask 0x7f
Register enable = BANK0_INFO0_REGWEN_6
31302928272625242322212019181716
 
1514131211109876543210
  HE_EN_6 ECC_EN_6 SCRAMBLE_EN_6 ERASE_EN_6 PROG_EN_6 RD_EN_6 EN_6
BitsTypeResetNameDescription
0rw0x0EN_6

For FLASH_CTRL6

1rw0x0RD_EN_6

For FLASH_CTRL6

2rw0x0PROG_EN_6

For FLASH_CTRL6

3rw0x0ERASE_EN_6

For FLASH_CTRL6

4rw0x0SCRAMBLE_EN_6

For FLASH_CTRL6

5rw0x0ECC_EN_6

For FLASH_CTRL6

6rw0x0HE_EN_6

For FLASH_CTRL6


FLASH_CTRL.BANK0_INFO0_PAGE_CFG_7 @ 0xb4

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x0, mask 0x7f
Register enable = BANK0_INFO0_REGWEN_7
31302928272625242322212019181716
 
1514131211109876543210
  HE_EN_7 ECC_EN_7 SCRAMBLE_EN_7 ERASE_EN_7 PROG_EN_7 RD_EN_7 EN_7
BitsTypeResetNameDescription
0rw0x0EN_7

For FLASH_CTRL7

1rw0x0RD_EN_7

For FLASH_CTRL7

2rw0x0PROG_EN_7

For FLASH_CTRL7

3rw0x0ERASE_EN_7

For FLASH_CTRL7

4rw0x0SCRAMBLE_EN_7

For FLASH_CTRL7

5rw0x0ECC_EN_7

For FLASH_CTRL7

6rw0x0HE_EN_7

For FLASH_CTRL7


FLASH_CTRL.BANK0_INFO0_PAGE_CFG_8 @ 0xb8

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x0, mask 0x7f
Register enable = BANK0_INFO0_REGWEN_8
31302928272625242322212019181716
 
1514131211109876543210
  HE_EN_8 ECC_EN_8 SCRAMBLE_EN_8 ERASE_EN_8 PROG_EN_8 RD_EN_8 EN_8
BitsTypeResetNameDescription
0rw0x0EN_8

For FLASH_CTRL8

1rw0x0RD_EN_8

For FLASH_CTRL8

2rw0x0PROG_EN_8

For FLASH_CTRL8

3rw0x0ERASE_EN_8

For FLASH_CTRL8

4rw0x0SCRAMBLE_EN_8

For FLASH_CTRL8

5rw0x0ECC_EN_8

For FLASH_CTRL8

6rw0x0HE_EN_8

For FLASH_CTRL8


FLASH_CTRL.BANK0_INFO0_PAGE_CFG_9 @ 0xbc

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x0, mask 0x7f
Register enable = BANK0_INFO0_REGWEN_9
31302928272625242322212019181716
 
1514131211109876543210
  HE_EN_9 ECC_EN_9 SCRAMBLE_EN_9 ERASE_EN_9 PROG_EN_9 RD_EN_9 EN_9
BitsTypeResetNameDescription
0rw0x0EN_9

For FLASH_CTRL9

1rw0x0RD_EN_9

For FLASH_CTRL9

2rw0x0PROG_EN_9

For FLASH_CTRL9

3rw0x0ERASE_EN_9

For FLASH_CTRL9

4rw0x0SCRAMBLE_EN_9

For FLASH_CTRL9

5rw0x0ECC_EN_9

For FLASH_CTRL9

6rw0x0HE_EN_9

For FLASH_CTRL9


FLASH_CTRL.BANK0_INFO1_REGWEN @ 0xc0

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  REGION_0
BitsTypeResetNameDescription
0rw0c0x1REGION_0

Info1 page write enable. Once set to 0, it can longer be configured to 1

0Page locked

Region can no longer be configured until next reset

1Page enabled

Region can be configured


FLASH_CTRL.BANK0_INFO1_PAGE_CFG @ 0xc4

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x0, mask 0x7f
Register enable = BANK0_INFO1_REGWEN
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  HE_EN_0 ECC_EN_0 SCRAMBLE_EN_0 ERASE_EN_0 PROG_EN_0 RD_EN_0 EN_0
BitsTypeResetNameDescription
0rw0x0EN_0

Region enabled, following fields apply

1rw0x0RD_EN_0

Region can be read

2rw0x0PROG_EN_0

Region can be programmed

3rw0x0ERASE_EN_0

Region can be erased

4rw0x0SCRAMBLE_EN_0

Region is scramble enabled.

5rw0x0ECC_EN_0

Region is ECC enabled.

6rw0x0HE_EN_0

Region is high endurance enabled.


FLASH_CTRL.BANK0_INFO2_REGWEN_0 @ 0xc8

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
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  REGION_0
BitsTypeResetNameDescription
0rw0c0x1REGION_0

Info2 page write enable. Once set to 0, it can longer be configured to 1

0Page locked

Region can no longer be configured until next reset

1Page enabled

Region can be configured


FLASH_CTRL.BANK0_INFO2_REGWEN_1 @ 0xcc

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
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  REGION_1
BitsTypeResetNameDescription
0rw0c0x1REGION_1

For FLASH_CTRL1


FLASH_CTRL.BANK0_INFO2_PAGE_CFG_0 @ 0xd0

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x0, mask 0x7f
Register enable = BANK0_INFO2_REGWEN_0
31302928272625242322212019181716
 
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  HE_EN_0 ECC_EN_0 SCRAMBLE_EN_0 ERASE_EN_0 PROG_EN_0 RD_EN_0 EN_0
BitsTypeResetNameDescription
0rw0x0EN_0

Region enabled, following fields apply

1rw0x0RD_EN_0

Region can be read

2rw0x0PROG_EN_0

Region can be programmed

3rw0x0ERASE_EN_0

Region can be erased

4rw0x0SCRAMBLE_EN_0

Region is scramble enabled.

5rw0x0ECC_EN_0

Region is ECC enabled.

6rw0x0HE_EN_0

Region is high endurance enabled.


FLASH_CTRL.BANK0_INFO2_PAGE_CFG_1 @ 0xd4

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x0, mask 0x7f
Register enable = BANK0_INFO2_REGWEN_1
31302928272625242322212019181716
 
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  HE_EN_1 ECC_EN_1 SCRAMBLE_EN_1 ERASE_EN_1 PROG_EN_1 RD_EN_1 EN_1
BitsTypeResetNameDescription
0rw0x0EN_1

For FLASH_CTRL1

1rw0x0RD_EN_1

For FLASH_CTRL1

2rw0x0PROG_EN_1

For FLASH_CTRL1

3rw0x0ERASE_EN_1

For FLASH_CTRL1

4rw0x0SCRAMBLE_EN_1

For FLASH_CTRL1

5rw0x0ECC_EN_1

For FLASH_CTRL1

6rw0x0HE_EN_1

For FLASH_CTRL1


FLASH_CTRL.BANK1_INFO0_REGWEN_0 @ 0xd8

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
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  REGION_0
BitsTypeResetNameDescription
0rw0c0x1REGION_0

Info0 page write enable. Once set to 0, it can longer be configured to 1

0Page locked

Region can no longer be configured until next reset

1Page enabled

Region can be configured


FLASH_CTRL.BANK1_INFO0_REGWEN_1 @ 0xdc

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
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  REGION_1
BitsTypeResetNameDescription
0rw0c0x1REGION_1

For FLASH_CTRL1


FLASH_CTRL.BANK1_INFO0_REGWEN_2 @ 0xe0

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
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  REGION_2
BitsTypeResetNameDescription
0rw0c0x1REGION_2

For FLASH_CTRL2


FLASH_CTRL.BANK1_INFO0_REGWEN_3 @ 0xe4

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
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  REGION_3
BitsTypeResetNameDescription
0rw0c0x1REGION_3

For FLASH_CTRL3


FLASH_CTRL.BANK1_INFO0_REGWEN_4 @ 0xe8

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
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  REGION_4
BitsTypeResetNameDescription
0rw0c0x1REGION_4

For FLASH_CTRL4


FLASH_CTRL.BANK1_INFO0_REGWEN_5 @ 0xec

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
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  REGION_5
BitsTypeResetNameDescription
0rw0c0x1REGION_5

For FLASH_CTRL5


FLASH_CTRL.BANK1_INFO0_REGWEN_6 @ 0xf0

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
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  REGION_6
BitsTypeResetNameDescription
0rw0c0x1REGION_6

For FLASH_CTRL6


FLASH_CTRL.BANK1_INFO0_REGWEN_7 @ 0xf4

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
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  REGION_7
BitsTypeResetNameDescription
0rw0c0x1REGION_7

For FLASH_CTRL7


FLASH_CTRL.BANK1_INFO0_REGWEN_8 @ 0xf8

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
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  REGION_8
BitsTypeResetNameDescription
0rw0c0x1REGION_8

For FLASH_CTRL8


FLASH_CTRL.BANK1_INFO0_REGWEN_9 @ 0xfc

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
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  REGION_9
BitsTypeResetNameDescription
0rw0c0x1REGION_9

For FLASH_CTRL9


FLASH_CTRL.BANK1_INFO0_PAGE_CFG_0 @ 0x100

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x0, mask 0x7f
Register enable = BANK1_INFO0_REGWEN_0
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  HE_EN_0 ECC_EN_0 SCRAMBLE_EN_0 ERASE_EN_0 PROG_EN_0 RD_EN_0 EN_0
BitsTypeResetNameDescription
0rw0x0EN_0

Region enabled, following fields apply

1rw0x0RD_EN_0

Region can be read

2rw0x0PROG_EN_0

Region can be programmed

3rw0x0ERASE_EN_0

Region can be erased

4rw0x0SCRAMBLE_EN_0

Region is scramble enabled.

5rw0x0ECC_EN_0

Region is ECC enabled.

6rw0x0HE_EN_0

Region is high endurance enabled.


FLASH_CTRL.BANK1_INFO0_PAGE_CFG_1 @ 0x104

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x0, mask 0x7f
Register enable = BANK1_INFO0_REGWEN_1
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  HE_EN_1 ECC_EN_1 SCRAMBLE_EN_1 ERASE_EN_1 PROG_EN_1 RD_EN_1 EN_1
BitsTypeResetNameDescription
0rw0x0EN_1

For FLASH_CTRL1

1rw0x0RD_EN_1

For FLASH_CTRL1

2rw0x0PROG_EN_1

For FLASH_CTRL1

3rw0x0ERASE_EN_1

For FLASH_CTRL1

4rw0x0SCRAMBLE_EN_1

For FLASH_CTRL1

5rw0x0ECC_EN_1

For FLASH_CTRL1

6rw0x0HE_EN_1

For FLASH_CTRL1


FLASH_CTRL.BANK1_INFO0_PAGE_CFG_2 @ 0x108

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x0, mask 0x7f
Register enable = BANK1_INFO0_REGWEN_2
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  HE_EN_2 ECC_EN_2 SCRAMBLE_EN_2 ERASE_EN_2 PROG_EN_2 RD_EN_2 EN_2
BitsTypeResetNameDescription
0rw0x0EN_2

For FLASH_CTRL2

1rw0x0RD_EN_2

For FLASH_CTRL2

2rw0x0PROG_EN_2

For FLASH_CTRL2

3rw0x0ERASE_EN_2

For FLASH_CTRL2

4rw0x0SCRAMBLE_EN_2

For FLASH_CTRL2

5rw0x0ECC_EN_2

For FLASH_CTRL2

6rw0x0HE_EN_2

For FLASH_CTRL2


FLASH_CTRL.BANK1_INFO0_PAGE_CFG_3 @ 0x10c

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x0, mask 0x7f
Register enable = BANK1_INFO0_REGWEN_3
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  HE_EN_3 ECC_EN_3 SCRAMBLE_EN_3 ERASE_EN_3 PROG_EN_3 RD_EN_3 EN_3
BitsTypeResetNameDescription
0rw0x0EN_3

For FLASH_CTRL3

1rw0x0RD_EN_3

For FLASH_CTRL3

2rw0x0PROG_EN_3

For FLASH_CTRL3

3rw0x0ERASE_EN_3

For FLASH_CTRL3

4rw0x0SCRAMBLE_EN_3

For FLASH_CTRL3

5rw0x0ECC_EN_3

For FLASH_CTRL3

6rw0x0HE_EN_3

For FLASH_CTRL3


FLASH_CTRL.BANK1_INFO0_PAGE_CFG_4 @ 0x110

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x0, mask 0x7f
Register enable = BANK1_INFO0_REGWEN_4
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  HE_EN_4 ECC_EN_4 SCRAMBLE_EN_4 ERASE_EN_4 PROG_EN_4 RD_EN_4 EN_4
BitsTypeResetNameDescription
0rw0x0EN_4

For FLASH_CTRL4

1rw0x0RD_EN_4

For FLASH_CTRL4

2rw0x0PROG_EN_4

For FLASH_CTRL4

3rw0x0ERASE_EN_4

For FLASH_CTRL4

4rw0x0SCRAMBLE_EN_4

For FLASH_CTRL4

5rw0x0ECC_EN_4

For FLASH_CTRL4

6rw0x0HE_EN_4

For FLASH_CTRL4


FLASH_CTRL.BANK1_INFO0_PAGE_CFG_5 @ 0x114

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x0, mask 0x7f
Register enable = BANK1_INFO0_REGWEN_5
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  HE_EN_5 ECC_EN_5 SCRAMBLE_EN_5 ERASE_EN_5 PROG_EN_5 RD_EN_5 EN_5
BitsTypeResetNameDescription
0rw0x0EN_5

For FLASH_CTRL5

1rw0x0RD_EN_5

For FLASH_CTRL5

2rw0x0PROG_EN_5

For FLASH_CTRL5

3rw0x0ERASE_EN_5

For FLASH_CTRL5

4rw0x0SCRAMBLE_EN_5

For FLASH_CTRL5

5rw0x0ECC_EN_5

For FLASH_CTRL5

6rw0x0HE_EN_5

For FLASH_CTRL5


FLASH_CTRL.BANK1_INFO0_PAGE_CFG_6 @ 0x118

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x0, mask 0x7f
Register enable = BANK1_INFO0_REGWEN_6
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  HE_EN_6 ECC_EN_6 SCRAMBLE_EN_6 ERASE_EN_6 PROG_EN_6 RD_EN_6 EN_6
BitsTypeResetNameDescription
0rw0x0EN_6

For FLASH_CTRL6

1rw0x0RD_EN_6

For FLASH_CTRL6

2rw0x0PROG_EN_6

For FLASH_CTRL6

3rw0x0ERASE_EN_6

For FLASH_CTRL6

4rw0x0SCRAMBLE_EN_6

For FLASH_CTRL6

5rw0x0ECC_EN_6

For FLASH_CTRL6

6rw0x0HE_EN_6

For FLASH_CTRL6


FLASH_CTRL.BANK1_INFO0_PAGE_CFG_7 @ 0x11c

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x0, mask 0x7f
Register enable = BANK1_INFO0_REGWEN_7
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  HE_EN_7 ECC_EN_7 SCRAMBLE_EN_7 ERASE_EN_7 PROG_EN_7 RD_EN_7 EN_7
BitsTypeResetNameDescription
0rw0x0EN_7

For FLASH_CTRL7

1rw0x0RD_EN_7

For FLASH_CTRL7

2rw0x0PROG_EN_7

For FLASH_CTRL7

3rw0x0ERASE_EN_7

For FLASH_CTRL7

4rw0x0SCRAMBLE_EN_7

For FLASH_CTRL7

5rw0x0ECC_EN_7

For FLASH_CTRL7

6rw0x0HE_EN_7

For FLASH_CTRL7


FLASH_CTRL.BANK1_INFO0_PAGE_CFG_8 @ 0x120

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x0, mask 0x7f
Register enable = BANK1_INFO0_REGWEN_8
31302928272625242322212019181716
 
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  HE_EN_8 ECC_EN_8 SCRAMBLE_EN_8 ERASE_EN_8 PROG_EN_8 RD_EN_8 EN_8
BitsTypeResetNameDescription
0rw0x0EN_8

For FLASH_CTRL8

1rw0x0RD_EN_8

For FLASH_CTRL8

2rw0x0PROG_EN_8

For FLASH_CTRL8

3rw0x0ERASE_EN_8

For FLASH_CTRL8

4rw0x0SCRAMBLE_EN_8

For FLASH_CTRL8

5rw0x0ECC_EN_8

For FLASH_CTRL8

6rw0x0HE_EN_8

For FLASH_CTRL8


FLASH_CTRL.BANK1_INFO0_PAGE_CFG_9 @ 0x124

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x0, mask 0x7f
Register enable = BANK1_INFO0_REGWEN_9
31302928272625242322212019181716
 
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  HE_EN_9 ECC_EN_9 SCRAMBLE_EN_9 ERASE_EN_9 PROG_EN_9 RD_EN_9 EN_9
BitsTypeResetNameDescription
0rw0x0EN_9

For FLASH_CTRL9

1rw0x0RD_EN_9

For FLASH_CTRL9

2rw0x0PROG_EN_9

For FLASH_CTRL9

3rw0x0ERASE_EN_9

For FLASH_CTRL9

4rw0x0SCRAMBLE_EN_9

For FLASH_CTRL9

5rw0x0ECC_EN_9

For FLASH_CTRL9

6rw0x0HE_EN_9

For FLASH_CTRL9


FLASH_CTRL.BANK1_INFO1_REGWEN @ 0x128

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
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  REGION_0
BitsTypeResetNameDescription
0rw0c0x1REGION_0

Info1 page write enable. Once set to 0, it can longer be configured to 1

0Page locked

Region can no longer be configured until next reset

1Page enabled

Region can be configured


FLASH_CTRL.BANK1_INFO1_PAGE_CFG @ 0x12c

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x0, mask 0x7f
Register enable = BANK1_INFO1_REGWEN
31302928272625242322212019181716
 
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  HE_EN_0 ECC_EN_0 SCRAMBLE_EN_0 ERASE_EN_0 PROG_EN_0 RD_EN_0 EN_0
BitsTypeResetNameDescription
0rw0x0EN_0

Region enabled, following fields apply

1rw0x0RD_EN_0

Region can be read

2rw0x0PROG_EN_0

Region can be programmed

3rw0x0ERASE_EN_0

Region can be erased

4rw0x0SCRAMBLE_EN_0

Region is scramble enabled.

5rw0x0ECC_EN_0

Region is ECC enabled.

6rw0x0HE_EN_0

Region is high endurance enabled.


FLASH_CTRL.BANK1_INFO2_REGWEN_0 @ 0x130

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
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  REGION_0
BitsTypeResetNameDescription
0rw0c0x1REGION_0

Info2 page write enable. Once set to 0, it can longer be configured to 1

0Page locked

Region can no longer be configured until next reset

1Page enabled

Region can be configured


FLASH_CTRL.BANK1_INFO2_REGWEN_1 @ 0x134

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  REGION_1
BitsTypeResetNameDescription
0rw0c0x1REGION_1

For FLASH_CTRL1


FLASH_CTRL.BANK1_INFO2_PAGE_CFG_0 @ 0x138

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x0, mask 0x7f
Register enable = BANK1_INFO2_REGWEN_0
31302928272625242322212019181716
 
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  HE_EN_0 ECC_EN_0 SCRAMBLE_EN_0 ERASE_EN_0 PROG_EN_0 RD_EN_0 EN_0
BitsTypeResetNameDescription
0rw0x0EN_0

Region enabled, following fields apply

1rw0x0RD_EN_0

Region can be read

2rw0x0PROG_EN_0

Region can be programmed

3rw0x0ERASE_EN_0

Region can be erased

4rw0x0SCRAMBLE_EN_0

Region is scramble enabled.

5rw0x0ECC_EN_0

Region is ECC enabled.

6rw0x0HE_EN_0

Region is high endurance enabled.


FLASH_CTRL.BANK1_INFO2_PAGE_CFG_1 @ 0x13c

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x0, mask 0x7f
Register enable = BANK1_INFO2_REGWEN_1
31302928272625242322212019181716
 
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  HE_EN_1 ECC_EN_1 SCRAMBLE_EN_1 ERASE_EN_1 PROG_EN_1 RD_EN_1 EN_1
BitsTypeResetNameDescription
0rw0x0EN_1

For FLASH_CTRL1

1rw0x0RD_EN_1

For FLASH_CTRL1

2rw0x0PROG_EN_1

For FLASH_CTRL1

3rw0x0ERASE_EN_1

For FLASH_CTRL1

4rw0x0SCRAMBLE_EN_1

For FLASH_CTRL1

5rw0x0ECC_EN_1

For FLASH_CTRL1

6rw0x0HE_EN_1

For FLASH_CTRL1


FLASH_CTRL.BANK_CFG_REGWEN @ 0x140

Bank configuration registers configuration enable.

Reset default = 0x1, mask 0x1
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  BANK
BitsTypeResetNameDescription
0rw0c0x1BANK

Bank register write enable. Once set to 0, it can longer be configured to 1

0Bank locked

Bank can no longer be configured until next reset

1Bank enabled

Bank can be configured


FLASH_CTRL.MP_BANK_CFG @ 0x144

Memory properties bank configuration

Reset default = 0x0, mask 0x3
Register enable = BANK_CFG_REGWEN
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  ERASE_EN_1 ERASE_EN_0
BitsTypeResetNameDescription
0rw0x0ERASE_EN_0

Bank wide erase enable

1rw0x0ERASE_EN_1

Bank wide erase enable


FLASH_CTRL.OP_STATUS @ 0x148

Flash Operation Status

Reset default = 0x0, mask 0x3
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  err done
BitsTypeResetNameDescription
0rwxdone

Flash operation done. Set by HW, cleared by SW

1rwxerr

Flash operation error. Set by HW, cleared by SW. See ERR_CODE for more details.


FLASH_CTRL.STATUS @ 0x14c

Flash Controller Status

Reset default = 0xa, mask 0x1f
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  init_wip prog_empty prog_full rd_empty rd_full
BitsTypeResetNameDescription
0roxrd_full

Flash read FIFO full, software must consume data

1ro0x1rd_empty

Flash read FIFO empty

2roxprog_full

Flash program FIFO full

3ro0x1prog_empty

Flash program FIFO empty, software must provide data

4roxinit_wip

Flash controller undergoing init, inclusive of phy init


FLASH_CTRL.ERR_CODE_INTR_EN @ 0x150

Interrupt enable mask for error code. Only enabled bits will generate interrupts. Bits that are not enabled will still be reflected in the ERR_CODE register, but will not trigger an interrupt

Reset default = 0x0, mask 0x1f
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  ecc_multi_err ecc_single_err mp_err flash_alert_en flash_err_en
BitsTypeResetNameDescription
0rwxflash_err_en

interrupt mask for flash error

1rwxflash_alert_en

interrupt mask for flash alert

2rwxmp_err

interrupt mask for memory properties error

3rwxecc_single_err

interrupt mask for single bit ecc error

4rwxecc_multi_err

interrupt mask for multiple bits ecc error


FLASH_CTRL.ERR_CODE @ 0x154

Flash error code register. This register tabulates detailed error status of the flash. This is separate from OP_STATUS, which is used to indicate the current state of the software initiated flash operation.

Reset default = 0x0, mask 0x1f
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  ecc_multi_err ecc_single_err mp_err flash_alert flash_err
BitsTypeResetNameDescription
0rw1cxflash_err

The flash memory itself has an error, please check the vendor specs for details of the error.

1rw1cxflash_alert

The flash memory itself has triggered an alert, please check the vendor specs for details of the error.

2rw1cxmp_err

Flash access has encountered an access permission error. Please see ERR_ADDR for exact address.

3rw1cxecc_single_err

Flash access has encountered a single bit ECC error. Please see !!ECC_SINGLE_ERR_ADDR for exact address.

4rw1cxecc_multi_err

Flash access has encountered a multi bit ECC error. Please see !!ECC_MULTI_ERR_ADDR for exact address.


FLASH_CTRL.ERR_ADDR @ 0x158

Access permission error address

Reset default = 0x0, mask 0x1ff
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  ERR_ADDR
BitsTypeResetNameDescription
8:0ro0x0ERR_ADDR

FLASH_CTRL.ECC_SINGLE_ERR_CNT @ 0x15c

Total number of single bit ECC error count

Reset default = 0x0, mask 0xff
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  ECC_SINGLE_ERR_CNT
BitsTypeResetNameDescription
7:0rw1c0x0ECC_SINGLE_ERR_CNT

This count will not wrap when saturated


FLASH_CTRL.ECC_SINGLE_ERR_ADDR_0 @ 0x160

Latest single bit error address (correctable)

Reset default = 0x0, mask 0xfffff
31302928272625242322212019181716
  ECC_SINGLE_ERR_ADDR_0...
1514131211109876543210
...ECC_SINGLE_ERR_ADDR_0
BitsTypeResetNameDescription
19:0ro0x0ECC_SINGLE_ERR_ADDR_0

FLASH_CTRL.ECC_SINGLE_ERR_ADDR_1 @ 0x164

Latest single bit error address (correctable)

Reset default = 0x0, mask 0xfffff
31302928272625242322212019181716
  ECC_SINGLE_ERR_ADDR_1...
1514131211109876543210
...ECC_SINGLE_ERR_ADDR_1
BitsTypeResetNameDescription
19:0ro0x0ECC_SINGLE_ERR_ADDR_1

For ECC_SINGLE_ERR1


FLASH_CTRL.ECC_MULTI_ERR_CNT @ 0x168

Total number of multi bit ECC error count

Reset default = 0x0, mask 0xff
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  ECC_MULTI_ERR_CNT
BitsTypeResetNameDescription
7:0rw1c0x0ECC_MULTI_ERR_CNT

This count will not wrap when saturated


FLASH_CTRL.ECC_MULTI_ERR_ADDR_0 @ 0x16c

Latest multi bit error address (uncorrectable)

Reset default = 0x0, mask 0xfffff
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  ECC_MULTI_ERR_ADDR_0...
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...ECC_MULTI_ERR_ADDR_0
BitsTypeResetNameDescription
19:0ro0x0ECC_MULTI_ERR_ADDR_0

FLASH_CTRL.ECC_MULTI_ERR_ADDR_1 @ 0x170

Latest multi bit error address (uncorrectable)

Reset default = 0x0, mask 0xfffff
31302928272625242322212019181716
  ECC_MULTI_ERR_ADDR_1...
1514131211109876543210
...ECC_MULTI_ERR_ADDR_1
BitsTypeResetNameDescription
19:0ro0x0ECC_MULTI_ERR_ADDR_1

For ECC_MULTI_ERR1


FLASH_CTRL.PHY_ERR_CFG_REGWEN @ 0x174

Controls the configurability of the PHY_ERR_CFG register.

Reset default = 0x1, mask 0x1
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  EN
BitsTypeResetNameDescription
0rw0c0x1EN

Configuration enable.


FLASH_CTRL.PHY_ERR_CFG @ 0x178

Phy error configuration

Reset default = 0x0, mask 0x1
Register enable = PHY_ERR_CFG_REGWEN
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  ECC_MULTI_ERR_DATA_EN
BitsTypeResetNameDescription
0rwxECC_MULTI_ERR_DATA_EN

Transaction error response for ECC multi bit errors in data type transactions. When set to 1, the error response is propagated to the source. When set to 0, the error response is silenced.

Note this register only controls whether an error response is generated to the source for data transactions. It does not control whether ERR_CODE and its associated error status register collects error information.

This can be used by software to dictate whether a multi-bit error should be reflected as a bus error to bus hosts or the flash controller.

The reason this may not be desired is because software may want to triage the actual bit change, and that would not be possible if an error response is always generated. The hosts may simply react on the error and discard the data.


FLASH_CTRL.PHY_ALERT_CFG @ 0x17c

Phy alert configuration

Reset default = 0x0, mask 0x3
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  alert_trig alert_ack
BitsTypeResetNameDescription
0rwxalert_ack

Acknowledge flash phy alert

1rwxalert_trig

Trigger flash phy alert


FLASH_CTRL.PHY_STATUS @ 0x180

Flash Phy Status

Reset default = 0x6, mask 0x7
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  prog_repair_avail prog_normal_avail init_wip
BitsTypeResetNameDescription
0roxinit_wip

Flash phy controller initializing

1ro0x1prog_normal_avail

Normal program supported

2ro0x1prog_repair_avail

Program repair supported


FLASH_CTRL.Scratch @ 0x184

Flash Controller Scratch

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
data...
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...data
BitsTypeResetNameDescription
31:0rwxdata

Flash ctrl scratch register


FLASH_CTRL.FIFO_LVL @ 0x188

Programmable depth where FIFOs should generate interrupts

Reset default = 0xf0f, mask 0x1f1f
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  RD   PROG
BitsTypeResetNameDescription
4:0rw0xfPROG

When the program FIFO drains to this level, trigger an interrupt. Default value is set such that interrupt does not trigger at reset.

7:5Reserved
12:8rw0xfRD

When the read FIFO fills to this level, trigger an interrupt. Default value is set such that interrupt does not trigger at reset.


FLASH_CTRL.FIFO_RST @ 0x18c

Reset for flash controller FIFOs

Reset default = 0x0, mask 0x1
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  EN
BitsTypeResetNameDescription
0rw0x0EN

Active high resets for both program and read FIFOs. This is especially useful after the controller encounters an error of some kind. This bit will hold the FIFO in reset as long as it is set.


FLASH_CTRL.prog_fifo @ + 0x190
1 item wo window
Byte writes are not supported
310
+0x190 
+0x194 
 ...
+0x18c 
+0x190 

Flash program FIFO.

The FIFO is 16 entries of 4B flash words. This FIFO can only be programmed by software after a program operation has been initiated via the CONTROL register. This ensures accidental programming of the program FIFO cannot lock up the system.


FLASH_CTRL.rd_fifo @ + 0x194
1 item ro window
Byte writes are not supported
310
+0x194 
+0x198 
 ...
+0x190 
+0x194 

Flash read FIFO.

The FIFO is 16 entries of 4B flash words


Registers visible under device interface prim