Flash Controller HWIP Technical Specification

Overview

This document specifies flash hardware IP functionality. As the final feature set will largely depend on how similar flash IPs are, it is at the moment unclear where the open-source / proprietary boundaries should lie. This document thus makes a best effort estimate as to what that boundary should be and breaks the functionality down accordingly.

This document assumes flash functionality shall be divided into two partitions.

  • Flash protocol controller
  • Flash physical controller

This module conforms to the Comportable guideline for peripheral functionality. See that document for integration overview within the broader top level system.

Features

Flash Protocol Controller Features

  • Support controller initiated read, program and erase of flash.
    • Erase can be either of a page, or an entire bank.
  • Parameterized support for number of flash banks (default to 2)
  • For each flash bank, parameterized support for number of flash pages (default to 256)
  • For each flash page, parameterized support for number of words and word size (default to 256 words of 4-bytes each)
  • Parameterized support for burst writes, up to 64B
    • Controller currently does not support page boundary checks; it is thus legal for software to burst write across a page boundary
  • Features to be added if required
    • Parameterizable data width
    • Program verification
      • may not be required if flash physical controller supports alternative mechanisms of verification.
    • Erase verification
      • may not be required if flash physical controller supports alternative mechanisms of verification.
    • Parity / ECC support on a per flash page granularity
      • may not be required depending on flash reliability or overall system security strategy.
    • Flash redundant pages
      • Flash may contain additional pages used to remap broken pages for yield recovery.
      • The storage, loading and security of redundant pages may also be implemented in the physical controller.
    • Flash information pages
      • Flash may contain additional pages outside of the data banks to hold manufacturing information (such as wafer location).
      • Extra logic may not be required if flash information pages is treated as just a separate address.

Flash Physical Controller Features

As the flash physical controller is highly dependent on flash memory selected, the default flash physical controller simply emulates real flash behavior with on-chip memories. The goal of the emulated flash is to provide software developers with a reasonable representation of a well-behaving flash operating under nominal conditions.

Below are the emulated properties

  • Flash reset to all 1's
  • Writing of a word will take 50 (parameterizable) clock cycles
  • Erasing of a page will take 200 (parameterizable) clock cycles
  • Erasing of a bank will take 2000 (parameterizable) clock cycles
  • A bit, once written to 0, cannot be written back to 1 until an erase operation has been performed
  • Support for simultaneous controller (read / program / erase) and host (read) operations.
    • Host operations are always prioritized unless controller operation is already ongoing.
  • The arbitration resolution is done at the bank level
    • If a bank is busy with an operation, a new operation can be issued to a different bank in parallel.
    • If a bank is busy with an operation, a new operation issued to the same bank will block until the operation completes.

The flash physical controller does NOT emulate the following properties

  • Flash lifetime
    • Typically flash memory has an upward limit of 100K+ program / erase cycles.
  • Flash line program disturb
    • Typically flash memory has limits on the number of program accesses to a single memory line (2 ~ 16) before erase is required,
  • Flash power loss corruption
    • Typically flash memory has strict requirements how power loss should be handled to prevent flash failure.
  • Dedicated flash power supplies

Depending on need, it may be necessary to add controller logic to perform the following functions

  • Flash BIST
    • Technology dependent mechanism to perform flash self test during manufacuring.
  • Flash custom controls
    • There may be additional tuning controls for a specific flash technology.
  • Power loss handling
    • Specific power loss handling if power is lost during an erase or program operation.
  • Additional security lockdown
    • As the physical controller represents the final connecting logic to the actual flash memory, additional security considerations may be required to ensure backdoor access paths do not exist.

Theory of Operation

Block Diagram

Flash Protocol Controller

The Flash Protocol Controller sits between the host software interface and the physical flash. Its primary function is to translate software requests into a high level protocol for the actual flash block. Importantly, the flash protocol controller shall not be responsible for the detailed timing and waveform control of the flash. Instead, it shall maintain FIFOs / interrupts for the software to process data.

Flash Physical Controller

The Flash Physical Controller is the wrapper module that contains the actual flash memory instantiation. It is responsible for converting high level protocol commands (such as read, program, erase) into low level signaling and timing specific to a particular flash IP. It is also responsible for any BIST, redundancy handling, remapping features or custom configurations required for the flash memory.

The diagram below summarizes the high level breakdown.

Flash High Level Abstraction

Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module FLASH_CTRL has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: none

Bus Device Interface: tlul

Bus Host Interface: none

Peripheral Pins for Chip IO: none

Interrupts:

Interrupt NameDescription
prog_emptyProgram FIFO empty
prog_lvlProgram FIFO drained to level
rd_fullRead FIFO full
rd_lvlRead FIFO filled to level
op_doneOperation complete
op_errorOperation failed with error

Security Alerts: none

Signals

In addition to the interrupts and bus signals, the tables below lists the flash protocol controller I/Os.

Signal Direction Description
flash_i input Inputs from physical controller, connects to flash_ctrl_o of physical controller
flash_o output Outputs to physical controller, connects to flash_ctrl_i of physical controller

Each of flash_i and flash_o is a struct that packs together additional signals, as shown below

Signal Source Destination Description
req protocol controller physical controller Protocol controller initiated transaction
addr protocol controller physical controller Protocol controller initiated transaction address
rd protocol controller physical controller Protocol controller initiated read
prog protocol controller physical controller Protocol controller initiated program
pg_erase protocol controller physical controller Protocol controller initiated page erase
prog_data protocol controller physical controller Protocol controller initiated program data, 1 flash word wide
bk_erase protocol controller physical controller Protocol controller initiated bank erase
rd_done physical controller protocol controller Physical controller read done
prog_done physical controller protocol controller Physical controller program done
erase_done physical controller protocol controller Physical controller erase done
init_busy physical controller protocol controller Physical controller reset release initialization in progress
rd_data physical controller protocol controller Physical Controller read data, 1 flash word wide

The physical controller IOs are listed and described below.

Signal Direction Description
host_req_i input Host initiated direct read, should always be highest priority. Host is only able to perform direct reads
host_addr_i input Address of host initiated direct read
host_req_rdy_o output Host request ready, ‘1’ implies transaction has been accepted, but not necessarily finished
host_req_done_o output Host request completed
host_rdata_o output Host read data, 1 flash word wide
flash_ctrl_i input Inputs from protocol controller, connects to flash_o of protocol controller
flash_ctrl_o output Outputs to protocol controller, connects to flash_i of protcol controller

Design Detials

Flash Protocol Controller Description

The flash protocol controller uses a simple FIFO interface to communicate between the software and flash physical controller. There is a read fifo for read operations, and a program fifo for program operations. Note, this means flash can be read both through the controller and the main bus interface. This may prove useful if the controller wishes to allocate specific regions to HW FSMs only, but is not a necessary feature.

When software initiates a read transaction of a programmable number of flash words, the flash controller will fill up the read FIFO for software to consume. Likewise, when software initiates a program transaction, software will fill up the program FIFO for the controller to consume.

The controller is designed such that the overall number of words in a transaction can significantly exceed the FIFO depth. In the case of read, once the FIFO is full, the controller will cease writing more entries and wait for software to consume the contents (an interrupt will be triggered to the software to alert it to such an event). In the case of program, the controller will stop writing to flash once all existing data is consumed - it will likewise trigger an interrupt to software to prepare more data. See detailed steps in theory of operation. The following is a diagram of the controller construction as well as its over connectivity with the flash module.

Flash Protocol Controller

Host Read

Unlike controller initiated reads, host reads have separate rdy / done signals to ensure transactions can be properly pipelined. As host reads are usually tied to host execution upstream, additional latency can severely harm performance and is not desired. The expected waveform from the perspective of the physical controller is shown below.

The host_req_done_o is always single cycle pulsed and upstream logic is expected to always accept and correctly handle the return. The same cycle the return data is posted a new command / address can be accepted. While the example shows flash reads completing in back to back cycles, this is typically not the case.

Controller Read

Unlike host reads, controller reads are not as performance critical and do not have command / data pipeline requirements. Instead, the protocol controller will hold the read request and address lines until the done is seen. Once the done is seen, the controller then transitions to the next read operation. The expected waveform from the perspective of the physical controller is shown below.

Controller Program

Program behavior is similar to reads. The protocol controller will hold the request, address and data lines until the programming is complete. The expected waveform from the perspective of the physical controller is shown below.

Programmers Guide

Issuing a Controller Read

To issue a flash read, the programmer must

  • Specify the address of the first flash word to read
  • Specify the number of total flash words to read, beginning at the supplied address
  • Specify the operation to be ‘READ’ type
  • Set the ‘START’ bit for the operation to begin

The above fields can be set in the CONTROL and ADDR registers. See library code for implementation.

It is acceptable for total number of flash words to be significantly greater than the depth of the read FIFO. In this situation, the read FIFO will fill up (or hit programmable fill value), pause the flash read and trigger an interrupt to software. Once there is space inside the FIFO, the controller will resume reading until the appropriate number of words have been read. Once the total count has been reached, the flash controller will post OP_DONE in the OP_STATUS register.

Issuing a Controller Program

To program flash, the same procedure as read is followed. However, instead of setting the CONTROL register for read operation, a program operation is selected instead. Software will then fill the program FIFO and wait for the controller to consume this data. Similar to the read case, the controller will automatically stall when there is insufficient data in the FIFO. When all desired words have been programmed, the controller will post OP_DONE in the OP_STATUS register.

Register Table

The flash protocol controller maintains two separate access windows for the FIFO. It is implemented this way because the access window supports transaction back-pressure should the FIFO become full (in case of write) or empty (in case of read).

FLASH_CTRL.INTR_STATE @ + 0x0
Interrupt State Register
Reset default = 0x0, mask 0x3f
31302928272625242322212019181716
 
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  op_error op_done rd_lvl rd_full prog_lvl prog_empty
BitsTypeResetNameDescription
0rw1c0x0prog_emptyProgram FIFO empty
1rw1c0x0prog_lvlProgram FIFO drained to level
2rw1c0x0rd_fullRead FIFO full
3rw1c0x0rd_lvlRead FIFO filled to level
4rw1c0x0op_doneOperation complete
5rw1c0x0op_errorOperation failed with error


FLASH_CTRL.INTR_ENABLE @ + 0x4
Interrupt Enable Register
Reset default = 0x0, mask 0x3f
31302928272625242322212019181716
 
1514131211109876543210
  op_error op_done rd_lvl rd_full prog_lvl prog_empty
BitsTypeResetNameDescription
0rw0x0prog_emptyEnable interrupt when INTR_STATE.prog_empty is set
1rw0x0prog_lvlEnable interrupt when INTR_STATE.prog_lvl is set
2rw0x0rd_fullEnable interrupt when INTR_STATE.rd_full is set
3rw0x0rd_lvlEnable interrupt when INTR_STATE.rd_lvl is set
4rw0x0op_doneEnable interrupt when INTR_STATE.op_done is set
5rw0x0op_errorEnable interrupt when INTR_STATE.op_error is set


FLASH_CTRL.INTR_TEST @ + 0x8
Interrupt Test Register
Reset default = 0x0, mask 0x3f
31302928272625242322212019181716
 
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  op_error op_done rd_lvl rd_full prog_lvl prog_empty
BitsTypeResetNameDescription
0wo0x0prog_emptyWrite 1 to force INTR_STATE.prog_empty to 1
1wo0x0prog_lvlWrite 1 to force INTR_STATE.prog_lvl to 1
2wo0x0rd_fullWrite 1 to force INTR_STATE.rd_full to 1
3wo0x0rd_lvlWrite 1 to force INTR_STATE.rd_lvl to 1
4wo0x0op_doneWrite 1 to force INTR_STATE.op_done to 1
5wo0x0op_errorWrite 1 to force INTR_STATE.op_error to 1


FLASH_CTRL.CONTROL @ + 0xc
Control register
Reset default = 0x0, mask 0xfff00f1
31302928272625242322212019181716
  NUM
1514131211109876543210
  FIFO_RST ERASE_SEL OP   START
BitsTypeResetNameDescription
0rw0x0STARTStart flash transaction. This bit shall only be set after the other fields of the CONTROL register and ADDR have been programmed
3:1Reserved
5:4rw0x0OPFlash operation selection
0ReadFlash Read. Read desired number of flash words
1ProgFlash Program. Program desired number of flash words
2EraseFlash Erase Operation. See ERASE_SEL for details on erase operation
Other values are reserved.
6rw0x0ERASE_SELFlash operation selection
0Page EraseErase 1 page of flash
1Bank EraseErase 1 bank of flash
7rw0x0FIFO_RSTRST FIFOs
15:8Reserved
27:16rw0x0NUMNumber of flash words the flash operation should read or program.


FLASH_CTRL.ADDR @ + 0x10
Address for flash operation
Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
START...
1514131211109876543210
...START
BitsTypeResetNameDescription
31:0rw0x0STARTStart address of a flash transaction. Software should supply the full byte address. The flash controller will then truncate the address as needed. For read operations, the flash controller will truncate to the closest, lower word aligned address. For example, if 0x13 is supplied, the controller will perform a read at address 0x10. Program operations behave similarly, the controller does not have read modified write support. For page erases, the controller will truncate to the closest lower page aligned address. Similarly for bank erases, the controller will truncate to the closest lower bank aligned address.


FLASH_CTRL.REGION_CFG_REGWEN @ + 0x14
Memory region registers configuration enable.
Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  EN
BitsTypeResetNameDescription
0rw0c0x1ENRegion register write enable. Once set to 0, it can longer be configured to 1
0Region lockedRegion can no longer be configured until next reset
1Region enabledRegion can be configured


FLASH_CTRL.MP_REGION_CFG0 @ + 0x18
Memory protection configuration
Reset default = 0x0, mask 0x1ff1fff
Register enable = REGION_CFG_REGWEN
31302928272625242322212019181716
  SIZE0
1514131211109876543210
  BASE0 ERASE_EN0 PROG_EN0 RD_EN0 EN0
BitsTypeResetNameDescription
0rw0x0EN0Region enabled, following fields apply for FLASH_CTRL0
1rw0x0RD_EN0Region can be read for FLASH_CTRL0
2rw0x0PROG_EN0Region can be programmed for FLASH_CTRL0
3rw0x0ERASE_EN0Region can be erased for FLASH_CTRL0
12:4rw0x0BASE0Region base page. Note the granularity is page, not byte or word for FLASH_CTRL0
15:13Reserved
24:16rw0x0SIZE0Region size in number of pages for FLASH_CTRL0


FLASH_CTRL.MP_REGION_CFG1 @ + 0x1c
Memory protection configuration
Reset default = 0x0, mask 0x1ff1fff
Register enable = REGION_CFG_REGWEN
31302928272625242322212019181716
  SIZE1
1514131211109876543210
  BASE1 ERASE_EN1 PROG_EN1 RD_EN1 EN1
BitsTypeResetNameDescription
0rw0x0EN1Region enabled, following fields apply for FLASH_CTRL1
1rw0x0RD_EN1Region can be read for FLASH_CTRL1
2rw0x0PROG_EN1Region can be programmed for FLASH_CTRL1
3rw0x0ERASE_EN1Region can be erased for FLASH_CTRL1
12:4rw0x0BASE1Region base page. Note the granularity is page, not byte or word for FLASH_CTRL1
15:13Reserved
24:16rw0x0SIZE1Region size in number of pages for FLASH_CTRL1


FLASH_CTRL.MP_REGION_CFG2 @ + 0x20
Memory protection configuration
Reset default = 0x0, mask 0x1ff1fff
Register enable = REGION_CFG_REGWEN
31302928272625242322212019181716
  SIZE2
1514131211109876543210
  BASE2 ERASE_EN2 PROG_EN2 RD_EN2 EN2
BitsTypeResetNameDescription
0rw0x0EN2Region enabled, following fields apply for FLASH_CTRL2
1rw0x0RD_EN2Region can be read for FLASH_CTRL2
2rw0x0PROG_EN2Region can be programmed for FLASH_CTRL2
3rw0x0ERASE_EN2Region can be erased for FLASH_CTRL2
12:4rw0x0BASE2Region base page. Note the granularity is page, not byte or word for FLASH_CTRL2
15:13Reserved
24:16rw0x0SIZE2Region size in number of pages for FLASH_CTRL2


FLASH_CTRL.MP_REGION_CFG3 @ + 0x24
Memory protection configuration
Reset default = 0x0, mask 0x1ff1fff
Register enable = REGION_CFG_REGWEN
31302928272625242322212019181716
  SIZE3
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  BASE3 ERASE_EN3 PROG_EN3 RD_EN3 EN3
BitsTypeResetNameDescription
0rw0x0EN3Region enabled, following fields apply for FLASH_CTRL3
1rw0x0RD_EN3Region can be read for FLASH_CTRL3
2rw0x0PROG_EN3Region can be programmed for FLASH_CTRL3
3rw0x0ERASE_EN3Region can be erased for FLASH_CTRL3
12:4rw0x0BASE3Region base page. Note the granularity is page, not byte or word for FLASH_CTRL3
15:13Reserved
24:16rw0x0SIZE3Region size in number of pages for FLASH_CTRL3


FLASH_CTRL.MP_REGION_CFG4 @ + 0x28
Memory protection configuration
Reset default = 0x0, mask 0x1ff1fff
Register enable = REGION_CFG_REGWEN
31302928272625242322212019181716
  SIZE4
1514131211109876543210
  BASE4 ERASE_EN4 PROG_EN4 RD_EN4 EN4
BitsTypeResetNameDescription
0rw0x0EN4Region enabled, following fields apply for FLASH_CTRL4
1rw0x0RD_EN4Region can be read for FLASH_CTRL4
2rw0x0PROG_EN4Region can be programmed for FLASH_CTRL4
3rw0x0ERASE_EN4Region can be erased for FLASH_CTRL4
12:4rw0x0BASE4Region base page. Note the granularity is page, not byte or word for FLASH_CTRL4
15:13Reserved
24:16rw0x0SIZE4Region size in number of pages for FLASH_CTRL4


FLASH_CTRL.MP_REGION_CFG5 @ + 0x2c
Memory protection configuration
Reset default = 0x0, mask 0x1ff1fff
Register enable = REGION_CFG_REGWEN
31302928272625242322212019181716
  SIZE5
1514131211109876543210
  BASE5 ERASE_EN5 PROG_EN5 RD_EN5 EN5
BitsTypeResetNameDescription
0rw0x0EN5Region enabled, following fields apply for FLASH_CTRL5
1rw0x0RD_EN5Region can be read for FLASH_CTRL5
2rw0x0PROG_EN5Region can be programmed for FLASH_CTRL5
3rw0x0ERASE_EN5Region can be erased for FLASH_CTRL5
12:4rw0x0BASE5Region base page. Note the granularity is page, not byte or word for FLASH_CTRL5
15:13Reserved
24:16rw0x0SIZE5Region size in number of pages for FLASH_CTRL5


FLASH_CTRL.MP_REGION_CFG6 @ + 0x30
Memory protection configuration
Reset default = 0x0, mask 0x1ff1fff
Register enable = REGION_CFG_REGWEN
31302928272625242322212019181716
  SIZE6
1514131211109876543210
  BASE6 ERASE_EN6 PROG_EN6 RD_EN6 EN6
BitsTypeResetNameDescription
0rw0x0EN6Region enabled, following fields apply for FLASH_CTRL6
1rw0x0RD_EN6Region can be read for FLASH_CTRL6
2rw0x0PROG_EN6Region can be programmed for FLASH_CTRL6
3rw0x0ERASE_EN6Region can be erased for FLASH_CTRL6
12:4rw0x0BASE6Region base page. Note the granularity is page, not byte or word for FLASH_CTRL6
15:13Reserved
24:16rw0x0SIZE6Region size in number of pages for FLASH_CTRL6


FLASH_CTRL.MP_REGION_CFG7 @ + 0x34
Memory protection configuration
Reset default = 0x0, mask 0x1ff1fff
Register enable = REGION_CFG_REGWEN
31302928272625242322212019181716
  SIZE7
1514131211109876543210
  BASE7 ERASE_EN7 PROG_EN7 RD_EN7 EN7
BitsTypeResetNameDescription
0rw0x0EN7Region enabled, following fields apply for FLASH_CTRL7
1rw0x0RD_EN7Region can be read for FLASH_CTRL7
2rw0x0PROG_EN7Region can be programmed for FLASH_CTRL7
3rw0x0ERASE_EN7Region can be erased for FLASH_CTRL7
12:4rw0x0BASE7Region base page. Note the granularity is page, not byte or word for FLASH_CTRL7
15:13Reserved
24:16rw0x0SIZE7Region size in number of pages for FLASH_CTRL7


FLASH_CTRL.DEFAULT_REGION @ + 0x38
Default region permissions
Reset default = 0x0, mask 0x7
31302928272625242322212019181716
 
1514131211109876543210
  ERASE_EN PROG_EN RD_EN
BitsTypeResetNameDescription
0rw0x0RD_ENRegion can be read
1rw0x0PROG_ENRegion can be programmed
2rw0x0ERASE_ENRegion can be erased


FLASH_CTRL.BANK_CFG_REGWEN @ + 0x3c
Bank configuration registers configuration enable.
Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  BANK
BitsTypeResetNameDescription
0rw0c0x1BANKBank register write enable. Once set to 0, it can longer be configured to 1
0Bank lockedBank can no longer be configured until next reset
1Bank enabledBank can be configured


FLASH_CTRL.MP_BANK_CFG @ + 0x40
Memory protect bank configuration
Reset default = 0x0, mask 0x3
Register enable = BANK_CFG_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  ERASE_EN1 ERASE_EN0
BitsTypeResetNameDescription
0rw0x0ERASE_EN0Bank wide erase enable for FLASH_CTRL0
1:1for FLASH_CTRL1


FLASH_CTRL.OP_STATUS @ + 0x44
Flash Operation Status
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  err done
BitsTypeResetNameDescription
0rw0x0doneFlash operation done. Set by HW, cleared by SW
1rw0x0errFlash operation error. Set by HW, cleared by SW


FLASH_CTRL.STATUS @ + 0x48
Flash Controller Status
Reset default = 0xa, mask 0x3ff1f
31302928272625242322212019181716
  error_bank error_page...
1514131211109876543210
...error_page   init_wip prog_empty prog_full rd_empty rd_full
BitsTypeResetNameDescription
0ro0x0rd_fullFlash read fifo full, software must consume data
1ro0x1rd_emptyFlash read fifo empty
2ro0x0prog_fullFlash program fifo full
3ro0x1prog_emptyFlash program fifo empty, software must provide data
4ro0x0init_wipFlash controller undergoing init
7:5Reserved
16:8ro0x0error_pageFlash controller error page.
17ro0x0error_bankFlash controller error bank.


FLASH_CTRL.Scratch @ + 0x4c
Flash Controller Scratch
Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
data...
1514131211109876543210
...data
BitsTypeResetNameDescription
31:0rw0x0dataFlash ctrl scratch register


FLASH_CTRL.FIFO_LVL @ + 0x50
Programmable depth where fifos should generate interrupts
Reset default = 0xf0f, mask 0x1f1f
31302928272625242322212019181716
 
1514131211109876543210
  RD   PROG
BitsTypeResetNameDescription
4:0rw0xfPROGWhen the program fifo drains to this level, trigger an interrupt. Default value is set such that interrupt does not trigger at reset.
7:5Reserved
12:8rw0xfRDWhen the read fifo fills to this level, trigger an interrupt. Default value is set such that interrupt does not trigger at reset.


FLASH_CTRL.prog_fifo @ + 0x54
1 item wo window
Byte writes are not supported
310
+0x54 
+0x58 
 ...
+0x50 
+0x54 
Flash program fifo. The fifo is 16 entries of 4B flash words


FLASH_CTRL.rd_fifo @ + 0x58
1 item ro window
Byte writes are not supported
310
+0x58 
+0x5c 
 ...
+0x54 
+0x58 
Flash read fifo. The fifo is 16 entries of 4B flash words