Flash Controller HWIP Technical Specification

Overview

This document describes the flash hardware functionality. The flash hardware is broken down into 3 major components

  • Open source flash controllers
  • Closed source vendor flash wrapper
  • Closed source vendor flash module

A breakdown of the 3 can be seen below Flash High Level Boundaries

This open source flash controller is divided into two partitions.

  • Flash protocol controller
  • Flash physical controller

The remaining document focuses primarily on the function of these blocks.

This module conforms to the Comportable guideline for peripheral functionality. See that document for integration overview within the broader top level system.

Features

Flash Protocol Controller Features

The flash protocol controller interfaces with software and other hardware components in the system (such as life cycle and key manager). Regardless of the flash size underneath, the flash controller maintains the same data resolution as the bus and processor (default 4B). The flash physical controller (see section below) is then responsible for bridging that gap.

The protocol controller currently supports the following features:

  • Controller initiated read, program and erase of flash.
    • Erase can be either of a page, or an entire bank.
  • Support for differentiation between informational and data flash partitions.
  • Parameterized support for burst program, up to 64B
    • Longer programs are supported, however the protocol controller will directly back-pressure the bus.
  • Flash memory protection at page boundaries
  • Features to be added if required
    • Program verification
      • may not be required if flash memory supports alternative mechanisms of verification.
    • Erase verification
      • may not be required if flash memory supports alternative mechanisms of verification.
    • Flash redundant pages
      • Flash may contain additional pages used to remap broken pages for yield recovery.
      • The storage, loading and security of redundant pages may also be implemented in the physical controller or flash memory.

Features to be implemented

  • Enhanced memory protection
  • Life cycle feature support
  • Key manager feature support

Flash Physical Controller Features

The flash physical controller wraps the actual flash memory and translates both host and controller initiated requests into low level flash transactions.

The physical controller supports the following features

  • Multiple banks of flash memory
  • For each flash bank, parameterized support for number of flash pages (default to 256)
  • For each flash page, parameterized support for number of words and word size (default to 128 words of 8-bytes each)
  • Data and informational paritions within each bank of flash memory
  • Arbitration between host requests and controller requests at the bank level
    • Host requests are always favored, however the controller priority can escalate if it repeatedly loses arbitration
    • Since banks are arbitrated independently, where transactions may take different amounts of times to complete, the physical controller is also responsible for ensuring in-order response to both the controller and host.
  • Flash read stage
    • Each bank maintains a parameterizable number of read buffers in front of the flash memory
    • The read buffers behave as miniature read-only-caches to store flash data when flash words are greater than bus words.
  • Flash program stage
    • Flash data work packing when flash word size is an integer multiple of bus word size.

Features to be implemented

  • Flash scrambling
  • Flash ECC

Theory of Operation

Block Diagram

Flash Protocol Controller

The Flash Protocol Controller sits between the host software interface and the flash physical controller, which contains the physical flash. Its primary function is to translate software requests into a high level protocol for the actual flash block. Importantly, the flash protocol controller is not responsible for the detailed timing and waveform control of the flash. Instead, it maintains FIFOs / interrupts for the software to process data, as well as high level abstraction of region protection controls.

Flash Physical Controller

The Flash Physical Controller is the wrapper module that contains the actual vendor flash memory instantiation. It is responsible for arbitrating high level protocol commands (such as read, program, erase) as well as any additional security and reliability features. The contained vendor wrapper module is then responsible for converting high level commands into low level signaling and timing specific to a particular flash vendor. The vendor wrapper module is also responsible for any BIST, redundancy handling, remapping features or custom configurations required for the flash.

The diagram below summarizes the high level breakdown.

Flash High Level Abstraction

Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module FLASH_CTRL has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: none

Bus Device Interface: tlul

Bus Host Interface: none

Peripheral Pins for Chip IO: none

Interrupts:

Interrupt NameDescription
prog_emptyProgram FIFO empty
prog_lvlProgram FIFO drained to level
rd_fullRead FIFO full
rd_lvlRead FIFO filled to level
op_doneOperation complete
op_errorOperation failed with error

Security Alerts: none

Signals

In addition to the interrupts and bus signals, the tables below lists the flash protocol controller I/Os.

Signal Direction Description
flash_i input Inputs from physical controller, connects to flash_ctrl_o of physical controller
flash_o output Outputs to physical controller, connects to flash_ctrl_i of physical controller

Each of flash_i and flash_o is a struct that packs together additional signals, as shown below

Signal Source Destination Description
req protocol controller physical controller Protocol controller initiated transaction
addr protocol controller physical controller Protocol controller initiated transaction address
rd protocol controller physical controller Protocol controller initiated read
prog protocol controller physical controller Protocol controller initiated program
pg_erase protocol controller physical controller Protocol controller initiated page erase
prog_data protocol controller physical controller Protocol controller initiated program data, 1 flash word wide
bk_erase protocol controller physical controller Protocol controller initiated bank erase
rd_done physical controller protocol controller Physical controller read done
prog_done physical controller protocol controller Physical controller program done
erase_done physical controller protocol controller Physical controller erase done
init_busy physical controller protocol controller Physical controller reset release initialization in progress
rd_data physical controller protocol controller Physical Controller read data, 1 flash word wide

The physical controller IOs are listed and described below.

Signal Direction Description
host_req_i input Host initiated direct read, should always be highest priority. Host is only able to perform direct reads
host_addr_i input Address of host initiated direct read
host_req_rdy_o output Host request ready, ‘1’ implies transaction has been accepted, but not necessarily finished
host_req_done_o output Host request completed
host_rdata_o output Host read data, 1 flash word wide
flash_ctrl_i input Inputs from protocol controller, connects to flash_o of protocol controller
flash_ctrl_o output Outputs to protocol controller, connects to flash_i of protcol controller

Design Detials

Flash Protocol Controller Description

The flash protocol controller uses a simple FIFO interface to communicate between the software and flash physical controller. There is a read fifo for read operations, and a program fifo for program operations. Note, this means flash can be read both through the controller and the main bus interface. This may prove useful if the controller wishes to allocate specific regions to HW FSMs only, but is not a necessary feature.

When software initiates a read transaction of a programmable number of flash words, the flash controller will fill up the read FIFO for software to consume. Likewise, when software initiates a program transaction, software will fill up the program FIFO for the controller to consume.

The controller is designed such that the overall number of words in a transaction can significantly exceed the FIFO depth. In the case of read, once the FIFO is full, the controller will cease writing more entries and wait for software to consume the contents (an interrupt will be triggered to the software to alert it to such an event). In the case of program, the controller will stop writing to flash once all existing data is consumed - it will likewise trigger an interrupt to software to prepare more data. See detailed steps in theory of operation. The following is a diagram of the controller construction as well as its over connectivity with the flash module.

Flash Protocol Controller

Host Read

Unlike controller initiated reads, host reads have separate rdy / done signals to ensure transactions can be properly pipelined. As host reads are usually tied to host execution upstream, additional latency can severely harm performance and is not desired. The expected waveform from the perspective of the physical controller is shown below.

The host_req_done_o is always single cycle pulsed and upstream logic is expected to always accept and correctly handle the return. The same cycle the return data is posted a new command / address can be accepted. While the example shows flash reads completing in back to back cycles, this is typically not the case.

Controller Read

Unlike host reads, controller reads are not as performance critical and do not have command / data pipeline requirements. Instead, the protocol controller will hold the read request and address lines until the done is seen. Once the done is seen, the controller then transitions to the next read operation. The expected waveform from the perspective of the physical controller is shown below.

Controller Program

Program behavior is similar to reads. The protocol controller will hold the request, address and data lines until the programming is complete. The expected waveform from the perspective of the physical controller is shown below.

Programmers Guide

Issuing a Controller Read

To issue a flash read, the programmer must

  • Specify the address of the first flash word to read
  • Specify the number of total flash words to read, beginning at the supplied address
  • Specify the operation to be ‘READ’ type
  • Set the ‘START’ bit for the operation to begin

The above fields can be set in the CONTROL and ADDR registers. See library code for implementation.

It is acceptable for total number of flash words to be significantly greater than the depth of the read FIFO. In this situation, the read FIFO will fill up (or hit programmable fill value), pause the flash read and trigger an interrupt to software. Once there is space inside the FIFO, the controller will resume reading until the appropriate number of words have been read. Once the total count has been reached, the flash controller will post OP_DONE in the OP_STATUS register.

Issuing a Controller Program

To program flash, the same procedure as read is followed. However, instead of setting the CONTROL register for read operation, a program operation is selected instead. Software will then fill the program FIFO and wait for the controller to consume this data. Similar to the read case, the controller will automatically stall when there is insufficient data in the FIFO. When all desired words have been programmed, the controller will post OP_DONE in the OP_STATUS register.

Register Table

The flash protocol controller maintains two separate access windows for the FIFO. It is implemented this way because the access window supports transaction back-pressure should the FIFO become full (in case of write) or empty (in case of read).

FLASH_CTRL.INTR_STATE @ + 0x0
Interrupt State Register
Reset default = 0x0, mask 0x3f
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  op_error op_done rd_lvl rd_full prog_lvl prog_empty
BitsTypeResetNameDescription
0rw1c0x0prog_emptyProgram FIFO empty
1rw1c0x0prog_lvlProgram FIFO drained to level
2rw1c0x0rd_fullRead FIFO full
3rw1c0x0rd_lvlRead FIFO filled to level
4rw1c0x0op_doneOperation complete
5rw1c0x0op_errorOperation failed with error


FLASH_CTRL.INTR_ENABLE @ + 0x4
Interrupt Enable Register
Reset default = 0x0, mask 0x3f
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  op_error op_done rd_lvl rd_full prog_lvl prog_empty
BitsTypeResetNameDescription
0rw0x0prog_emptyEnable interrupt when INTR_STATE.prog_empty is set
1rw0x0prog_lvlEnable interrupt when INTR_STATE.prog_lvl is set
2rw0x0rd_fullEnable interrupt when INTR_STATE.rd_full is set
3rw0x0rd_lvlEnable interrupt when INTR_STATE.rd_lvl is set
4rw0x0op_doneEnable interrupt when INTR_STATE.op_done is set
5rw0x0op_errorEnable interrupt when INTR_STATE.op_error is set


FLASH_CTRL.INTR_TEST @ + 0x8
Interrupt Test Register
Reset default = 0x0, mask 0x3f
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  op_error op_done rd_lvl rd_full prog_lvl prog_empty
BitsTypeResetNameDescription
0wo0x0prog_emptyWrite 1 to force INTR_STATE.prog_empty to 1
1wo0x0prog_lvlWrite 1 to force INTR_STATE.prog_lvl to 1
2wo0x0rd_fullWrite 1 to force INTR_STATE.rd_full to 1
3wo0x0rd_lvlWrite 1 to force INTR_STATE.rd_lvl to 1
4wo0x0op_doneWrite 1 to force INTR_STATE.op_done to 1
5wo0x0op_errorWrite 1 to force INTR_STATE.op_error to 1


FLASH_CTRL.CTRL_REGWEN @ + 0xc
Controls the configurability of the CONTROL register. This register ensures the contents of CONTROL cannot be changed by software once a flash operation has begun. It unlocks whenever the existing flash operation completes, regardless of success or error.
Reset default = 0x1, mask 0x1
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  EN
BitsTypeResetNameDescription
0ro0x1ENConfiguration enable. This bit defaults to 1 and is set to 0 by hardware when flash operation is initiated. When the controller completes the flash operation, this bit is set back to 1 to allow software configuration of CONTROL


FLASH_CTRL.CONTROL @ + 0x10
Control register
Reset default = 0x0, mask 0xfff00f1
Register enable = CTRL_REGWEN
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  NUM
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  PARTITION_SEL ERASE_SEL OP   START
BitsTypeResetNameDescription
0rw0x0STARTStart flash transaction. This bit shall only be set after the other fields of the CONTROL register and ADDR have been programmed
3:1Reserved
5:4rw0x0OPFlash operation selection
0ReadFlash Read. Read desired number of flash words
1ProgFlash Program. Program desired number of flash words
2EraseFlash Erase Operation. See ERASE_SEL for details on erase operation
Other values are reserved.
6rw0x0ERASE_SELFlash operation selection
0Page EraseErase 1 page of flash
1Bank EraseErase 1 bank of flash
7rw0x0PARTITION_SELSelects either info or data partition for operation. When 0, select data partition - this is the portion of flash that is accessible both by the host and by the controller. When 1, select info partition - this is the portion of flash that is only accessible by the controller.
15:8Reserved
27:16rw0x0NUMNumber of flash words the flash operation should read or program.


FLASH_CTRL.ADDR @ + 0x14
Address for flash operation
Reset default = 0x0, mask 0xffffffff
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START...
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...START
BitsTypeResetNameDescription
31:0rw0x0STARTStart address of a flash transaction. Software should supply the full byte address. The flash controller will then truncate the address as needed. For read operations, the flash controller will truncate to the closest, lower word aligned address. For example, if 0x13 is supplied, the controller will perform a read at address 0x10. Program operations behave similarly, the controller does not have read modified write support. For page erases, the controller will truncate to the closest lower page aligned address. Similarly for bank erases, the controller will truncate to the closest lower bank aligned address.


FLASH_CTRL.SCRAMBLE_EN @ + 0x18
Scramble enable for flash
Reset default = 0x0, mask 0x1
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  VAL
BitsTypeResetNameDescription
0rw0x0VALTemporary enable bit for flash scramble. See #2630.


FLASH_CTRL.REGION_CFG_REGWEN @ + 0x1c
Memory region registers configuration enable.
Reset default = 0x1, mask 0x1
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  EN
BitsTypeResetNameDescription
0rw0c0x1ENRegion register write enable. Once set to 0, it can longer be configured to 1
0Region lockedRegion can no longer be configured until next reset
1Region enabledRegion can be configured


FLASH_CTRL.MP_REGION_CFG0 @ + 0x20
Memory protection configuration
Reset default = 0x0, mask 0x13ff1fff
Register enable = REGION_CFG_REGWEN
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  PARTITION0   SIZE0
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  BASE0 ERASE_EN0 PROG_EN0 RD_EN0 EN0
BitsTypeResetNameDescription
0rw0x0EN0Region enabled, following fields apply for FLASH_CTRL0
1rw0x0RD_EN0Region can be read for FLASH_CTRL0
2rw0x0PROG_EN0Region can be programmed for FLASH_CTRL0
3rw0x0ERASE_EN0Region can be erased for FLASH_CTRL0
12:4rw0x0BASE0Region base page. Note the granularity is page, not byte or word for FLASH_CTRL0
15:13Reserved
25:16rw0x0SIZE0Region size in number of pages for FLASH_CTRL0
27:26Reserved
28rw0x0PARTITION0Region partition select 0 selects data partition 1 selects info partition for FLASH_CTRL0


FLASH_CTRL.MP_REGION_CFG1 @ + 0x24
Memory protection configuration
Reset default = 0x0, mask 0x13ff1fff
Register enable = REGION_CFG_REGWEN
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  PARTITION1   SIZE1
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  BASE1 ERASE_EN1 PROG_EN1 RD_EN1 EN1
BitsTypeResetNameDescription
0rw0x0EN1Region enabled, following fields apply for FLASH_CTRL1
1rw0x0RD_EN1Region can be read for FLASH_CTRL1
2rw0x0PROG_EN1Region can be programmed for FLASH_CTRL1
3rw0x0ERASE_EN1Region can be erased for FLASH_CTRL1
12:4rw0x0BASE1Region base page. Note the granularity is page, not byte or word for FLASH_CTRL1
15:13Reserved
25:16rw0x0SIZE1Region size in number of pages for FLASH_CTRL1
27:26Reserved
28rw0x0PARTITION1Region partition select 0 selects data partition 1 selects info partition for FLASH_CTRL1


FLASH_CTRL.MP_REGION_CFG2 @ + 0x28
Memory protection configuration
Reset default = 0x0, mask 0x13ff1fff
Register enable = REGION_CFG_REGWEN
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  PARTITION2   SIZE2
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  BASE2 ERASE_EN2 PROG_EN2 RD_EN2 EN2
BitsTypeResetNameDescription
0rw0x0EN2Region enabled, following fields apply for FLASH_CTRL2
1rw0x0RD_EN2Region can be read for FLASH_CTRL2
2rw0x0PROG_EN2Region can be programmed for FLASH_CTRL2
3rw0x0ERASE_EN2Region can be erased for FLASH_CTRL2
12:4rw0x0BASE2Region base page. Note the granularity is page, not byte or word for FLASH_CTRL2
15:13Reserved
25:16rw0x0SIZE2Region size in number of pages for FLASH_CTRL2
27:26Reserved
28rw0x0PARTITION2Region partition select 0 selects data partition 1 selects info partition for FLASH_CTRL2


FLASH_CTRL.MP_REGION_CFG3 @ + 0x2c
Memory protection configuration
Reset default = 0x0, mask 0x13ff1fff
Register enable = REGION_CFG_REGWEN
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  PARTITION3   SIZE3
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  BASE3 ERASE_EN3 PROG_EN3 RD_EN3 EN3
BitsTypeResetNameDescription
0rw0x0EN3Region enabled, following fields apply for FLASH_CTRL3
1rw0x0RD_EN3Region can be read for FLASH_CTRL3
2rw0x0PROG_EN3Region can be programmed for FLASH_CTRL3
3rw0x0ERASE_EN3Region can be erased for FLASH_CTRL3
12:4rw0x0BASE3Region base page. Note the granularity is page, not byte or word for FLASH_CTRL3
15:13Reserved
25:16rw0x0SIZE3Region size in number of pages for FLASH_CTRL3
27:26Reserved
28rw0x0PARTITION3Region partition select 0 selects data partition 1 selects info partition for FLASH_CTRL3


FLASH_CTRL.MP_REGION_CFG4 @ + 0x30
Memory protection configuration
Reset default = 0x0, mask 0x13ff1fff
Register enable = REGION_CFG_REGWEN
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  PARTITION4   SIZE4
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  BASE4 ERASE_EN4 PROG_EN4 RD_EN4 EN4
BitsTypeResetNameDescription
0rw0x0EN4Region enabled, following fields apply for FLASH_CTRL4
1rw0x0RD_EN4Region can be read for FLASH_CTRL4
2rw0x0PROG_EN4Region can be programmed for FLASH_CTRL4
3rw0x0ERASE_EN4Region can be erased for FLASH_CTRL4
12:4rw0x0BASE4Region base page. Note the granularity is page, not byte or word for FLASH_CTRL4
15:13Reserved
25:16rw0x0SIZE4Region size in number of pages for FLASH_CTRL4
27:26Reserved
28rw0x0PARTITION4Region partition select 0 selects data partition 1 selects info partition for FLASH_CTRL4


FLASH_CTRL.MP_REGION_CFG5 @ + 0x34
Memory protection configuration
Reset default = 0x0, mask 0x13ff1fff
Register enable = REGION_CFG_REGWEN
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  PARTITION5   SIZE5
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  BASE5 ERASE_EN5 PROG_EN5 RD_EN5 EN5
BitsTypeResetNameDescription
0rw0x0EN5Region enabled, following fields apply for FLASH_CTRL5
1rw0x0RD_EN5Region can be read for FLASH_CTRL5
2rw0x0PROG_EN5Region can be programmed for FLASH_CTRL5
3rw0x0ERASE_EN5Region can be erased for FLASH_CTRL5
12:4rw0x0BASE5Region base page. Note the granularity is page, not byte or word for FLASH_CTRL5
15:13Reserved
25:16rw0x0SIZE5Region size in number of pages for FLASH_CTRL5
27:26Reserved
28rw0x0PARTITION5Region partition select 0 selects data partition 1 selects info partition for FLASH_CTRL5


FLASH_CTRL.MP_REGION_CFG6 @ + 0x38
Memory protection configuration
Reset default = 0x0, mask 0x13ff1fff
Register enable = REGION_CFG_REGWEN
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  PARTITION6   SIZE6
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  BASE6 ERASE_EN6 PROG_EN6 RD_EN6 EN6
BitsTypeResetNameDescription
0rw0x0EN6Region enabled, following fields apply for FLASH_CTRL6
1rw0x0RD_EN6Region can be read for FLASH_CTRL6
2rw0x0PROG_EN6Region can be programmed for FLASH_CTRL6
3rw0x0ERASE_EN6Region can be erased for FLASH_CTRL6
12:4rw0x0BASE6Region base page. Note the granularity is page, not byte or word for FLASH_CTRL6
15:13Reserved
25:16rw0x0SIZE6Region size in number of pages for FLASH_CTRL6
27:26Reserved
28rw0x0PARTITION6Region partition select 0 selects data partition 1 selects info partition for FLASH_CTRL6


FLASH_CTRL.MP_REGION_CFG7 @ + 0x3c
Memory protection configuration
Reset default = 0x0, mask 0x13ff1fff
Register enable = REGION_CFG_REGWEN
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  PARTITION7   SIZE7
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  BASE7 ERASE_EN7 PROG_EN7 RD_EN7 EN7
BitsTypeResetNameDescription
0rw0x0EN7Region enabled, following fields apply for FLASH_CTRL7
1rw0x0RD_EN7Region can be read for FLASH_CTRL7
2rw0x0PROG_EN7Region can be programmed for FLASH_CTRL7
3rw0x0ERASE_EN7Region can be erased for FLASH_CTRL7
12:4rw0x0BASE7Region base page. Note the granularity is page, not byte or word for FLASH_CTRL7
15:13Reserved
25:16rw0x0SIZE7Region size in number of pages for FLASH_CTRL7
27:26Reserved
28rw0x0PARTITION7Region partition select 0 selects data partition 1 selects info partition for FLASH_CTRL7


FLASH_CTRL.DEFAULT_REGION @ + 0x40
Default region permissions
Reset default = 0x0, mask 0x7
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  ERASE_EN PROG_EN RD_EN
BitsTypeResetNameDescription
0rw0x0RD_ENRegion can be read
1rw0x0PROG_ENRegion can be programmed
2rw0x0ERASE_ENRegion can be erased


FLASH_CTRL.BANK_CFG_REGWEN @ + 0x44
Bank configuration registers configuration enable.
Reset default = 0x1, mask 0x1
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  BANK
BitsTypeResetNameDescription
0rw0c0x1BANKBank register write enable. Once set to 0, it can longer be configured to 1
0Bank lockedBank can no longer be configured until next reset
1Bank enabledBank can be configured


FLASH_CTRL.MP_BANK_CFG @ + 0x48
Memory protect bank configuration
Reset default = 0x0, mask 0x3
Register enable = BANK_CFG_REGWEN
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  ERASE_EN1 ERASE_EN0
BitsTypeResetNameDescription
0rw0x0ERASE_EN0Bank wide erase enable for FLASH_CTRL0
1:1for FLASH_CTRL1


FLASH_CTRL.OP_STATUS @ + 0x4c
Flash Operation Status
Reset default = 0x0, mask 0x3
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  err done
BitsTypeResetNameDescription
0rw0x0doneFlash operation done. Set by HW, cleared by SW
1rw0x0errFlash operation error. Set by HW, cleared by SW


FLASH_CTRL.STATUS @ + 0x50
Flash Controller Status
Reset default = 0xa, mask 0x3ff1f
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  error_bank error_page...
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...error_page   init_wip prog_empty prog_full rd_empty rd_full
BitsTypeResetNameDescription
0ro0x0rd_fullFlash read FIFO full, software must consume data
1ro0x1rd_emptyFlash read FIFO empty
2ro0x0prog_fullFlash program FIFO full
3ro0x1prog_emptyFlash program FIFO empty, software must provide data
4ro0x0init_wipFlash controller undergoing init
7:5Reserved
16:8ro0x0error_pageFlash controller error page.
17ro0x0error_bankFlash controller error bank.


FLASH_CTRL.Scratch @ + 0x54
Flash Controller Scratch
Reset default = 0x0, mask 0xffffffff
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data...
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...data
BitsTypeResetNameDescription
31:0rw0x0dataFlash ctrl scratch register


FLASH_CTRL.FIFO_LVL @ + 0x58
Programmable depth where FIFOs should generate interrupts
Reset default = 0xf0f, mask 0x1f1f
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  RD   PROG
BitsTypeResetNameDescription
4:0rw0xfPROGWhen the program FIFO drains to this level, trigger an interrupt. Default value is set such that interrupt does not trigger at reset.
7:5Reserved
12:8rw0xfRDWhen the read FIFO fills to this level, trigger an interrupt. Default value is set such that interrupt does not trigger at reset.


FLASH_CTRL.FIFO_RST @ + 0x5c
Reset for flash controller FIFOs
Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
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  EN
BitsTypeResetNameDescription
0rw0x0ENActive high resets for both program and read FIFOs. This is especially useful after the controller encounters an error of some kind. This bit will hold the FIFO in reset as long as it is set.


FLASH_CTRL.prog_fifo @ + 0x60
1 item wo window
Byte writes are not supported
310
+0x60 
+0x64 
 ...
+0x5c 
+0x60 
Flash program FIFO. The FIFO is 16 entries of 4B flash words. This FIFO can only be programmed by software after a program operation has been initiated via the CONTROL register. This ensures accidental programming of the program FIFO cannot lock up the system.


FLASH_CTRL.rd_fifo @ + 0x64
1 item ro window
Byte writes are not supported
310
+0x64 
+0x68 
 ...
+0x60 
+0x64 
Flash read FIFO. The FIFO is 16 entries of 4B flash words