FLASH_CTRL Checklist

This checklist is for Hardware Stage transitions for the FLASH_CTRL peripheral. All checklist items refer to the content in the Checklist.

Design Checklist

D1

Type Item Resolution Note/Collaterals
Documentation SPEC_COMPLETE Done [FLASH_CTRL Spec][]
Documentation CSR_DEFINED Done
RTL CLKRST_CONNECTED Done
RTL IP_TOP Done
RTL IP_INSTANCED Done
RTL MEM_INSTANCED_80 Done Top level non-volatile memory
RTL FUNC_IMPLEMENTED Done
RTL ASSERT_KNOWN_ADDED Done
Code Quality LINT_SETUP Done
Review Reviewer(s) Done sjgitty, msfschaffner
Review Signoff date Done 2019-11-08

D2

Type Item Resolution Note/Collaterals
Documentation NEW_FEATURES N/A
Documentation BLOCK_DIAGRAM Done
Documentation DOC_INTERFACE Done
Documentation MISSING_FUNC N/A
Documentation FEATURE_FROZEN Done
RTL FEATURE_COMPLETE Done
RTL AREA_SANITY_CHECK In Progress
RTL PORT_FROZEN Done
RTL ARCHITECTURE_FROZEN Done
RTL REVIEW_TODO Done
RTL STYLE_X In Progress
Code Quality LINT_PASS Done
Code Quality CDC_SETUP N/A
Code Quality FPGA_TIMING Done
Code Quality CDC_SYNCMACRO Not Started
Review Reviewer(s) Not Started
Review Signoff date Not Started

D3

Type Item Resolution Note/Collaterals
Documentation NEW_FEATURES_D3 Not Started
RTL TODO_COMPLETE Not Started
Code Quality LINT_COMPLETE Not Started
Code Quality CDC_COMPLETE Not Started
Review REVIEW_RTL Not Started
Review REVIEW_DELETED_FF Not Started
Review REVIEW_SW_CSR Not Started
Review REVIEW_SW_FATAL_ERR Not Started
Review REVIEW_SW_CHANGE Not Started
Review REVIEW_SW_ERRATA Not Started
Review Reviewer(s) Not Started
Review Signoff date Not Started

Verification Checklist

V1

Type Item Resolution Note/Collaterals
Documentation DV_PLAN_DRAFT_COMPLETED Not Started
Documentation TESTPLAN_COMPLETED Not Started
Testbench TB_TOP_CREATED Not Started
Testbench PRELIMINARY_ASSERTION_CHECKS_ADDED Not Started
Testbench TB_ENV_CREATED Not Started
Testbench RAL_MODEL_GEN_AUTOMATED Not Started
Testbench TB_GEN_AUTOMATED Not Started
Tests SANITY_TEST_PASSING Not Started
Tests CSR_MEM_TEST_SUITE_PASSING Not Started
Tool Setup ALT_TOOL_SETUP Not Started
Regression SANITY_REGRESSION_SETUP Not Started
Regression NIGHTLY_REGRESSION_SETUP Not Started
Coverage COVERAGE_MODEL_ADDED Not Started
Integration PRE_VERIFIED_SUB_MODULES_V1 Not Started
Review DESIGN_SPEC_REVIEWED Not Started
Review DV_PLAN_TESTPLAN_REVIEWED Not Started
Review STD_TEST_CATEGORIES_PLANNED Not Started
Review V2_CHECKLIST_SCOPED Not Started
Review Reviewer(s) Not Started
Review Signoff date Not Started

V2

Type Item Resolution Note/Collaterals
Documentation DESIGN_DELTAS_CAPTURED_V2 Not Started
Documentation DV_PLAN_COMPLETED Not Started
Testbench ALL_INTERFACES_EXERCISED Not Started
Testbench ALL_ASSERTION_CHECKS_ADDED Not Started
Testbench TB_ENV_COMPLETED Not Started
Tests ALL_TESTS_PASSING Not Started
Tests FW_SIMULATED Not Started
Regression NIGHTLY_REGRESSION_V2 Not Started
Coverage CODE_COVERAGE_V2 Not Started
Coverage FUNCTIONAL_COVERAGE_V2 Not Started
Issues NO_HIGH_PRIORITY_ISSUES_PENDING Not Started
Issues ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED Not Started
Integration PRE_VERIFIED_SUB_MODULES_V2 Not Started
Review V3_CHECKLIST_SCOPED Not Started
Review Reviewer(s) Not Started
Review Signoff date Not Started

V3

Type Item Resolution Note/Collaterals
Documentation DESIGN_DELTAS_CAPTURED_V3 Not Started
Testbench ALL_TODOS_RESOLVED Not Started
Tests X_PROP_ANALYSIS_COMPLETED Not Started
Regression NIGHTLY_REGRESSION_AT_100 Not Started
Coverage CODE_COVERAGE_AT_100 Not Started
Coverage FUNCTIONAL_COVERAGE_AT_100 Not Started
Issues NO_ISSUES_PENDING Not Started
Code Quality NO_TOOL_WARNINGS_THROWN Not Started
Integration PRE_VERIFIED_SUB_MODULES_V3 Not Started
Review Reviewer(s) Not Started
Review Signoff date Not Started