FLASH_CTRL DV document


  • DV
    • Verify all flash_ctrl IP features by running dynamic simulations with a SV/UVM based testbench
    • Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
  • FPV
    • Verify TileLink device protocol compliance with an SVA based testbench

Current status

Design features

For detailed information on flash_ctrl design features, please see the flash_ctrl HWIP technical specification. The design-under-test (DUT) wraps the flash_ctrl IP, flash_phy and the TLUL SRAM adapter that converts the incoming TL accesses from the from host (CPU) interface into flash requests. These modules are instantiated and connected to each other and to the rest of the design at the top level. For the IP level DV, we replicate the instantiations and connections in flash_ctrl_wrapper module mainained in DV, located at hw/ip/flash_ctrl/dv/tb/flash_ctrl_wrapper.sv. In future, we will consider having the wrapper maintained in the RTL area instead.

Testbench architecture

The flash_ctrl UVM DV testbench has been constructed based on the CIP testbench architecture.

Block diagram

Block diagram

Top level testbench

Top level testbench is located at hw/ip/flash_ctrl/dv/tb/tb.sv. It instantiates the flash_ctrl_wrapper. In addition, the testbench instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db:

In future, as the design (and DV) matures, the following interfaces will be instantiated and hooked up to the DUT:

  • Secret key interface from the OTP
  • Interface to the key_mgr
  • Interface from the life cycle manager

Common DV utility components

The following utilities provide generic helper tasks and functions to perform activities that are common across the project:


flash_ctrl UVM environment instantiates a (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into flash_ctrl device. There is an additional instance of the tl_agent for the host interface to the flash_phy, to directly fetch the contents of the flash memory, bypassing the flash_ctrl.

The tl_agent monitor supplies partial TileLink request packets as well as completed TileLink response packets over the TLM analysis port for further processing within the flash_ctrl scoreboard.


The flash_ctrl RAL model is created with the ralgen FuseSoC generator script automatically when the simulation is at the build stage.

It can be created manually by invoking regtool:

Sequence cfg

An efficient way to develop test sequences is by providing some random varibles that are used to configure the DUT / drive stimulus. The random variables are constrained using weights and knobs that can be controlled. These weights and knobs take on a “default” value that will result in the widest exploration of the design state space, when the test sequence is randomized and run as-is. To steer the randomization towards a particular distribution or to achieve interesting combinations of the random variables, the test sequence can be extended to create a spacialized variant. In this extended sequence, nothing would need to be done, other than setting those weights and knobs appropriately. This helps increase the likelihood of hitting the design corners that would otherwise be difficult to achieve, while maximizing reuse.

This object aims to provide such run-time controls. An example of such a knob is num_en_mp_regions, which controls how many flash memory protection regions to configure, set to ‘all’ by default.

Env cfg

The flash_ctrl_env_cfg, environment configuration object provides access to the following elements:

  • Build-time controls to configure the UVM environment composition during the build_phase
  • Downstream agent configuration objects for ease of lookup from any environment component
    • This includes the tl_agent_cfg objects for both TL interfaces
  • All virtual interfaces that connect to the DUT listed above (retrieved from the uvm_config_db)
  • Sequence configuration object described above

All environment components contain a handle to an instance of this class (that was created in the test class via the parent dv_base_test). By housing all of the above, all pertinent information is more easily shared with all environment components.

Stimulus strategy

Test sequences

All test sequences reside in hw/ip/flash_ctrl/dv/env/seq_lib. The flash_ctrl_base_vseq virtual sequence is extended from cip_base_vseq and serves as a starting point. All test sequences are extended from flash_ctrl_base_vseq. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. Some of the most commonly used tasks / functions are as follows:

  • task 1:
  • task 2:

Functional coverage

To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:

  • cg1:
  • cg2:

Self-checking strategy


The flash_ctrl_scoreboard is primarily used for end to end checking. It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:

  • analysis port1:
  • analysis port2:


  • TLUL assertions: The tb/flash_ctrl_bind.sv binds the tlul_assert assertions to the IP to ensure TileLink interface protocol compliance.
  • Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
  • assert prop 1:
  • assert prop 2:

Global types & methods

All common types and methods defined at the package level can be found in flash_ctrl_env_pkg. Some of them in use are:

[list a few parameters, types & methods; no need to mention all]

Building and running tests

We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:

$ cd $REPO_TOP
$ ./util/dvsim/dvsim.py hw/ip/flash_ctrl/dv/flash_ctrl_sim_cfg.hjson -i flash_ctrl_smoke



Milestone Name Tests Description
V1 smoke flash_ctrl_smoke

Randomly read, program or erase (page or a bank) a randomized chunk of flash memory. Only the data partition is accessed. No extra features enabled. Flash memory is invalidated and the targeted chunk is initialized with random data for reads and all 1s for writes. Interrupts are not enabled, Completion is ascertained through polling. The success of each operation is verified via backdoor.

V1 csr_hw_reset flash_ctrl_csr_hw_reset

Verify the reset values as indicated in the RAL specification.

  • Write all CSRs with a random value.
  • Apply reset to the DUT as well as the RAL model.
  • Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_rw flash_ctrl_csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

  • Loop through each CSR to write it with a random value.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_bit_bash flash_ctrl_csr_bit_bash

Verify no aliasing within individual bits of a CSR.

  • Walk a 1 through each CSR by flipping 1 bit at a time.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • This verify that writing a specific bit within the CSR did not affect any of the other bits.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_aliasing flash_ctrl_csr_aliasing

Verify no aliasing within the CSR address space.

  • Loop through each CSR to write it with a random value
  • Shuffle and read ALL CSRs back.
  • All CSRs except for the one that was written in this iteration should read back the previous value.
  • The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_mem_rw_with_rand_resetflash_ctrl_csr_mem_rw_with_rand_reset

Verify random reset during CSR/memory access.

  • Run csr_rw sequence to randomly access CSRs
  • If memory exists, run mem_partial_access in parallel with csr_rw
  • Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
V1 mem_walk flash_ctrl_mem_walk

Verify accessibility of all memories in the design.

  • Run the standard UVM mem walk sequence on all memories in the RAL model.
  • It is mandatory to run this test from all available interfaces the memories are accessible from.
V1 mem_partial_access flash_ctrl_mem_partial_access

Verify partial-accessibility of all memories in the design.

  • Do partial reads and writes into the memories and verify the outcome for correctness.
  • Also test outstanding access on memories
V2 backpressure

Sanity + randomly pick between back-pressured reads / writes and fifo status-polled reads / writes via the controller.

V2 all_partitions flash_ctrl_rand_ops

Sanity + both, legal data and info partitions are accessed. In future, support for multiple info partitions may be added - those will be covered as well.

V2 host_read_check

Sanity + the success of each operation is verified by randomly choosing between backdoor and via the host interface.

V2 host_illegal_access

Do a bunch of illegal accesses via host interface to ensure that an error response is appropriately seen. This includes writes, out of bound reads, protocol violated reads and all other unsupported accesses.

V2 host_outstanding_access

Drive back-to-back access to ensure coverage on the maximum supported outstanding on this interface.

V2 intr_enabled

Sanity + enable all interrupts and verify correctness of assertion and de-assertion of each pin. Replace polling with waits on interrrupts.

V2 host_ctrl_arb

Continuously read data from host interface while randomly programming or reading from the flash controller. Ensure the expected bandwidths are seen on both interfaces. Also, initiate reads from the host to all banks back and forth to ensure the responses arrive in-order.

V2 host_read_collide

Read LSB bus word via host and program or read the MSB bus word at the same time. This will cause the internal flash word wide buffer to be updated. Then read the MSB bus word within the same flash data word - it should read back the updated data, proving that the internal buffer was cleared from the previous step.

V2 en_mp_regions

Protect randomized and legal ranges of data and info partitions and ensure that the corresponding read / program / erase enable bits are working. TBD - future support for sub-page protection may be added - that will be tracked as a part of this test as well.

V2 redundant_pages

TBD - support for adding redundant pages may be added in future for yield recovery. THis is a placeholder to verify that feature.

V2 lc_ctrl_if

TBD - verify the interface between flash controller and the life cycle controller.

V2 key_mgr_if

TBD - verify the seed output to the key manager.

V2 scramble

Enable scrambling, along with randomized scramble keys. Program a fresh chunk of memory and read back (both, via controller and host) to ensure data integrity. On program, verify via backdoor scrambling was done on the raw data correctly. When reading via host, read the same memory via host multiple times back-to-back and ensure the timing is correct (subsequent reads should be faster). When scrambling is not enabled, ensure that the raw data is written and read back.

V2 ecc

Randomly enable ECC for a randomly selected set of pages. Randomly corrupt a single bit in the memory that is about to be read and ensure that the ECC works - the corrupted bit should be fixed. Corrupt randomly either the data or the ECC bits. Randomly corrupt 2 bits in the same word and ensure that the read results in error. Ensure that pages with ECC not enabled reads back corrupted data without any errors.

V2 read_ecc_metadata

TBD - in futurem support for reading the metadata from the ECC bits may be supported - this is a placeholder to verify that feature.

V2 error

This test will attempt to generate flash error in all possible ways:

  1. Read / program / erase a protected chunk
  2. Set num words to 0 or out of bounds on read or program
  3. Inject double bit errors when ECC is enabled
  4. Program or read out-of-bounds info partition
  5. Erase whole bank with bank erase not enabled
  6. Randomly wiggle scramble enable in the middle of an op and ensure that the FSM does not get locked up
V2 flash_macro_timing

When verifying against the real flash macro (which will be in a closed source repo), check that the read / program / erase timing parameters are correct.

V2 stress_all flash_ctrl_stress_all

This enables all of the above features to fully stress all the moving parts in the design.

V2 flash_init

TBD - if supported - verify flash initialization routine upon reset.

V2 tlul_to_vendor

TBD - if supported - verify TLUL split to the vendor wrapper.

V2 alert_test flash_ctrl_alert_test

Verify common alert_test CSR that allows SW to mock-inject alert requests.

  • Enable a random set of alert requests by writing random value to alert_test CSR.
  • Check each alert_tx.alert_p pin to verify that only the requested alerts are triggered.
  • During alert_handshakes, write alert_test CSR again to verify that: If alert_test writes to current ongoing alert handshake, the alert_test request will be ignored. If alert_test writes to current idle alert handshake, a new alert_handshake should be triggered.
  • Wait for the alert handshakes to finish and verify alert_tx.alert_p pins all sets back to 0.
  • Repeat the above steps a bunch of times.
V2 intr_test flash_ctrl_intr_test

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

  • Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
  • Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s).
  • Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
  • Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
  • Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
  • Repeat the above steps a bunch of times.
V2 tl_d_oob_addr_access flash_ctrl_tl_errors

Access out of bounds address and verify correctness of response / behavior

V2 tl_d_illegal_access flash_ctrl_tl_errors

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the [TLUL spec]({{< relref "hw/ip/tlul/doc/_index.md#explicit-error-cases" >}})

  • TL-UL protocol error cases
    • invalid opcode
    • some mask bits not set when opcode is PutFullData
    • mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
    • mask and address misaligned, e.g. a_address = 0x01, a_mask = 'b0001
    • address and size aren't aligned, e.g. a_address = 0x01, a_size != 0
    • size is greater than 2
  • OpenTitan defined error cases
    • access unmapped address, expect d_error = 1 when devmode_i == 1
    • write a CSR with unaligned address, e.g. a_address[1:0] != 0
    • write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
    • write a memory with a_mask != '1 when it doesn't support partial accesses
    • read a WO (write-only) memory
    • write a RO (read-only) memory
V2 tl_d_outstanding_access flash_ctrl_csr_hw_reset

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

V2 tl_d_partial_access flash_ctrl_csr_hw_reset

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

V3 tl_intg_err flash_ctrl_tl_intg_err

Verify that the data integrity check violation generates an alert.

Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.

V3 stress_all_with_rand_resetflash_ctrl_stress_all_with_rand_reset

This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.


Name Description

Cover the following error cases on TL-UL bus:

  • TL-UL protocol error cases.
  • OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.


Cover the kinds of integrity errors with byte enabled write on memory.

Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.