FLASH_CTRL DV Plan
- Verify all
flash_ctrlIP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
- Verify all
- Verify TileLink device protocol compliance with an SVA based testbench
For detailed information on
flash_ctrl design features, please see the
flash_ctrl HWIP technical specification.
The design-under-test (DUT) wraps the
flash_phy and the TLUL SRAM adapter that converts the incoming TL accesses from the from host (CPU) interface into flash requests.
These modules are instantiated and connected to each other and to the rest of the design at the top level.
For the IP level DV, we replicate the instantiations and connections in
flash_ctrl_wrapper module mainained in DV, located at
In future, we will consider having the wrapper maintained in the RTL area instead.
flash_ctrl UVM DV testbench has been constructed based on the CIP testbench architecture.
Top level testbench
Top level testbench is located at
It instantiates the
In addition, the testbench instantiates the following interfaces, connects them to the DUT and sets their handle into
- Clock and reset interface
- TileLink host interface for the flash controller
- TileLink host interface for the eflash
- Interrupts (
- Memory backdoor interfaces
In future, as the design (and DV) matures, the following interfaces will be instantiated and hooked up to the DUT:
- Secret key interface from the OTP
- Interface to the
- Interface from the life cycle manager
Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
flash_ctrl UVM environment instantiates a (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into
There is an additional instance of the
tl_agent for the host interface to the
flash_phy, to directly fetch the contents of the flash memory, bypassing the
tl_agent monitor supplies partial TileLink request packets as well as completed TileLink response packets over the TLM analysis port for further processing within the
UVM RAL Model
flash_ctrl RAL model is created with the
ralgen FuseSoC generator script automatically when the simulation is at the build stage.
It can be created manually by invoking
An efficient way to develop test sequences is by providing some random varibles that are used to configure the DUT / drive stimulus. The random variables are constrained using weights and knobs that can be controlled. These weights and knobs take on a “default” value that will result in the widest exploration of the design state space, when the test sequence is randomized and run as-is. To steer the randomization towards a particular distribution or to achieve interesting combinations of the random variables, the test sequence can be extended to create a spacialized variant. In this extended sequence, nothing would need to be done, other than setting those weights and knobs appropriately. This helps increase the likelihood of hitting the design corners that would otherwise be difficult to achieve, while maximizing reuse.
This object aims to provide such run-time controls.
An example of such a knob is
num_en_mp_regions, which controls how many flash memory protection regions to configure, set to ‘all’ by default.
flash_ctrl_env_cfg, environment configuration object provides access to the following elements:
- Build-time controls to configure the UVM environment composition during the
- Downstream agent configuration objects for ease of lookup from any environment component
- This includes the
tl_agent_cfgobjects for both TL interfaces
- This includes the
- All virtual interfaces that connect to the DUT listed above (retrieved from the
- Sequence configuration object described above
All environment components contain a handle to an instance of this class (that was created in the test class via the parent
By housing all of the above, all pertinent information is more easily shared with all environment components.
All test sequences reside in
flash_ctrl_base_vseq virtual sequence is extended from
cip_base_vseq and serves as a starting point.
All test sequences are extended from
It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:
- task 1:
- task 2:
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:
flash_ctrl_scoreboard is primarily used for end to end checking.
It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:
- analysis port1:
- analysis port2:
- TLUL assertions: The
tlul_assertassertions to the IP to ensure TileLink interface protocol compliance.
- Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
- assert prop 1:
- assert prop 2:
Global types & methods
All common types and methods defined at the package level can be found in
flash_ctrl_env_pkg. Some of them in use are:
[list a few parameters, types & methods; no need to mention all]
Building and running tests
We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a basic sanity test:
$ cd $REPO_TOP $ ./util/dvsim/dvsim.py hw/ip/flash_ctrl/dv/flash_ctrl_sim_cfg.hjson -i flash_ctrl_sanity
Randomly read, program or erase (page or a bank) a randomized chunk of flash memory. Only the data partition is accessed. No extra features enabled. Flash memory is invalidated and the targeted chunk is initialized with random data for reads and all 1s for writes. Interrupts are not enabled, Completion is ascertained through polling. The success of each operation is verified via backdoor.
Verify the reset values as indicated in the RAL specification.
Verify accessibility of CSRs as indicated in the RAL specification.
Verify no aliasing within individual bits of a CSR.
Verify no aliasing within the CSR address space.
Verify random reset during CSR/memory access.
Verify accessibility of all memories in the design.
Verify partial-accessibility of all memories in the design.
Sanity + randomly pick between back-pressured reads / writes and fifo status-polled reads / writes via the controller.
Sanity + both, legal data and info partitions are accessed. In future, support for multiple info partitions may be added - those will be covered as well.
Sanity + the success of each operation is verified by randomly choosing between backdoor and via the host interface.
Do a bunch of illegal accesses via host interface to ensure that an error response is appropriately seen. This includes writes, out of bound reads, protocol violated reads and all other unsupported accesses.
Drive back-to-back access to ensure coverage on the maximum supported outstanding on this interface.
Sanity + enable all interrupts and verify correctness of assertion and de-assertion of each pin. Replace polling with waits on interrrupts.
Continuously read data from host interface while randomly programming or reading from the flash controller. Ensure the expected bandwidths are seen on both interfaces. Also, initiate reads from the host to all banks back and forth to ensure the responses arrive in-order.
Read LSB bus word via host and program or read the MSB bus word at the same time. This will cause the internal flash word wide buffer to be updated. Then read the MSB bus word within the same flash data word - it should read back the updated data, proving that the internal buffer was cleared from the previous step.
Protect randomized and legal ranges of data and info partitions and ensure that the corresponding read / program / erase enable bits are working. TBD - future support for sub-page protection may be added - that will be tracked as a part of this test as well.
TBD - support for adding redundant pages may be added in future for yield recovery. THis is a placeholder to verify that feature.
TBD - verify the interface between flash controller and the life cycle controller.
TBD - verify the seed output to the key manager.
Enable scrambling, along with randomized scramble keys. Program a fresh chunk of memory and read back (both, via controller and host) to ensure data integrity. On program, verify via backdoor scrambling was done on the raw data correctly. When reading via host, read the same memory via host multiple times back-to-back and ensure the timing is correct (subsequent reads should be faster). When scrambling is not enabled, ensure that the raw data is written and read back.
Randomly enable ECC for a randomly selected set of pages. Randomly corrupt a single bit in the memory that is about to be read and ensure that the ECC works - the corrupted bit should be fixed. Corrupt randomly either the data or the ECC bits. Randomly corrupt 2 bits in the same word and ensure that the read results in error. Ensure that pages with ECC not enabled reads back corrupted data without any errors.
TBD - in futurem support for reading the metadata from the ECC bits may be supported - this is a placeholder to verify that feature.
This test will attempt to generate flash error in all possible ways:
When verifying against the real flash macro (which will be in a closed source repo), check that the read / program / erase timing parameters are correct.
This enables all of the above features to fully stress all the moving parts in the design.
TBD - if supported - verify flash initialization routine upon reset.
TBD - if supported - verify TLUL split to the vendor wrapper.
Verify common intr_test CSRs that allows SW to mock-inject interrupts.
Access out of bounds address and verify correctness of response / behavior
Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested
Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.
Access CSR with one or more bytes of data For read, expect to return all word value of the CSR For write, enabling bytes should cover all CSR valid fields
This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.