GPIO DV document
Goals
- DV
- Verify all GPIO IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
- FPV
- Verify TileLink device protocol compliance with an SVA based testbench
Current status
Design features
For detailed information on GPIO design features, please see the GPIO design specification.
Testbench architecture
GPIO testbench has been constructed based on the CIP testbench architecture.
Block diagram
Top level testbench
Top level testbench is located at hw/ip/gpio/dv/tb/tb.sv
. It instantiates the GPIO DUT module hw/ip/gpio/rtl/gpio.sv
.
In addition, it instantiates the following interfaces and sets their handle into uvm_config_db
:
- Clock and reset interface
- TileLink host interfac
- GPIO IOs (
pins_if
) - Interrupts (
pins_if
)
Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
Global types & methods
All common types and methods defined at the package level can be found in gpio_env_pkg
. Some of them in use are:
parameter uint NUM_GPIOS = 32;
parameter uint FILTER_CYCLES = 16;
TL_agent
GPIO testbench instantiates (handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into GPIO device.
UVM RAL Model
The GPIO RAL model is created with the ralgen
FuseSoC generator script automatically when the simulation is at the build stage.
It can be created manually by invoking regtool
:
Stimulus strategy
Test sequences
All test sequences reside in hw/ip/gpio/dv/env/seq_lib
.
The gpio_base_vseq
virtual sequence is extended from cip_base_vseq
and serves as a starting point.
All test sequences are extended from gpio_base_vseq
. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:
set_gpio_pulls
: This function overrides values ofpullup_en
andpulldown_en
members of randomizedgpio_env_cfg
drive_gpio_in
: This task writes all bits ofdirect_oe
register to 0’s first and then drives specified value on dut GPIO inputsundrive_gpio_in
: This task drives all dut GPIO inputs to ‘z’ values, so that dut GPIO outputs may be driven
Functional coverage
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:
gpio_pin_values_cov_obj
: Covers values and transitions on all GPIO IOsintr_state_cov_obj
: Coversintr_state
values and transitions for all GPIO interruptsintr_ctrl_en_cov_objs
: Covers values and transitions on all bits of following interrupt control enable registers:intr_ctrl_en_rising
intr_ctrl_en_falling
intr_ctrl_en_lvlhigh
intr_ctrl_en_lvllow
intr_event_type_cov_objs
: Covers all GPIO interrupts with following interrupt control registers and their cross coverage withintr_enable
andintr_state
:intr_ctrl_en_rising
intr_ctrl_en_falling
intr_ctrl_en_lvlhigh
intr_ctrl_en_lvllow
data_in_cov_obj
: Covers values and transitions on all bits of data_in registerout_oe_cov_objs
: Covers values and transitions on all bits ofdirect_out
,direct_oe
,masked_out_lower
,masked_oe_lower
,masked_out_upper
andmasked_oe_upper
registersout_oe_mask_data_cov_objs
: Coversmask
,data
fields and their cross coverage formasked_out_lower
/masked_oe_lower
andmasked_out_upper
/masked_oe_upper
registersdata_out_data_oe_cov_obj
: Covers data_out, data_oe and their cross coverage based on writes todirect_out
,direct_oe
,masked_out_lower
,masked_oe_lower
,masked_out_upper
andmasked_oe_upper
registers
Self-checking strategy
Scoreboard
The gpio_scoreboard
is primarily used for end to end checking.
It creates the following tlm analysis fifos to retrieve the data monitored by tlul interface agent monitors:
- tl_a_chan_fifo: tl address channel
- tl_d_chan_fifo: tl data channel
GPIO scoreboard monitors all valid GPIO CSR register accesses, activity on GPIO IOs, and interrupt pins. For any monitored write transaction, CSR values are updated in RAL. Based on monitored activity, GPIO scoreboard predicts updated values of required CSRs.
For any activity monitored on GPIO IOs or any write to *out* or *oe* registers, gpio_predict_and_compare
task is called which in turn predict any possible update for data_in
register and GPIO pins. A checker compares predicted value of GPIO pins against actual monitored value.
GPIO IO update or CSR write on most of the GPIO registers may result in GPIO interrupt event. For any such interrupt event, GPIO scoreboard predicts any possible update to intr_state
register. This also includes inter_test
reg functionality.
Any CSR read transaction would check actual read data against predicted value. Additionally, CSR read on intr_state would also check if monitored value of interrupt pins match the predicted value.
Assertions
- TLUL assertions: The
tb/gpio_bind.sv
binds thetlul_assert
assertions to the IP to ensure TileLink interface protocol compliance. - Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset
IntrGpioKnown
: Checks that GPIO interrupt pins do not have any unknownsCioGpioEnOKnown
: Checks that GPIO output does not have any unknownsCioGpioOKnown
: Checks that GPIO output enable does not have any unknowns
Building and running tests
We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:
$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/gpio/dv/gpio_sim_cfg.hjson -i gpio_smoke
Testplan
Testpoints
Milestone | Name | Tests | Description |
---|---|---|---|
V1 | smoke | gpio_smoke gpio_smoke_no_pullup_pulldown | GPIO smoke test that exercises gpio pins as inputs or outputs, and performs data integrity checks by triggering scoreboard checks by reading data_in register. This test repeats following steps are random no. of times:
|
V1 | csr_hw_reset | gpio_csr_hw_reset | Verify the reset values as indicated in the RAL specification.
|
V1 | csr_rw | gpio_csr_rw | Verify accessibility of CSRs as indicated in the RAL specification.
|
V1 | csr_bit_bash | gpio_csr_bit_bash | Verify no aliasing within individual bits of a CSR.
|
V1 | csr_aliasing | gpio_csr_aliasing | Verify no aliasing within the CSR address space.
|
V1 | csr_mem_rw_with_rand_reset | gpio_csr_mem_rw_with_rand_reset | Verify random reset during CSR/memory access.
|
V1 | regwen_csr_and_corresponding_lockable_csr | gpio_csr_rw gpio_csr_aliasing | Verify regwen CSR and its corresponding lockable CSRs.
Note:
This is only applicable if the block contains regwen and locakable CSRs. |
V2 | direct_and_masked_out | gpio_random_dout_din gpio_random_dout_din_no_pullup_pulldown | GPIO test that programs
|
V2 | out_in_regs_read_write | gpio_dout_din_regs_random_rw | GPIO test that exercises functionality of DATA_OUT and DATA_OE internal registers,
and
|
V2 | gpio_interrupt_programming | gpio_intr_rand_pgm | GPIO test which programs one or multiple interrupt registers to check GPIO interrupt
functionality
Every random iteration in this test would do either of following steps, and then read
|
V2 | random_interrupt_trigger | gpio_rand_intr_trigger | GPIO test that randomly generates and clears multiple GPIO interrupts for each
random programming of interrupt registers, and performs checks by reading
|
V2 | interrupt_and_noise_filter | gpio_intr_with_filter_rand_intr_event | GPIO test that exercise GPIO noise filter functionaliy along with random interrupt programming and randomly toggling each GPIO pin value, independently of other GPIO pins. Each random iteration performs following operations:
|
V2 | noise_filter_stress | gpio_filter_stress | GPIO test that stresses noise filter functionality by driving each GPIO pin such independently of other pins, and driving could be either synchronous to clock or asynchronous. Each iteration in test does following:
|
V2 | regs_long_reads_and_writes | gpio_random_long_reg_writes_reg_reads | GPIO test that performs back-to-back register writes and back-to-back register reads on randomly selected GPIO registers. Each iteration in this test performs one out of following operations:
|
V2 | full_random | gpio_full_random | GPIO full random test that performs any of following in each iteration:
|
V2 | stress_all | gpio_stress_all | Stress_all test is a random mix of all the test above except csr tests, gpio full random, intr_test and other gpio test that disabled scoreboard |
V2 | alert_test | gpio_alert_test | Verify common
|
V2 | intr_test | gpio_intr_test | Verify common intr_test CSRs that allows SW to mock-inject interrupts.
|
V2 | tl_d_oob_addr_access | gpio_tl_errors | Access out of bounds address and verify correctness of response / behavior |
V2 | tl_d_illegal_access | gpio_tl_errors | Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the [TLUL spec]({{< relref "hw/ip/tlul/doc/_index.md#explicit-error-cases" >}})
|
V2 | tl_d_outstanding_access | gpio_csr_hw_reset gpio_csr_rw gpio_csr_aliasing gpio_same_csr_outstanding | Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address. |
V2 | tl_d_partial_access | gpio_csr_hw_reset gpio_csr_rw gpio_csr_aliasing gpio_same_csr_outstanding | Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields. |
V2S | tl_intg_err | gpio_tl_intg_err gpio_sec_cm | Verify that the data integrity check violation generates an alert.
|
V2S | sec_cm_bus_integrity | Verify the countermeasure(s) BUS.INTEGRITY. | |
V3 | stress_all_with_rand_reset | gpio_stress_all_with_rand_reset | This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers. |
Covergroups
Name | Description |
---|---|
regwen_val_when_new_value_written_cg | Cover each lockable reg field with these 2 cases:
This is only applicable if the block contains regwen and locakable CSRs. |
tl_errors_cg | Cover the following error cases on TL-UL bus:
|
tl_intg_err_cg | Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check. Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied. |