GPIO DV Plan

Goals

  • DV
    • Verify all GPIO IP features by running dynamic simulations with a SV/UVM based testbench
    • Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
  • FPV
    • Verify TileLink device protocol compliance with an SVA based testbench

Current status

Design features

For detailed information on GPIO design features, please see the GPIO design specification.

Testbench architecture

GPIO testbench has been constructed based on the CIP testbench architecture.

Block diagram

Block diagram

Top level testbench

Top level testbench is located at hw/ip/gpio/dv/tb/tb.sv. It instantiates the GPIO DUT module hw/ip/gpio/rtl/gpio.sv. In addition, it instantiates the following interfaces and sets their handle into uvm_config_db:

Common DV utility components

The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

Global types & methods

All common types and methods defined at the package level can be found in gpio_env_pkg. Some of them in use are:

parameter uint NUM_GPIOS = 32;
parameter uint FILTER_CYCLES = 16;

TL_agent

GPIO testbench instantiates (handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into GPIO device.

UVM RAL Model

The GPIO RAL model is created with the ralgen FuseSoC generator script automatically when the simulation is at the build stage.

It can be created manually (separately) by running make in the the hw/ area.

Stimulus strategy

Test sequences

All test sequences reside in hw/ip/gpio/dv/env/seq_lib. The gpio_base_vseq virtual sequence is extended from cip_base_vseq and serves as a starting point. All test sequences are extended from gpio_base_vseq. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. Some of the most commonly used tasks / functions are as follows:

  • set_gpio_pulls: This function overrides values of pullup_en and pulldown_en members of randomized gpio_env_cfg
  • drive_gpio_in: This task writes all bits of direct_oe register to 0's first and then drives specified value on dut GPIO inputs
  • undrive_gpio_in: This task drives all dut GPIO inputs to ‘z’ values, so that dut GPIO outputs may be driven

Functional coverage

To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:

  • gpio_pin_values_cov_obj: Covers values and transitions on all GPIO IOs
  • intr_state_cov_obj: Covers intr_state values and transitions for all GPIO interrupts
  • intr_ctrl_en_cov_objs: Covers values and transitions on all bits of following interrupt control enable registers:
    • intr_ctrl_en_rising
    • intr_ctrl_en_falling
    • intr_ctrl_en_lvlhigh
    • intr_ctrl_en_lvllow
  • intr_event_type_cov_objs: Covers all GPIO interrupts with following interrupt control registers and their cross coverage with intr_enable and intr_state:
    • intr_ctrl_en_rising
    • intr_ctrl_en_falling
    • intr_ctrl_en_lvlhigh
    • intr_ctrl_en_lvllow
  • data_in_cov_obj: Covers values and transitions on all bits of data_in register
  • out_oe_cov_objs: Covers values and transitions on all bits of direct_out, direct_oe, masked_out_lower, masked_oe_lower, masked_out_upper and masked_oe_upper registers
  • out_oe_mask_data_cov_objs: Covers mask, data fields and their cross coverage for masked_out_lower / masked_oe_lower and masked_out_upper / masked_oe_upper registers
  • data_out_data_oe_cov_obj: Covers data_out, data_oe and their cross coverage based on writes to direct_out, direct_oe, masked_out_lower, masked_oe_lower, masked_out_upper and masked_oe_upper registers

Self-checking strategy

Scoreboard

The gpio_scoreboard is primarily used for end to end checking. It creates the following tlm analysis fifos to retrieve the data monitored by tlul interface agent monitors:

  • tl_a_chan_fifo: tl address channel
  • tl_d_chan_fifo: tl data channel

GPIO scoreboard monitors all valid GPIO CSR register accesses, activity on GPIO IOs, and interrupt pins. For any monitored write transaction, CSR values are updated in RAL. Based on monitored activity, GPIO scoreboard predicts updated values of required CSRs.

For any activity monitored on GPIO IOs or any write to *out* or *oe* registers, gpio_predict_and_compare task is called which in turn predict any possible update for data_in register and GPIO pins. A checker compares predicted value of GPIO pins against actual monitored value.

GPIO IO update or CSR write on most of the GPIO registers may result in GPIO interrupt event. For any such interrupt event, GPIO scoreboard predicts any possible update to intr_state register. This also includes inter_test reg functionality.

Any CSR read transaction would check actual read data against predicted value. Additionally, CSR read on intr_state would also check if monitored value of interrupt pins match the predicted value.

Assertions

  • TLUL assertions: The tb/gpio_bind.sv binds the tlul_assert assertions to the IP to ensure TileLink interface protocol compliance.
  • Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset
  • IntrGpioKnown: Checks that GPIO interrupt pins do not have any unknowns
  • CioGpioEnOKnown: Checks that GPIO output does not have any unknowns
  • CioGpioOKnown: Checks that GPIO output enable does not have any unknowns

Building and running tests

We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here's how to run a basic sanity test:

$ cd hw/ip/gpio/dv
$ make TEST_NAME=gpio_sanity

Testplan

Milestone Name Description Tests
V1 sanity <p>Basic GPIO sanity test that exercises gpio pins as inputs or outputs, and performs data integrity checks by triggering scoreboard checks by reading data_in register. This test repeats following steps are random no. of times:</p> <ul> <li>Configures all gpio pins as inputs, drives random value on cio_gpio_i signal and reads data_in register after random delay</li> <li>Configures all gpio pins as outputs, programs direct_out and direct_oe registers to random values and reads data_in register after random delay</li> </ul> gpio_sanity<br> gpio_sanity_no_pullup_pulldown<br>
V1 csr_hw_reset <p>Verify the reset values as indicated in the RAL specification.</p> <ul> <li>Write all CSRs with a random value.</li> <li>Apply reset to the DUT as well as the RAL model.</li> <li>Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.</li> <li>It is mandatory to run this test for all available interfaces the CSRs are accessible from.</li> <li>Shuffle the list of CSRs first to remove the effect of ordering.</li> </ul> gpio_csr_hw_reset<br>
V1 csr_rw <p>Verify accessibility of CSRs as indicated in the RAL specification.</p> <ul> <li>Loop through each CSR to write it with a random value.</li> <li>Read the CSR back and check for correctness while adhering to its access policies.</li> <li>It is mandatory to run this test for all available interfaces the CSRs are accessible from.</li> <li>Shuffle the list of CSRs first to remove the effect of ordering.</li> </ul> gpio_csr_rw<br>
V1 csr_bit_bash <p>Verify no aliasing within individual bits of a CSR.</p> <ul> <li>Walk a 1 through each CSR by flipping 1 bit at a time.</li> <li>Read the CSR back and check for correctness while adhering to its access policies.</li> <li>This verify that writing a specific bit within the CSR did not affect any of the other bits.</li> <li>It is mandatory to run this test for all available interfaces the CSRs are accessible from.</li> <li>Shuffle the list of CSRs first to remove the effect of ordering.</li> </ul> gpio_csr_bit_bash<br>
V1 csr_aliasing <p>Verify no aliasing within the CSR address space.</p> <ul> <li>Loop through each CSR to write it with a random value</li> <li>Shuffle and read ALL CSRs back.</li> <li>All CSRs except for the one that was written in this iteration should read back the previous value.</li> <li>The CSR that was written in this iteration is checked for correctness while adhering to its access policies.</li> <li>It is mandatory to run this test for all available interfaces the CSRs are accessible from.</li> <li>Shuffle the list of CSRs first to remove the effect of ordering.</li> </ul> gpio_csr_aliasing<br>
V1 csr_mem_rw_with_rand_reset<p>Verify random reset during CSR/memory access.</p> <ul> <li>Run csr_rw sequence to randomly access CSRs</li> <li>If memory exists, run mem_partial_access in parallel with csr_rw</li> <li>Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value</li> <li>It is mandatory to run this test for all available interfaces the CSRs are accessible from.</li> </ul> gpio_csr_mem_rw_with_rand_reset<br>
V2 direct_and_masked_out <p>GPIO test that programs <code>DIRECT_OUT</code>, <code>DIRECT_OE</code>, <code>MASKED_OUT_LOWER</code>, <code>MASKED_OE_LOWER</code>, <code>MASKED_OUT_UPPER</code> and <code>MASKED_OE_UPPER</code> registers and checks their effect on GPIO pins as well as DATA_IN register value. Every random iteration in this test would either:</p> <ul> <li>Program one or more of <code>\*OUT\*</code> and <code>\*OE\*</code> registers, or</li> <li>Drive new random value on GPIO pins</li> </ul> gpio_random_dout_din<br> gpio_random_dout_din_no_pullup_pulldown<br>
V2 out_in_regs_read_write <p>GPIO test that exercises functionality of DATA_OUT and DATA_OE internal registers, and <code>DATA_IN</code> register by programming any of <code>\*OUT\</code> and <code>\*OE\*</code> registers, respectively. Every random iteration in this test would perform one out of following operations:</p> <ul> <li>Drive new random value on GPIO pins</li> <li>Write random value to any one of <code>\*OUT\*</code>, <code>\*OE\*</code> or <code>DATA_IN</code> registers</li> <li>Read any one of <code>\*OUT\*</code>, <code>\*OE\*</code> or <code>DATA_IN</code> registers</li> </ul> gpio_dout_din_regs_random_rw<br>
V2 gpio_interrupt_programming<p>GPIO test which programs one or multiple interrupt registers to check GPIO interrupt functionality Every random iteration in this test would do either of following steps, and then read <code>INTR_STATE</code> register value:</p> <ul> <li>Drive new random value on GPIO pins (and thereby generate random interrupt event)</li> <li>Write random value to one or more interrupt registers that include <code>INTR_ENABLE</code>, <code>INTR_CTRL_EN_FALLING</code>, <code>INTR_CTRL_EN_LVL_LOW</code>, <code>INTR_CTRL_EN_LVL_HIGH</code> and <code>INTR_STATE</code></li> </ul> gpio_intr_rand_pgm<br>
V2 random_interrupt_trigger <p>GPIO test that randomly generates and clears multiple GPIO interrupts for each random programming of interrupt registers, and performs checks by reading <code>DATA_IN</code> and <code>INTR_STATE</code> registers. Each random iteration of this test performs following operations:</p> <ol> <li>Programs one more interrupt registers to random values</li> <li>Following two operations are performed in parallel: <ul> <li>Drive random value on GPIO pins multiple times, every time at a random time intervals (random number of clock cycles)</li> <li>Randomize random time interval (random number of clock cycles) and read either <code>DATA_IN</code> or <code>INTR_STATE</code> register value at randomized time interval After every read, optionally perform random interrupt clearing operation by writing to <code>INTR_STATE</code> register</li> </ul> </li> </ol> gpio_rand_intr_trigger<br>
V2 interrupt_and_noise_filter<p>GPIO test that exercise GPIO noise filter functionaliy along with random interrupt programming and randomly toggling each GPIO pin value, independently of other GPIO pins. Each random iteration performs following operations:</p> <ol> <li>programs random values in one or more interrupt registers</li> <li>optionally, programs new random value in <code>CTRL_EN_INPUT_FILTER</code> register</li> <li>performs following operations in parallel: <ul> <li>drives each GPIO pin independently such that each pin has stable value for random number of clock cycles within the range <code>[1:FILTER_CYCLES]</code>, and also predicts updates in values of <code>DATA_IN</code> and <code>INTR_STATE</code> registers</li> <li>multiple registers reads, each for either <code>DATA_IN</code> or <code>INTR_STATE</code></li> </ul> </li> </ol> gpio_intr_with_filter_rand_intr_event<br>
V2 noise_filter_stress <p>GPIO test that stresses noise filter functionality by driving each GPIO pin such independently of other pins, and driving could be either synchronous to clock or asynchronous. Each iteration in test does following:</p> <ol> <li>Programs one or more interrupt registers with random values</li> <li>Programs noise filter register with random value</li> <li>Drives each GPIO pin with the mix of both synchronous and asynchronous driving, and each pin is driven independently of others</li> </ol> gpio_filter_stress<br>
V2 regs_long_reads_and_writes<p>GPIO test that performs back-to-back register writes and back-to-back register reads on randomly selected GPIO registers. Each iteration in this test performs one out of following operations:</p> <ul> <li>Drive new random value on GPIO pins</li> <li>Perform multiple random writes on randomly selected GPIO registers</li> <li>Perform multiple random reads on randomly selected GPIO registers</li> </ul> gpio_random_long_reg_writes_reg_reads<br>
V2 full_random <p>GPIO full random test that performs any of following in each iteration:</p> <ul> <li>Drive new random value on GPIO pins such that GPIO inputs and GPIO outputs shall not result in unknown value on any pin</li> <li>Write to one or more of <code>DIRECT_OUT</code>, <code>DIRECT_OE</code>, <code>MASKED_OUT_UPPER</code>, <code>MASKED_OE_UPPER</code>, <code>MASKED_OE_LOWER</code> and <code>MASKED_OE_LOWER</code> registers such that GPIO inputs and GPIO outputs shall not result in unknown value on any pin</li> <li>Write to one or more of GPIO interrupt registers that include <code>INTR_ENABLE</code>, <code>INTR_CTRL_EN_FALLING</code>, <code>INTR_CTRL_EN_RISING</code>, <code>INTR_CTRL_EN_LVL_HIGH</code>, <code>INTR_CTRL_EN_LVL_LOW</code> and <code>INTR_STATE</code></li> <li>Write to other GPIO registers <code>DATA_IN</code>, <code>INTR_TEST</code>, <code>CTRL_EN_INPUT_FILTER</code></li> <li>Read any one of the GPIO registers</li> <li>Apply hard reset</li> </ul> gpio_full_random<br>
V2 stress_all <p>Stress_all test is a random mix of all the test above except csr tests, gpio full random, intr_test and other gpio test that disabled scoreboard</p> gpio_stress_all<br>
V2 intr_test <p>Verify common intr_test CSRs that allows SW to mock-inject interrupts.</p> <ul> <li>Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).</li> <li>Randomly &quot;turn on&quot; interrupts by writing random value(s) to intr_test CSR(s).</li> <li>Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.</li> <li>Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.</li> <li>Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).</li> <li>Repeat the above steps a bunch of times.</li> </ul> gpio_intr_test<br>
V2 stress_all_with_rand_reset<p>This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.</p> gpio_stress_all_with_rand_reset<br>
V2 oob_addr_access <p>Access out of bounds address and verify correctness of response / behavior</p>gpio_tl_errors<br>
V2 illegal_access <p>Drive unsupported requests via TL interface and verify correctness of response / behavior</p> gpio_tl_errors<br>
V2 outstanding_access <p>Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.</p> gpio_csr_hw_reset<br> gpio_csr_rw<br> gpio_csr_aliasing<br> gpio_same_csr_outstanding<br>
V2 partial_access <p>Do partial accesses.</p> gpio_csr_hw_reset<br> gpio_csr_rw<br> gpio_csr_aliasing<br>