GPIO DV Plan
- Verify all GPIO IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
- Verify TileLink device protocol compliance with an SVA based testbench
For detailed information on GPIO design features, please see the GPIO design specification.
GPIO testbench has been constructed based on the CIP testbench architecture.
Top level testbench
Top level testbench is located at
hw/ip/gpio/dv/tb/tb.sv. It instantiates the GPIO DUT module
In addition, it instantiates the following interfaces and sets their handle into
Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
Global types & methods
All common types and methods defined at the package level can be found in
gpio_env_pkg. Some of them in use are:
parameter uint NUM_GPIOS = 32; parameter uint FILTER_CYCLES = 16;
GPIO testbench instantiates (handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into GPIO device.
UVM RAL Model
The GPIO RAL model is created with the
ralgen FuseSoC generator script automatically when the simulation is at the build stage.
It can be created manually (separately) by running
make in the the
All test sequences reside in
gpio_base_vseq virtual sequence is extended from
cip_base_vseq and serves as a starting point.
All test sequences are extended from
gpio_base_vseq. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:
set_gpio_pulls: This function overrides values of
pulldown_enmembers of randomized
drive_gpio_in: This task writes all bits of
direct_oeregister to 0's first and then drives specified value on dut GPIO inputs
undrive_gpio_in: This task drives all dut GPIO inputs to ‘z’ values, so that dut GPIO outputs may be driven
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:
gpio_pin_values_cov_obj: Covers values and transitions on all GPIO IOs
intr_statevalues and transitions for all GPIO interrupts
intr_ctrl_en_cov_objs: Covers values and transitions on all bits of following interrupt control enable registers:
intr_event_type_cov_objs: Covers all GPIO interrupts with following interrupt control registers and their cross coverage with
data_in_cov_obj: Covers values and transitions on all bits of data_in register
out_oe_cov_objs: Covers values and transitions on all bits of
datafields and their cross coverage for
data_out_data_oe_cov_obj: Covers data_out, data_oe and their cross coverage based on writes to
gpio_scoreboard is primarily used for end to end checking.
It creates the following tlm analysis fifos to retrieve the data monitored by tlul interface agent monitors:
- tl_a_chan_fifo: tl address channel
- tl_d_chan_fifo: tl data channel
GPIO scoreboard monitors all valid GPIO CSR register accesses, activity on GPIO IOs, and interrupt pins. For any monitored write transaction, CSR values are updated in RAL. Based on monitored activity, GPIO scoreboard predicts updated values of required CSRs.
For any activity monitored on GPIO IOs or any write to *out* or *oe* registers,
gpio_predict_and_compare task is called which in turn predict any possible update for
data_in register and GPIO pins. A checker compares predicted value of GPIO pins against actual monitored value.
GPIO IO update or CSR write on most of the GPIO registers may result in GPIO interrupt event. For any such interrupt event, GPIO scoreboard predicts any possible update to
intr_state register. This also includes
inter_test reg functionality.
Any CSR read transaction would check actual read data against predicted value. Additionally, CSR read on intr_state would also check if monitored value of interrupt pins match the predicted value.
- TLUL assertions: The
tlul_assertassertions to the IP to ensure TileLink interface protocol compliance.
- Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset
IntrGpioKnown: Checks that GPIO interrupt pins do not have any unknowns
CioGpioEnOKnown: Checks that GPIO output does not have any unknowns
CioGpioOKnown: Checks that GPIO output enable does not have any unknowns
Building and running tests
We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here's how to run a basic sanity test:
$ cd hw/ip/gpio/dv $ make TEST_NAME=gpio_sanity
Basic GPIO sanity test that exercises gpio pins as inputs or outputs, and performs data integrity checks by triggering scoreboard checks by reading data_in register. This test repeats following steps are random no. of times:
Verify the reset values as indicated in the RAL specification.
Verify accessibility of CSRs as indicated in the RAL specification.
Verify no aliasing within individual bits of a CSR.
Verify no aliasing within the CSR address space.
GPIO test that programs
GPIO test that exercises functionality of DATA_OUT and DATA_OE internal registers,
GPIO test which programs one or multiple interrupt registers to check GPIO interrupt
Every random iteration in this test would do either of following steps, and then read
GPIO test that randomly generates and clears multiple GPIO interrupts for each
random programming of interrupt registers, and performs checks by reading
GPIO test that exercise GPIO noise filter functionaliy along with random interrupt programming and randomly toggling each GPIO pin value, independently of other GPIO pins. Each random iteration performs following operations:
GPIO test that stresses noise filter functionality by driving each GPIO pin such independently of other pins, and driving could be either synchronous to clock or asynchronous. Each iteration in test does following:
GPIO test that performs back-to-back register writes and back-to-back register reads on randomly selected GPIO registers. Each iteration in this test performs one out of following operations:
GPIO full random test that performs any of following in each iteration:
Stress_all test is a random mix of all the test above except csr tests, gpio full random, intr_test and other gpio test that disabled scoreboard
Verify common intr_test CSRs that allows SW to mock-inject interrupts.
This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.
Access out of bounds address and verify correctness of response / behavior
Drive unsupported requests via TL interface and verify correctness of response / behavior
Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.
Do partial accesses.