HMAC DV Plan
- Verify all HMAC IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
- Verify TileLink device protocol compliance with an SVA based testbench
For detailed information on HMAC design features, please see the HMAC design specification.
HMAC testbench has been constructed based on the CIP testbench architecture.
Top level testbench
Top level testbench is located at
hw/ip/hmac/dv/tb/tb.sv. It instantiates the
HMAC DUT module
hw/ip/hmac/rtl/hmac.sv. In addition, it instantiates the following
interfaces and sets their handle into
Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
Global types & methods
All common types and methods defined at the package level can be found in
Some of them in use are:
parameter uint32 HMAC_MSG_FIFO_DEPTH = 16; parameter uint32 HMAC_MSG_FIFO_DEPTH_BYTES = HMAC_MSG_FIFO_DEPTH * 4; parameter uint32 HMAC_MSG_FIFO_SIZE = 2048;
HMAC instantiates (handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into HMAC device.
UVM RAL Model
The HMAC RAL model is created with the
ralgen FuseSoC generator script automatically when the simulation is at the build stage.
It can be created manually (separately) by running
make in the the
To check the correctness of the output for SHA256 and HMAC, the testbench uses the C reference model. Messages and keys generated by constrained random test sequences are passed on to the reference model. Then the hmac scoreboard will compare the reference model's expected digest data with the DUT output.
All test sequences reside in
virtual sequence is extended from
cip_base_vseq and serves as a starting point.
All test sequences are extended from
hmac_base_vseq. It provides commonly used handles,
variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:
hmac_init: initialize hmac settings including configurations and interrupte enables
csr_rd_digest: read digest values from the CSR registers
wr_key: write key values into the CSR registers
wr_msg: write messages into the hmac_msg_fifo
compare_digest: compare the read digest result with the expected values
Standard test vectors
Besides contrained random test sequences, hmac test sequences also includes standard SHA256 and HMAC test vectors from NIST and IETF. The standard test vectors provide messages, keys (for HMAC only), and expected results. The expected results are used to cross verify both the DUT and DPI-C model outputs.
To ensure high quality constrained random stimulus, it is necessary to develop functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:
cfg_cg: Covers configuration registers in HMAC
intr_cg: Covers interrupt registers in HMAC
status_cg: Covers status registers in HMAC
msg_len_cg: Covers streamed-in message length in HMAC
hmac_scoreboard is primarily used for end to end checking. It creates the
following analysis ports to retrieve the data monitored by corresponding
- tl_a_chan_fifo: tl address channel
- tl_d_chan_fifo: tl data channel
Hmac scoreboard monitors all hmac valid CSR registers, hmac msg_fifo (addr: ‘h800 to ‘hfff), and interrupt pins.
For a write transaction, during the address channel, CSR values are updated in RAL. Msg_fifo values are updated to an internal msg queue. Once the data finishes streaming, hmac scoreboard will input the msg queue to the C model and calculate the expected output, then update the corresponding RAL registers.
For a read transaction, during the address channel, for status related CSRs (such as fifo_full, fifo_empty, etc), hmac will predict its value according to the cycle accurate model. During the data channel, hmac scoreboard will compare the read data with expected data in RAL.
Scoreboard cycle accurate checking model
Hmac scoreboard contains a cycle accurate checking to model the hmac
internal message fifo. It has two pointers(
hmac_wr_cnt) to simulate the
read and write of the hmac internal message fifo. These two pointers are updated at the
negedge of the clock cycle to avoid glitch. Read pointer is incremented one
clock cycle after the write pointer (except if HMAC is enabled, then read will
first wait 80 clock cycles for the key padding). Hmac fifo full is asserted when
hmac_wr_cnt - hmac_wr_cnt == 16. Hmac fifo depth is checked against the difference
- TLUL assertions: The
tlul_assertassertions to hmac to ensure TileLink interface protocol compliance.
- Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
Building and running tests
We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here's how to run a basic sanity test:
$ cd hw/ip/hmac/dv $ make TEST_NAME=hmac_sanity
|V1||sanity||<p>Basic sanity test performs a few round of HMAC or SHA256-ONLY transactions with the prodecures below:</p> <ul> <li>Set configuration register to randomly enable SHA256, hmac, endian_swap, and digest_swap</li> <li>Set interrupt enable register to randomly enable fifo_full, hmac_done, and err_code interupts</li> <li>Randomly read previous digest result</li> <li>Write key</li> <li>Trigger HMAC hash_start</li> <li>Write HMAC message fifo with message length between 0 and 64 bytes</li> <li>check status and interrupt</li> <li>Trigger HMAC hash_process</li> <li>After hmac_done interrupt, read and check digest data</li> </ul>||hmac_sanity<br>|
|V1||csr_hw_reset||<p>Verify the reset values as indicated in the RAL specification.</p> <ul> <li>Write all CSRs with a random value.</li> <li>Apply reset to the DUT as well as the RAL model.</li> <li>Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.</li> <li>It is mandatory to run this test for all available interfaces the CSRs are accessible from.</li> <li>Shuffle the list of CSRs first to remove the effect of ordering.</li> </ul>||hmac_csr_hw_reset<br>|
|V1||csr_rw||<p>Verify accessibility of CSRs as indicated in the RAL specification.</p> <ul> <li>Loop through each CSR to write it with a random value.</li> <li>Read the CSR back and check for correctness while adhering to its access policies.</li> <li>It is mandatory to run this test for all available interfaces the CSRs are accessible from.</li> <li>Shuffle the list of CSRs first to remove the effect of ordering.</li> </ul>||hmac_csr_rw<br>|
|V1||csr_bit_bash||<p>Verify no aliasing within individual bits of a CSR.</p> <ul> <li>Walk a 1 through each CSR by flipping 1 bit at a time.</li> <li>Read the CSR back and check for correctness while adhering to its access policies.</li> <li>This verify that writing a specific bit within the CSR did not affect any of the other bits.</li> <li>It is mandatory to run this test for all available interfaces the CSRs are accessible from.</li> <li>Shuffle the list of CSRs first to remove the effect of ordering.</li> </ul>||hmac_csr_bit_bash<br>|
|V1||csr_aliasing||<p>Verify no aliasing within the CSR address space.</p> <ul> <li>Loop through each CSR to write it with a random value</li> <li>Shuffle and read ALL CSRs back.</li> <li>All CSRs except for the one that was written in this iteration should read back the previous value.</li> <li>The CSR that was written in this iteration is checked for correctness while adhering to its access policies.</li> <li>It is mandatory to run this test for all available interfaces the CSRs are accessible from.</li> <li>Shuffle the list of CSRs first to remove the effect of ordering.</li> </ul>||hmac_csr_aliasing<br>|
|V1||csr_mem_rw_with_rand_reset||<p>Verify random reset during CSR/memory access.</p> <ul> <li>Run csr_rw sequence to randomly access CSRs</li> <li>If memory exists, run mem_partial_access in parallel with csr_rw</li> <li>Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value</li> <li>It is mandatory to run this test for all available interfaces the CSRs are accessible from.</li> </ul>||hmac_csr_mem_rw_with_rand_reset<br>|
|V2||long_msg||<p>Long_msg test is based on the sanity test. The message length is between 0 and 10,000 bytes.</p>||hmac_long_msg<br>|
|V2||back_pressure||<p>Back_pressure test is based on the long_msg test. The test disabled all the protocol delays to make sure to have high chance of hitting the FIFO_FULL status.</p>||hmac_back_pressure<br>|
|V2||test_vectors||<p>From <a href="https://csrc.nist.gov/Projects/Cryptographic-Algorithm-Validation-Program/Secure-Hashing#shavs">NIST</a> and <a href="https://tools.ietf.org/html/rfc4868">IETF</a> websites, this test intends to use HMAC and SHA test vectors to check if the reference model predicts correct data, and check if DUT returns correct data.</p>||hmac_test_sha_vectors<br> hmac_test_hmac_vectors<br>|
|V2||burst_wr||<p>Burst_wr test is based on the long_msg test. The test intends to test burst write a pre-defined size of message without any status or interrupt checking.</p>||hmac_burst_wr<br>|
|V2||datapath_stress||<p>Datapath_stress test is based on the long_msg test. It enabled HMAC and message length is set to N*64+1 in order to stress the datapath.</p>||hmac_datapath_stress<br>|
|V2||error||<p>This error case runs sequences that will cause interrupt bit hmac_err to set. This sequence includes:</p> <ul> <li>Write msg_fifo or set hash_start when sha is disabled</li> <li>Update secret key when hash is in process</li> <li>Set hash_start when hash is active</li> <li>Write msg before hash_start is set</li> </ul>||hmac_error<br>|
|V2||stress_all||<p>Stress_all test is a random mix of all the test above except csr tests.</p>||hmac_stress_all<br>|
|V2||intr_test||<p>Verify common intr_test CSRs that allows SW to mock-inject interrupts.</p> <ul> <li>Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).</li> <li>Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s).</li> <li>Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.</li> <li>Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.</li> <li>Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).</li> <li>Repeat the above steps a bunch of times.</li> </ul>||hmac_intr_test<br>|
|V2||stress_all_with_rand_reset||<p>This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.</p>||hmac_stress_all_with_rand_reset<br>|
|V2||oob_addr_access||<p>Access out of bounds address and verify correctness of response / behavior</p>||hmac_tl_errors<br>|
|V2||illegal_access||<p>Drive unsupported requests via TL interface and verify correctness of response / behavior</p>||hmac_tl_errors<br>|
|V2||outstanding_access||<p>Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.</p>||hmac_csr_hw_reset<br> hmac_csr_rw<br> hmac_csr_aliasing<br> hmac_same_csr_outstanding<br>|
|V2||partial_access||<p>Do partial accesses.</p>||hmac_csr_hw_reset<br> hmac_csr_rw<br> hmac_csr_aliasing<br>|
|V3||write_config_and_secret_key_during_msg_wr||<p>Change config registers and secret keys during msg write, make sure access is blocked.</p>||hmac_sanity<br>|