HMAC DV Plan

Goals

  • DV
    • Verify all HMAC IP features by running dynamic simulations with a SV/UVM based testbench
    • Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
  • FPV
    • Verify TileLink device protocol compliance with an SVA based testbench

Current status

Design features

For detailed information on HMAC design features, please see the HMAC design specification.

Testbench architecture

HMAC testbench has been constructed based on the CIP testbench architecture.

Block diagram

Block diagram

Top level testbench

Top level testbench is located at hw/ip/hmac/dv/tb/tb.sv. It instantiates the HMAC DUT module hw/ip/hmac/rtl/hmac.sv. In addition, it instantiates the following interfaces and sets their handle into uvm_config_db:

Common DV utility components

The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

Global types & methods

All common types and methods defined at the package level can be found in env/hmac_env_pkg. Some of them in use are:

parameter uint32 HMAC_MSG_FIFO_DEPTH       = 16;
parameter uint32 HMAC_MSG_FIFO_DEPTH_BYTES = HMAC_MSG_FIFO_DEPTH * 4;
parameter uint32 HMAC_MSG_FIFO_SIZE        = 2048;

TL_agent

HMAC instantiates (handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into HMAC device.

UVM RAL Model

The HMAC RAL model is created with the ralgen FuseSoC generator script automatically when the simulation is at the build stage.

It can be created manually by invoking regtool:

Reference models

To check the correctness of the output for SHA256 and HMAC, the testbench uses the C reference model. Messages and keys generated by constrained random test sequences are passed on to the reference model. Then the hmac scoreboard will compare the reference model’s expected digest data with the DUT output.

Stimulus strategy

Test sequences

All test sequences reside in hw/ip/hmac/dv/env/seq_lib. The hmac_base_vseq virtual sequence is extended from cip_base_vseq and serves as a starting point. All test sequences are extended from hmac_base_vseq. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. Some of the most commonly used tasks / functions are as follows:

  • hmac_init : initialize hmac settings including configurations and interrupte enables
  • csr_rd_digest : read digest values from the CSR registers
  • wr_key : write key values into the CSR registers
  • wr_msg : write messages into the hmac_msg_fifo
  • compare_digest: compare the read digest result with the expected values
Standard test vectors

Besides contrained random test sequences, hmac test sequences also includes standard SHA256 and HMAC test vectors from NIST and IETF. The standard test vectors provide messages, keys (for HMAC only), and expected results. The expected results are used to cross verify both the DUT and DPI-C model outputs.

Functional coverage

To ensure high quality constrained random stimulus, it is necessary to develop functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:

  • cfg_cg: Covers configuration registers in HMAC
  • intr_cg: Covers interrupt registers in HMAC
  • status_cg: Covers status registers in HMAC
  • msg_len_cg: Covers streamed-in message length in HMAC

Self-checking strategy

Scoreboard

The hmac_scoreboard is primarily used for end to end checking. It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:

  • tl_a_chan_fifo: tl address channel
  • tl_d_chan_fifo: tl data channel

Hmac scoreboard monitors all hmac valid CSR registers, hmac msg_fifo (addr: ‘h800 to ‘hfff), and interrupt pins.

For a write transaction, during the address channel, CSR values are updated in RAL. Msg_fifo values are updated to an internal msg queue. Once the data finishes streaming, hmac scoreboard will input the msg queue to the C model and calculate the expected output, then update the corresponding RAL registers.

For a read transaction, during the address channel, for status related CSRs (such as fifo_full, fifo_empty, etc), hmac will predict its value according to the cycle accurate model. During the data channel, hmac scoreboard will compare the read data with expected data in RAL.

Scoreboard cycle accurate checking model

Hmac scoreboard contains a cycle accurate checking to model the hmac internal message fifo. It has two pointers(hmac_wr_cnt and hmac_wr_cnt) to simulate the read and write of the hmac internal message fifo. These two pointers are updated at the negedge of the clock cycle to avoid glitch. Read pointer is incremented one clock cycle after the write pointer (except if HMAC is enabled, then read will first wait 80 clock cycles for the key padding). Hmac fifo full is asserted when hmac_wr_cnt - hmac_wr_cnt == 16. Hmac fifo depth is checked against the difference between hmac_wr_cnt and hmac_rd_cnt.

Assertions

  • TLUL assertions: The tb/hmac_bind.sv binds the tlul_assert assertions to hmac to ensure TileLink interface protocol compliance.
  • Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.

Building and running tests

We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a basic sanity test:

$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/hmac/dv/hmac_sim_cfg.hjson -i hmac_sanity

Testplan

Milestone Name Description Tests
V1 sanity

Basic sanity test performs a few round of HMAC or SHA256-ONLY transactions with the prodecures below:

  • Set configuration register to randomly enable SHA256, hmac, endian_swap, and digest_swap
  • Set interrupt enable register to randomly enable fifo_full, hmac_done, and err_code interupts
  • Randomly read previous digest result
  • Write key
  • Trigger HMAC hash_start
  • Write HMAC message fifo with message length between 0 and 64 bytes
  • check status and interrupt
  • Trigger HMAC hash_process
  • After hmac_done interrupt, read and check digest data
hmac_sanity
V1 csr_hw_reset

Verify the reset values as indicated in the RAL specification.

  • Write all CSRs with a random value.
  • Apply reset to the DUT as well as the RAL model.
  • Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
hmac_csr_hw_reset
V1 csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

  • Loop through each CSR to write it with a random value.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
hmac_csr_rw
V1 csr_bit_bash

Verify no aliasing within individual bits of a CSR.

  • Walk a 1 through each CSR by flipping 1 bit at a time.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • This verify that writing a specific bit within the CSR did not affect any of the other bits.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
hmac_csr_bit_bash
V1 csr_aliasing

Verify no aliasing within the CSR address space.

  • Loop through each CSR to write it with a random value
  • Shuffle and read ALL CSRs back.
  • All CSRs except for the one that was written in this iteration should read back the previous value.
  • The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
hmac_csr_aliasing
V1 csr_mem_rw_with_rand_reset

Verify random reset during CSR/memory access.

  • Run csr_rw sequence to randomly access CSRs
  • If memory exists, run mem_partial_access in parallel with csr_rw
  • Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
hmac_csr_mem_rw_with_rand_reset
V2 long_msg

Long_msg test is based on the sanity test. The message length is between 0 and 10,000 bytes.

hmac_long_msg
V2 back_pressure

Back_pressure test is based on the long_msg test. The test disabled all the protocol delays to make sure to have high chance of hitting the FIFO_FULL status.

hmac_back_pressure
V2 test_vectors

From NIST and IETF websites, this test intends to use HMAC and SHA test vectors to check if the reference model predicts correct data, and check if DUT returns correct data.

hmac_test_sha_vectors
hmac_test_hmac_vectors
V2 burst_wr

Burst_wr test is based on the long_msg test. The test intends to test burst write a pre-defined size of message without any status or interrupt checking.

hmac_burst_wr
V2 datapath_stress

Datapath_stress test is based on the long_msg test. It enabled HMAC and message length is set to N*64+1 in order to stress the datapath.

hmac_datapath_stress
V2 error

This error case runs sequences that will cause interrupt bit hmac_err to set. This sequence includes:

  • Write msg_fifo or set hash_start when sha is disabled
  • Update secret key when hash is in process
  • Set hash_start when hash is active
  • Write msg before hash_start is set
hmac_error
V2 stress_all

Stress_all test is a random mix of all the test above except csr tests.

hmac_stress_all
V2 intr_test

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

  • Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
  • Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s).
  • Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
  • Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
  • Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
  • Repeat the above steps a bunch of times.
hmac_intr_test
V2 stress_all_with_rand_reset

This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.

hmac_stress_all_with_rand_reset
V2 tl_d_oob_addr_access

Access out of bounds address and verify correctness of response / behavior

hmac_tl_errors
V2 tl_d_illegal_access

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested

  • TL-UL protocol error cases
    • Unsupported opcode. e.g a_opcode isn't Get, PutPartialData or PutFullData
    • Mask isn't all active if opcode = PutFullData
    • Mask isn't in enabled lanes, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
    • Mask doesn't align with address, e.g. a_address = 0x01, a_mask = 'b0001
    • Address and size aren't aligned, e.g. a_address = 0x01, a_size != 0
    • Size is over 2.
  • OpenTitan defined error cases
    • Access unmapped address, return d_error = 1 when devmode_i == 1
    • Write CSR with unaligned address, e.g. a_address[1:0] != 0
    • Write CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
    • Write a memory without enabling all lanes (a_mask = '1) if memory doesn't support byte enabled write
    • Read a WO (write-only) memory
hmac_tl_errors
V2 tl_d_outstanding_access

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

hmac_csr_hw_reset
hmac_csr_rw
hmac_csr_aliasing
hmac_same_csr_outstanding
V2 tl_d_partial_access

Access CSR with one or more bytes of data For read, expect to return all word value of the CSR For write, enabling bytes should cover all CSR valid fields

hmac_csr_hw_reset
hmac_csr_rw
hmac_csr_aliasing
hmac_same_csr_outstanding
V3 write_config_and_secret_key_during_msg_wr

Change config registers and secret keys during msg write, make sure access is blocked.

hmac_sanity