HMAC DV Plan
- Verify all HMAC IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
- Verify TileLink device protocol compliance with an SVA based testbench
For detailed information on HMAC design features, please see the HMAC design specification.
HMAC testbench has been constructed based on the CIP testbench architecture.
Top level testbench
Top level testbench is located at
hw/ip/hmac/dv/tb/tb.sv. It instantiates the
HMAC DUT module
hw/ip/hmac/rtl/hmac.sv. In addition, it instantiates the following
interfaces and sets their handle into
Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
Global types & methods
All common types and methods defined at the package level can be found in
Some of them in use are:
parameter uint32 HMAC_MSG_FIFO_DEPTH = 16; parameter uint32 HMAC_MSG_FIFO_DEPTH_BYTES = HMAC_MSG_FIFO_DEPTH * 4; parameter uint32 HMAC_MSG_FIFO_SIZE = 2048;
HMAC instantiates (handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into HMAC device.
UVM RAL Model
The HMAC RAL model is created with the
ralgen FuseSoC generator script automatically when the simulation is at the build stage.
It can be created manually by invoking
To check the correctness of the output for SHA256 and HMAC, the testbench uses the C reference model. Messages and keys generated by constrained random test sequences are passed on to the reference model. Then the hmac scoreboard will compare the reference model’s expected digest data with the DUT output.
All test sequences reside in
virtual sequence is extended from
cip_base_vseq and serves as a starting point.
All test sequences are extended from
hmac_base_vseq. It provides commonly used handles,
variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:
hmac_init: initialize hmac settings including configurations and interrupte enables
csr_rd_digest: read digest values from the CSR registers
wr_key: write key values into the CSR registers
wr_msg: write messages into the hmac_msg_fifo
compare_digest: compare the read digest result with the expected values
Standard test vectors
Besides contrained random test sequences, hmac test sequences also includes standard SHA256 and HMAC test vectors from NIST and IETF. The standard test vectors provide messages, keys (for HMAC only), and expected results. The expected results are used to cross verify both the DUT and DPI-C model outputs.
To ensure high quality constrained random stimulus, it is necessary to develop functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:
cfg_cg: Covers configuration registers in HMAC
intr_cg: Covers interrupt registers in HMAC
status_cg: Covers status registers in HMAC
msg_len_cg: Covers streamed-in message length in HMAC
hmac_scoreboard is primarily used for end to end checking. It creates the
following analysis ports to retrieve the data monitored by corresponding
- tl_a_chan_fifo: tl address channel
- tl_d_chan_fifo: tl data channel
Hmac scoreboard monitors all hmac valid CSR registers, hmac msg_fifo (addr: ‘h800 to ‘hfff), and interrupt pins.
For a write transaction, during the address channel, CSR values are updated in RAL. Msg_fifo values are updated to an internal msg queue. Once the data finishes streaming, hmac scoreboard will input the msg queue to the C model and calculate the expected output, then update the corresponding RAL registers.
For a read transaction, during the address channel, for status related CSRs (such as fifo_full, fifo_empty, etc), hmac will predict its value according to the cycle accurate model. During the data channel, hmac scoreboard will compare the read data with expected data in RAL.
Scoreboard cycle accurate checking model
Hmac scoreboard contains a cycle accurate checking to model the hmac
internal message fifo. It has two pointers(
hmac_wr_cnt) to simulate the
read and write of the hmac internal message fifo. These two pointers are updated at the
negedge of the clock cycle to avoid glitch. Read pointer is incremented one
clock cycle after the write pointer (except if HMAC is enabled, then read will
first wait 80 clock cycles for the key padding). Hmac fifo full is asserted when
hmac_wr_cnt - hmac_wr_cnt == 16. Hmac fifo depth is checked against the difference
- TLUL assertions: The
tlul_assertassertions to hmac to ensure TileLink interface protocol compliance.
- Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
Building and running tests
We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a basic sanity test:
$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/hmac/dv/hmac_sim_cfg.hjson -i hmac_sanity
Basic sanity test performs a few round of HMAC or SHA256-ONLY transactions with the prodecures below:
Verify the reset values as indicated in the RAL specification.
Verify accessibility of CSRs as indicated in the RAL specification.
Verify no aliasing within individual bits of a CSR.
Verify no aliasing within the CSR address space.
Verify random reset during CSR/memory access.
Long_msg test is based on the sanity test. The message length is between 0 and 10,000 bytes.
Back_pressure test is based on the long_msg test. The test disabled all the protocol delays to make sure to have high chance of hitting the FIFO_FULL status.
Burst_wr test is based on the long_msg test. The test intends to test burst write a pre-defined size of message without any status or interrupt checking.
Datapath_stress test is based on the long_msg test. It enabled HMAC and message length is set to N*64+1 in order to stress the datapath.
This error case runs sequences that will cause interrupt bit hmac_err to set. This sequence includes:
Stress_all test is a random mix of all the test above except csr tests.
Verify common intr_test CSRs that allows SW to mock-inject interrupts.
This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.
Access out of bounds address and verify correctness of response / behavior
Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested
Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.
Access CSR with one or more bytes of data For read, expect to return all word value of the CSR For write, enabling bytes should cover all CSR valid fields
Change config registers and secret keys during msg write, make sure access is blocked.