# Overview

This document specifies I2C hardware IP functionality. This module conforms to the Comportable guideline for peripheral functionality. See that document for integration overview within the broader top level system.

## Features

• Two-pin clock-data parallel bidirectional external interface
• The initial revision only supports I2C as a Host (“I2C Master”1).
• Support for standard (100 kbaud), fast (400 kbaud) and fast-plus (1 Mbaud) modes
• Bandwidth up to 1 Mbaud
• Support for all “Mandatory” features as specified for I2C Hosts (as listed in Table 2 of the I2C specification):
• Start Condition
• Stop Condition
• Acknowledge
• Support for the following optional capabilities:
• Clock stretching (may be required by some target devices)
• No support at this time for I2C Target (“I2C Slave”1) functionality
• No support at this time for any of the features related to multi-host control:
• No support for host-host clock synchronization
• No support for host bus arbitration.
• Byte-formatted register interface with two separate queues, one for holding read data, the other for holding bytes to be transmitted (addresses or write data)
• Direct SCL and SDA control in “Override mode” (for debugging)
• SCL and SDA ports mapped to I/O via the pinmux.
• Interrupts for FIFO overflow, target NACK, SCL/SDA signal interference, timeout, and unstable SDA signal levels.

1 lowRISC is avoiding the fraught terms master/slave and defaulting to host/target where applicable.

## Description

This IP block implements the I2C specification, though with some variation in nomenclature. For the purposes of this document, a “I2C Host” meets the specifications put forth for a “Master” device. Furthermore, a device which meets the specifications put forward for an I2C “Slave” device is here referred to as an “I2C Target” or “I2C Target Device”.

At a high-level, the I2C protocol is a clock-parallel serial protocol, with at least one host issuing transactions to a number of targets on the same bus. Though I2C optionally allows for multiple hosts on the same bus, we do not support this feature at this time.

Every transaction consists of a number of bytes transmitted, either from host-to-target or target-to-host. Each byte is typically followed by a single bit acknowledgement (ACK) from the receiving side. Typically each transaction consists of:

1. A START signal, issued by host.
2. An address, issued by host, encoded as 7 or 10 bits.
3. A R/W bit indicating whether the transaction is a read from the target device, or a write to the target device. The R/W bit is encoded along with the address.
4. An Acknowledge signal (ACK) sent by the target device.
5. Data bytes, where the number of bytes required is indicated by the host, in a manner which differs between reads and writes.
• For write transactions, the target device sends an ACK signal after every byte received. The host indicates the end of a transaction by sending a STOP or RESTART signal.
• For read transactions, the target device continues to send data as long as the host acknowledges the target-issued data by sending an ACK signal. Once the host has received all the required data it indicates that no more data is needed by explicitly de-asserting the ACK signal (this is called a NACK signal) just before sending a STOP or RESTART signal.
6. A STOP signal or a RESTART signal.

This protocol is generally quite flexible with respect to timing constraints, and slow enough to be managed by a software microcontroller, however such an implementation requires frequent activity on the part of the microcontroller. This IP presents a simple register interface and state-machine to manage the corresponding I/O pins directly using a byte-formatted programming model.

## Compatibility

This IP block should be compatible with any target device covered by the I2C specification, operating at speeds up to 1 Mbaud. In order to support any target device, this IP issues addresses in 7-bit encoding whenever possible, as not all target devices may be able to support 10-bit encoding. (It remains the obligation of system designers to ensure that devices which cannot support 10-bit encoding remain in a 7-bit address space.) This IP also supports clock-stretching, should that be required by target devices.

# Theory of Operations

## Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module i2c has the following hardware interfaces defined.

Primary Clock: clk_fixed

Other Clocks: none

Bus Device Interface: tlul

Bus Host Interface: none

Peripheral Pins for Chip IO:

Pin namedirectionDescription
sda_rxinputSerial input data bit
scl_rxinputSerial input clock bit
sda_txoutputSerial output data bit
scl_txoutputSerial output clock bit

Interrupts:

Interrupt NameDescription
fmt_watermarkraised when the FMT FIFO depth falls below the lowwater mark.
rx_watermarkraised if the RX FIFO is past the highwater mark.
fmt_overflowraised if the FMT FIFO has overflowed.
rx_overflowraised if the RX FIFO has overflowed.
nakraised if there is no ACK in response to an address or data write
scl_interferenceraised if the SCL line drops early (not supported without clock synchronization).
sda_interferenceraised if the SDA line goes low when master is trying to assert high
stretch_timeoutraised if target stretches the clock beyond the allowed timeout period
sda_unstableraised if the target does not assert a constant value of SDA during transmission.

## Design Details

### Virtual Open Drain

In devices which lack a true open drain buffer functionality, this IP implements a “virtual Open Drain” functionality. The SDA and SCL outputs are assumed to be connected to a tri-state buffer, with independent enable outputs for both signals.

Rather than toggling the buffer inputs, the buffer inputs are continuously asserted low, and instead the buffer enable signals are toggled. The SDA or SCL buffers are enabled for a logical “Low” output on the respective signal, and are disabled for logical “High” outputs. This arrangement allows the the output pins to float high if there is no conflict from external devices, or to be pulled low if there is a conflict (as is required for clock-stretching or–in future revisions– muli-host functionality).

This arrangement is necessary for FPGA builds.

### Override Mode for Direct Pin Access

The I2C hardware interface consists of two external pins, SCL and SDA, whose behavior is described in the I2C specification. These pins are typically controlled by an internal state machine. However, there is a simpler “override” mode, by which these pins can be directly manipulated by software. This override mode is useful for troubleshooting or error-recovery.

To enter override mode, the register field OVRD.TXOVRDEN is asserted by software. In this state the output drivers scl_tx_o and sda_tx_o are controlled directly by the register fields OVRD.SCLVAL and OVRD.SDAVAL. When OVRD.SCLVAL and OVRD.SDAVAL are set high, the virtual open drain configuration will leave the output resistively pulled high, and controllable by remote targets. In this state, with SCL or SDA asserted high, the register fields VAL.SCL_RX and VAL.SDA_RX can be used to receive inputs (including remote acknowledgments) from target devices.

### Byte-Formatted Programming Mode

The state machine-controlled mode allows for higher-speed operation with less frequent software interaction. In this mode, the I2C pins are controlled by the I2C state machine, which in turn is controlled by a sequence of formatting indicators. The formatting indicators indicate:

• The sequence of bytes which should be transmitted on the SDA and SCL pins.
• The periods between transmitted bytes when the state-machine should stop transmission and instead read back a fixed number of bytes.
• Which bytes should be preceded by a START symbol.
• Which bytes should be followed by a STOP symbol The format indicator consists of 13-bits. That is of one single Format Byte (entered into the format FIFO through FDATA.FBYTE), and five (5) 1-bit flags (entered into the format FIFO through registers FDATA.READ, FDATA.RCONT, FDATA.START, FDATA.STOP and FDATA.NAKOK)

The I2C reads each format indicator from the head of FMT_FIFO, and processes them in turn. If none of the flags are set for the format indicator, the I2C FSM simply transmits the Format Byte onto the SCL and SDA pins according to the specification, waits for acknowledgement, and then proceeds to the next format indicator. The format flags modulate the behavior as follows.

• READ (corresponds to FDATA.READ): Signifies the Format Byte (FDATA.FBYTE) should be treated as an unsigned number, R, and prompts the state machine to read R bytes from the target device. Bytes read from the bus, are inserted into the RX FIFO where they can be accessed by software. A value of 0 is treated as a read of 256B. To read a larger byte stream, multiple 256B reads can be chained together using the RCONT flag.
• RCONT (corresponds to FIFO inputs FDATA.RCONT, only used with READ):
• If RCONT is set, the Format Byte represents part of a longer sequence of reads, allowing for reads to be chained indefinitely.
• The RCONT flag indicates the the final byte returned with the current read should be responded to with an ACK, allowing the target to continue sending data. (Note that the first R-1 bytes read will still be acknowledged regardless of whether RCONT is asserted or not.)
• START (corresponds to FDATA.START, Ignored when used with READ): Issue a START condition before transmitting the Format Byte on the bus.
• This flag may also be used to issue a repeated start condition.
• STOP (corresponds to FDATA.STOP): Issue a STOP signal after processing this current entry in the FMT FIFO.
• Note that this flag is not compatible with (READ & RCONT), and will cause bus conflicts.
• NAKOK (corresponds to FDATA.NAKOK, Not compatible with READ): Typically every byte transmitted must also receive an ACK signal, and the IP will raise an exception if no ACK is received. However, there are some I2C commands which do not require an ACK. In those cases this flag should be asserted with FBYTE indicating no ACK is expected and no interrupt should be raised if the ACK is not received.

### Timing Control Registers

For standard mode, fast-mode and fast-mode plus, the timing requirements for each transaction are detailed in Table 10 of the I2C specification. In order to claim complete compatibility at each mode, the state machine timings need to be adapted to whether there are Standard-mode, Fast-mode and Fast-mode Plus targets on the bus. Furthermore, depending on the actual capacitance of the bus, even a bus with all Fast-mode Plus capable targets may have to operate at slower speeds than 1Mbaud. For example, the host may need to run at lower frequencies, as discussed in Section 5.2 of the specification, but the computation of the nominal frequency will depend on timing specifications in Table 10, in this case particularly, the limits on tLOW, tHIGH, tr, and tf. Assuming no clock stretching, for a given set of these four parameters the baud rate is then given to be: $$1/f_{SCL}=t_{LOW}+t_{HIGH}+t_{r}+t_{f}.$$

Thus in order to ensure compliance with the spec in any particular configuration, software will program the I2C host IP with explicit values for each of the following timing parameters, as defined in Figure 38 of the specification.

• tLOW: set in register TIMING0.TLOW.
• tHIGH: set in register TIMING0.THIGH.
• tr: set in register TIMING1.T_R. (Note: The rise time cannot be explicitly controlled by internal hardware, and will be a function of the capacitance of the bus. Thus this parameter is largely budgetary, meaning that it tells the state machine how much time to wait for an RC rise.)
• tf: set in register TIMING1.T_F. (Note: The fall time cannot be explicitly controlled by internal hardware, and is a function of the pin driver. Thus this parameter is also budgetary. Given that the actual fall time cannot be controlled to stay above the minimum values set in Table 10 of the specification, and so this in this regard this module currently is not strictly compliant to the I2C spec.)
• tSU,STA: set in register TIMING2.TSU_STA
• tHD,STA: set in register TIMING2.THD_STA
• tSU,DAT: set in register TIMING3.TSU_DAT. Taken to be synonymous with TSU,ACK
• tHD,DAT: set in register TIMING3.THD_DAT. Taken to be synonymous with THD,ACK. Moreover, since the pin driver fall time is likely to be less then one clock cycle, this parameter is also taken to be synonymous with the parameters TVD,DAT and TVD,ACK
• tSU,STO: set in register TIMING4.TSU_STO.
• tBUF: set in register TIMING4.T_BUF

The values programmed into the registers TIMING0 through TIMING4 are to be expressed in units of the bus clock period. Note in order to ensure compliance with the I2C spec, firmware must program these registers with values within the ranges laid out in Table 10 of the specification. These values can be directly computed using DIFs given the desired speed standard, the desired operating frequency, and the actual line capacitance. These timing parameters are then fed directly to the I2C state machine to control the bus timing.

A detailed description of the algorithm for determining these parameters–as well as a couple of concrete examples–are given in the Programmers Guide section of this document.

### Timeout Control

A malfunctioning (or otherwise very slow) target device can hold SCL low indefinitely, stalling the bus. For this reason TIMEOUT_CTRL provides a clock-stretching timeout mechanism to notify firmware of this sort of condition. If TIMEOUT_CTRL.EN is asserted, an interrupt will be asserted when the IP detects that another device (a target or, in possible future revisions, an alternate master) has been holding SCL low for more than TIMEOUT_CTRL.VAL clock ticks.

This feature is added as a utility, though it is not required by the I2C specification. However, in some applications it could be used in protocols which build upon I2C. For instance, SMBus applications using this IP could in principle use this to support SMBus timeouts. (Note: This is just an example application of this feature. Other features may also be required for complete SMBus functionality.)

### Interrupts

The I2C module has a few interrupts including general data flow interrupts and unexpected event interrupts.

If the RX FIFO exceeds the designated depth of entries, the interrupt rx_watermark is raised to inform firmware. Firmware can configure the watermark value via the register FIFO_CTRL.RXILVL.

Meanwhile it the FMT FIFO level falls below a designated depth of entries the fmt_watermark interrupt is raised. (Note that this behavior differs from similar interrupts in other modules, such as the UART IP module.) Firmware can configure the watermark value via the register FIFO_CTRL.FMTILVL.

If either FIFO receives an additional write request when its FIFO is full, the interrupt fmt_overflow or rx_overflow is asserted and the format indicator or character is dropped.

If the module transmits a byte, but receives no ACK signal, the nak interrupt is usually asserted. In cases where a byte is transmitted and no ACK is expected or required, that byte should be submitted with NAKOK flag also asserted.

When the I2C module is in transmit mode, the scl_interference or sda_interference interrupts will be asserted if the IP identifies that some other device (host or target) on the bus is forcing either signal low and interfering with the transmission. If should be noted that the scl_interference interrupt is not raised in the case when the target device is stretching the clock. (However, it may be raised if the target allows SCL to go high and then pulls SCL down before the end of the current clock cycle.)

A target device should never assert 0 on the SDA lines, and in the absence of multi-host support, the sda_interference interrupt is raised whenever the host IP detects that another device is pulling SDA low.

On the other hand, it is legal for the a target device to assert SCL low for clock stretching purposes. With clock stretching, the target can delay the start of the following SCL pulse by holding SCL low between clock pulses. However the target device must assert SCL low before the start of the SCL pulse. If SCL is pulled low during an SCL pulse which has already started, this interruption of the SCL pulse will be registered as an exception by the I2C core, which will then assert the scl_interference interrupt.

Though normal clock stretching does not count as SCL interference, if the module detects that a target device has held SCL low and stretched the any given SCL cycle for more than TIMEOUT_CTRL.VAL clock ticks this will cause the stretch timeout interrupt to be asserted. This interrupt is suppressed, however, if TIMEOUT_CTRL.EN is deasserted low.

Except for START and STOP symbols, the I2C specification requires that the SDA signal remains constant whenever SCL is high. The sda_unstable interrupt is asserted if, when receiving data or acknowledgement pulse, the value of the SDA signal does not remain constant over the duration of the SCL pulse.

### Implementation Details: Format Flag Parsing

To illustrate the behavior induced by various flags added to the formatting queue, the following figure shows a simplified version of the I2C_Host state machine. In this simplified view, many sequential states have been collapsed into four sub-sequences of states (shown in square brackets):

• Issue start
• Issue stop
• Transmit Byte

Within each of these sub-sequences, state transitions depend only on the SDA/SCL inputs or internal timers. Each sub-sequence has a terminal event–generically labeled “[completed]” which prompts the transition to another sequence or state.

However, all transitions which are dependent on formatting flags are shown explicitly in this figure.

# Programmers guide

## Initialization

After reset, the initialization of the I2C HWIP primarily consists of four steps:

1. Timing parameter initialization
2. FIFO reset and configuration
3. Interrupt configuration
4. Enable I2C Host functionality

### Timing Parameter Tuning Algorithm

Of the four initialization steps, the timing parameter initialization is the most involved. With so many timing parameters, it is essential to have dedicated device interface functions (DIF’s) to determine appropriate values for the 10 timing parameters.

The values of these parameters will depend primarily on three bus details:

• The speed mode of the slowest device on the bus: standard mode (100 kbaud), fast mode (400 kbaud) or fast-mode plus (1 Mbaud).
• The input clock period, tclk in ns.
• The expected signal rise time, tr, in ns.
• This is not a firmware-controlled parameter. Rather, it is a function of the capacitance and physical design of the bus. The specification provides detailed guidelines on how to manage capacitance in an I2C system:
• Section 5.2 of the I2C specification indicates that Fast-mode plus devices may operate at reduced clock speeds if the bus capacitance drives signal rise times (tr) outside the nominal 120ns limit. Excess capacitance can also be compensated for by reducing the size of the bus pullup resistor, so long as the total open-drain current does not exceed 20mA for fast-mode plus devices (as described in section 7.1 of the I2C specificaion). However the specification places a hard limit on rise times capping them at 1000ns.
• If there are standard- or fast-mode target devices on the bus, the specified open-drain current limit is reduced to 3mA (section 7.1), thus further restricting the minimum value of the pull-up resistor.
• In fast-mode bus designs, where the total line capacitance exceeds 200pF, the specification recommends replacing the pull-up resistor with an active current source, supplying 3mA or less (section 5.1). Regardless of the physical construction of the bus, the rise time (tr) is a system dependent, parameter that needs to be made known to firmware for I2C initialization.
• The expected fall time, tf, in ns.
• Like tr, this parameter is not firmware controlled rather it is a function of the SCL driver, which in a strictly compliant device is expected to manage the slew-rate for the falling edge of the SDA and SCL signals, through proper design of the SCL output buffer.
• See table 10 of the I2C specification for more details.
• (optional) The desired SCL cycle period, tSCL,user in ns.
• By default the device should operate at the maximum frequency for that mode. However, If the system developer wishes to operate at slower than the mode-specific maximum, a larger than minimum period could be allowed as an additional functional parameter when calculating the timing parameters.

Based on the inputs, the timing paramaters may be chosen using the following algorithm:

1. The physical timing parameters tHD,STA, tSU,STA, tHD.DAT, tSU,DAT, tBUF, and tSTO, tHIGH, and tLOW all have minimum allowed values which depend on the choice of speed mode (standard-mode, fast-mode or fast-mode plus). Using the speed mode input, look up the appropriate minimum value (in ns) for each parameter (i.e. tHD,STA,min, tSU,STA,min, etc)
2. For each of these eight parameters, obtain an integer minimum by dividing the physical minimum parameter by the clock frequency and rounding up to the next highest integer: $$\textrm{THIGH_MIN}=\lceil{t_{HIGH,min}/t_{clk}}\rceil$$ $$\textrm{TLOW_MIN}=\lceil{t_{LOW,min}/t_{clk}}\rceil$$ $$\textrm{THD_STA_MIN}= \lceil{t_{HD,STA,min}/t_{clk}}\rceil$$ $$\textrm{TSU_STA_MIN}= \lceil{t_{SU,STA,min}/t_{clk}}\rceil$$ $$\textrm{THD_DAT_MIN}= \lceil{t_{HD,DAT,min}/t_{clk}}\rceil$$ $$\textrm{TSU_DAT_MIN}= \lceil{t_{HD,DAT,min}/t_{clk}}\rceil$$ $$\textrm{T_BUF_MIN}= \lceil{t_{BUF,min}/t_{clk}}\rceil$$ $$\textrm{T_STO_MIN}= \lceil{t_{STO,min}/t_{clk}}\rceil$$

3. Input the integer timing parameters, THD_STA_MIN, TSU_STA_MIN, THD_DAT_MIN, TSU_DAT_MIN, T_BUF_MIN and T_STO_MIN into their corresponding registers (TIMING2.THD_STA, TIMING2.TSU_STA, TIMING3.THD_DAT, TIMING3.TSU_DAT, TIMING4.T_BUF, TIMING4.T_STO)

• This step allows the firmware to manage SDA signal delays to ensure that the SDA outputs are compliant with the specification.
• The registers TIMING0.THIGH and TIMING0.TLOW will be taken care of in a later step.
4. Take the given values for for tf and tr and convert them to integer counts as well: $$\textrm{T_R}= \lceil{t_{r}/t_{clk}}\rceil$$ $$\textrm{T_F}= \lceil{t_{f}/t_{clk}}\rceil$$

5. Store T_R and T_F in their corresponding registers: TIMING1.T_R and TIMING1.T_F.

6. Based on the input speed mode, look up the maximum permissable SCL frequency (fSCL,max)and calculate the minimum permissable SCL period: $$t_{SCL,min}= 1/f_{SCL,max}$$

7. As with each of the other physical parameters convert tSCL,min and, if provided, the tSCL,user to integers, MINPERIOD and USERPERIOD.. $$MINPERIOD = \lceil{t_{SCL,min}/t_{clk}}\rceil$$ $$USERPERIOD = \lceil{t_{SCL,user}/t_{clk}}\rceil$$

8. Let PERIOD=max(MINPERIOD, USERPERIOD).

9. Each SCL cycle will now be at least PERIOD clock cycles in duration, divided between four segments: T_R, THIGH, T_F, and TLOW.

• In other words: PERIOD=T_R+THIGH+T_F+TLOW.
• With T_R and T_F already established, the remaining integer parameters THIGH and TLOW are to be divided among the remaining clock cycles in PERIOD: $$\textrm{THIGH}+\textrm{TLOW} \ge\textrm{PERIOD}-\textrm{T_F}-\textrm{T_R}$$
• Since tHIGH and tLOW both have minimum allowable values, which depends on the mode, high values of tr or tf may force an increase in the total SCL period, slowing down the data transit rate.
• The balance between tHIGH and tLOW can be manipulated in a variety of different ways (depending on the desired SCL duty cycle).
• It is, for instance, perfectly acceptable to simply set TLOW to the minimum possible value: $$\textrm{TIMING0.TLOW}=\textrm{TLOW_MIN}$$
10. THIGH is then set to satisfy both constraints in the desired SCL period and in the minimum permissable values for tHIGH: $$\textrm{TIMING0.THIGH}=\max(\textrm{PERIOD}-\textrm{T_R} - \textrm{TIMING0.TLOW} -\textrm{T_F}, \textrm{THIGH_MIN})$$

#### Timing parameter examples

The following tables show a couple of examples for calculating timing register parameters for Fast-mode Plus devices. Both examples assume a desired datarate of 1 Mbaud (the bus maximum) for an SCL period of 1us, and an internal device clock period of 3ns.

Parameter Spec. Min. (ns) Reg. Val. Phys. Val (ns) Comment
TIMING0.THIGH 260 120 360 Chosen to satisfy SCL Period Minimum
TIMING0.TLOW 500 167 501 Spec. tLOW Minimum
TIMING1.T_F 20ns * (VDD/5.5V) 7 21 Signal slew-rate should be controlled
TIMING1.T_R 0 40 120 Based on pull-up resistance, line capacitance
SCL Period 1000 N/A 1002 Constraint on THIGH+TLOW+T_R+T_F
TIMING2.THD_STA 260 87 261 Spec. Minimum
TIMING2.TSU_STA 260 87 261 Spec. Minimum
TIMING3.THD_DAT 0 0 0 Spec. Minimum
TIMING3.TSU_DAT 260 87 261 Spec. Minimum
TIMING4.T_BUF 500 167 501 Spec. Minimum
TIMING4.T_STO 260 87 161 Spec. Minimum

This next example shows how the first SCL timing registers: TIMING0 and TIMING1 are altered in a high-capacitance Fast-mode Plus bus, where the physical value of tr driven to an atypical value of 400ns. As in the previous example the integer register values are determined based on a system clock period, tclk, of 3ns. All other parameters in registers TIMING2, TIMING3, TIMING4 are unchanged from the previous example.

Parameter Spec. Min. (ns) Reg. Val. Phys. Val (ns) Comment
TIMING0.THIGH 260 87 261 Spec. tHIGH Minimum
TIMING0.TLOW 500 167 501 Spec. tLOW Minimum
TIMING1.T_F 20ns * (VDD/5.5V) 7 21 Signal slew-rate should be controlled
TIMING1.T_R 0 134 402 Atypicallly high line capacitance
SCL Period 1000 N/A 395 Forced longer than minimum by long T_R

## Register Table

i2c.INTR_STATE @ + 0x0
Interrupt State Register
Reset default = 0x0, mask 0x1ff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sda_unstable stretch_timeout sda_interference scl_interference nak rx_overflow fmt_overflow rx_watermark fmt_watermark
BitsTypeResetNameDescription
0rw1c0x0fmt_watermarkraised when the FMT FIFO depth falls below the lowwater mark.
1rw1c0x0rx_watermarkraised if the RX FIFO is past the highwater mark.
2rw1c0x0fmt_overflowraised if the FMT FIFO has overflowed.
3rw1c0x0rx_overflowraised if the RX FIFO has overflowed.
4rw1c0x0nakraised if there is no ACK in response to an address or data write
5rw1c0x0scl_interferenceraised if the SCL line drops early (not supported without clock synchronization).
6rw1c0x0sda_interferenceraised if the SDA line goes low when master is trying to assert high
7rw1c0x0stretch_timeoutraised if target stretches the clock beyond the allowed timeout period
8rw1c0x0sda_unstableraised if the target does not assert a constant value of SDA during transmission.

i2c.INTR_ENABLE @ + 0x4
Interrupt Enable Register
Reset default = 0x0, mask 0x1ff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sda_unstable stretch_timeout sda_interference scl_interference nak rx_overflow fmt_overflow rx_watermark fmt_watermark
BitsTypeResetNameDescription
0rw0x0fmt_watermarkEnable interrupt when INTR_STATE.fmt_watermark is set
1rw0x0rx_watermarkEnable interrupt when INTR_STATE.rx_watermark is set
2rw0x0fmt_overflowEnable interrupt when INTR_STATE.fmt_overflow is set
3rw0x0rx_overflowEnable interrupt when INTR_STATE.rx_overflow is set
4rw0x0nakEnable interrupt when INTR_STATE.nak is set
5rw0x0scl_interferenceEnable interrupt when INTR_STATE.scl_interference is set
6rw0x0sda_interferenceEnable interrupt when INTR_STATE.sda_interference is set
7rw0x0stretch_timeoutEnable interrupt when INTR_STATE.stretch_timeout is set
8rw0x0sda_unstableEnable interrupt when INTR_STATE.sda_unstable is set

i2c.INTR_TEST @ + 0x8
Interrupt Test Register
Reset default = 0x0, mask 0x1ff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sda_unstable stretch_timeout sda_interference scl_interference nak rx_overflow fmt_overflow rx_watermark fmt_watermark
BitsTypeResetNameDescription
0wo0x0fmt_watermarkWrite 1 to force INTR_STATE.fmt_watermark to 1
1wo0x0rx_watermarkWrite 1 to force INTR_STATE.rx_watermark to 1
2wo0x0fmt_overflowWrite 1 to force INTR_STATE.fmt_overflow to 1
3wo0x0rx_overflowWrite 1 to force INTR_STATE.rx_overflow to 1
4wo0x0nakWrite 1 to force INTR_STATE.nak to 1
5wo0x0scl_interferenceWrite 1 to force INTR_STATE.scl_interference to 1
6wo0x0sda_interferenceWrite 1 to force INTR_STATE.sda_interference to 1
7wo0x0stretch_timeoutWrite 1 to force INTR_STATE.stretch_timeout to 1
8wo0x0sda_unstableWrite 1 to force INTR_STATE.sda_unstable to 1

i2c.CTRL @ + 0xc
I2C control register (Functions TBD)
Reset default = 0x0, mask 0x1
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLEHOST
BitsTypeResetNameDescription
0rw0x0ENABLEHOSTEnable Host I2C functionality

i2c.STATUS @ + 0x10
I2C live status register
Reset default = 0x3c, mask 0x3f
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXEMPTY TARGETIDLE HOSTIDLE FMTEMPTY RXFULL FMTFULL
BitsTypeResetNameDescription
0ro0x0FMTFULLFMT buffer is full
1ro0x0RXFULLRX buffer is full
2ro0x1FMTEMPTYFMT FIFO is empty
3ro0x1HOSTIDLEHost functionality is idle. No Host transaction is in progress
4ro0x1TARGETIDLETarget functionality is idle. No Target transaction is in progress
5ro0x1RXEMPTYRX FIFO is empty

i2c.RDATA @ + 0x14
Reset default = 0x0, mask 0xff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RDATA
BitsTypeResetNameDescription
7:0ro0x0RDATA

i2c.FDATA @ + 0x18
I2C Format Data
Reset default = 0x0, mask 0x0
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NAKOK RCONT READ STOP START FBYTE
BitsTypeResetNameDescription
7:0woxFBYTEFormat Byte. Directly transmitted if no flags are set.
8woxSTARTIssue a START condition before transmitting BYTE.
9woxSTOPIssue a STOP condition after this operation
11woxRCONTDo not NAK the last byte read, let the read operation continue
12woxNAKOKDo not signal an exception if the current byte is not ACK'd

i2c.FIFO_CTRL @ + 0x1c
I2C FIFO control register
Reset default = 0x0, mask 0x7c
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FMTILVL RXILVL FMTRST RXRST
BitsTypeResetNameDescription
0woxRXRSTRX fifo reset. Write 1 to the register resets RX_FIFO. Read returns 0
1woxFMTRSTFMT fifo reset. Write 1 to the register resets FMT_FIFO. Read returns 0
4:2rw0x0RXILVLTrigger level for RX interrupts. If the FIFO depth exceeds this setting, it raises rx_watermark interrupt.
 0 rxlvl1 1 character 1 rxlvl4 4 characters 2 rxlvl8 8 characters 3 rxlvl16 16 characters 4 rxlvl30 30 characters
Other values are reserved.
6:5rw0x0FMTILVLTrigger level for FMT interrupts. If the FIFO depth falls below this setting, it raises fmt_watermark interrupt.
 0 fmtlvl1 1 character 1 fmtlvl4 4 characters 2 fmtlvl8 8 characters 3 fmtlvl16 16 characters

i2c.FIFO_STATUS @ + 0x20
I2C FIFO status register
Reset default = 0x0, mask 0x3f003f
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RXLVL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FMTLVL
BitsTypeResetNameDescription
5:0ro0x0FMTLVLCurrent fill level of FMT fifo
15:6Reserved
21:16ro0x0RXLVLCurrent fill level of RX fifo

i2c.OVRD @ + 0x24
I2C override control register
Reset default = 0x0, mask 0x7
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDAVAL SCLVAL TXOVRDEN
BitsTypeResetNameDescription
0rw0x0TXOVRDENOverride the SDA and SCL TX signals.
1rw0x0SCLVALValue for SCL Override. Set to 0 to drive TX Low, and set to 1 for high-Z
2rw0x0SDAVALValue for SDA Override. Set to 0 to drive TX Low, and set to 1 for high-Z

i2c.VAL @ + 0x28
Oversampled RX values
Reset default = 0x0, mask 0xffffffff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SDA_RX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCL_RX
BitsTypeResetNameDescription
15:0ro0x0SCL_RXLast 16 oversampled values of SCL. Most recent bit is bit 0, oldest 15.
31:16ro0x0SDA_RXLast 16 oversampled values of SDA. Most recent bit is bit 16, oldest 31.

i2c.TIMING0 @ + 0x2c
Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification). All values are expressed in units of the input clock period.
Reset default = 0x0, mask 0xffffffff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TLOW 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 THIGH
BitsTypeResetNameDescription
15:0rw0x0THIGHThe actual time to hold SCL high in a given pulse
31:16rw0x0TLOWThe actual time to hold SCL low between any two SCL pulses

i2c.TIMING1 @ + 0x30
Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification). All values are expressed in units of the input clock period.
Reset default = 0x0, mask 0xffffffff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 T_F 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T_R
BitsTypeResetNameDescription
15:0rw0x0T_RThe nominal rise time to anticipate for the bus (depends on capacitance)
31:16rw0x0T_FThe nominal fall time to anticipate for the bus (influences SDA hold times)

i2c.TIMING2 @ + 0x34
Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification). All values are expressed in units of the input clock period.
Reset default = 0x0, mask 0xffffffff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 THD_STA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSU_STA
BitsTypeResetNameDescription
15:0rw0x0TSU_STAActual setup time for repeated start signals
31:16rw0x0THD_STAActual hold time for start signals

i2c.TIMING3 @ + 0x38
Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification). All values are expressed in units of the input clock period.
Reset default = 0x0, mask 0xffffffff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 THD_DAT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSU_DAT
BitsTypeResetNameDescription
15:0rw0x0TSU_DATActual setup time for data (or ack) bits
31:16rw0x0THD_DATActual hold time for data (or ack) bits (Note, where required, the parameters TVD_DAT is taken to be THD_DAT+T_F)

i2c.TIMING4 @ + 0x3c
Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification). All values are expressed in units of the input clock period.
Reset default = 0x0, mask 0xffffffff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 T_BUF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSU_STO
BitsTypeResetNameDescription
15:0rw0x0TSU_STOActual setup time for stop signals
31:16rw0x0T_BUFActual time between each STOP signal and the following START signal

i2c.TIMEOUT_CTRL @ + 0x40
I2C clock stretching timeout control
Reset default = 0x0, mask 0xffffffff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN VAL... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...VAL
BitsTypeResetNameDescription
30:0rw0x0VALClock stretching timeout value (in units of input clock frequency)
31rw0x0ENEnable timeout feature