Smoke test in which random (rd/wr) transactions are sent to the DUT and received asynchronously with scoreboard checks.

Stimulus:

• Configure DUT/Agent to Host/Target mode respectively
• Enable DUT host
• Clear/Enable interrupt (if needed)
• Program OVRD, FDATA register
• Randomize I2C timing in TIMING 0-4 registers and other parameters such as TL agent delays
• Randomize address and data for read/write transactions sent to the agent by the DUT

Checking:

• Check the timing behavior of START, STOP, ACK, NACK, and "repeated" START
• Read and write transfer matching

Smoke test in which random (rd/wr) transactions are sent to the DUT and received asynchronously with scoreboard checks.

Stimulus:

• Configure DUT/Agent to Target/Host mode respectively
• Enable DUT target
• Clear/Enable interrupt (if needed)
• Randomize I2C timing in TIMING 0-4 registers and other parameters such as TL agent delays
• Generate random addresses which are programmed to the DUT (target) and used for transaction sent by the agent (host)

Checking:

• Check the timing behavior of START, STOP, ACK, NACK, and "repeated" START
• Read and write transfer matching

Verify the reset values as indicated in the RAL specification.

• Write all CSRs with a random value.
• Apply reset to the DUT as well as the RAL model.
• Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify accessibility of CSRs as indicated in the RAL specification.

• Loop through each CSR to write it with a random value.
• Read the CSR back and check for correctness while adhering to its access policies.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify no aliasing within individual bits of a CSR.

• Walk a 1 through each CSR by flipping 1 bit at a time.
• Read the CSR back and check for correctness while adhering to its access policies.
• This verify that writing a specific bit within the CSR did not affect any of the other bits.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify no aliasing within the CSR address space.

• Loop through each CSR to write it with a random value
• Shuffle and read ALL CSRs back.
• All CSRs except for the one that was written in this iteration should read back the previous value.
• The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify random reset during CSR/memory access.

• Run csr_rw sequence to randomly access CSRs
• If memory exists, run mem_partial_access in parallel with csr_rw
• Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.

Verify regwen CSR and its corresponding lockable CSRs.

• Randomly access all CSRs
• Test when regwen CSR is set, its corresponding lockable CSRs become read-only registers

Note:

• If regwen CSR is HW read-only, this feature can be fully tested by common CSR tests - csr_rw and csr_aliasing.
• If regwen CSR is HW updated, a separate test should be created to test it.

This is only applicable if the block contains regwen and locakable CSRs.

Test error interrupts are asserted by the Host DUT due to interference and unstable signals on bus.

Stimulus:

• Configure DUT/Agent to Host/Target mode respectively
• In host transmit mode, device (target/host) forces sda or scl signal low within the clock pulse of host scl that asserts sda_interference or scl_interference interrupts
• In host receiving mode (data or ack bits), SDA signal is changed with the clock pulse of host scl that asserts intr_sda_unstable interrupts
• When error interrupt assertions are detected, dut, agent, and scoreboard will be reset on-the-fly then new transaction can be continue programming

Checking:

• Ensure all intr_scl_interference, intr_sda_interference, and intr_sda_unstable interrupts are asserted and stay asserted until cleared
• Ensure IP operation get back normal after on-the-fly reset finished

Support vseq (context) switching with random reset in between.

Stimulus:

• Configure DUT/Agent to Host/Target mode respectively
• Combine above sequences in one test to run sequentially except csr sequence and i2c_host_rx_oversample_vseq (requires zero_delays)
• Randomly add reset between each sequence

Checking:

• Ensure transactions are transmitted/received correctly,
• Ensure reset is handled correctly

Support random reset in parallel with stress_all and tl_errors sequences.

Stimulus:

• Configure DUT/Agent to Host/Target mode respectively
• Combine above sequences in one test to run sequentially except csr sequence and i2c_host_rx_oversample_vseq (requires zero_delays)
• Randomly add reset within the sequences then switch to another one

Checking:

• Ensure transactions are transmitted/received correctly
• Ensure reset is handled correctly

The Host DUT sends and receives transactions at max bandwidth.

Stimulus:

• Configure DUT/Agent to Host/Target mode respectively
• Reduce access latency for all fifos
• Issue long read/write back-to-back transactions
• Read rx_fifo as soon as read data valid
• Clear interrupt quickly

Checking:

• Ensure transactions are transmitted/received correctly

Test SCL/SDA override.

Stimulus:

• Configure DUT/Agent to Host/Target mode respectively
• Program OVRD register

Checking:

• Ensure scl_o, sda_o are overridden

Test the watermark interrupt of fmt_fifo and rx_fifo.

Stimulus:

• Configure DUT/Agent to Host/Target mode respectively
• Program random fmt_fifo and rx_fifo watermark level
• Write data quickly to fmt_fifo and rx_fifo for triggering watermark interrupts

Checking:

• Ensure the fmt_fifo and rx_fifo watermark interrupts are asserted
• Ensure the fmt_fifo and rx_fifo watermark interrupts stay asserted until cleared
• Ensure receving correct number of fmt_fifo and rx_fifo watermark interrupts

Test the overflow interrupt for fmt_fifo and rx_fifo.

Stimulus:

• Configure DUT/Agent to Host/Target mode respectively
• DUT keeps sending a number of format byte higher than the size of fmt_fifo and rx_fifo depth

Checking:

• Ensure excess format bytes are dropped
• Ensure fmt_overflow and rx_overflow interrupt are asserted

Test fmt_fifo and rx_fifo reset.

Stimulus:

• Configure DUT/Agent to Host/Target mode respectively
• Fill up the fmt_fifo with data to be sent out
• Reset the fifo randomly after a number of bytes shows up on fmt_fifo

Checking:

• Ensure the remaining entries are not show up after fmt_fifo is reset

Test fmt_fifo and rx_fifo in full states.

Stimulus:

• Configure DUT/Agent to Host/Target mode respectively
• Send enough read and write requests to fmt_fifo
• Hold reading data from rx_fifo until rx fifo is full

Checking:

• Check fifo full states by reading status register

Test stretch_timeout interrupts.

Stimulus:

• Configure DUT/Agent to Host/Target mode respectively
• Set timeout enable bit of TIMEOUT_CTRL register
• Program timeout values (higher than host scl clock pulse) into TIMEOUT_CTRL register
• Configure agent to pull down target (device) scl after the bit 9 (ACK) is transmitted

Checking:

• Ensure stretch_timeout is asserted and a correct number is received

Host mode: test oversampling on received channel.

Stimulus:

• Use input clock to sample the target sda (sample with baud rate equal to 1)
• Drive scl_rx using input clock

Checking:

• Read rx data oversampled value and ensure it is same as driven value

Test ack_stop interrupt is asserted by the Target DUT,

Stimulus:

• Configure DUT/Agent to Target/Host mode respectively
• Host agent send STOP after ACK

Checking:

• Ensure all acq_stop is asserted and stay asserted until cleared
• Ensure IP operation get back normal after on-the-fly reset finished

Support vseq (context) switching with random reset in between.

Stimulus:

• Configure DUT/Agent to Target/Host mode respectively
• Combine above sequences in one test to run sequentiall except csr sequence
• Randomly add reset between each sequence

Checking:

• Ensure transactions are transmitted/received correctly,
• Ensure reset is handled correctly

Support random reset in parallel with stress_all and tl_errors sequences.

Stimulus:

• Configure DUT/Agent to Target/Host mode respectively
• Combine above sequences in one test to run sequentially except csr sequence
• Randomly add reset within the sequences then switch to another one

Checking:

• Ensure transactions are transmitted/received correctly
• Ensure reset is handled correctly

The Host Agent sends and receives transactions at max bandwidth.

Stimulus:

• Configure DUT/Agent to Target/Host mode respectively
• Reduce access latency for all fifos
• Issue long read/write back-to-back transactions
• Read tx_fifo as soon as read data valid
• Clear interrupt quickly

Checking:

• Ensure transactions are transmitted/received correctly

Test the overflow interrupt for tx_fifo and acq_fifo overflow.

Stimulus:

• Configure DUT/Agent to Target/Host mode respectively
• Agent keeps sending a number of format byte higher than the size of tx_fifo and acq_fifo

Checking:

• Ensure excess format bytes are dropped
• Ensure tx_overflow and acq_overflow interrupt are asserted

Test tx_empty and tx_nonempty interrupt.

Stimulus:

• Configure DUT/Agent to Target/Host mode respectively
• Agent sends transaction to the DUT

Checking:

• During read transaction, ensure tx_empty interrupt is asserted when no data left in tx_fifo otherwise tx_empty interrupt must be asserted

Test tx_fifo and acq_fifo reset.

Stimulus:

• Configure DUT/Agent to Target/Host mode respectively
• Fill up the acq_fifo with data to be sent out
• Reset the fifo randomly after a random number of bytes shows up on acq_fifo

Checking:

• Ensure the remaining entries are not show up after fmt_fifo is reset,

Test acq_fifo and tx_fifo in full states.

Stimulus:

• Configure DUT/Agent to Target/Host mode respectively
• Send enough read and write requests to acq_fifo
• Hold reading data from tx_fifo until tx fifo is full

Checking:

• Check fifo full states by reading status register

Test host_timeout interrupts.

Stimulus:

• Configure DUT/Agent to Host/Target mode respectively
• Set timeout enable bit of HOST_TIMEOUT_CTRL register
• Agent stops sending clock during an ongoing transaction

Checking:

• Ensure host_timeout is asserted and a correct number is received

Verify common alert_test CSR that allows SW to mock-inject alert requests.

• Enable a random set of alert requests by writing random value to alert_test CSR.
• Check each alert_tx.alert_p pin to verify that only the requested alerts are triggered.
• During alert_handshakes, write alert_test CSR again to verify that: If alert_test writes to current ongoing alert handshake, the alert_test request will be ignored. If alert_test writes to current idle alert handshake, a new alert_handshake should be triggered.
• Wait for the alert handshakes to finish and verify alert_tx.alert_p pins all sets back to 0.
• Repeat the above steps a bunch of times.

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

• Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
• Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s).
• Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
• Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
• Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
• Repeat the above steps a bunch of times.

Access out of bounds address and verify correctness of response / behavior

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the [TLUL spec]({{< relref "hw/ip/tlul/doc/_index.md#explicit-error-cases" >}})

• TL-UL protocol error cases
  • invalid opcode
  • some mask bits not set when opcode is PutFullData
  • mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
  • mask and address misaligned, e.g. a_address = 0x01, a_mask = 'b0001
  • address and size aren't aligned, e.g. a_address = 0x01, a_size != 0
  • size is greater than 2
• OpenTitan defined error cases
  • access unmapped address, expect d_error = 1 when devmode_i == 1
  • write a CSR with unaligned address, e.g. a_address[1:0] != 0
  • write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
  • write a memory with a_mask != '1 when it doesn't support partial accesses
  • read a WO (write-only) memory
  • write a RO (read-only) memory
  • write with instr_type = True

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

Verify that the data integrity check violation generates an alert.

• Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.
• Inject a fault at the onehot check in u_reg.u_prim_reg_we_check and verify the corresponding fatal alert occurs

Verify the countermeasure(s) BUS.INTEGRITY.

Cover each lockable reg field with these 2 cases:

• When regwen = 1, a different value is written to the lockable CSR field, and a read occurs after that.
• When regwen = 0, a different value is written to the lockable CSR field, and a read occurs after that.

This is only applicable if the block contains regwen and locakable CSRs.

Cover the following error cases on TL-UL bus:

• TL-UL protocol error cases.
• OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.