I2C DV document

Goals

  • DV
    • Verify all I2C IP features by running dynamic simulations with a SV/UVM based testbench
    • Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
  • FPV
    • Verify TileLink device protocol compliance with an SVA based testbench

Current status

Design features

For detailed information on I2C design features, please see the I2C design specification.

Testbench architecture

I2C testbench has been constructed based on the CIP testbench architecture.

Block diagram

Block diagram

Top level testbench

Top level testbench is located at hw/ip/i2c/dv/tb/tb.sv. It instantiates the I2C DUT module hw/ip/i2c/rtl/i2c.sv. In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db:

Common DV utility components

The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

Global types & methods

All common types and methods defined at the package level can be found in i2c_env_pkg. Some of them in use are:

parameter uint I2C_FMT_FIFO_DEPTH = 32;
parameter uint I2C_RX_FIFO_DEPTH  = 32;

TL_agent

I2C instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into I2C device.

I2C agent

I2C agent is configured to work device mode and implemented as reactive agent

UVM RAL Model

The I2C RAL model is created with the ralgen FuseSoC generator script automatically when the simulation is at the build stage.

It can be created manually by invoking regtool:

Stimulus strategy

Test sequences

All test sequences reside in hw/ip/i2c/dv/env/seq_lib. The i2c_base_vseq virtual sequence is extended from cip_base_vseq and serves as a starting point. All test sequences are extended from i2c_base_vseq. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. Some of the most commonly used tasks / functions are as follows:

  • task 1:
  • task 2:

Functional coverage

To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:

  • cg1:
  • cg2:

Self-checking strategy

Scoreboard

The i2c_scoreboard is primarily used for end to end checking. It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:

  • analysis port1:
  • analysis port2:

Assertions

  • TLUL assertions: The tb/i2c_bind.sv binds the tlul_assert assertions to the IP to ensure TileLink interface protocol compliance.
  • Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
  • assertion 1
  • assertion 2

Building and running tests

We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:

$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/i2c/dv/i2c_sim_cfg.hjson -i i2c_smoke

Testplan

Testpoints

Milestone Name Tests Description
V1 host_smoke i2c_smoke

Smoke test in which random (rd/wr) transactions are sent to the DUT and received asynchronously with scoreboard checks.

Stimulus:

  • Configure DUT/Agent to Host/Target mode respectively
  • Enable DUT host
  • Clear/Enable interrupt (if needed)
  • Program OVRD, FDATA register
  • Randomize I2C timing in TIMING 0-4 registers and other parameters such as TL agent delays
  • Randomize address and data for read/write transactions sent to the agent by the DUT

Checking:

  • Check the timing behavior of START, STOP, ACK, NACK, and "repeated" START
  • Read and write transfer matching
V1 target_smoke i2c_smoke

Smoke test in which random (rd/wr) transactions are sent to the DUT and received asynchronously with scoreboard checks.

Stimulus:

  • Configure DUT/Agent to Target/Host mode respectively
  • Enable DUT target
  • Clear/Enable interrupt (if needed)
  • Randomize I2C timing in TIMING 0-4 registers and other parameters such as TL agent delays
  • Generate random addresses which are programmed to the DUT (target) and used for transaction sent by the agent (host)

Checking:

  • Check the timing behavior of START, STOP, ACK, NACK, and "repeated" START
  • Read and write transfer matching
V1 csr_hw_reset i2c_csr_hw_reset

Verify the reset values as indicated in the RAL specification.

  • Write all CSRs with a random value.
  • Apply reset to the DUT as well as the RAL model.
  • Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_rw i2c_csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

  • Loop through each CSR to write it with a random value.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_bit_bash i2c_csr_bit_bash

Verify no aliasing within individual bits of a CSR.

  • Walk a 1 through each CSR by flipping 1 bit at a time.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • This verify that writing a specific bit within the CSR did not affect any of the other bits.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_aliasing i2c_csr_aliasing

Verify no aliasing within the CSR address space.

  • Loop through each CSR to write it with a random value
  • Shuffle and read ALL CSRs back.
  • All CSRs except for the one that was written in this iteration should read back the previous value.
  • The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_mem_rw_with_rand_reset i2c_csr_mem_rw_with_rand_reset

Verify random reset during CSR/memory access.

  • Run csr_rw sequence to randomly access CSRs
  • If memory exists, run mem_partial_access in parallel with csr_rw
  • Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
V2 host_error_intr i2c_error_intr

Test error interrupts are asserted by the Host DUT due to interference and unstable signals on bus.

Stimulus:

  • Configure DUT/Agent to Host/Target mode respectively
  • In host transmit mode, device (target/host) forces sda or scl signal low within the clock pulse of host scl that asserts sda_interference or scl_interference interrupts
  • In host receiving mode (data or ack bits), SDA signal is changed with the clock pulse of host scl that asserts intr_sda_unstable interrupts
  • When error interrupt assertions are detected, dut, agent, and scoreboard will be reset on-the-fly then new transaction can be continue programming

Checking:

  • Ensure all intr_scl_interference, intr_sda_interference, and intr_sda_unstable interrupts are asserted and stay asserted until cleared
  • Ensure IP operation get back normal after on-the-fly reset finished
V2 host_stress_all i2c_stress_all

Support vseq (context) switching with random reset in between.

Stimulus:

  • Configure DUT/Agent to Host/Target mode respectively
  • Combine above sequences in one test to run sequentially except csr sequence and i2c_rx_oversample_vseq (requires zero_delays)
  • Randomly add reset between each sequence

Checking:

  • Ensure transactions are transmitted/received correctly,
  • Ensure reset is handled correctly
V2 host_stress_all_with_rand_reset i2c_stress_all_with_rand_reset

Support random reset in parallel with stress_all and tl_errors sequences.

Stimulus:

  • Configure DUT/Agent to Host/Target mode respectively
  • Combine above sequences in one test to run sequentially except csr sequence and i2c_rx_oversample_vseq (requires zero_delays)
  • Randomly add reset within the sequences then switch to another one

Checking:

  • Ensure transactions are transmitted/received correctly
  • Ensure reset is handled correctly
V2 host_perf i2c_perf

The Host DUT sends and receives transactions at max bandwidth.

Stimulus:

  • Configure DUT/Agent to Host/Target mode respectively
  • Reduce access latency for all fifos
  • Issue long read/write back-to-back transactions
  • Read rx_fifo as soon as read data valid
  • Clear interrupt quickly

Checking:

  • Ensure transactions are transmitted/received correctly
V2 host_override i2c_override

Test SCL/SDA override.

Stimulus:

  • Configure DUT/Agent to Host/Target mode respectively
  • Program OVRD register

Checking:

  • Ensure scl_o, sda_o are overridden
V2 host_fifo_watermark i2c_fifo_watermark

Test the watermark interrupt of fmt_fifo and rx_fifo.

Stimulus:

  • Configure DUT/Agent to Host/Target mode respectively
  • Program random fmt_fifo and rx_fifo watermark level
  • Write data quickly to fmt_fifo and rx_fifo for triggering watermark interrupts

Checking:

  • Ensure the fmt_fifo and rx_fifo watermark interrupts are asserted
  • Ensure the fmt_fifo and rx_fifo watermark interrupts stay asserted until cleared
  • Ensure receving correct number of fmt_fifo and rx_fifo watermark interrupts
V2 host_fifo_overflow i2c_fifo_overflow

Test the overflow interrupt for fmt_fifo and rx_fifo.

Stimulus:

  • Configure DUT/Agent to Host/Target mode respectively
  • DUT keeps sending a number of format byte higher than the size of fmt_fifo and rx_fifo depth

Checking:

  • Ensure excess format bytes are dropped
  • Ensure fmt_overflow and rx_overflow interrupt are asserted
V2 target_fifo_empty

Test tx_empty and tx_nonempty interrupt.

Stimulus:

  • Configure DUT/Agent to Target/Host mode respectively
  • Agent sends transaction to the DUT

Checking:

  • During read transaction, ensure tx_empty interrupt is asserted when no data left in tx_fifo otherwise tx_empty interrupt must be asserted
V2 host_fifo_reset

Test fmt_fifo and rx_fifo reset.

Stimulus:

  • Configure DUT/Agent to Host/Target mode respectively
  • Fill up the fmt_fifo with data to be sent out
  • Reset the fifo randomly after a number of bytes shows up on fmt_fifo

Checking:

  • Ensure the remaining entries are not show up after fmt_fifo is reset
V2 host_fifo_full i2c_fifo_full

Test fmt_fifo and rx_fifo in full states.

Stimulus:

  • Configure DUT/Agent to Host/Target mode respectively
  • Send enough read and write requests to fmt_fifo
  • Hold reading data from rx_fifo until rx fifo is full

Checking:

  • Check fifo full states by reading status register
V2 host_timeout

Test stretch_timeout interrupts.

Stimulus:

  • Configure DUT/Agent to Host/Target mode respectively
  • Set timeout enable bit of TIMEOUT_CTRL register
  • Program timeout values (higher than host scl clock pulse) into TIMEOUT_CTRL register
  • Configure agent to pull down target (device) scl after the bit 9 (ACK) is transmitted

Checking:

  • Ensure stretch_timeout is asserted and a correct number is received
V2 host_rx_oversample

Host mode: test oversampling on received channel.

Stimulus:

  • Use input clock to sample the target sda (sample with baud rate equal to 1)
  • Drive scl_rx using input clock

Checking:

  • Read rx data oversampled value and ensure it is same as driven value
V2 host_rw_loopback

Host and Target mode: do write data, read loopback, and compare.

Stimulus:

  • Drive DUT/Agent to write data to the Agent/DUT then read loopback

Checking:

  • Ensure read data is matched with write data
V2 target_error_intr i2c_error_intr

Test ack_stop interrupt is asserted by the Target DUT,

Stimulus:

  • Configure DUT/Agent to Target/Host mode respectively
  • Host agent send STOP after ACK

Checking:

  • Ensure all acq_stop is asserted and stay asserted until cleared
  • Ensure IP operation get back normal after on-the-fly reset finished
V2 target_stress_all i2c_stress_all

Support vseq (context) switching with random reset in between.

Stimulus:

  • Configure DUT/Agent to Target/Host mode respectively
  • Combine above sequences in one test to run sequentiall except csr sequence
  • Randomly add reset between each sequence

Checking:

  • Ensure transactions are transmitted/received correctly,
  • Ensure reset is handled correctly
V2 target_stress_all_with_rand_reseti2c_stress_all_with_rand_reset

Support random reset in parallel with stress_all and tl_errors sequences.

Stimulus:

  • Configure DUT/Agent to Target/Host mode respectively
  • Combine above sequences in one test to run sequentially except csr sequence and i2c_rx_oversample_vseq (requires zero_delays)
  • Randomly add reset within the sequences then switch to another one

Checking:

  • Ensure transactions are transmitted/received correctly
  • Ensure reset is handled correctly
V2 target_perf i2c_perf

The Host Agent sends and receives transactions at max bandwidth.

Stimulus:

  • Configure DUT/Agent to Target/Host mode respectively
  • Reduce access latency for all fifos
  • Issue long read/write back-to-back transactions
  • Read tx_fifo as soon as read data valid
  • Clear interrupt quickly

Checking:

  • Ensure transactions are transmitted/received correctly
V2 target_fifo_overflow i2c_fifo_overflow

Test the overflow interrupt for tx_fifo and acq_fifo overflow.

Stimulus:

  • Configure DUT/Agent to Target/Host mode respectively
  • Agent keeps sending a number of format byte higher than the size of tx_fifo and acq_fifo

Checking:

  • Ensure excess format bytes are dropped
  • Ensure tx_overflow and acq_overflow interrupt are asserted
V2 target_fifo_reset

Test tx_fifo and acq_fifo reset.

Stimulus:

  • Configure DUT/Agent to Target/Host mode respectively
  • Fill up the acq_fifo with data to be sent out
  • Reset the fifo randomly after a random number of bytes shows up on acq_fifo

Checking:

  • Ensure the remaining entries are not show up after fmt_fifo is reset,
V2 target_fifo_full i2c_fifo_full

Test acq_fifo and tx_fifo in full states.

Stimulus:

  • Configure DUT/Agent to Target/Host mode respectively
  • Send enough read and write requests to acq_fifo
  • Hold reading data from tx_fifo until tx fifo is full

Checking:

  • Check fifo full states by reading status register
V2 target_timeout

Test host_timeout interrupts.

Stimulus:

  • Configure DUT/Agent to Host/Target mode respectively
  • Set timeout enable bit of HOST_TIMEOUT_CTRL register
  • Agent stops sending clock during an ongoing transaction

Checking:

  • Ensure host_timeout is asserted and a correct number is received
V2 alert_test i2c_alert_test

Verify common alert_test CSR that allows SW to mock-inject alert requests.

  • Enable a random set of alert requests by writing random value to alert_test CSR.
  • Check each alert_tx.alert_p pin to verify that only the requested alerts are triggered.
  • During alert_handshakes, write alert_test CSR again to verify that: If alert_test writes to current ongoing alert handshake, the alert_test request will be ignored. If alert_test writes to current idle alert handshake, a new alert_handshake should be triggered.
  • Wait for the alert handshakes to finish and verify alert_tx.alert_p pins all sets back to 0.
  • Repeat the above steps a bunch of times.
V2 intr_test i2c_intr_test

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

  • Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
  • Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s).
  • Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
  • Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
  • Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
  • Repeat the above steps a bunch of times.
V2 tl_d_oob_addr_access i2c_tl_errors

Access out of bounds address and verify correctness of response / behavior

V2 tl_d_illegal_access i2c_tl_errors

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the [TLUL spec]({{< relref "hw/ip/tlul/doc/_index.md#explicit-error-cases" >}})

  • TL-UL protocol error cases
    • invalid opcode
    • some mask bits not set when opcode is PutFullData
    • mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
    • mask and address misaligned, e.g. a_address = 0x01, a_mask = 'b0001
    • address and size aren't aligned, e.g. a_address = 0x01, a_size != 0
    • size is greater than 2
  • OpenTitan defined error cases
    • access unmapped address, expect d_error = 1 when devmode_i == 1
    • write a CSR with unaligned address, e.g. a_address[1:0] != 0
    • write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
    • write a memory with a_mask != '1 when it doesn't support partial accesses
    • read a WO (write-only) memory
    • write a RO (read-only) memory
V2 tl_d_outstanding_access i2c_csr_hw_reset
i2c_csr_rw
i2c_csr_aliasing
i2c_same_csr_outstanding

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

V2 tl_d_partial_access i2c_csr_hw_reset
i2c_csr_rw
i2c_csr_aliasing
i2c_same_csr_outstanding

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

V3 tl_intg_err i2c_tl_intg_err

Verify that the data integrity check violation generates an alert.

Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.

Covergroups

Name Description
tl_errors_cg

Cover the following error cases on TL-UL bus:

  • TL-UL protocol error cases.
  • OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.
tl_intg_err_cg

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

tl_intg_err_mem_subword_cg

Cover the kinds of integrity errors with byte enabled write on memory.

Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.