I2C smoke test in which random (rd/wr) transactions are sent to the DUT and received asynchronously with scoreboard checks.

Stimulus:

• Enable I2C host
• Clear/Enable interrupt (if needed)
• Program OVRD, FDATA register
• Randomize I2C timing in TIMING 0-4 registers and other parameters such as TL agent delays
• Randomize address and data for read/write transactions sent to the device

Checking:

• Check the timing behavior of START, STOP, ACK, NACK, and "repeated" START
• Read and write transfer matching

Verify the reset values as indicated in the RAL specification.

• Write all CSRs with a random value.
• Apply reset to the DUT as well as the RAL model.
• Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify accessibility of CSRs as indicated in the RAL specification.

• Loop through each CSR to write it with a random value.
• Read the CSR back and check for correctness while adhering to its access policies.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify no aliasing within individual bits of a CSR.

• Walk a 1 through each CSR by flipping 1 bit at a time.
• Read the CSR back and check for correctness while adhering to its access policies.
• This verify that writing a specific bit within the CSR did not affect any of the other bits.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify no aliasing within the CSR address space.

• Loop through each CSR to write it with a random value
• Shuffle and read ALL CSRs back.
• All CSRs except for the one that was written in this iteration should read back the previous value.
• The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify random reset during CSR/memory access.

• Run csr_rw sequence to randomly access CSRs
• If memory exists, run mem_partial_access in parallel with csr_rw
• Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.

Test error interrupts are asserted by the host due to interference and unstable signals on bus.

Stimulus:

• In host transmit mode, device (target/host) forces sda or scl signal low within the clock pulse of host scl that asserts sda_interference or scl_interference interrupts
• In host receiving mode (data or ack bits), SDA signal is changed with the clock pulse of host scl that asserts intr_sda_unstable interrupts
• When error interrupt assertions are detected, dut, agent, and scoreboard will be reset on-the-fly then new transaction can be continue programming

Checking:

• Ensure all intr_scl_interference, intr_sda_interference, and intr_sda_unstable interrupts are asserted
• Ensure all intr_scl_interference, intr_sda_interference, and intr_sda_unstable interrupts stay asserted until cleared
• Ensure IP operation get back normal after on-the-fly reset finished

Support vseq (context) switching with random reset in between.

Stimulus:

• Combine above sequences in one test to run sequentially except csr sequence and i2c_rx_oversample_vseq (requires zero_delays)
• Randomly add reset between each sequence

Checking:

• Ensure transactions are transmitted/received correctly,
• Ensure reset is handled correctly

Support random reset in parallel with stress_all and tl_errors sequences.

Stimulus:

• Combine above sequences in one test to run sequentially except csr sequence and i2c_rx_oversample_vseq (requires zero_delays)
• Randomly add reset within the sequences then switch to another one

Checking:

• Ensure transactions are transmitted/received correctly
• Ensure reset is handled correctly

Send/receive transactions at max bandwidth.

Stimulus:

• Reduce access latency for fmt_fifo and rx_fifo
• Issue long read/write back-to-back transactions
• Read rx_fifo as soon as read data valid
• Clear interrupt quickly

Checking:

• Ensure transactions are transmitted/received correctly

Test SCL/SDA override.

Stimulus:

• Program OVRD register

Checking:

• Ensure scl_o, sda_o are overridden

Test the watermark interrupt of fmt_fifo and rx_fifo.

Stimulus:

• Program random fmt_fifo and rx_fifo watermark level
• Write data quickly to fmt_fifo and rx_fifo for triggering watermark interrupts

Checking:

• Ensure the fmt_fifo and rx_fifo watermark interrupts are asserted
• Ensure the fmt_fifo and rx_fifo watermark interrupts stay asserted until cleared
• Ensure receving correct number of fmt_fifo and rx_fifo watermark interrupts

Test the overflow interrupt of fmt_fifo and rx_fifo.

Stimulus:

• Keep sending a number of format byte higher than fmt_fifo and rx_fifo depth

Checking:

• Ensure excess format bytes are dropped
• Ensure fmt_overflow and rx_overflow interrupt are asserted
• Ensure receving correct number of fmt_fifo and rx_fifo watermark interrupts

Test fmt_fifo reset.

Stimulus:

• Fill up the fmt fifo with data to be sent out
• Reset the fmt_fifo randomly after a number of bytes shows up on fmt_fifo

Checking:

• Ensure the remaining entries are not show up after fmt_fifo is reset

Test rx_fifo reset.

Stimulus:

• Fill up the rx fifo by sending data bytes over rx
• Reset the rx_fifo randomly after a random number of bytes shows up on rx_fifo

Checking:

• Ensure that reads to rdata register yield 0s after rx_fifo is reset

Test fmt_fifo and rx_fifo in full states.

Stimulus:

• Send enough read and write requests to fmt_fifo
• Hold reading data from rx_fifo until rx fifo is full

Checking:

• Check fifo full states by reading status register

Test host clock stretching.

Stimulus:

• Set timeout enable bit into timeout_ctrl register
• Program timeout values (higher than host scl clock pulse) into timeout_ctrl register
• Configure agent to pull down target (device) scl after the bit 9 (ACK) is transmitted

Checking:

• Ensure stretch_timeout interrupt is asserted
• Ensure receving the correct number of stretch_timeout interrupt

Test oversampling on received channel.

Stimulus:

• Use input clock to sample the target sda (sample with baud rate equal to 1)
• Drive scl_rx using input clock

Checking:

• Read rx data oversampled value and ensure it is same as driven value

Test write data, read loopback, then compare.

Stimulus:

• Drive i2c host to write data to the device then read loopback

Checking:

• Ensure read data is matched with write data

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

• Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
• Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s).
• Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
• Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
• Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
• Repeat the above steps a bunch of times.

Access out of bounds address and verify correctness of response / behavior

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested

• TL-UL protocol error cases
  • Unsupported opcode. e.g a_opcode isn't Get, PutPartialData or PutFullData
  • Mask isn't all active if opcode = PutFullData
  • Mask isn't in enabled lanes, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
  • Mask doesn't align with address, e.g. a_address = 0x01, a_mask = 'b0001
  • Address and size aren't aligned, e.g. a_address = 0x01, a_size != 0
  • Size is over 2.
• OpenTitan defined error cases
  • Access unmapped address, return d_error = 1 when devmode_i == 1
  • Write CSR with unaligned address, e.g. a_address[1:0] != 0
  • Write CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
  • Write a memory without enabling all lanes (a_mask = '1) if memory doesn't support byte enabled write
  • Read a WO (write-only) memory

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

Access CSR with one or more bytes of data For read, expect to return all word value of the CSR For write, enabling bytes should cover all CSR valid fields