I2C DV document
Goals
- DV
- Verify all I2C IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
- FPV
- Verify TileLink device protocol compliance with an SVA based testbench
Current status
Design features
For detailed information on I2C design features, please see the I2C design specification.
Testbench architecture
I2C testbench has been constructed based on the CIP testbench architecture.
Block diagram
Top level testbench
Top level testbench is located at hw/ip/i2c/dv/tb/tb.sv
. It instantiates the I2C DUT module hw/ip/i2c/rtl/i2c.sv
.
In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db
:
- Clock and reset interface
- TileLink host interface
- I2C IOs
- Interrupts (
pins_if
)
Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
Global types & methods
All common types and methods defined at the package level can be found in
i2c_env_pkg
. Some of them in use are:
parameter uint I2C_FMT_FIFO_DEPTH = 32;
parameter uint I2C_RX_FIFO_DEPTH = 32;
TL_agent
I2C instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into I2C device.
I2C agent
I2C agent is configured to work device mode and implemented as reactive agent
UVM RAL Model
The I2C RAL model is created with the ralgen
FuseSoC generator script automatically when the simulation is at the build stage.
It can be created manually by invoking regtool
:
Stimulus strategy
Test sequences
All test sequences reside in hw/ip/i2c/dv/env/seq_lib
.
The i2c_base_vseq
virtual sequence is extended from cip_base_vseq
and serves as a starting point.
All test sequences are extended from i2c_base_vseq
.
It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:
- task 1:
- task 2:
Functional coverage
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:
- cg1:
- cg2:
Self-checking strategy
Scoreboard
The i2c_scoreboard
is primarily used for end to end checking.
It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:
- analysis port1:
- analysis port2:
Assertions
- TLUL assertions: The
tb/i2c_bind.sv
binds thetlul_assert
assertions to the IP to ensure TileLink interface protocol compliance. - Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
- assertion 1
- assertion 2
Building and running tests
We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:
$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/i2c/dv/i2c_sim_cfg.hjson -i i2c_host_smoke
Testplan
Testpoints
Milestone | Name | Tests | Description |
---|---|---|---|
V1 | host_smoke | i2c_host_smoke | Smoke test in which random (rd/wr) transactions are sent to the DUT and received asynchronously with scoreboard checks. Stimulus:
Checking:
|
V1 | target_smoke | Smoke test in which random (rd/wr) transactions are sent to the DUT and received asynchronously with scoreboard checks. Stimulus:
Checking:
| |
V1 | csr_hw_reset | i2c_csr_hw_reset | Verify the reset values as indicated in the RAL specification.
|
V1 | csr_rw | i2c_csr_rw | Verify accessibility of CSRs as indicated in the RAL specification.
|
V1 | csr_bit_bash | i2c_csr_bit_bash | Verify no aliasing within individual bits of a CSR.
|
V1 | csr_aliasing | i2c_csr_aliasing | Verify no aliasing within the CSR address space.
|
V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | Verify random reset during CSR/memory access.
|
V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw i2c_csr_aliasing | Verify regwen CSR and its corresponding lockable CSRs.
Note:
This is only applicable if the block contains regwen and locakable CSRs. |
V2 | host_error_intr | i2c_host_error_intr | Test error interrupts are asserted by the Host DUT due to interference and unstable signals on bus. Stimulus:
Checking:
|
V2 | host_stress_all | i2c_host_stress_all | Support vseq (context) switching with random reset in between. Stimulus:
Checking:
|
V2 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | Support random reset in parallel with stress_all and tl_errors sequences. Stimulus:
Checking:
|
V2 | host_perf | i2c_host_perf | The Host DUT sends and receives transactions at max bandwidth. Stimulus:
Checking:
|
V2 | host_override | i2c_host_override | Test SCL/SDA override. Stimulus:
Checking:
|
V2 | host_fifo_watermark | i2c_host_fifo_watermark | Test the watermark interrupt of fmt_fifo and rx_fifo. Stimulus:
Checking:
|
V2 | host_fifo_overflow | i2c_host_fifo_overflow | Test the overflow interrupt for fmt_fifo and rx_fifo. Stimulus:
Checking:
|
V2 | host_fifo_reset | i2c_host_fifo_reset_fmt i2c_host_fifo_reset_rx i2c_host_fifo_fmt_empty | Test fmt_fifo and rx_fifo reset. Stimulus:
Checking:
|
V2 | host_fifo_full | i2c_host_fifo_full | Test fmt_fifo and rx_fifo in full states. Stimulus:
Checking:
|
V2 | host_timeout | i2c_host_timeout | Test stretch_timeout interrupts. Stimulus:
Checking:
|
V2 | host_rx_oversample | i2c_host_rx_oversample | Host mode: test oversampling on received channel. Stimulus:
Checking:
|
V2 | target_error_intr | Test ack_stop interrupt is asserted by the Target DUT, Stimulus:
Checking:
| |
V2 | target_stress_all | Support vseq (context) switching with random reset in between. Stimulus:
Checking:
| |
V2 | target_stress_all_with_rand_reset | Support random reset in parallel with stress_all and tl_errors sequences. Stimulus:
Checking:
| |
V2 | target_perf | The Host Agent sends and receives transactions at max bandwidth. Stimulus:
Checking:
| |
V2 | target_fifo_overflow | Test the overflow interrupt for tx_fifo and acq_fifo overflow. Stimulus:
Checking:
| |
V2 | target_fifo_empty | Test tx_empty and tx_nonempty interrupt. Stimulus:
Checking:
| |
V2 | target_fifo_reset | Test tx_fifo and acq_fifo reset. Stimulus:
Checking:
| |
V2 | target_fifo_full | Test acq_fifo and tx_fifo in full states. Stimulus:
Checking:
| |
V2 | target_timeout | Test host_timeout interrupts. Stimulus:
Checking:
| |
V2 | alert_test | i2c_alert_test | Verify common
|
V2 | intr_test | i2c_intr_test | Verify common intr_test CSRs that allows SW to mock-inject interrupts.
|
V2 | tl_d_oob_addr_access | i2c_tl_errors | Access out of bounds address and verify correctness of response / behavior |
V2 | tl_d_illegal_access | i2c_tl_errors | Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the [TLUL spec]({{< relref "hw/ip/tlul/doc/_index.md#explicit-error-cases" >}})
|
V2 | tl_d_outstanding_access | i2c_csr_hw_reset i2c_csr_rw i2c_csr_aliasing i2c_same_csr_outstanding | Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address. |
V2 | tl_d_partial_access | i2c_csr_hw_reset i2c_csr_rw i2c_csr_aliasing i2c_same_csr_outstanding | Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields. |
V2S | tl_intg_err | i2c_tl_intg_err i2c_sec_cm | Verify that the data integrity check violation generates an alert.
|
V2S | sec_cm_bus_integrity | Verify the countermeasure(s) BUS.INTEGRITY. |
Covergroups
Name | Description |
---|---|
regwen_val_when_new_value_written_cg | Cover each lockable reg field with these 2 cases:
This is only applicable if the block contains regwen and locakable CSRs. |
tl_errors_cg | Cover the following error cases on TL-UL bus:
|
tl_intg_err_cg | Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check. Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied. |