I2C DV Plan

Goals

  • DV
    • Verify all I2C IP features by running dynamic simulations with a SV/UVM based testbench
    • Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
  • FPV
    • Verify TileLink device protocol compliance with an SVA based testbench

Current status

Design features

For detailed information on I2C design features, please see the I2C design specification.

Testbench architecture

I2C testbench has been constructed based on the CIP testbench architecture.

Block diagram

Block diagram

Top level testbench

Top level testbench is located at hw/ip/i2c/dv/tb/tb.sv. It instantiates the I2C DUT module hw/ip/i2c/rtl/i2c.sv. In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db:

Common DV utility components

The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

Global types & methods

All common types and methods defined at the package level can be found in i2c_env_pkg. Some of them in use are:

parameter uint I2C_FMT_FIFO_DEPTH = 32;
parameter uint I2C_RX_FIFO_DEPTH  = 32;
parameter uint I2C_ADDR_MAP_SIZE  = 128;

TL_agent

I2C instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into I2C device.

I2C agent

[describe or provide link to I2C agent documentation]

UVM RAL Model

The I2C RAL model is created with the hw/dv/tools/gen_ral_pkg.py wrapper script at the start of the simulation automatically and is placed in the build area, along with a corresponding fusesoc core file. The wrapper script invokes the regtool.py script from within to generate the RAL model.

It can be created manually by running make ral command from the dv area.

Stimulus strategy

Test sequences

All test sequences reside in hw/ip/i2c/dv/env/seq_lib. The i2c_base_vseq virtual sequence is extended from cip_base_vseq and serves as a starting point. All test sequences are extended from i2c_base_vseq. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. Some of the most commonly used tasks / functions are as follows:

  • task 1:
  • task 2:

Functional coverage

To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:

  • cg1:
  • cg2:

Self-checking strategy

Scoreboard

The i2c_scoreboard is primarily used for end to end checking. It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:

  • analysis port1:
  • analysis port2:

Assertions

  • TLUL assertions: The tb/i2c_bind.sv binds the tlul_assert assertions to the IP to ensure TileLink interface protocol compliance.
  • Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
  • assertion 1
  • assertion 2

Building and running tests

We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a basic sanity test:

$ cd hw/ip/foo/dv
$ make TEST_NAME=i2c_sanity

Testplan

Milestone Name Description Tests
V1 sanity

Basic I2C sanity test with few bytes transmitted and received asynchronously and in parallel with scoreboard checks (support options for ro, wo, or rw)

Stimulus:

  • Enable I2C host.
  • Clear/Enable interrupt (if nedded).
  • Program OVRD, FDATA register.
  • Randomize I2C timing in TIMING 0-4 registers and other parameters such as TL agent delays
  • Randomize address and data for write and read transfers sent to the device.

Checking:

  • Check the timing behavior of START, STOP, ACK, NACK, and "repeated" START.
  • Read and write transfer matching.
i2c_sanity_ro
i2c_sanity_wo
i2c_sanity_rw
V1 override

Test SCL/SDA override

Stimulus:

  • Program OVRD register.

Checking:

  • Check scl_o, sda_o override by programmed values in the OVRD register.
i2c_override
V1 csr_hw_reset

Verify the reset values as indicated in the RAL specification.

  • Write all CSRs with a random value.
  • Apply reset to the DUT as well as the RAL model.
  • Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
i2c_csr_hw_reset
V1 csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

  • Loop through each CSR to write it with a random value.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
i2c_csr_rw
V1 csr_bit_bash

Verify no aliasing within individual bits of a CSR.

  • Walk a 1 through each CSR by flipping 1 bit at a time.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • This verify that writing a specific bit within the CSR did not affect any of the other bits.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
i2c_csr_bit_bash
V1 csr_aliasing

Verify no aliasing within the CSR address space.

  • Loop through each CSR to write it with a random value
  • Shuffle and read ALL CSRs back.
  • All CSRs except for the one that was written in this iteration should read back the previous value.
  • The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
i2c_csr_aliasing
V2 fmt_watermark

Test fmt_watermark interrupt.

Stimulus:

  • Program random fmt (format) fifo watermark level and keep pushing data out by writing to wdata.

Checking:

  • As the number of pending data entries in the fmt fifo reaches the programmed watermark level, ensure that the fmt watermark interrupt is asserted.
  • Read the fifo status to cross-check, ensure interrupt stays asserted until cleared.
i2c_fmt_watermark
V2 rx_watermark

Test rx_watermark interrupt.

Stimulus:

  • Program random rx watermark level. Keep sending data over rx and read rdata register in parallel with randomized delays large enough to reach a point where the number of pending data items in rx fifo reaches the watermark level.

Checking:

  • When that happens, check that the interrupt is asserted.
i2c_rx_watermark
V2 fmt_reset

Test fmt_fifo reset.

Stimulus:

  • Fill up the fmt fifo with data to be sent out. After a random number (less than filled fifo size) of bytes shows up on fmt, reset the fifo.

Checking:

  • Ensure that the remaining data bytes do not show up after fmt_fifo is reset.
i2c_fmt_reset
V2 rx_reset

Test rx_reset reset.

Stimulus:

  • Fill up the rx fifo by sending data bytes in over rx. After a random number (less than filled fifo size) of bytes sent over rx, reset the fifo.

Checking:

  • Ensure that reads to rdata register yield 0s after rx_fifo is reset.
i2c_rx_reset
V2 fmt_overflow

Test fmt_overflow interrupt.

Stimulus:

  • Keep writing over 32 bytes of data into wdata register.

Checking:

  • Ensure excess data bytes are dropped and overflow interrupt is asserted.
i2c_fmt_overflow
V2 rx_overflow

Test rx_overflow interrupt.

Stimulus:

  • Keep sending over 32 bytes of data over rx.

Checking:

  • Ensure excess data bytes are dropped.
i2c_rx_overflow
V2 fmt_rx_fifo_full

Test fmt_fifo and rx_fifo in full states.

Stimulus:

  • Send over 32 bytes of data but stop when fmt/rx fifo is full.

Checking:

  • Check full states by reading fifo status register.
i2c_fmt_rx_fifo_full
V2 rx_timeout

Test rx_timeout state.

Stimulus:

  • Program timeout_ctrl register to randomize the timeout. Send random number of data over rx and read fewer data than sent and let the DUT sit idle or the programmed timeout duration.

Checking:

  • Ensure timeout interrupt fires.
i2c_rx_timeout
V2 stress

Test multiple interrupts asserted.

Stimulus:

  • Do combinations of multiple of above scenarios to get multiple interrupts asserted at the same time. Scoreboard should be robust enough to deal with all scenarios.

Checking:

  • Ensure all interrupt asserted.
i2c_stress
V2 rw_loopback

Test write data, read loopback, then compare.

Stimulus:

  • Drive i2c host to write data to the device then read loopback.

Checking:

  • After loopback is done, read data should be match with write data.
i2c_rw_loopback
V2 intr_test

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

  • Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
  • Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s).
  • Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
  • Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
  • Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
  • Repeat the above steps a bunch of times.
i2c_intr_test
V2 oob_addr_access

Access out of bounds address and verify correctness of response / behavior

i2c_tl_errors
V2 illegal_access

Drive unsupported requests via TL interface and verify correctness of response / behavior

i2c_tl_errors
V2 outstanding_access

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

i2c_csr_hw_reset
i2c_csr_rw
i2c_csr_aliasing
i2c_same_csr_outstanding
V2 partial_access

Do partial accesses.

i2c_csr_hw_reset
i2c_csr_rw
i2c_csr_aliasing