I2C DV Plan

Goals

  • DV
    • Verify all I2C IP features by running dynamic simulations with a SV/UVM based testbench
    • Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
  • FPV
    • Verify TileLink device protocol compliance with an SVA based testbench

Current status

Design features

For detailed information on I2C design features, please see the I2C design specification.

Testbench architecture

I2C testbench has been constructed based on the CIP testbench architecture.

Block diagram

Block diagram

Top level testbench

Top level testbench is located at hw/ip/i2c/dv/tb/tb.sv. It instantiates the I2C DUT module hw/ip/i2c/rtl/i2c.sv. In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db:

Common DV utility components

The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

Global types & methods

All common types and methods defined at the package level can be found in i2c_env_pkg. Some of them in use are:

parameter uint I2C_FMT_FIFO_DEPTH = 32;
parameter uint I2C_RX_FIFO_DEPTH  = 32;
parameter uint I2C_ADDR_MAP_SIZE  = 128;

TL_agent

I2C instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into I2C device.

I2C agent

I2C agent is configured to work device mode and implemented as reactive slave

UVM RAL Model

The I2C RAL model is created with the ralgen FuseSoC generator script automatically when the simulation is at the build stage.

It can be created manually (separately) by running make in the the hw/ area.

Stimulus strategy

Test sequences

All test sequences reside in hw/ip/i2c/dv/env/seq_lib. The i2c_base_vseq virtual sequence is extended from cip_base_vseq and serves as a starting point. All test sequences are extended from i2c_base_vseq. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. Some of the most commonly used tasks / functions are as follows:

  • task 1:
  • task 2:

Functional coverage

To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:

  • cg1:
  • cg2:

Self-checking strategy

Scoreboard

The i2c_scoreboard is primarily used for end to end checking. It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:

  • analysis port1:
  • analysis port2:

Assertions

  • TLUL assertions: The tb/i2c_bind.sv binds the tlul_assert assertions to the IP to ensure TileLink interface protocol compliance.
  • Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
  • assertion 1
  • assertion 2

Building and running tests

We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here's how to run a basic sanity test:

$ cd hw/ip/foo/dv
$ make TEST_NAME=i2c_sanity

Testplan

Milestone Name Description Tests
V1 sanity <p>Basic I2C sanity test in which random (rd/wr) transactions are sent to the DUT and received asynchronously with scoreboard checks.</p> <p>Stimulus:</p> <ul> <li>Enable I2C host</li> <li>Clear/Enable interrupt (if needed)</li> <li>Program OVRD, FDATA register</li> <li>Randomize I2C timing in TIMING 0-4 registers and other parameters such as TL agent delays</li> <li>Randomize address and data for read/write transactions sent to the device</li> </ul> <p>Checking:</p> <ul> <li>Check the timing behavior of START, STOP, ACK, NACK, and &quot;repeated&quot; START</li> <li>Read and write transfer matching</li> </ul> i2c_sanity<br>
V1 csr_hw_reset <p>Verify the reset values as indicated in the RAL specification.</p> <ul> <li>Write all CSRs with a random value.</li> <li>Apply reset to the DUT as well as the RAL model.</li> <li>Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.</li> <li>It is mandatory to run this test for all available interfaces the CSRs are accessible from.</li> <li>Shuffle the list of CSRs first to remove the effect of ordering.</li> </ul> i2c_csr_hw_reset<br>
V1 csr_rw <p>Verify accessibility of CSRs as indicated in the RAL specification.</p> <ul> <li>Loop through each CSR to write it with a random value.</li> <li>Read the CSR back and check for correctness while adhering to its access policies.</li> <li>It is mandatory to run this test for all available interfaces the CSRs are accessible from.</li> <li>Shuffle the list of CSRs first to remove the effect of ordering.</li> </ul> i2c_csr_rw<br>
V1 csr_bit_bash <p>Verify no aliasing within individual bits of a CSR.</p> <ul> <li>Walk a 1 through each CSR by flipping 1 bit at a time.</li> <li>Read the CSR back and check for correctness while adhering to its access policies.</li> <li>This verify that writing a specific bit within the CSR did not affect any of the other bits.</li> <li>It is mandatory to run this test for all available interfaces the CSRs are accessible from.</li> <li>Shuffle the list of CSRs first to remove the effect of ordering.</li> </ul> i2c_csr_bit_bash<br>
V1 csr_aliasing <p>Verify no aliasing within the CSR address space.</p> <ul> <li>Loop through each CSR to write it with a random value</li> <li>Shuffle and read ALL CSRs back.</li> <li>All CSRs except for the one that was written in this iteration should read back the previous value.</li> <li>The CSR that was written in this iteration is checked for correctness while adhering to its access policies.</li> <li>It is mandatory to run this test for all available interfaces the CSRs are accessible from.</li> <li>Shuffle the list of CSRs first to remove the effect of ordering.</li> </ul> i2c_csr_aliasing<br>
V1 csr_mem_rw_with_rand_reset<p>Verify random reset during CSR/memory access.</p> <ul> <li>Run csr_rw sequence to randomly access CSRs</li> <li>If memory exists, run mem_partial_access in parallel with csr_rw</li> <li>Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value</li> <li>It is mandatory to run this test for all available interfaces the CSRs are accessible from.</li> </ul> i2c_csr_mem_rw_with_rand_reset<br>
V2 error <p>Test if the host receives interference and unstable scl and sda.</p> <p>Stimulus:</p> <ul> <li>Within the clock pulse of the host scl, the device randomly asserts/deasserts its scl and sda</li> </ul> <p>Checking:</p> <ul> <li>Ensure all intr_scl_interference, intr_sda_interference, and intr_sda_unstable interrupts are asserted</li> <li>Ensure all intr_scl_interference, intr_sda_interference, and intr_sda_unstable interrupts stay asserted until cleared</li> </ul> i2c_error<br>
V2 stress_all_with_reset <p>Pull reset at random times, ensure DUT are reset and recovered/ correctly and there is no residual data left in the registers.</p> <p>Stimulus:</p> <ul> <li>Randomly reset DUT</li> <li>Restart send/receive transaction</li> </ul> <p>Checking:</p> <ul> <li>Ensure registers are properly reset</li> </ul> i2c_stress_all_with_rand_reset<br>
V2 perf <p>Send/receive transactions at max bandwidth.</p> <p>Stimulus:</p> <ul> <li>Reduce access latency for fmt_fifo and rx_fifo</li> <li>Issue long read/write back-to-back transactions</li> <li>Read rx_fifo as soon as read data valid</li> </ul> <p>Checking:</p> <ul> <li>Ensure transactions are transceivered correctly</li> </ul> i2c_perf<br>
V2 stress <p>Test multiple interrupts asserted.</p> <p>Stimulus:</p> <ul> <li>Do combinations of multiple of above scenarios to get multiple interrupts asserted at the same time</li> <li>Scoreboard should be robust enough to deal with all scenarios</li> </ul> <p>Checking:</p> <ul> <li>Ensure multiple interrupts are asserted</li> </ul> i2c_stress<br>
V2 override <p>Test SCL/SDA override.</p> <p>Stimulus:</p> <ul> <li>Program OVRD register</li> </ul> <p>Checking:</p> <ul> <li>Ensure scl_o, sda_o are overridden</li> </ul> i2c_override<br>
V2 fifo_watermark <p>Test the watermark interrupt of fmt_fifo and rx_fifo.</p> <p>Stimulus:</p> <ul> <li>Program random fmt_fifo and rx_fifo watermark level</li> <li>Write data quickly to fmt_fifo and rx_fifo for triggering watermark interrupts</li> </ul> <p>Checking:</p> <ul> <li>Ensure the fmt_fifo and rx_fifo watermark interrupts are asserted</li> <li>Ensure the fmt_fifo and rx_fifo watermark interrupts stay asserted until cleared</li> <li>Ensure receving correct number of fmt_fifo and rx_fifo watermark interrupts</li> </ul> i2c_fifo_watermark<br>
V2 fmt_reset <p>Test fmt_fifo reset.</p> <p>Stimulus:</p> <ul> <li>Fill up the fmt fifo with data to be sent out</li> <li>Reset the fmt_fifo randomly after a number of bytes shows up on fmt_fifo</li> </ul> <p>Checking:</p> <ul> <li>Ensure the remaining entries are not show up after fmt_fifo is reset</li> </ul>
V2 rx_reset <p>Test rx_reset reset.</p> <p>Stimulus:</p> <ul> <li>Fill up the rx fifo by sending data bytes over rx</li> <li>Reset the rx_fifo randomly after a random number of bytes shows up on rx_fifo,</li> </ul> <p>Checking:</p> <ul> <li>Ensure that reads to rdata register yield 0s after rx_fifo is reset</li> </ul>
V2 fmt_overflow <p>Test fmt_overflow interrupt.</p> <p>Stimulus:</p> <ul> <li>Keep sending a number of format byte higher than fmt_fifo depth, delay the target response</li> </ul> <p>Checking:</p> <ul> <li>Ensure excess format bytes are dropped</li> <li>Ensure intr_fmt_overflow interrupt is asserted</li> </ul>
V2 rx_overflow <p>Test rx_overflow interrupt.</p> <p>Stimulus:</p> <ul> <li>Request a number of bytes higher than rx_fifo depth, delay rx_fifo reading</li> </ul> <p>Checking:</p> <ul> <li>Ensure excess data bytes are dropped</li> <li>Ensure intr_rx_overflow interrupt is asserted</li> </ul>
V2 fmt_rx_fifo_full <p>Test fmt_fifo and rx_fifo in full states.</p> <p>Stimulus:</p> <ul> <li>Send enough read requests, not read data out, then stop until both fmt and rx fifo is full</li> </ul> <p>Checking:</p> <ul> <li>Check fifo full states by reading status register</li> </ul>
V2 rx_timeout <p>Test rx_timeout state.</p> <p>Stimulus:</p> <ul> <li>Program timeout enable bit into timeout_ctrl register</li> <li>Program timeout values (higher than host scl clock pulse) into timeout_ctrl register</li> <li>Configure agent to pull down target(device) scl after the bit 9 (acknowledge bit) is transmitted</li> </ul> <p>Checking:</p> <ul> <li>Ensure intr_stretch_timeout interrupt is asserted</li> </ul>
V2 rx_oversample <p>Test rc oversampling.</p> <p>Stimulus:</p> <ul> <li>Use input clock to sample the target sda (sample with baud rate equal to 1)</li> <li>Drive scl_rx using input clock</li> </ul> <p>Checking:</p> <ul> <li>Read rx data oversampled value and ensure it is same as driven value</li> </ul>
V2 rw_loopback <p>Test write data, read loopback, then compare.</p> <p>Stimulus:</p> <ul> <li>Drive i2c host to write data to the device then read loopback</li> </ul> <p>Checking:</p> <ul> <li>Ensure read data is matched with write data</li> </ul>
V2 intr_test <p>Verify common intr_test CSRs that allows SW to mock-inject interrupts.</p> <ul> <li>Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).</li> <li>Randomly &quot;turn on&quot; interrupts by writing random value(s) to intr_test CSR(s).</li> <li>Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.</li> <li>Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.</li> <li>Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).</li> <li>Repeat the above steps a bunch of times.</li> </ul> i2c_intr_test<br>
V2 oob_addr_access <p>Access out of bounds address and verify correctness of response / behavior</p>i2c_tl_errors<br>
V2 illegal_access <p>Drive unsupported requests via TL interface and verify correctness of response / behavior</p> i2c_tl_errors<br>
V2 outstanding_access <p>Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.</p> i2c_csr_hw_reset<br> i2c_csr_rw<br> i2c_csr_aliasing<br> i2c_same_csr_outstanding<br>
V2 partial_access <p>Do partial accesses.</p> i2c_csr_hw_reset<br> i2c_csr_rw<br> i2c_csr_aliasing<br>