I2C DV Plan
- Verify all I2C IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
- Verify TileLink device protocol compliance with an SVA based testbench
For detailed information on I2C design features, please see the I2C design specification.
I2C testbench has been constructed based on the CIP testbench architecture.
Top level testbench
Top level testbench is located at
hw/ip/i2c/dv/tb/tb.sv. It instantiates the I2C DUT module
In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into
Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
Global types & methods
All common types and methods defined at the package level can be found in
i2c_env_pkg. Some of them in use are:
parameter uint I2C_FMT_FIFO_DEPTH = 32; parameter uint I2C_RX_FIFO_DEPTH = 32; parameter uint I2C_ADDR_MAP_SIZE = 128;
I2C instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into I2C device.
[describe or provide link to I2C agent documentation]
UVM RAL Model
The I2C RAL model is created with the
hw/dv/tools/gen_ral_pkg.py wrapper script at the start of the simulation automatically and is placed in the build area, along with a corresponding
fusesoc core file.
The wrapper script invokes the regtool.py script from within to generate the RAL model.
It can be created manually by running
make ral command from the
All test sequences reside in
i2c_base_vseq virtual sequence is extended from
cip_base_vseq and serves as a starting point.
All test sequences are extended from
It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:
- task 1:
- task 2:
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:
i2c_scoreboard is primarily used for end to end checking.
It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:
- analysis port1:
- analysis port2:
- TLUL assertions: The
tlul_assertassertions to the IP to ensure TileLink interface protocol compliance.
- Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
- assertion 1
- assertion 2
Building and running tests
We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a basic sanity test:
$ cd hw/ip/foo/dv $ make TEST_NAME=i2c_sanity
Basic I2C sanity test with few bytes transmitted and received asynchronously and in parallel with scoreboard checks (support options for ro, wo, or rw)
Test SCL/SDA override
Verify the reset values as indicated in the RAL specification.
Verify accessibility of CSRs as indicated in the RAL specification.
Verify no aliasing within individual bits of a CSR.
Verify no aliasing within the CSR address space.
Test fmt_watermark interrupt.
Test rx_watermark interrupt.
Test fmt_fifo reset.
Test rx_reset reset.
Test fmt_overflow interrupt.
Test rx_overflow interrupt.
Test fmt_fifo and rx_fifo in full states.
Test rx_timeout state.
Test multiple interrupts asserted.
Test write data, read loopback, then compare.
Verify common intr_test CSRs that allows SW to mock-inject interrupts.
Access out of bounds address and verify correctness of response / behavior
Drive unsupported requests via TL interface and verify correctness of response / behavior
Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.
Do partial accesses.