I2C DV Plan

Goals

  • DV
    • Verify all I2C IP features by running dynamic simulations with a SV/UVM based testbench
    • Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
  • FPV
    • Verify TileLink device protocol compliance with an SVA based testbench

Current status

Design features

For detailed information on I2C design features, please see the I2C design specification.

Testbench architecture

I2C testbench has been constructed based on the CIP testbench architecture.

Block diagram

Block diagram

Top level testbench

Top level testbench is located at hw/ip/i2c/dv/tb/tb.sv. It instantiates the I2C DUT module hw/ip/i2c/rtl/i2c.sv. In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db:

Common DV utility components

The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

Global types & methods

All common types and methods defined at the package level can be found in i2c_env_pkg. Some of them in use are:

parameter uint I2C_FMT_FIFO_DEPTH = 32;
parameter uint I2C_RX_FIFO_DEPTH  = 32;

TL_agent

I2C instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into I2C device.

I2C agent

I2C agent is configured to work device mode and implemented as reactive agent

UVM RAL Model

The I2C RAL model is created with the ralgen FuseSoC generator script automatically when the simulation is at the build stage.

It can be created manually by invoking regtool:

Stimulus strategy

Test sequences

All test sequences reside in hw/ip/i2c/dv/env/seq_lib. The i2c_base_vseq virtual sequence is extended from cip_base_vseq and serves as a starting point. All test sequences are extended from i2c_base_vseq. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. Some of the most commonly used tasks / functions are as follows:

  • task 1:
  • task 2:

Functional coverage

To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:

  • cg1:
  • cg2:

Self-checking strategy

Scoreboard

The i2c_scoreboard is primarily used for end to end checking. It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:

  • analysis port1:
  • analysis port2:

Assertions

  • TLUL assertions: The tb/i2c_bind.sv binds the tlul_assert assertions to the IP to ensure TileLink interface protocol compliance.
  • Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
  • assertion 1
  • assertion 2

Building and running tests

We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a basic sanity test:

$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/i2c/dv/i2c_sim_cfg.hjson -i i2c_sanity

Testplan

Milestone Name Description Tests
V1 sanity

Basic I2C sanity test in which random (rd/wr) transactions are sent to the DUT and received asynchronously with scoreboard checks.

Stimulus:

  • Enable I2C host
  • Clear/Enable interrupt (if needed)
  • Program OVRD, FDATA register
  • Randomize I2C timing in TIMING 0-4 registers and other parameters such as TL agent delays
  • Randomize address and data for read/write transactions sent to the device

Checking:

  • Check the timing behavior of START, STOP, ACK, NACK, and "repeated" START
  • Read and write transfer matching
i2c_sanity
V1 csr_hw_reset

Verify the reset values as indicated in the RAL specification.

  • Write all CSRs with a random value.
  • Apply reset to the DUT as well as the RAL model.
  • Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
i2c_csr_hw_reset
V1 csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

  • Loop through each CSR to write it with a random value.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
i2c_csr_rw
V1 csr_bit_bash

Verify no aliasing within individual bits of a CSR.

  • Walk a 1 through each CSR by flipping 1 bit at a time.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • This verify that writing a specific bit within the CSR did not affect any of the other bits.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
i2c_csr_bit_bash
V1 csr_aliasing

Verify no aliasing within the CSR address space.

  • Loop through each CSR to write it with a random value
  • Shuffle and read ALL CSRs back.
  • All CSRs except for the one that was written in this iteration should read back the previous value.
  • The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
i2c_csr_aliasing
V1 csr_mem_rw_with_rand_reset

Verify random reset during CSR/memory access.

  • Run csr_rw sequence to randomly access CSRs
  • If memory exists, run mem_partial_access in parallel with csr_rw
  • Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
i2c_csr_mem_rw_with_rand_reset
V2 error_intr

Test error interrupts are asserted by the host due to interference and unstable signals on bus.

Stimulus:

  • In host transmit mode, device (target/host) forces sda or scl signal low within the clock pulse of host scl that asserts sda_interference or scl_interference interrupts
  • In host receiving mode (data or ack bits), SDA signal is changed with the clock pulse of host scl that asserts intr_sda_unstable interrupts
  • When error interrupt assertions are detected, dut, agent, and scoreboard will be reset on-the-fly then new transaction can be continue programming Checking:
  • Ensure all intr_scl_interference, intr_sda_interference, and intr_sda_unstable interrupts are asserted
  • Ensure all intr_scl_interference, intr_sda_interference, and intr_sda_unstable interrupts stay asserted until cleared
  • Ensure IP operation get back normal after on-the-fly reset finished
i2c_error_intr
V2 stress_all_with_reset

Pull reset at random times, ensure DUT are reset and recovered/ correctly and there is no residual data left in the registers.

Stimulus:

  • Randomly reset DUT
  • Restart send/receive transaction

Checking:

  • Ensure registers are properly reset
i2c_stress_all_with_rand_reset
V2 perf

Send/receive transactions at max bandwidth.

Stimulus:

  • Reduce access latency for fmt_fifo and rx_fifo
  • Issue long read/write back-to-back transactions
  • Read rx_fifo as soon as read data valid
  • Clear interrupt quickly Checking:
  • Ensure transactions are transceivered correctly
i2c_perf
V2 stress

Test multiple interrupts asserted.

Stimulus:

  • Do combinations of multiple of above scenarios to get multiple interrupts asserted at the same time
  • Scoreboard should be robust enough to deal with all scenarios

Checking:

  • Ensure multiple interrupts are asserted
i2c_stress
V2 override

Test SCL/SDA override.

Stimulus:

  • Program OVRD register

Checking:

  • Ensure scl_o, sda_o are overridden
i2c_override
V2 fifo_watermark

Test the watermark interrupt of fmt_fifo and rx_fifo.

Stimulus:

  • Program random fmt_fifo and rx_fifo watermark level
  • Write data quickly to fmt_fifo and rx_fifo for triggering watermark interrupts

Checking:

  • Ensure the fmt_fifo and rx_fifo watermark interrupts are asserted
  • Ensure the fmt_fifo and rx_fifo watermark interrupts stay asserted until cleared
  • Ensure receving correct number of fmt_fifo and rx_fifo watermark interrupts
i2c_fifo_watermark
V2 fifo_overflow

Test the overflow interrupt of fmt_fifo and rx_fifo.

Stimulus:

  • Keep sending a number of format byte higher than fmt_fifo and rx_fifo depth

Checking:

  • Ensure excess format bytes are dropped
  • Ensure fmt_overflow and rx_overflow interrupt are asserted
  • Ensure receving correct number of fmt_fifo and rx_fifo watermark interrupts
i2c_fifo_overflow
V2 fmt_reset

Test fmt_fifo reset.

Stimulus:

  • Fill up the fmt fifo with data to be sent out
  • Reset the fmt_fifo randomly after a number of bytes shows up on fmt_fifo

Checking:

  • Ensure the remaining entries are not show up after fmt_fifo is reset
V2 rx_reset

Test rx_fifo reset.

Stimulus:

  • Fill up the rx fifo by sending data bytes over rx
  • Reset the rx_fifo randomly after a random number of bytes shows up on rx_fifo

Checking:

  • Ensure that reads to rdata register yield 0s after rx_fifo is reset
V2 fifo_full

Test fmt_fifo and rx_fifo in full states.

Stimulus:

  • Send enough read and write requests to fmt_fifo
  • Hold reading data from rx_fifo until rx fifo is full

Checking:

  • Check fifo full states by reading status register
i2c_fifo_full
V2 stretch_timeout,

Test host clock stretching.

Stimulus:

  • Set timeout enable bit into timeout_ctrl register
  • Program timeout values (higher than host scl clock pulse) into timeout_ctrl register
  • Configure agent to pull down target (device) scl after the bit 9 (ACK) is transmitted

Checking:

  • Ensure stretch_timeout interrupt is asserted
  • Ensure receving the correct number of stretch_timeout interrupt
i2c_stretch_timeout
V2 rx_oversample

Test rc oversampling.

Stimulus:

  • Use input clock to sample the target sda (sample with baud rate equal to 1)
  • Drive scl_rx using input clock

Checking:

  • Read rx data oversampled value and ensure it is same as driven value
V2 rw_loopback

Test write data, read loopback, then compare.

Stimulus:

  • Drive i2c host to write data to the device then read loopback

Checking:

  • Ensure read data is matched with write data
V2 intr_test

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

  • Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
  • Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s).
  • Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
  • Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
  • Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
  • Repeat the above steps a bunch of times.
i2c_intr_test
V2 tl_d_oob_addr_access

Access out of bounds address and verify correctness of response / behavior

i2c_tl_errors
V2 tl_d_illegal_access

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested

  • TL-UL protocol error cases
    • Unsupported opcode. e.g a_opcode isn't Get, PutPartialData or PutFullData
    • Mask isn't all active if opcode = PutFullData
    • Mask isn't in enabled lanes, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
    • Mask doesn't align with address, e.g. a_address = 0x01, a_mask = 'b0001
    • Address and size aren't aligned, e.g. a_address = 0x01, a_size != 0
    • Size is over 2.
  • OpenTitan defined error cases
    • Access unmapped address, return d_error = 1 when devmode_i == 1
    • Write CSR with unaligned address, e.g. a_address[1:0] != 0
    • Write CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
    • Write a memory without enabling all lanes (a_mask = '1) if memory doesn't support byte enabled write
    • Read a WO (write-only) memory
i2c_tl_errors
V2 tl_d_outstanding_access

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

i2c_csr_hw_reset
i2c_csr_rw
i2c_csr_aliasing
i2c_same_csr_outstanding
V2 tl_d_partial_access

Access CSR with one or more bytes of data For read, expect to return all word value of the CSR For write, enabling bytes should cover all CSR valid fields

i2c_csr_hw_reset
i2c_csr_rw
i2c_csr_aliasing
i2c_same_csr_outstanding