KEYMGR DV document
Goals
- DV
- Verify all KEYMGR IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
- FPV
- Verify TileLink device protocol compliance with an SVA based testbench
Current status
Design features
For detailed information on KEYMGR design features, please see the KEYMGR HWIP technical specification.
Testbench architecture
KEYMGR testbench has been constructed based on the CIP testbench architecture.
Block diagram
Top level testbench
Top level testbench is located at hw/ip/keymgr/dv/tb/tb.sv
. It instantiates the KEYMGR DUT module hw/ip/keymgr/rtl/keymgr.sv
.
In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db
:
- Clock and reset interface
- TileLink host interface
- KEYMGR IOs (
keymgr_if
) - Interrupts (
pins_if
) - Alerts (
alert_esc_if
) - Devmode (
pins_if
)
Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
Compile-time configurations
[list compile time configurations, if any and what are they used for]
Global types & methods
All common types and methods defined at the package level can be found in
keymgr_env_pkg
. Some of them in use are:
[list a few parameters, types & methods; no need to mention all]
TL_agent
KEYMGR testbench instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into KEYMGR device.
EDN Agent
The KEYMGR testbench instantiates a push_pull_agent
in Pull
mode as the agent modelling the EDN interface (this is already handled in the CIP base classes).
This agent will return random data as entropy when the KEYMGR sends a request.
KMAC_APP Agent
The KEYMGR testbench instantiates a kmac_app_agent
to request a KMAC hash operation on the secret data.
UVM RAL Model
The KEYMGR RAL model is created with the ralgen
FuseSoC generator script automatically when the simulation is at the build stage.
It can be created manually by invoking regtool
:
Reference models
[Describe reference models in use if applicable, example: SHA256/HMAC]
Stimulus strategy
Test sequences
All test sequences reside in hw/ip/keymgr/dv/env/seq_lib
.
The keymgr_base_vseq
virtual sequence is extended from cip_base_vseq
and serves as a starting point.
All test sequences are extended from keymgr_base_vseq
.
It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:
- keymgr_operations: This task issues operations as set in the inputs, such as advance operation, generating sw/hw output.
- wait_op_done: This task polls the
op_status
until it returns success / fail status, as well as checking if the status is expected. - keymgr_rd_clr: This reads
sw_share_output
to allow scoreboard to check the values.
Functional coverage
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The covergroups defined in testplan have been developed to prove that the test intent has been adequately met.
Self-checking strategy
Scoreboard
The keymgr_scoreboard
is primarily used for end to end checking.
It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:
- tl_a_chan_fifo: An analysis FIFO to hold transactions from TL address channel.
- tl_d_chan_fifo: An analysis FIFO to hold transactions from TL data channel.
- req_fifo: An analysis FIFO to hold request data sent to KMAC.
- rsp_fifo: An analysis FIFO to hold response digests received from KMAC.
- edn_fifo: An analysis FIFO to hold transactions coming from the EDN interface.
Assertions
- TLUL assertions: The
tb/keymgr_bind.sv
binds thetlul_assert
assertions to the IP to ensure TileLink interface protocol compliance. - Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
- Check(Kmac|Aes|Otbn)Key: Check keys on the 3 sideload interfaces.
- CheckEdn1stReq / CheckEdn2ndReq: Check KEYMGR sends 2 EDN request periodically based on the CSR
reseed_interval
.
Building and running tests
We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:
$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/keymgr/dv/keymgr_sim_cfg.hjson -i keymgr_smoke
Testplan
Testpoints
Milestone | Name | Tests | Description |
---|---|---|---|
V1 | smoke | keymgr_smoke | Smoke test accessing a major datapath within the keymgr. Test operations (advance, gen-id and gen-sw-out) in every state Stimulus:
Checks:
|
V1 | random | keymgr_random | Extend from smoke to randomize all SW input data
Most of other sequences are derived from this to have similar init and sequence. Stimulus and checks are the same as smoke. |
V1 | csr_hw_reset | keymgr_csr_hw_reset | Verify the reset values as indicated in the RAL specification.
|
V1 | csr_rw | keymgr_csr_rw | Verify accessibility of CSRs as indicated in the RAL specification.
|
V1 | csr_bit_bash | keymgr_csr_bit_bash | Verify no aliasing within individual bits of a CSR.
|
V1 | csr_aliasing | keymgr_csr_aliasing | Verify no aliasing within the CSR address space.
|
V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | Verify random reset during CSR/memory access.
|
V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw keymgr_csr_aliasing | Verify regwen CSR and its corresponding lockable CSRs.
Note:
This is only applicable if the block contains regwen and locakable CSRs. |
V2 | cfgen_during_op | keymgr_cfg_regwen |
Stimulus and checks:
Test command and reg access gated by |
V2 | sideload | keymgr_sideload keymgr_sideload_kmac keymgr_sideload_aes keymgr_sideload_otbn | Keymgr contains HW sideload interfaces to output keys for KMAC, AES, OTBN. Stimulus:
Checks: Verify the sideload data and status for correctness. |
V2 | direct_to_disabled_state | keymgr_direct_to_disabled | Stimulus and checks:
Directly go to |
V2 | lc_disable | keymgr_lc_disable | Life cycle can disable keymgr and let keymgr wipe secret immediately. Stimulus: Test life cycle disables keymgr in any state. Checks:
|
V2 | kmac_error_response | keymgr_kmac_rsp_err | Verify Stimulus: Drive error from KMAC interface when VALID is high. Checks: Same as above entry - "invalid_cmd". |
V2 | invalid_kmac_input | keymgr_sw_invalid_input | Verify Stimulus: Randomize KEY_VERSION and MAX_*_VER registers. Checks: when KEY_VERSION > MAX_*_VER
|
V2 | invalid_kmac_data | keymgr_hwsw_invalid_input | Verify Stimulus: Use all 0s or 1s as KMAC input digest data Checks:
|
V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | Verify Stimulus: Create these 2 direct tests:
Checks:
|
V2 | stress_all | keymgr_stress_all |
|
V2 | intr_test | keymgr_intr_test | Verify common intr_test CSRs that allows SW to mock-inject interrupts.
|
V2 | alert_test | keymgr_alert_test | Verify common
|
V2 | tl_d_oob_addr_access | keymgr_tl_errors | Access out of bounds address and verify correctness of response / behavior |
V2 | tl_d_illegal_access | keymgr_tl_errors | Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the [TLUL spec]({{< relref "hw/ip/tlul/doc/_index.md#explicit-error-cases" >}})
|
V2 | tl_d_outstanding_access | keymgr_csr_hw_reset keymgr_csr_rw keymgr_csr_aliasing keymgr_same_csr_outstanding | Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address. |
V2 | tl_d_partial_access | keymgr_csr_hw_reset keymgr_csr_rw keymgr_csr_aliasing keymgr_same_csr_outstanding | Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields. |
V2S | sec_cm_additional_check | keymgr_sec_cm | Verify the outcome of injecting faults to security countermeasures. Stimulus:
As mentioned in Checks:
|
V2S | tl_intg_err | keymgr_tl_intg_err keymgr_sec_cm | Verify that the data integrity check violation generates an alert.
|
V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | Verify shadowed registers' update error.
|
V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | Verify reading a shadowed register will clear its staged value.
|
V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | Verify shadowed registers' storage error.
|
V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | Verify toggle shadowed_rst_n pin can trigger storage error.
|
V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | Run shadow_reg_update_error sequence in parallel with csr_rw sequence.
|
V2S | prim_count_check | keymgr_sec_cm | Verify that violating prim_count counter properties generate a fatal alert. Stimulus:
Checks:
|
V2S | prim_fsm_check | keymgr_sec_cm | Verify that entering to an undefined state generates a fatal alert. Stimulus:
Checks:
|
V2S | sec_cm_bus_integrity | Verify the countermeasure(s) BUS.INTEGRITY. | |
V2S | sec_cm_config_shadow | Verify the countermeasure(s) CONFIG.SHADOW. | |
V2S | sec_cm_op_config_regwen | Verify the countermeasure(s) OP.CONFIG.REGWEN. | |
V2S | sec_cm_reseed_config_regwen | Verify the countermeasure(s) RESEED.CONFIG.REGWEN. | |
V2S | sec_cm_sw_binding_config_regwen | Verify the countermeasure(s) SW_BINDING.CONFIG.REGWEN. | |
V2S | sec_cm_max_key_ver_config_regwen | Verify the countermeasure(s) MAX_KEY_VER.CONFIG.REGWEN. | |
V2S | sec_cm_lc_ctrl_intersig_mubi | Verify the countermeasure(s) LC_CTRL.INTERSIG.MUBI. | |
V2S | sec_cm_constants_consistency | Verify the countermeasure(s) CONSTANTS.CONSISTENCY. | |
V2S | sec_cm_intersig_consistency | Verify the countermeasure(s) INTERSIG.CONSISTENCY. | |
V2S | sec_cm_hw_key_sw_noaccess | Verify the countermeasure(s) HW.KEY.SW_NOACCESS. | |
V2S | sec_cm_output_keys_ctrl_redun | Verify the countermeasure(s) OUTPUT_KEYS.CTRL.REDUN. | |
V2S | sec_cm_ctrl_fsm_sparse | Verify the countermeasure(s) CTRL.FSM.SPARSE. | |
V2S | sec_cm_data_fsm_sparse | Verify the countermeasure(s) DATA.FSM.SPARSE. | |
V2S | sec_cm_ctrl_fsm_local_esc | Verify the countermeasure(s) CTRL.FSM.LOCAL_ESC. | |
V2S | sec_cm_ctrl_fsm_consistency | Verify the countermeasure(s) CTRL.FSM.CONSISTENCY. | |
V2S | sec_cm_ctrl_fsm_global_esc | Verify the countermeasure(s) CTRL.FSM.GLOBAL_ESC. | |
V2S | sec_cm_ctrl_ctr_redun | Verify the countermeasure(s) CTRL.CTR.REDUN. | |
V2S | sec_cm_kmac_if_fsm_sparse | Verify the countermeasure(s) KMAC_IF.FSM.SPARSE. | |
V2S | sec_cm_kmac_if_ctr_redun | Verify the countermeasure(s) KMAC_IF.CTR.REDUN. | |
V2S | sec_cm_kmac_if_cmd_ctrl_consistency | Verify the countermeasure(s) KMAC_IF_CMD.CTRL.CONSISTENCY. | |
V2S | sec_cm_kmac_if_done_ctrl_consistency | Verify the countermeasure(s) KMAC_IF_DONE.CTRL.CONSISTENCY. | |
V2S | sec_cm_reseed_ctr_redun | Verify the countermeasure(s) RESEED.CTR.REDUN. | |
V2S | sec_cm_side_load_sel_ctrl_consistency | Verify the countermeasure(s) SIDE_LOAD_SEL.CTRL.CONSISTENCY. | |
V2S | sec_cm_ctrl_key_integrity | Verify the countermeasure(s) CTRL.KEY.INTEGRITY. | |
V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers. |
Covergroups
Name | Description |
---|---|
control_w_regwen_cg |
|
err_code_cg |
|
fault_status_cg |
|
hw_invalid_input_cg | Cover all HW invalid inputs, including
|
key_version_compare_cg |
|
keymgr_sw_input_cg |
|
lc_disable_cg |
|
regwen_val_when_new_value_written_cg | Cover each lockable reg field with these 2 cases:
This is only applicable if the block contains regwen and locakable CSRs. |
reseed_interval_cg |
|
sideload_clear_cg |
|
state_and_op_cg |
|
sync_async_fault_cross_cg |
|
tl_errors_cg | Cover the following error cases on TL-UL bus:
|
tl_intg_err_cg | Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check. Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied. |