Smoke test accessing a major datapath within the keymgr. Test operations (advance, gen-id and gen-sw-out) in every state

Stimulus:

• Go through state from StReset to StDisabled.
• Issue gen-id, gen-sw-output operation in each state, including invalid operations in states other than normal operating states (StCreatorRootKey, StOwnerIntKey and StOwnerRootKey).
• Randomize CDI_SEL and DEST_SEL.
• Use default/fixed values for HW/SW inputs.

Checks:

• Check STATUS reg for each operation.
• Check interrupts op_done is triggered when operation is done.
• Check err and alert recov_operation_err are triggered after invalid operation.
• Check KMAC key, KMAC data and output SW data for correctness.
• For invalid operations, check KMAC key, KMAC data and output SW data don't match to any of saved meaningful data, which are collected from valid operations. This checking method is also applied to other error cases.

Extend from smoke to randomize all SW input data

• Fully randomize SW inputs: rom_ext_desc_, software_binding_, salt_, max__key_ver, *_key_ver_regwen.
• Randomize key_version any value less than max_*_key_ver, to avoid triggerring invalid_kmac_input error.
• Fully randomize HW inputs from flash, otp and life cycle.
• Randomize *sw_binding_regwen. Ensure this gates the *_sw_binding and it will be cleared after a successful advance operation.

Most of other sequences are derived from this to have similar init and sequence.

Stimulus and checks are the same as smoke.

Verify the reset values as indicated in the RAL specification.

• Write all CSRs with a random value.
• Apply reset to the DUT as well as the RAL model.
• Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify accessibility of CSRs as indicated in the RAL specification.

• Loop through each CSR to write it with a random value.
• Read the CSR back and check for correctness while adhering to its access policies.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify no aliasing within individual bits of a CSR.

• Walk a 1 through each CSR by flipping 1 bit at a time.
• Read the CSR back and check for correctness while adhering to its access policies.
• This verify that writing a specific bit within the CSR did not affect any of the other bits.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify no aliasing within the CSR address space.

• Loop through each CSR to write it with a random value
• Shuffle and read ALL CSRs back.
• All CSRs except for the one that was written in this iteration should read back the previous value.
• The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify random reset during CSR/memory access.

• Run csr_rw sequence to randomly access CSRs
• If memory exists, run mem_partial_access in parallel with csr_rw
• Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.

Verify shadowed registers' update error.

• Randomly pick a shadowed register in the DUT.
• Write it twice with different values.
• Verify that the update error alert is triggered and the register value remains unchanged.
• Verify the update_error status register field is set to 1.
• Repeat the above steps a bunch of times.

Verify reading a shadowed register will clear its staged value.

• Randomly pick a shadowed register in the DUT.
• Write it once and read it back to clear the staged value.
• Then write it twice with the same new value (but different from the previous step).
• Read it back to verify the new value and ensure that the update error alert did not trigger.
• Verify the update_error status register field remains the same value.
• Repeat the above steps a bunch of times.

Verify shadowed registers' storage error.

• Randomly pick a shadowed register in the DUT.
• Backdoor write to shadowed or committed flops to create a storage fatal alert.
• Check if fatal alert continuously fires until reset.
• Verify that all other frontdoor write attempts are blocked during the storage error.
• Verify that storage_error status register field is set to 1.
• Reset the DUT.
• Read all CSRs to ensure the DUT is properly reset.
• Repeat the above steps a bunch of times.

Verify toggle shadowed_rst_n pin can trigger storage error.

• Randomly drive shadowed_rst_n pin to low or rst_n pin to low.
• check if any registers have been written before the reset. If so check if storage error fatal alert is triggered.
• Check status register.
• Drive shadowed_rst_n pin or rst_n pin back to high.
• If fatal alert is triggered, reset the DUT.
• Read all CSRs to ensure the DUT is properly reset.
• Repeat the above steps a bunch of times.

Run shadow_reg_update_error sequence in parallel with csr_rw sequence.

• Randomly select one of the above sequences.
• Apply csr_rw sequence in parallel but disable the csr_access_abort to ensure all shadowed registers' write/read to be executed without aborting.
• Repeat the above steps a bunch of times.

cfg_regwen is RO reg and it gates bunch of write access of other registers, which is not tested in common CSR tests.

Stimulus and checks: Test command and reg access gated by cfg_regwen is ignored during operation.

Keymgr contains HW sideload interfaces to output keys for KMAC, AES, OTBN.

Stimulus:

• Generate a keymgr output to HW sideload interface, exercising all the sideload interfaces.
• Randomly program any value to Sideload_clear after any operation.

Checks: Verify the sideload data and status for correctness.

Stimulus and checks: Directly go to StDisabled from any state and check StDisabled is entered correctly.

Life cycle can disable keymgr and let keymgr wipe secret immediately.

Stimulus: Test life cycle disables keymgr in any state.

Checks:

• If keymgr is not initialized, check it can't be initialized until life cycle enables keymgr.
• If keymgr is in a valid state after StReset, key output to KMAC is wiped immediately and SW output will be invalid after OP is done.
• If keymgr in disabled state, check the behavior is consistent with normal behavior.

Verify keymgr behavior on error response received from KMAC after sending data to it.

Stimulus: Drive error from KMAC interface when VALID is high.

Checks: Same as above entry - "invalid_cmd".

Verify keymgr behavior with invalid key version.

Stimulus: Randomize KEY_VERSION and MAX_*_VER registers.

Checks: when KEY_VERSION > MAX_*_VER

• Check interrupts err is triggered.
• Check alert recov_operation_err is triggered and err_code is INVALID_KMAC_INPUT.
• Check KMAC output key is corrupted and working state remains the same.

Verify keymgr behavior with invalid data patterns.

Stimulus: Use all 0s or 1s as KMAC input digest data

Checks:

• Check interrupts err is triggered.
• Check alert recov_operation_err is triggered and err_code is INVALID_KMAC_DATA.
• Check SW output isn't updated and working state remains the same.

Verify keymgr behavior with invalid data patterns.

Stimulus: Create these 2 direct tests:

• Sync (transactional) fault occurs followed by async (non-transactional) fault.
• Async (non-transactional) fault occurs followed by sync (transactional) fault.

Checks:

• Check interrupts err is triggered.
• Check alert fatal_fault_err is triggered.
• Check fault_status is updated correctly.

• Combine above sequences in one test to run sequentially, except csr sequence and keymgr_cfg_regwen (requires zero_delays).
• Randomly add reset between each sequence.

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

• Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
• Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s).
• Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
• Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
• Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
• Repeat the above steps a bunch of times.

Verify common alert_test CSR that allows SW to mock-inject alert requests.

• Enable a random set of alert requests by writing random value to alert_test CSR.
• Check each alert_tx.alert_p pin to verify that only the requested alerts are triggered.
• During alert_handshakes, write alert_test CSR again to verify that: If alert_test writes to current ongoing alert handshake, the alert_test request will be ignored. If alert_test writes to current idle alert handshake, a new alert_handshake should be triggered.
• Wait for the alert handshakes to finish and verify alert_tx.alert_p pins all sets back to 0.
• Repeat the above steps a bunch of times.

Access out of bounds address and verify correctness of response / behavior

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the [TLUL spec]({{< relref "hw/ip/tlul/doc/_index.md#explicit-error-cases" >}})

• TL-UL protocol error cases
  • invalid opcode
  • some mask bits not set when opcode is PutFullData
  • mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
  • mask and address misaligned, e.g. a_address = 0x01, a_mask = 'b0001
  • address and size aren't aligned, e.g. a_address = 0x01, a_size != 0
  • size is greater than 2
• OpenTitan defined error cases
  • access unmapped address, expect d_error = 1 when devmode_i == 1
  • write a CSR with unaligned address, e.g. a_address[1:0] != 0
  • write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
  • write a memory with a_mask != '1 when it doesn't support partial accesses
  • read a WO (write-only) memory
  • write a RO (read-only) memory

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

Verify the outcome of injecting faults to security countermeasures.

Stimulus: As mentioned in prim_count_check, prim_one_hot_check and prim_fsm_check.

Checks:

• Besides checking alert and fault_status, issue an operation after injecting faults, then ensure that op_status is failed and design enters StInvalid.

Verify that the data integrity check violation generates an alert.

Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.

Verify that violating prim_count counter properties generate a fatal alert.

Stimulus:

• At the falling edge (non-active edge), force the counter to a different value than expected.
• Randomly force the counter back to a normal value to ensure the error is latched and won't go away until reset.
• Within the next few cycles, the violation of hardened counter property should generate a fatal alert.
• Repeat for ALL prim_count instances in the DUT.

Checks:

• Check that fatal alert is triggered.
• Check that err_code/fault_status is updated correctly and preserved until reset.
• Verify any operations that follow fail (as applicable).

Verify that entering to an undefined state generates a fatal alert.

Stimulus:

• Backdoor force the FSM to any of the undefined values.
• Randomly force the FSM back to a defined state to ensure the error is latched and won't go away until reset.
• Within the next few cycles, the FSM landing in an invalid state should trigger a fatal alert.
• Repeat for ALL prim_fsm instances in the DUT.

Checks:

• Check that fatal alert is triggered.
• Check that err_code/fault_status is updated correctly and preserved until reset.
• Verify any operations that follow fail (as applicable).

This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.

• Similar to keymgr_sw_input_cg, create a separate cg as there are some reserved fields scattered in the CSR.

• Cover err_codes values except invalid_shadow_update as that is tested in a common direct test.
• This is sampled when err_codes is read.

• Cover fault_statusvalues exceptREGFILE_INTGandSHADOW` as they are tested in a common direct test.
• This is sampled when fault_status is read.

Cover all HW invalid inputs, including

• all ones/zeros on OTP root key.
• OTP root key valid is low.
• all ones/zeros on LC keymgr health state.
• all ones/zeros on ROM degist.
• ROM degist valid is low.
• all ones/zeros on flash creator seeds.
• all ones/zeros on flash owner seeds.

• Cover comparison results (equal, less, greater) of key_version and current max value.
• Cross with state and operation (gen-sw-out or gen-hw-out).

• Cover all bits of SW inputs are toggled.
• SW input includes these CSRS: *_sw_binding, salt, key_version, max_*_key_ver*.
• Cross with the corresponding regwen.

• Cover LC disable occurs at any of all the states or during any of all the operations.
• This is sampled once LC disables keymgr.

• Cover small values of reseed_interval are used, so that TB can actually check EDN request is sent in the right interval.
• Also Cover some large values to ensure all bits are toggled.

• Cover all the sideload_clear values are used after any of all the operations and in any of all the states.
• Cover sideload_clear with any combination of availability of 3 sideload interfaces.
• This is sampled once sideload_clear is programmed after an operation.

• Cover all operations with cdi_sel, dest_sel and op_status (only fail or success) at any of all working_states.
• This is sampled once an operation is done.

• Cover sync and async fault cross with each other, including 2 cases - sync fault occurs first and async fault occurs first.
• This is sampled after fault_status is read in the sequence.

Cover the following error cases on TL-UL bus:

• TL-UL protocol error cases.
• OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.