KEYMGR DV document

Goals

DV
- Verify all KEYMGR IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
FPV
- Verify TileLink device protocol compliance with an SVA based testbench

Current status

Design features

For detailed information on KEYMGR design features, please see the KEYMGR HWIP technical specification.

Testbench architecture

KEYMGR testbench has been constructed based on the CIP testbench architecture.

Block diagram

Top level testbench

Top level testbench is located at hw/ip/keymgr/dv/tb/tb.sv. It instantiates the KEYMGR DUT module hw/ip/keymgr/rtl/keymgr.sv. In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db:

Common DV utility components

The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

Compile-time configurations

[list compile time configurations, if any and what are they used for]

Global types & methods

All common types and methods defined at the package level can be found in keymgr_env_pkg. Some of them in use are:

[list a few parameters, types & methods; no need to mention all]

TL_agent

KEYMGR testbench instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into KEYMGR device.

UVC/agent 1

[Describe here or add link to its README]

UVC/agent 2

[Describe here or add link to its README]

UVM RAL Model

The KEYMGR RAL model is created with the ralgen FuseSoC generator script automatically when the simulation is at the build stage.

It can be created manually by invoking regtool:

Reference models

[Describe reference models in use if applicable, example: SHA256/HMAC]

Stimulus strategy

Test sequences

All test sequences reside in hw/ip/keymgr/dv/env/seq_lib. The keymgr_base_vseq virtual sequence is extended from cip_base_vseq and serves as a starting point. All test sequences are extended from keymgr_base_vseq. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. Some of the most commonly used tasks / functions are as follows:

task 1:
task 2:

Functional coverage

To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:

cg1:
cg2:

Self-checking strategy

Scoreboard

The keymgr_scoreboard is primarily used for end to end checking. It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:

analysis port1:
analysis port2:

Assertions

TLUL assertions: The tb/keymgr_bind.sv binds the tlul_assert assertions to the IP to ensure TileLink interface protocol compliance.
Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
assert prop 1:
assert prop 2:

Building and running tests

We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:

$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/keymgr/dv/keymgr_sim_cfg.hjson -i keymgr_smoke

Testplan

Testpoints

Milestone	Name	Tests	Description
V1	smoke	keymgr_smoke	Smoke test accessing a major datapath within the keymgr. Test operations (advance, gen-id and gen-sw-out) in every state Stimulus: Go through state from `StReset` to `StDisabled`. Issue gen-id, gen-sw-output operation in each state, including invalid operations in states other than normal operating states (`StCreatorRootKey`, `StOwnerIntKey` and `StOwnerRootKey`). Checks: Check STATUS reg for each operation. Check interrupts `op_done` is triggered when operation is done. Check `err` and alert `recov_operation_err` are triggered after invalid operation. Check KMAC key, KMAC data and output SW data for correctness. For invalid operations, check KMAC key, KMAC data and output SW data don't match to any of saved meaningful data, which are collected from valid operations. This checking method is also applied to other error cases.
V1	random	keymgr_random	Extend from smoke to randomize all SW input data Fully randomize SW input: rom_ext_desc_, software_binding_, salt_, max__key_ver, _key_ver_en. Randomize key_version any value less than max__key_ver, to avoid triggerring `invalid_kmac_input` error. Fully randomize HW input from flash, otp and life cycle. Most of other sequences are derived from this to have similar init and sequence. Stimulus and checks are the same as smoke.
V1	csr_hw_reset	keymgr_csr_hw_reset	Verify the reset values as indicated in the RAL specification. Write all CSRs with a random value. Apply reset to the DUT as well as the RAL model. Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.
V1	csr_rw	keymgr_csr_rw	Verify accessibility of CSRs as indicated in the RAL specification. Loop through each CSR to write it with a random value. Read the CSR back and check for correctness while adhering to its access policies. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.
V1	csr_bit_bash	keymgr_csr_bit_bash	Verify no aliasing within individual bits of a CSR. Walk a 1 through each CSR by flipping 1 bit at a time. Read the CSR back and check for correctness while adhering to its access policies. This verify that writing a specific bit within the CSR did not affect any of the other bits. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.
V1	csr_aliasing	keymgr_csr_aliasing	Verify no aliasing within the CSR address space. Loop through each CSR to write it with a random value Shuffle and read ALL CSRs back. All CSRs except for the one that was written in this iteration should read back the previous value. The CSR that was written in this iteration is checked for correctness while adhering to its access policies. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	Verify random reset during CSR/memory access. Run csr_rw sequence to randomly access CSRs If memory exists, run mem_partial_access in parallel with csr_rw Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value It is mandatory to run this test for all available interfaces the CSRs are accessible from.
V2	cfgen_during_op	keymgr_cfg_regwen	CFGEN is RO reg and it gates bunch of write access of other registers, which isn't tested in common CSR tests. Stimulus and checks: Test command and reg access gated by CFGEN is ignored during operation.
V2	cfgen_at_st_random	keymgr_cfg_regwen	`StRandom` is a temporary state during init operation, which will set CSR CFGEN. Stimulus and checks: Test command and reg access gated by CFGEN is ignored during `StRandom`.
V2	sideload	keymgr_sideload	Keymgr contains HW sideload interfaces to output keys for KMAC, HMAC, AES. Stimulus: Generate a keymgr output to HW sideload interface, excising all the sideload interfaces. Checks: Verify the sideload data and status for correctness.
V2	init_n_start	keymgr_random	Stimulus and checks: Verify all combinations of `init` and `start`. If both are set in `StReset`, check `INVALID_OP` error is triggered. If it's in other state, `init` is ignored.
V2	direct_to_disabled_state	keymgr_direct_to_disabled	Stimulus and checks: Directly go to `StDisabled` from any state and check `StDisabled` is entered correctly.
V2	lc_disable	keymgr_lc_disable	Life cycle can disable keymgr and let keymgr wipe secret immediately. Stimulus: Test life cycle disables keymgr in any state. Checks: If keymgr is not initialized, check it can't be initialized until life cycle enables keymgr. If keymgr is in a valid state after init, key output to KMAC is wiped immediately and SW output will be invalid after OP is done. If keymgr in disabled state, check the behavior is consistent with normal behavior.
V2	invalid_cmd	keymgr_cmd_invalid	Verify `keymgr` security countermeasures on fault injection. Stimulus: Force one of these or both Force advance, gen_id and gen_out to not one-hot Path: `dut.u_ctrl.adv_en_o/id_en_o/gen_en_o` Force KMAC FSM to default branch to trigger FSM error Path: `dut.u_kmac_if.state_d` Checks: Check interrupts `err` is triggered. Check alert `fatal_fault_err` is triggered and err_code is `INVALID_CMD`. Check KMAC output key and output data to SW are corrupted, also keymgr enters StDisabled.
V2	kmac_error_response	keymgr_kmac_rsp_err	Verify `keymgr` behavior on error response received from `KMAC` after sending data to it. Stimulus: Drive error from KMAC interface when VALID is high. Checks: Same as above entry - "invalid_cmd".
V2	invalid_kmac_input	keymgr_sw_invalid_input	Verify `keymgr` behavior with invalid key version. Stimulus: Randomize KEY_VERSION and MAX__VER registers. Checks: when KEY_VERSION > MAX__VER Check interrupts `err` is triggered. Check alert `recov_operation_err` is triggered and err_code is `INVALID_KMAC_INPUT`. Check KMAC output key is corrupted and working state remains the same.
V2	invalid_kmac_data	keymgr_hwsw_invalid_input	Verify `keymgr` behavior with invalid data patterns. Stimulus: Use all 0s or 1s as KMAC input digest data Checks: Check interrupts `err` is triggered. Check alert `recov_operation_err` is triggered and err_code is `INVALID_KMAC_DATA`. Check SW output isn't updated and working state remains the same.
V2	stress_all	keymgr_stress_all	Combine above sequences in one test to run sequentially, except csr sequence and keymgr_cfg_regwen (requires zero_delays) Randomly add reset between each sequence
V2	intr_test	keymgr_intr_test	Verify common intr_test CSRs that allows SW to mock-inject interrupts. Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s). Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s). Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR. Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set. Clear a random set of interrupts by writing a randomly value to intr_state CSR(s). Repeat the above steps a bunch of times.
V2	alert_test	keymgr_alert_test	Verify common `alert_test` CSR that allows SW to mock-inject alert requests. Enable a random set of alert requests by writing random value to alert_test CSR. Check each `alert_tx.alert_p` pin to verify that only the requested alerts are triggered. During alert_handshakes, write `alert_test` CSR again to verify that: If `alert_test` writes to current ongoing alert handshake, the `alert_test` request will be ignored. If `alert_test` writes to current idle alert handshake, a new alert_handshake should be triggered. Wait for the alert handshakes to finish and verify `alert_tx.alert_p` pins all sets back to 0. Repeat the above steps a bunch of times.
V2	tl_d_oob_addr_access	keymgr_tl_errors	Access out of bounds address and verify correctness of response / behavior
V2	tl_d_illegal_access	keymgr_tl_errors	Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the [TLUL spec]({{< relref "hw/ip/tlul/doc/_index.md#explicit-error-cases" >}}) TL-UL protocol error cases invalid opcode some mask bits not set when opcode is `PutFullData` mask does not match the transfer size, e.g. `a_address = 0x00`, `a_size = 0`, `a_mask = 'b0010` mask and address misaligned, e.g. `a_address = 0x01`, `a_mask = 'b0001` address and size aren't aligned, e.g. `a_address = 0x01`, `a_size != 0` size is greater than 2 OpenTitan defined error cases access unmapped address, expect `d_error = 1` when `devmode_i == 1` write a CSR with unaligned address, e.g. `a_address[1:0] != 0` write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte write a memory with `a_mask != '1` when it doesn't support partial accesses read a WO (write-only) memory write a RO (read-only) memory
V2	tl_d_outstanding_access	keymgr_csr_hw_reset keymgr_csr_rw keymgr_csr_aliasing keymgr_same_csr_outstanding	Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.
V2	tl_d_partial_access	keymgr_csr_hw_reset keymgr_csr_rw keymgr_csr_aliasing keymgr_same_csr_outstanding	Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.
V2	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.
V3	tl_intg_err	keymgr_tl_intg_err	Verify that the data integrity check violation generates an alert. Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.

Covergroups

Name Description

tl_errors_cg

Name	Description
tl_errors_cg	Cover the following error cases on TL-UL bus: TL-UL protocol error cases. OpenTitan defined error cases, refer to testpoint `tl_d_illegal_access`.
tl_intg_err_cg	Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.
tl_intg_err_mem_subword_cg	Cover the kinds of integrity errors with byte enabled write on memory. Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.

Cover the following error cases on TL-UL bus:

TL-UL protocol error cases.
OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.

tl_intg_err_cg

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

tl_intg_err_mem_subword_cg

Cover the kinds of integrity errors with byte enabled write on memory.

Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.