Life Cycle Controller Technical Specification

Overview

TODO: populate with spec text. this is an empty shell to be able to link to from other docs.

Features

Life Cycle Controller Overview

Theory of Operations

Hardware Interfaces

Parameters

Parameter Default (Max) Top Earlgrey Description

Signals

Referring to the Comportable guideline for peripheral device functionality, the module lc_ctrl has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: none

Bus Device Interface: tlul

Bus Host Interface: none

Peripheral Pins for Chip IO: none

Interrupts: none

Security Alerts: none

Signal Direction Type Description

Register Table

lc_ctrl.STATUS @ + 0x0
LC status register.
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  DUMMY
BitsTypeResetNameDescription
1:0ro0x0DUMMYfoo


lc_ctrl.CTRL @ + 0x4
LC control register.
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  DUMMY
BitsTypeResetNameDescription
1:0ro0x0DUMMYfoo