LC_CTRL DV document

Goals

  • DV
    • Verify all LC_CTRL IP features by running dynamic simulations with a SV/UVM based testbench
    • Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
  • FPV
    • Verify TileLink device protocol compliance with an SVA based testbench

Current status

Design features

For detailed information on LC_CTRL design features, please see the LC_CTRL HWIP technical specification.

Testbench architecture

LC_CTRL testbench has been constructed based on the CIP testbench architecture.

Block diagram

Block diagram

Top level testbench

Top level testbench is located at hw/ip/lc_ctrl/dv/tb/tb.sv. It instantiates the LC_CTRL DUT module hw/ip/lc_ctrl/rtl/lc_ctrl.sv. In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db:

Common DV utility components

The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

Compile-time configurations

[list compile time configurations, if any and what are they used for]

Global types & methods

All common types and methods defined at the package level can be found in lc_ctrl_env_pkg. Some of them in use are:

[list a few parameters, types & methods; no need to mention all]

TL_agent

LC_CTRL testbench instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into LC_CTRL device.

UVC/agent 1

[Describe here or add link to its README]

UVC/agent 2

[Describe here or add link to its README]

UVM RAL Model

The LC_CTRL RAL model is created with the ralgen FuseSoC generator script automatically when the simulation is at the build stage.

It can be created manually by invoking regtool:

Reference models

[Describe reference models in use if applicable, example: SHA256/HMAC]

Stimulus strategy

Test sequences

All test sequences reside in hw/ip/lc_ctrl/dv/env/seq_lib. The lc_ctrl_base_vseq virtual sequence is extended from cip_base_vseq and serves as a starting point. All test sequences are extended from lc_ctrl_base_vseq. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. Some of the most commonly used tasks / functions are as follows:

  • task 1:
  • task 2:

Functional coverage

To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:

  • cg1:
  • cg2:

Self-checking strategy

Scoreboard

The lc_ctrl_scoreboard is primarily used for end to end checking. It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:

  • analysis port1:
  • analysis port2:

Assertions

  • TLUL assertions: The tb/lc_ctrl_bind.sv binds the tlul_assert assertions to the IP to ensure TileLink interface protocol compliance.
  • Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
  • assert prop 1:
  • assert prop 2:

Building and running tests

We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:

$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/lc_ctrl/dv/lc_ctrl_sim_cfg.hjson -i lc_ctrl_smoke

Testplan

Testpoints

Milestone Name Tests Description
V1 smoke lc_ctrl_smoke

Smoke test accessing lc_ctrl state transition datapath.

Stimulus:

  • Initialize lc_ctrl by sending pwrmgr req and otp_ctrl valid random data.
  • Request a valid next LC state by writing CSRs: transition_target, transition_token*, and transition_cmd.

Checks:

  • After lc_ctrl initialization finishes, check lc_ctrl broadcast outputs, check the value of lc_state and lc_transition_cnt CSRs, and check device_id and id_state CSRs.
  • After lc_ctrl state transition request, check status to ensure the transition is valid and successful.
  • Check token matching for both conditional and unconditional requests.
  • Once the transition is successful, check lc_ctrl broadcast outputs are all turned off.
V1 csr_hw_reset lc_ctrl_csr_hw_reset

Verify the reset values as indicated in the RAL specification.

  • Write all CSRs with a random value.
  • Apply reset to the DUT as well as the RAL model.
  • Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_rw lc_ctrl_csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

  • Loop through each CSR to write it with a random value.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_bit_bash lc_ctrl_csr_bit_bash

Verify no aliasing within individual bits of a CSR.

  • Walk a 1 through each CSR by flipping 1 bit at a time.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • This verify that writing a specific bit within the CSR did not affect any of the other bits.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_aliasing lc_ctrl_csr_aliasing

Verify no aliasing within the CSR address space.

  • Loop through each CSR to write it with a random value
  • Shuffle and read ALL CSRs back.
  • All CSRs except for the one that was written in this iteration should read back the previous value.
  • The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_mem_rw_with_rand_resetlc_ctrl_csr_mem_rw_with_rand_reset

Verify random reset during CSR/memory access.

  • Run csr_rw sequence to randomly access CSRs
  • If memory exists, run mem_partial_access in parallel with csr_rw
  • Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
V2 state_post_trans lc_ctrl_state_post_trans

This test is based on smoke test. After smoke sequence, this test adds additional lc_state transition request before issuing reset. This should happen regardless if the transition is successful. Use scoreboard to ensure lc_ctrl ignores this additional lc_state transition request and check state count.

V2 regwen_during_op lc_ctrl_regwen_during_op

Transition_regwen is RO register and it gates bunch of write access of other registers.

Checks:

  • Check transition_regwen register is set to 1 during lc_state transition request.
  • Check that accessing its locked CSRs is gated during the transition operation.
V2 lc_prog_failure lc_ctrl_prog_failure

This test checks lc_program failure by setting the error bit after otp program request.

Checks:

  • Check if status register reflects the correct error bit.
  • Check if lc_program_failure alert is triggered.
  • Check if lc_state moves to escalation state.
V2 lc_state_failure lc_ctrl_state_failure

This test checks lc_state failure by:

  • Driving invalid data to lc_ctrl input otp_lc_data_i fields lc_state and lc_cnt.
  • Backdoor changing lc_ctrl FSM's to invalid value. For invalid value, the testbench will test using random value and valid A/B/C/D values with different orders.

Checks:

  • Check if status register reflects the correct error bit.
  • Check if lc_state_failure alert is triggered.
  • Check if lc_state moves to escalation state.
V2 lc_errors lc_ctrl_errors

This test randomly executes the error senarios:

  • otp_ctrl input lc_trans_cnt reaches 16
  • lc_ctrl state transition request is invalid
  • input LC token does not match the output from otp_ctrl
  • flash rma responses to lc_ctrl request with error
  • lc_ctrl clock bypass responses with error
  • input otp_lc_data's error bit is set to 1 Note that all the above scenarios except the last one requires a reset to recover.

Checks:

  • Check if status register reflects the correct error bit.
  • Check if lc_state moves to correct exit state.
  • Check if lc_trans_cnt is incremented.
V2 security_escalation lc_ctrl_security_escalation
lc_ctrl_errors
lc_ctrl_state_failure
lc_ctrl_prog_failure
lc_ctrl_jtag_errors
lc_ctrl_jtag_state_failure
lc_ctrl_jtag_prog_failure

This test checks two security escalation responses:

  • wipe secrets: permanently asserts lc_escalate_en signal
  • scrap state: lc_ctrl moves to escalation state, check the state will be cleared up upon next power cycle
V2 jtag_access lc_ctrl_jtag_access
lc_ctrl_jtag_smoke
lc_ctrl_jtag_state_post_trans
lc_ctrl_jtag_errors
lc_ctrl_jtag_prog_failure
lc_ctrl_jtag_errors
lc_ctrl_jtag_regwen_during_op
lc_ctrl_jtag_csr_hw_reset
lc_ctrl_jtag_csr_rw
lc_ctrl_jtag_csr_bit_bash
lc_ctrl_jtag_csr_aliasing
lc_ctrl_jtag_same_csr_outstanding
lc_ctrl_jtag_csr_mem_rw_with_rand_reset
lc_ctrl_jtag_alert_test

This test checks jtag debug interface in lc_ctrl. This test will use both JTAG TAP and TLUL to access the CSR space. All above CSR sequences should be accessible via both interfaces.

V2 jtag_priority lc_ctrl_jtag_priority

This test covers a corner case in JTAG and TLUL interfaces.

Stimulus:

  • Issue mux_claim operation from TLUL and JTAG interfaces at the same time.

Checks:

  • Ensure TAP interface has the priority.
  • Ensure right after the mux_claim operation, the non-prioritized interface returns 0 from the CSR readings. This checking ensures there is no token leakage between interfaces.
V2 stress_all lc_ctrl_stress_all
  • Combine above sequences in one test to run sequentially, except csr sequence.
  • Random selection of Tilelink or JTAG CSR for each sequence
  • Randomly add reset between each sequence.
V2 alert_test lc_ctrl_alert_test

Verify common alert_test CSR that allows SW to mock-inject alert requests.

  • Enable a random set of alert requests by writing random value to alert_test CSR.
  • Check each alert_tx.alert_p pin to verify that only the requested alerts are triggered.
  • During alert_handshakes, write alert_test CSR again to verify that: If alert_test writes to current ongoing alert handshake, the alert_test request will be ignored. If alert_test writes to current idle alert handshake, a new alert_handshake should be triggered.
  • Wait for the alert handshakes to finish and verify alert_tx.alert_p pins all sets back to 0.
  • Repeat the above steps a bunch of times.
V2 tl_d_oob_addr_access lc_ctrl_tl_errors

Access out of bounds address and verify correctness of response / behavior

V2 tl_d_illegal_access lc_ctrl_tl_errors

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the [TLUL spec]({{< relref "hw/ip/tlul/doc/_index.md#explicit-error-cases" >}})

  • TL-UL protocol error cases
    • invalid opcode
    • some mask bits not set when opcode is PutFullData
    • mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
    • mask and address misaligned, e.g. a_address = 0x01, a_mask = 'b0001
    • address and size aren't aligned, e.g. a_address = 0x01, a_size != 0
    • size is greater than 2
  • OpenTitan defined error cases
    • access unmapped address, expect d_error = 1 when devmode_i == 1
    • write a CSR with unaligned address, e.g. a_address[1:0] != 0
    • write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
    • write a memory with a_mask != '1 when it doesn't support partial accesses
    • read a WO (write-only) memory
    • write a RO (read-only) memory
V2 tl_d_outstanding_access lc_ctrl_csr_hw_reset
lc_ctrl_csr_rw
lc_ctrl_csr_aliasing
lc_ctrl_same_csr_outstanding

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

V2 tl_d_partial_access lc_ctrl_csr_hw_reset
lc_ctrl_csr_rw
lc_ctrl_csr_aliasing
lc_ctrl_same_csr_outstanding

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

V2S tl_intg_err lc_ctrl_tl_intg_err

Verify that the data integrity check violation generates an alert.

Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.

Covergroups

Name Description
tl_errors_cg

Cover the following error cases on TL-UL bus:

  • TL-UL protocol error cases.
  • OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.
tl_intg_err_cg

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.