LC_CTRL DV document
- Verify all LC_CTRL IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the DV plan below towards closing code and functional coverage on the IP and all of its sub-modules
- Verify TileLink device protocol compliance with an SVA based testbench
For detailed information on LC_CTRL design features, please see the LC_CTRL HWIP technical specification.
LC_CTRL testbench has been constructed based on the CIP testbench architecture.
Top level testbench
Top level testbench is located at
hw/ip/lc_ctrl/dv/tb/tb.sv. It instantiates the LC_CTRL DUT module
In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into
- Clock and reset interface
- TileLink host interface
- LC_CTRL IOs
- Interrupts (
- Alerts (
- Devmode (
Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
[list compile time configurations, if any and what are they used for]
Global types & methods
All common types and methods defined at the package level can be found in
lc_ctrl_env_pkg. Some of them in use are:
[list a few parameters, types & methods; no need to mention all]
LC_CTRL testbench instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into LC_CTRL device.
[Describe here or add link to its README]
[Describe here or add link to its README]
UVM RAL Model
The LC_CTRL RAL model is created with the
ralgen FuseSoC generator script automatically when the simulation is at the build stage.
It can be created manually by invoking
[Describe reference models in use if applicable, example: SHA256/HMAC]
All test sequences reside in
lc_ctrl_base_vseq virtual sequence is extended from
cip_base_vseq and serves as a starting point.
All test sequences are extended from
It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:
- task 1:
- task 2:
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:
lc_ctrl_scoreboard is primarily used for end to end checking.
It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:
- analysis port1:
- analysis port2:
- TLUL assertions: The
tlul_assertassertions to the IP to ensure TileLink interface protocol compliance.
- Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
- assert prop 1:
- assert prop 2:
Building and running tests
We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:
$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/lc_ctrl/dv/lc_ctrl_sim_cfg.hjson -i lc_ctrl_smoke
Smoke test accessing lc_ctrl state transition datapath.
Verify the reset values as indicated in the RAL specification.
Verify accessibility of CSRs as indicated in the RAL specification.
Verify no aliasing within individual bits of a CSR.
Verify no aliasing within the CSR address space.
Verify random reset during CSR/memory access.
This test is based on smoke test. After smoke sequence, this test adds additional lc_state transition request before issuing reset. This should happen regardless if the transition is successful. Use scoreboard to ensure lc_ctrl ignores this additional lc_state transition request and check state count.
This test checks lc_program failure by setting the error bit after otp program request.
This test checks lc_state failure by:
This test randomly executes the error senarios:
This test checks two security escalation responses:
This test checks jtag debug interface in lc_ctrl. This test will use both JTAG TAP and TLUL to access the CSR space. All above CSR sequences should be accessible via both interfaces.
This test covers a corner case in JTAG and TLUL interfaces.
Access out of bounds address and verify correctness of response / behavior
Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested
Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.
Access CSR with one or more bytes of data For read, expect to return all word value of the CSR For write, enabling bytes should cover all CSR valid fields