NMI Generator Technical Specification
Overview
This document specifies the functionality of the non-maskable interrupt generator (nmi_gen
) peripheral.
This module conforms to the OpenTitan guideline for peripheral device functionality..
See that document for integration overview within the broader OpenTitan top level system.
The module provides a mechanism to test the alert handler escalation signals (see alert handler spec), and will be modified or even replaced in the near future.
Features
- Contains four escalation receivers to receive escalation signals from the alert handler
- Produces four regular interrupts that are derived from the alert handler escalation signals
Description
The NMI generator module is a simple wrapper module that instantiates four escalation receivers (which are described in more detail in the alert handler spec). The output of these receivers are converted into regular interrupt requests that can be connected to the PLIC/processor core in order to test the escalation mechanism.
Parameters
The following table lists the main parameters used throughout the nmi_gen
design.
Localparam | Default (Max) | Description |
---|---|---|
N_ESC_SEV | 4 (-) | Number of escalation receivers (should be left as is). |
Signals
Referring to the
Comportable guideline for peripheral device functionality,
the module NMI_GEN
has
the following hardware interfaces defined.
Primary Clock: clk_i
Other Clocks: none
Bus Device Interface: tlul
Bus Host Interface:
Peripheral Pins for Chip IO: none
Interrupts:
Interrupt Name | Description |
---|---|
esc0 | Escalation interrupt 0 |
esc1 | Escalation interrupt 1 |
esc2 | Escalation interrupt 2 |
Security Alerts: none
The table below lists other nmi_gen
signals.
Signal | Direction | Type | Description |
---|---|---|---|
esc_tx_i[N_ESC_SEV-1:0] |
input |
packed esc_tx_t array |
Differentially encoded escalation signals coming from the alert handler. |
esc_rx_o[N_ESC_SEV-1:0] |
output |
packed esc_rx_t array |
Differentially encoded response signals to alert handler. |
Register Table
NMI_GEN.INTR_STATE @ 0x0
Interrupt State Register Reset default = 0x0, mask 0x7
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw1c | 0x0 | esc0 | Escalation interrupt 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw1c | 0x0 | esc1 | Escalation interrupt 1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw1c | 0x0 | esc2 | Escalation interrupt 2 |
NMI_GEN.INTR_ENABLE @ 0x4
Interrupt Enable Register Reset default = 0x0, mask 0x7
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x0 | esc0 | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw | 0x0 | esc1 | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw | 0x0 | esc2 | Enable interrupt when |
NMI_GEN.INTR_TEST @ 0x8
Interrupt Test Register Reset default = 0x0, mask 0x7
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | wo | 0x0 | esc0 | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | wo | 0x0 | esc1 | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | wo | 0x0 | esc2 | Write 1 to force |