NMI Generator Technical Specification

Overview

This document specifies the functionality of the non-maskable interrupt generator (nmi_gen) peripheral. This module conforms to the OpenTitan guideline for peripheral device functionality.. See that document for integration overview within the broader OpenTitan top level system. The module provides a mechanism to test the alert handler escalation signals (see alert handler spec), and will be modified or even replaced in the near future.

Features

  • Contains four escalation receivers to receive escalation signals from the alert handler
  • Produces four regular interrupts that are derived from the alert handler escalation signals

Description

The NMI generator module is a simple wrapper module that instantiates four escalation receivers (which are described in more detail in the alert handler spec). The output of these receivers are converted into regular interrupt requests that can be connected to the PLIC/processor core in order to test the escalation mechanism.

NMI Generator Block Diagram

Parameters

The following table lists the main parameters used throughout the nmi_gen design.

Localparam Default (Max) Description
N_ESC_SEV 4 (-) Number of escalation receivers (should be left as is).

Signals

Referring to the Comportable guideline for peripheral device functionality, the module NMI_GEN has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: none

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO: none

Interrupts:

Interrupt NameDescription
esc0

Escalation interrupt 0

esc1

Escalation interrupt 1

esc2

Escalation interrupt 2

Security Alerts: none

The table below lists other nmi_gen signals.

Signal Direction Type Description
esc_tx_i[N_ESC_SEV-1:0] input packed esc_tx_t array Differentially encoded escalation signals coming from the alert handler.
esc_rx_o[N_ESC_SEV-1:0] output packed esc_rx_t array Differentially encoded response signals to alert handler.

Register Table

NMI_GEN.INTR_STATE @ 0x0

Interrupt State Register

Reset default = 0x0, mask 0x7
31302928272625242322212019181716
 
1514131211109876543210
  esc2 esc1 esc0
BitsTypeResetNameDescription
0rw1c0x0esc0

Escalation interrupt 0

1rw1c0x0esc1

Escalation interrupt 1

2rw1c0x0esc2

Escalation interrupt 2


NMI_GEN.INTR_ENABLE @ 0x4

Interrupt Enable Register

Reset default = 0x0, mask 0x7
31302928272625242322212019181716
 
1514131211109876543210
  esc2 esc1 esc0
BitsTypeResetNameDescription
0rw0x0esc0

Enable interrupt when INTR_STATE.esc0 is set.

1rw0x0esc1

Enable interrupt when INTR_STATE.esc1 is set.

2rw0x0esc2

Enable interrupt when INTR_STATE.esc2 is set.


NMI_GEN.INTR_TEST @ 0x8

Interrupt Test Register

Reset default = 0x0, mask 0x7
31302928272625242322212019181716
 
1514131211109876543210
  esc2 esc1 esc0
BitsTypeResetNameDescription
0wo0x0esc0

Write 1 to force INTR_STATE.esc0 to 1.

1wo0x0esc1

Write 1 to force INTR_STATE.esc1 to 1.

2wo0x0esc2

Write 1 to force INTR_STATE.esc2 to 1.