PADCTRL DV Plan
Goals
-
DV:
- PADCTRL is decided to verify in FPV only
-
FPV:
- Verify all the PADCTRL outputs by writing assumptions and assertions with a FPV based testbench
- Verify TileLink device protocol compliance with a FPV based testbench
Current status
- Design & verification stage
- FPV dashboard (link TBD)
Design features
For detailed information on PADCTRL design features, please see the PADCTRL design specification.
Testbench architecture
PADCTRL FPV testbench has been constructed based on the formal architecture. The PADCTRL testbench consists of two RTL modules: padctrl and padring.
Block diagram
TLUL assertions
- The
../fpv/tb/padctrl_bind.svbinds thetlul_assertassertions with padctrl to ensure TileLink interface protocol compliance - TODO: Plan to implement csr assertions under
../fpv/vip/to assert the TileLink writes and reads correct CSRs
PADCTRL assertions
- The
../fpv/tb/padctrl_bind_fpv.svbinds modulepadctrl_assert_fpvwith the padctrl RTL. The assertion file ensures padctrl's outputs (mio_attr_oanddio_attr_o) under the generic or Xilinx implementation are verified. - The
../fpv/tb/padctrl_bind_fpv.svalso binds modulepadring_assert_fpvwith the padring RTL. The assertion file ensures all the padring's outputs are verified.
Symbolic variables
Due to there are large number of muxed and dedicated IOs, the symbolic variable is used to reduce the number of repeated assertions code.
In padctrl_assert_fpv and padring_assert_fpv, we declared two symbolic variables mio_sel and dio_sel to represent the index for muxed IO and dedicated IO.
Detailed explanation is listed in the Symbolic Variables section.
Testplan
| Milestone | Name | Description | Tests |
|---|---|---|---|
| V2 | MioWarl_A | In either generic or Xilinx mode, if a muxed IO's pad attribute is written to the mio_pads registers via the TLUL interface, this assertion checks if the corresponding mio_attr_o's reserved bits remain 0. This assertion intends to test the write_any_read_legal access policy for the mio_pads registers. | padctrl_assert |
| V2 | MioAttr_A | In either generic or Xilinx mode, if a muxed IO's pad attribute is written to the mio_pads registers via the TLUL interface, this assertion checks if the corresponding mio_attr_o value is updated correctly. | padctrl_assert |
| V2 | MioBackwardCheck_A | If the output mio_attr_o has changed, then a valid write to the mio_pads register must have taken place or the write enable signal must have risen in the previous cycle. | padctrl_assert |
| V2 | DioWarl_A | In either generic or Xilinx mode, if a dedicated IO's pad attribute is written to the dio_pads registers via the TLUL interface, this assertion checks if the corresponding dio_attr_o's reserved bits remain 0. This assertion intends to test the write_any_read_legal access policy for the dio_pads registers. | padctrl_assert |
| V2 | DioAttr_A | In either generic or Xilinx mode, if a dedicated IO's pad attribute is written to the dio_pads registers via the TLUL interface, this assertion checks if the corresponding dio_attr_o value is updated correctly. | padctrl_assert |
| V2 | DioBackwardCheck_A | If the output dio_attr_o has changed, then a valid write to the dio_pads register must have taken place or the write enable signal must have risen in the previous cycle. | padctrl_assert |
| V2 | ClkConn_A | This assertion checks that clk_pad_i is correctly connected to clk_o. | padring_assert |
| V2 | RstConn_A | This assertion checks that rst_pad_ni is correctly connected to rst_no. | padring_assert |
| V2 | MioIn_A | This assertion checks the muxed IO output mio_in_o based on mio_pad_io and mio_attr_i inversion bit. | padring_assert |
| V2 | MioInBackwardCheck_A | If the muxed IO output mio_in_o has changed, then mio_pad_io or mio_attr_i must be changed in the same clock cycle. | padring_assert |
| V2 | MioOutNormal_A | If the selected muxed IO output is enabled and the corresponding attribute is not open drain, then the mio_pad_io must be the (possibly inverted) muxed IO output value. | padring_assert |
| V2 | MioOutOd0_A | If the selected muxed IO output is enabled, the open drain attribute is set, and the expected mio_output value is 0, then the mio_pad_io must be 0. | padring_assert |
| V2 | MioOutOd1_A | If the selected muxed IO output is enabled, the open drain attribute is set, and the expected mio_output value is not 0, then the mio_pad_io must be either 0, 1, x or high z. | padring_assert |
| V2 | MioOutBackwardCheck_A | If the muxed IO output mio_pad_io has changed and mio_oe_i is enabled, then mio_attr_i or mio_output_value must be changed in the same clock cycle. | padring_assert |
| V2 | MioOe_A | If the selected muxed IO output is not enabled, the mio_pad_io must be either 0, 1, x or high z. | padring_assert |
| V2 | DioIn_A | This assertion checks the dedicated IO output dio_in_o based on dio_pad_io and dio_attr_i inversion bit. | padring_assert |
| V2 | DioInBackwardCheck_A | If dedicated IO output dio_in_o has changed, then dio_pad_io or dio_attr_i must be changed in the same clock cycle. | padring_assert |
| V2 | DioOutNormal_A | If the selected dedicated IO output is enabled and the corresponding attribute is not open drain, then the dio_pad_io must be the (possibly inverted) dedicated IO output value. | padring_assert |
| V2 | DioOutOd0_A | If the selected dedicated IO output is enabled, the open drain attribute is set, and the expected dio_output value is 0, then the dio_pad_io must be 0. | padring_assert |
| V2 | DioOutOd1_A | If the selected dedicated IO output is enabled, the open drain attribute is set, and the expected dio_output value is not 0, then the dio_pad_io must be either 0, 1, x or high z. | padring_assert |
| V2 | DioOutBackwardCheck_A | If the dedicated IO output dio_pad_io has changed and dio_oe_i is enabled, then dio_attr_i or dio_output_value must be changed in the same clock cycle. | padring_assert |
| V2 | DioOe_A | If the selected dedicated IO output is not enabled, the dio_pad_io must be either 0, 1, x or high z. | padring_assert |
| V2 | fpv_csr_rw | Write assertions to verify all the CSRs from the TileLink. Each CSR will include a read assertion to ensure the read value from the TileLink is expected, and a write assertion to ensure the write value is updated correctly to DUT according to the register's access. | padctrl_fpv_csr_rw |