PATTGEN DV document

Goals

DV
- Verify all PATTGEN IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the DV plan below towards closing code and functional coverage on the IP and all of its sub-modules
FPV
- Verify TileLink device protocol compliance with an SVA based testbench

Current status

Design features

For detailed information on PATTGEN design features, please see the PATTGEN design specification.

Testbench architecture

PATTGEN testbench has been constructed based on the CIP testbench architecture.

Block diagram

Top level testbench

Top level testbench is located at hw/ip/pattgen/dv/tb/tb.sv. It instantiates the PATTGEN DUT module hw/ip/pattgen/rtl/pattgen.sv. In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db:

Common DV utility components

The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

Global types & methods

All common types and methods defined at the package level can be found in pattgen_env_pkg. Some of them in use are:

parameter uint NUM_PATTGEN_CHANNELS = 2;

TL_agent

PATTGEN instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into PATTGEN device.

PATTGEN agent

PATTGEN agent is configured to work device mode. The agent monitor captures patterns generated in channels then sends to the scoreboard for verification
Since the DUT does not require any response thus agent driver is fairly simple.

UVM RAL Model

The PATTGEN RAL model is created with the ralgen FuseSoC generator script automatically when the simulation is at the build stage.

It can be created manually by invoking regtool:

Stimulus strategy

Test sequences

All test sequences reside in hw/ip/pattgen/dv/env/seq_lib. The pattgen_base_vseq virtual sequence is extended from cip_base_vseq and serves as a starting point. All test sequences are extended from pattgen_base_vseq. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. Some of the most commonly used tasks / functions are as follows:

task 1:
task 2:

Functional coverage

To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:

cg1:
cg2:

Self-checking strategy

Scoreboard

The pattgen_scoreboard is primarily used for end to end checking. It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:

analysis port1:
analysis port2:

Assertions

TLUL assertions: The tb/pattgen_bind.sv binds the tlul_assert assertions to the IP to ensure TileLink interface protocol compliance.
Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
assertion 1
assertion 2

Building and running tests

We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:

$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/pattgen/dv/pattgen_sim_cfg.hjson -i pattgen_smoke

DV plan

Milestone	Name	Description	Tests
V1	smoke	Smoke test for pattgen ip in which dut is randomly programmed to generate random patterns on output channels. Stimulus: Program the configuration registers of the output channels Randomly activate the output channels Re-program the configuration registers of the output channels once completion interrupts are asserted Checking: Check divided clock rate for the active channels matching with the values of pre-divider registers Check generated pattern matching on the active channels matching with the values of pattern data registers Check completion interrupts are asserted once a pattern is completely generated on the active channels	pattgen_smoke
V1	csr_hw_reset	Verify the reset values as indicated in the RAL specification. Write all CSRs with a random value. Apply reset to the DUT as well as the RAL model. Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.	pattgen_csr_hw_reset
V1	csr_rw	Verify accessibility of CSRs as indicated in the RAL specification. Loop through each CSR to write it with a random value. Read the CSR back and check for correctness while adhering to its access policies. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.	pattgen_csr_rw
V1	csr_bit_bash	Verify no aliasing within individual bits of a CSR. Walk a 1 through each CSR by flipping 1 bit at a time. Read the CSR back and check for correctness while adhering to its access policies. This verify that writing a specific bit within the CSR did not affect any of the other bits. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.	pattgen_csr_bit_bash
V1	csr_aliasing	Verify no aliasing within the CSR address space. Loop through each CSR to write it with a random value Shuffle and read ALL CSRs back. All CSRs except for the one that was written in this iteration should read back the previous value. The CSR that was written in this iteration is checked for correctness while adhering to its access policies. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.	pattgen_csr_aliasing
V1	csr_mem_rw_with_rand_reset	Verify random reset during CSR/memory access. Run csr_rw sequence to randomly access CSRs If memory exists, run mem_partial_access in parallel with csr_rw Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value It is mandatory to run this test for all available interfaces the CSRs are accessible from.	pattgen_csr_mem_rw_with_rand_reset
V2	perf	Checking ip operation at min/max bandwidth Stimulus: Program the pre-divider registers to high/low values (slow/fast data rate) Program the pattern data registers, the pattern length per output, and repeat counter registers to high/low values Start and stop channels quickly Clear interrupts quickly Checking: Ensure patterns are correctly generated Ensure interrupts are robust asserted and cleared (e.g. at the high data rate)	pattgen_perf
V2	error	Reset then re-start the output channel on the fly. Stimulus: Programm the configuration registers of the output channels Randomly reset the in progress output channels Re-program the configuration registers of the output channels Checking: Ensure patterns are dropped when reset Ensure the output channels get back normal after reset	pattgen_error
V2	stress_all	Combine above sequences in one test then randomly select for running. Stimulus: Start sequences and randomly add reset between each sequence Checking: All sequences should be finished and checked by the scoreboard	pattgen_stress_all
V2	intr_test	Verify common intr_test CSRs that allows SW to mock-inject interrupts. Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s). Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s). Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR. Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set. Clear a random set of interrupts by writing a randomly value to intr_state CSR(s). Repeat the above steps a bunch of times.	pattgen_intr_test
V2	stress_all_with_rand_reset	This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.	pattgen_stress_all_with_rand_reset
V2	tl_d_oob_addr_access	Access out of bounds address and verify correctness of response / behavior	pattgen_tl_errors
V2	tl_d_illegal_access	Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested TL-UL protocol error cases Unsupported opcode. e.g a_opcode isn't Get, PutPartialData or PutFullData Mask isn't all active if opcode = PutFullData Mask isn't in enabled lanes, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010 Mask doesn't align with address, e.g. a_address = 0x01, a_mask = 'b0001 Address and size aren't aligned, e.g. a_address = 0x01, a_size != 0 Size is over 2. OpenTitan defined error cases Access unmapped address, return d_error = 1 when devmode_i == 1 Write CSR with unaligned address, e.g. a_address[1:0] != 0 Write CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte Write a memory without enabling all lanes (a_mask = '1) if memory doesn't support byte enabled write Read a WO (write-only) memory	pattgen_tl_errors
V2	tl_d_outstanding_access	Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.	pattgen_csr_hw_reset pattgen_csr_rw pattgen_csr_aliasing pattgen_same_csr_outstanding
V2	tl_d_partial_access	Access CSR with one or more bytes of data For read, expect to return all word value of the CSR For write, enabling bytes should cover all CSR valid fields	pattgen_csr_hw_reset pattgen_csr_rw pattgen_csr_aliasing pattgen_same_csr_outstanding