PATTGEN DV document

Goals

DV
- Verify all PATTGEN IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the testplan below towards closing code and func tional coverage on the IP and all of its sub-modules
FPV
- Verify TileLink device protocol compliance with an SVA based testbench
- Build comprehensive coverage framework to measure coverage provided by existing tests

Current status

Design features

Two independent programmable channels generating serial data
Channels are configured by register model output values
The core of each channel is a state machine built on three independent counters For detailed information on PATTGEN design features, please see the PATTGEN design specification.

Testbench architecture

PATTGEN testbench has been constructed based on the CIP testbench architecture.

The coverage framework is bound to RTL for coverage collection

Block diagram

Top level testbench

Top level testbench is located at hw/ip/pattgen/dv/tb/tb.sv. It instantiates the PATTGEN DUT module hw/ip/pattgen/rtl/pattgen.sv. In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db:

Common DV utility components

The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

Global types & methods

All common types and methods defined at the package level can be found in pattgen_env_pkg. Some of them in use are:

parameter uint NUM_PATTGEN_CHANNELS = 2;

TL_agent

PATTGEN instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into PATTGEN device.

PATTGEN agent

PATTGEN agent is configured to work device mode. The agent monitor captures patterns generated in channels then sends to the scoreboard for verification
Since the DUT does not require any response thus agent driver is fairly simple.

UVM RAL Model

The PATTGEN RAL model is created with the ralgen FuseSoC generator script automatically when the simulation is at the build stage. It can be created manually by invoking regtool:

Test sequences

All test sequences reside in hw/ip/pattgen/dv/env/seq_lib. The pattgen_base_vseq virtual sequence is extended from cip_base_vseq and serves as a starting point. All test sequences are extended from pattgen_base_vseq. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. Some of the most commonly used tasks / functions are as follows:

setup_pattgen_channel: test writing configuration values to CSR registers
start_pattgen_channels: randomly activate data transfer in channels
stop_pattgen_channels: terminate data transfer in channels and check for randomly injected errors
control_channels: wait for bus availability and program CSR configuration values into channels

Functional coverage

Covergroups are captured at the end of the testplan

Self-checking strategy

Scoreboard

The pattgen_scoreboard is primarily used for end to end checking. It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:

analysis port1:
analysis port2:

Assertions

TLUL assertions: The tb/pattgen_bind.sv binds the tlul_assert assertions to the IP to ensure TileLink interface protocol compliance.
Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
assertion 1
assertion 2

Building and running tests

We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:

$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/pattgen/dv/pattgen_sim_cfg.hjson -i pattgen_smoke

Testplan

Testpoints

Milestone	Name	Tests	Description
V1	smoke	pattgen_smoke	Smoke test for pattgen ip in which dut is randomly programmed to generate random patterns on output channels. Stimulus: Program the configuration registers of the output channels Randomly activate the output channels Re-program the configuration registers of the output channels once completion interrupts are asserted Checking: Check divided clock rate for the active channels matching with the values of pre-divider registers Check generated pattern matching on the active channels matching with the values of pattern data registers Check completion interrupts are asserted once a pattern is completely generated on the active channels
V1	csr_hw_reset	pattgen_csr_hw_reset	Verify the reset values as indicated in the RAL specification. Write all CSRs with a random value. Apply reset to the DUT as well as the RAL model. Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.
V1	csr_rw	pattgen_csr_rw	Verify accessibility of CSRs as indicated in the RAL specification. Loop through each CSR to write it with a random value. Read the CSR back and check for correctness while adhering to its access policies. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.
V1	csr_bit_bash	pattgen_csr_bit_bash	Verify no aliasing within individual bits of a CSR. Walk a 1 through each CSR by flipping 1 bit at a time. Read the CSR back and check for correctness while adhering to its access policies. This verify that writing a specific bit within the CSR did not affect any of the other bits. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.
V1	csr_aliasing	pattgen_csr_aliasing	Verify no aliasing within the CSR address space. Loop through each CSR to write it with a random value Shuffle and read ALL CSRs back. All CSRs except for the one that was written in this iteration should read back the previous value. The CSR that was written in this iteration is checked for correctness while adhering to its access policies. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	Verify random reset during CSR/memory access. Run csr_rw sequence to randomly access CSRs If memory exists, run mem_partial_access in parallel with csr_rw Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value It is mandatory to run this test for all available interfaces the CSRs are accessible from.
V2	perf	pattgen_perf	Checking ip operation at min/max bandwidth Stimulus: Program the pre-divider registers to high/low values (slow/fast data rate) Program the pattern data registers, the pattern length per output, and repeat counter registers to high/low values Start and stop channels quickly Clear interrupts quickly Checking: Ensure patterns are correctly generated Ensure interrupts are robust asserted and cleared (e.g. at the high data rate)
V2	cnt_rollover	cnt_rollover	Checking ip operation with random counter values Stimulus: Program the pre-divider and size registers to unconstraint random values Program the clk_cnt, bit_cnt and rep_cnt to values less than but close to predivider and size registers, so that counting would take a reasonable number of clock cycles include programming for corner cases repeat programming a random number of times Start and stop channels quickly Clear interrupts quickly Checking: Include functional cover point that rollover value is reached and counter is re-enabled: Ensure patterns are correctly generated Ensure interrupts are robust asserted and cleared (e.g. at the high data rate)
V2	error	pattgen_error	Reset then re-start the output channel on the fly. Stimulus: Programm the configuration registers of the output channels Randomly re-enable the in progress output channels Re-program the configuration registers of the output channels Checking: Ensure patterns are dropped when re-enabled Ensure the output channels get back normal after re-enable
V2	stress_all	pattgen_stress_all	Stress_all test is a random mix of all the test above except csr tests.
V2	alert_test	pattgen_alert_test	Verify common `alert_test` CSR that allows SW to mock-inject alert requests. Enable a random set of alert requests by writing random value to alert_test CSR. Check each `alert_tx.alert_p` pin to verify that only the requested alerts are triggered. During alert_handshakes, write `alert_test` CSR again to verify that: If `alert_test` writes to current ongoing alert handshake, the `alert_test` request will be ignored. If `alert_test` writes to current idle alert handshake, a new alert_handshake should be triggered. Wait for the alert handshakes to finish and verify `alert_tx.alert_p` pins all sets back to 0. Repeat the above steps a bunch of times.
V2	intr_test	pattgen_intr_test	Verify common intr_test CSRs that allows SW to mock-inject interrupts. Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s). Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s). Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR. Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set. Clear a random set of interrupts by writing a randomly value to intr_state CSR(s). Repeat the above steps a bunch of times.
V2	tl_d_oob_addr_access	pattgen_tl_errors	Access out of bounds address and verify correctness of response / behavior
V2	tl_d_illegal_access	pattgen_tl_errors	Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the [TLUL spec]({{< relref "hw/ip/tlul/doc/_index.md#explicit-error-cases" >}}) TL-UL protocol error cases invalid opcode some mask bits not set when opcode is `PutFullData` mask does not match the transfer size, e.g. `a_address = 0x00`, `a_size = 0`, `a_mask = 'b0010` mask and address misaligned, e.g. `a_address = 0x01`, `a_mask = 'b0001` address and size aren't aligned, e.g. `a_address = 0x01`, `a_size != 0` size is greater than 2 OpenTitan defined error cases access unmapped address, expect `d_error = 1` when `devmode_i == 1` write a CSR with unaligned address, e.g. `a_address[1:0] != 0` write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte write a memory with `a_mask != '1` when it doesn't support partial accesses read a WO (write-only) memory write a RO (read-only) memory
V2	tl_d_outstanding_access	pattgen_csr_hw_reset pattgen_csr_rw pattgen_csr_aliasing pattgen_same_csr_outstanding	Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.
V2	tl_d_partial_access	pattgen_csr_hw_reset pattgen_csr_rw pattgen_csr_aliasing pattgen_same_csr_outstanding	Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.
V2S	tl_intg_err	pattgen_tl_intg_err	Verify that the data integrity check violation generates an alert. Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.

Covergroups

Name	Description
ctrl_cg	Covers that all valid enable and polarity settings for the Pattgen control register have been tested. Individual enable and polarity settings that will be covered include: Enable pattern generator functionality for Channel 0 (ENABLE_CH0) Enable pattern generator functionality for Channel 1 (ENABLE_CH1) Clock (pcl) polarity for Channel 0 (POLARITY_CH0) Clock (pcl) polarity for Channel 1 (POLARITY_CH1) All valid combinations of the above will also be crossed.
inter_cg	intr_cg is defined in cip_base_env_cov and referenced in pattgen_scoreboard
pattern_data_ch0_0_cg	Covers various data_0 values of the channel0 seed pattern ranges, to ensure that Pattgen can operate successfully on different pattern lengths. we will cover that an acceptable distribution of lengths has been seen, and specifically cover corner cases. The covergroup takes data from TL_UL scoreboard input
pattern_data_ch0_1_cg	Similar to pattern_data_ch0_0_cg, except using data_1 values
pattern_data_ch1_0_cg	Similar to pattern_data_ch0_0_cg.
pattern_data_ch1_1_cg	Similar to pattern_data_ch0_1_cg.
pattern_len_ch0_cg	Covers various Lengths of the channel0 seed pattern ranges, to ensure that Pattgen can operate successfully on different pattern lengths. we will cover that an acceptable distribution of lengths has been seen, and specifically cover some corner cases.
pattern_len_ch1_cg	Similar to channel 0.
pattern_prediv_ch0_cg	Covers various numbers of clock divide ratios of the channel0, to ensure that Pattgen can operate successfully on different clock divide ratios. we will cover that an acceptable distribution of lengths has been seen, and specifically cover corner cases.
pattern_prediv_ch1_cg	Similar to channel 0.
pattern_reps_ch0_cg	Covers various numbers of channel repetitions of the channel0, to ensure that Pattgen can operate successfully on different pattern lengths. we will cover that an acceptable distribution of lengths has been seen, and specifically cover all corner cases.
pattern_reps_ch1_cg	Similar to channel 0.
pattgen_op_cg	The following coverage strategy is implemented: The counters are covered at the max and min corner cases and for the middle values Data bus has functional coverage using walking ones and zeroes One bit width variables are wrapped in one cover point while counters and data have designated cover points Channel enable signal is stand alone cover point
program_while_busy_cg	Program the DUT while pattern is being produced to insure current pattern is not being corrupt.
roll_cg	Covers that all the counters revert to zero when they reach the maximum value. Individual initial and maximum counter values that will be covered include: Initial and maximum values of clock divide counter Initial and maximum values of length counter Initial and maxim values of repetition counter All valid combinations of the above will also be crossed.
tl_errors_cg	Cover the following error cases on TL-UL bus: TL-UL protocol error cases. OpenTitan defined error cases, refer to testpoint `tl_d_illegal_access`.
tl_intg_err_cg	Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check. Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.