Pinmux Technical Specification

Overview

This document specifies the functionality of the pin multiplexer (pinmux) peripheral. This module conforms to the OpenTitan guideline for peripheral device functionality.. See that document for integration overview within the broader OpenTitan top level system. The module provides a mechanism to reconfigure the peripheral-to-pin mapping at runtime, which greatly enhances the system flexibility. This IP is closely related to the padctrl instance which provides additional control of pad attributes (pull-up, pull-down, open drain, drive strength, keeper and inversion). See (TODO) for more information.

Features

Configurable number of chip bidirectional pins
Configurable number of peripheral inputs and outputs
Programmable mapping from peripheral outputs (and output enables) to top-level outputs (and output enables)
Programmable mapping from top-level inputs to peripheral inputs

Description

The pinmux peripheral is a programmable module designed to wire arbitrary peripheral inputs and outputs to arbitrary multiplexable chip bidirectional pins. It gives much flexibility at the top level of the device, allowing most data pins to be flexibly wired and controlled by many peripherals. It is assumed that all available pins that the pinmux connects to are bidirectional, controlled by logic within this module. This document does not define how these are connected to pads at the toplevel, since that is governed by the padctrl IP (TODO). However, some discussion is shared in a later section.

The number of available peripheral IOs and muxed IOs is configurable, in other words modifiable at design time. This configurability is implemented by representing inputs / outputs as packed arrays, in combination with the SystemVerilog parameters NPeriphIn, NPeriphOut and NMioPads. Note however that the register file is also affected by this configuration and needs to be regenerated for each design instance.

The assignment of which peripheral output goes to the output data signal of which chip pin is programmable, in other words, modifiable by software at run time. Similarly the assignment of which peripheral input is driven by which chip input is programmable. By default, all peripheral inputs are tied to zero or one (this default is design-time programmable via the InputDefault parameter). Further, all output enables are set to zero, which essentially causes all pads to be in high-Z state after reset.

In addition to wiring programmability, each peripheral input can be set constantly to 0 or 1, and each chip output can be set constantly to 0, 1 or high-Z. Additional features such as output keeper or inversion are not provided by the pinmux since they are implemented in the padctrl IP which operates at the chip-level. This separation of physical pad attributes and logical wiring makes it possible to place the pads into an always-on domain without restricting possible power-down modes of the pinmux. One could imagine this to be a useful feature if a deep sleep mode were implemented in future; chip outputs could hold their output values and not be affected by internal power loss.

Theory of Operations

The pin multiplexor module intends to give maximum flexibility of peripheral and chip wiring to the software running on the device. The assumption is that the wiring is done once at the initialization of the application based upon usage of the device within the broader system. How this wiring is most effectively done is outside the scope of this document, but a section below briefly discusses use cases.

Block Diagram

The diagram below shows connectivity between four arbitrary chip pins, named MIO_00 .. MIO_03, and several peripheral inputs and outputs. This shows the connectivity available in all directions, as well as the control registers described later in this document. Two example peripherals (uart and spidev) are attached to the pinmux in this example, one with one input and one output, the other with three inputs and one output. The diagram also shows the padring module (from the padctrl IP) which instantiates the bidirectional chip pads with output enable control.

Pinmux Block Diagram

Note that apart from selecting a specific input pad, the periph_insel[*] signals can also be used to tie the peripheral input to 0 or 1. Likewise, the output select signals mio_outsel[*] can also be used to constantly drive an output pin to 0/1 or to put it into high-Z state (default). The output enable and the associated data signal (i.e. periph_to_mio and periph_to_mio_oe) are indexed with the same select signal to allow the peripheral hardware to determine the pad direction instead of demoting that control to software.

Additional details about the signal names and parameters are given in the sections below.

Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module PINMUX has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: clk_aon_i

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO: none

Interrupts: none

Security Alerts: none

Parameters

The following table lists the main parameters used throughout the pinmux design. Note that the pinmux is generated based on the system configuration, and hence these parameters are placed into a package as “localparams”.

Localparam	Default (Max)	Top Earlgrey	Description
`NPeriphOut`	16 (-)	32	Number of peripheral outputs.
`NPeriphIn`	16 (-)	32	Number of peripheral input.
`NMioPads`	8 (-)	32	Number of muxed bidirectional pads (depending on padctrl setup).

Additional IOs

The table below lists the pinmux signals. The number of IOs is parametric, and hence the signals are stacked in packed arrays.

Signal	Direction	Type	Description
`periph_to_mio_i[NPeriphOut-1:0]`	`input`	packed `logic`	Signals from `NPeriphOut` peripheral outputs coming into the pinmux.
`periph_to_mio_oe_i[NPeriphOut-1:0]`	`input`	packed `logic`	Signals from `NPeriphOut` peripheral output enables coming into the pinmux.
`mio_to_periph_o[NPeriphIn-1:0]`	`output`	packed `logic`	Signals to `NPeriphIn` peripherals coming from the pinmux.
`mio_out_o[NMioPads-1:0]`	`output`	packed `logic`	Signals to `NMioPads` bidirectional pads as output data.
`mio_oe_o[NMioPads-1:0]`	`output`	packed `logic`	Signals to `NMioPads` bidirectional pads as output enables.
`mio_in_i[NMioPads-1:0]`	`input`	packed `logic`	Signals from `NMioPads` bidirectional pads as input data.

Programmers Guide

Software should determine and program the pinmux mapping at startup, or reprogram it when the functionality requirements change at runtime. This can be achieved by writing the following values to the PERIPH_INSEL and MIO_OUTSEL registers. Note that the pinmux configuration should be sequenced after any IO attribute-specific configuration in the padctrl module to avoid any unwanted electric behavior and/or contention.

`periph_insel` Value	Selected Input Signal
0	Constant zero
1	Constant one
2 + k	Corresponding MIO input signal at index k

The global default at reset is 0, but the default of individual signals can be overridden at design time, if needed.

`mio_outsel` Value	Selected Output signal
0	Constant zero
1	Constant one
2	High-Z
3 + k	Corresponding peripheral output signal at index k

The global default at reset is 2, but the default of individual signals can be overridden at design time, if needed.

The pinmux configuration can be locked down by writing 0 to register REGEN. The configuration can then not be altered anymore unless the system is reset.

Register Table

The register description below matches the instance in the Earl Grey top level design.

Similar register descriptions can be generated with different parameterizations.

PINMUX.MIO_PERIPH_INSEL_REGWEN_0 @ 0x0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_0

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_0

PINMUX.MIO_PERIPH_INSEL_REGWEN_1 @ 0x4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_1

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_1

For MIO_PERIPH_INSEL1

PINMUX.MIO_PERIPH_INSEL_REGWEN_2 @ 0x8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_2

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_2

For MIO_PERIPH_INSEL2

PINMUX.MIO_PERIPH_INSEL_REGWEN_3 @ 0xc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_3

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_3

For MIO_PERIPH_INSEL3

PINMUX.MIO_PERIPH_INSEL_REGWEN_4 @ 0x10

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_4

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_4

For MIO_PERIPH_INSEL4

PINMUX.MIO_PERIPH_INSEL_REGWEN_5 @ 0x14

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_5

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_5

For MIO_PERIPH_INSEL5

PINMUX.MIO_PERIPH_INSEL_REGWEN_6 @ 0x18

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_6

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_6

For MIO_PERIPH_INSEL6

PINMUX.MIO_PERIPH_INSEL_REGWEN_7 @ 0x1c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_7

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_7

For MIO_PERIPH_INSEL7

PINMUX.MIO_PERIPH_INSEL_REGWEN_8 @ 0x20

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_8

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_8

For MIO_PERIPH_INSEL8

PINMUX.MIO_PERIPH_INSEL_REGWEN_9 @ 0x24

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_9

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_9

For MIO_PERIPH_INSEL9

PINMUX.MIO_PERIPH_INSEL_REGWEN_10 @ 0x28

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_10

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_10

For MIO_PERIPH_INSEL10

PINMUX.MIO_PERIPH_INSEL_REGWEN_11 @ 0x2c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_11

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_11

For MIO_PERIPH_INSEL11

PINMUX.MIO_PERIPH_INSEL_REGWEN_12 @ 0x30

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_12

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_12

For MIO_PERIPH_INSEL12

PINMUX.MIO_PERIPH_INSEL_REGWEN_13 @ 0x34

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_13

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_13

For MIO_PERIPH_INSEL13

PINMUX.MIO_PERIPH_INSEL_REGWEN_14 @ 0x38

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_14

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_14

For MIO_PERIPH_INSEL14

PINMUX.MIO_PERIPH_INSEL_REGWEN_15 @ 0x3c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_15

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_15

For MIO_PERIPH_INSEL15

PINMUX.MIO_PERIPH_INSEL_REGWEN_16 @ 0x40

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_16

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_16

For MIO_PERIPH_INSEL16

PINMUX.MIO_PERIPH_INSEL_REGWEN_17 @ 0x44

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_17

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_17

For MIO_PERIPH_INSEL17

PINMUX.MIO_PERIPH_INSEL_REGWEN_18 @ 0x48

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_18

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_18

For MIO_PERIPH_INSEL18

PINMUX.MIO_PERIPH_INSEL_REGWEN_19 @ 0x4c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_19

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_19

For MIO_PERIPH_INSEL19

PINMUX.MIO_PERIPH_INSEL_REGWEN_20 @ 0x50

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_20

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_20

For MIO_PERIPH_INSEL20

PINMUX.MIO_PERIPH_INSEL_REGWEN_21 @ 0x54

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_21

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_21

For MIO_PERIPH_INSEL21

PINMUX.MIO_PERIPH_INSEL_REGWEN_22 @ 0x58

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_22

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_22

For MIO_PERIPH_INSEL22

PINMUX.MIO_PERIPH_INSEL_REGWEN_23 @ 0x5c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_23

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_23

For MIO_PERIPH_INSEL23

PINMUX.MIO_PERIPH_INSEL_REGWEN_24 @ 0x60

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_24

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_24

For MIO_PERIPH_INSEL24

PINMUX.MIO_PERIPH_INSEL_REGWEN_25 @ 0x64

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_25

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_25

For MIO_PERIPH_INSEL25

PINMUX.MIO_PERIPH_INSEL_REGWEN_26 @ 0x68

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_26

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_26

For MIO_PERIPH_INSEL26

PINMUX.MIO_PERIPH_INSEL_REGWEN_27 @ 0x6c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_27

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_27

For MIO_PERIPH_INSEL27

PINMUX.MIO_PERIPH_INSEL_REGWEN_28 @ 0x70

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_28

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_28

For MIO_PERIPH_INSEL28

PINMUX.MIO_PERIPH_INSEL_REGWEN_29 @ 0x74

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_29

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_29

For MIO_PERIPH_INSEL29

PINMUX.MIO_PERIPH_INSEL_REGWEN_30 @ 0x78

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_30

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_30

For MIO_PERIPH_INSEL30

PINMUX.MIO_PERIPH_INSEL_REGWEN_31 @ 0x7c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_31

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_31

For MIO_PERIPH_INSEL31

PINMUX.MIO_PERIPH_INSEL_REGWEN_32 @ 0x80

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_32

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_32

For MIO_PERIPH_INSEL32

PINMUX.MIO_PERIPH_INSEL_REGWEN_33 @ 0x84

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_33

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_33

For MIO_PERIPH_INSEL33

PINMUX.MIO_PERIPH_INSEL_REGWEN_34 @ 0x88

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_34

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_34

For MIO_PERIPH_INSEL34

PINMUX.MIO_PERIPH_INSEL_REGWEN_35 @ 0x8c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_35

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_35

For MIO_PERIPH_INSEL35

PINMUX.MIO_PERIPH_INSEL_REGWEN_36 @ 0x90

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_36

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_36

For MIO_PERIPH_INSEL36

PINMUX.MIO_PERIPH_INSEL_REGWEN_37 @ 0x94

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_37

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_37

For MIO_PERIPH_INSEL37

PINMUX.MIO_PERIPH_INSEL_REGWEN_38 @ 0x98

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_38

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_38

For MIO_PERIPH_INSEL38

PINMUX.MIO_PERIPH_INSEL_REGWEN_39 @ 0x9c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_39

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_39

For MIO_PERIPH_INSEL39

PINMUX.MIO_PERIPH_INSEL_REGWEN_40 @ 0xa0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_40

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_40

For MIO_PERIPH_INSEL40

PINMUX.MIO_PERIPH_INSEL_REGWEN_41 @ 0xa4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_41

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_41

For MIO_PERIPH_INSEL41

PINMUX.MIO_PERIPH_INSEL_REGWEN_42 @ 0xa8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_42

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_42

For MIO_PERIPH_INSEL42

PINMUX.MIO_PERIPH_INSEL_REGWEN_43 @ 0xac

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_43

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_43

For MIO_PERIPH_INSEL43

PINMUX.MIO_PERIPH_INSEL_REGWEN_44 @ 0xb0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_44

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_44

For MIO_PERIPH_INSEL44

PINMUX.MIO_PERIPH_INSEL_REGWEN_45 @ 0xb4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_45

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_45

For MIO_PERIPH_INSEL45

PINMUX.MIO_PERIPH_INSEL_REGWEN_46 @ 0xb8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_46

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_46

For MIO_PERIPH_INSEL46

PINMUX.MIO_PERIPH_INSEL_REGWEN_47 @ 0xbc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_47

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_47

For MIO_PERIPH_INSEL47

PINMUX.MIO_PERIPH_INSEL_REGWEN_48 @ 0xc0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_48

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_48

For MIO_PERIPH_INSEL48

PINMUX.MIO_PERIPH_INSEL_REGWEN_49 @ 0xc4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_49

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_49

For MIO_PERIPH_INSEL49

PINMUX.MIO_PERIPH_INSEL_REGWEN_50 @ 0xc8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_50

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_50

For MIO_PERIPH_INSEL50

PINMUX.MIO_PERIPH_INSEL_REGWEN_51 @ 0xcc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_51

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_51

For MIO_PERIPH_INSEL51

PINMUX.MIO_PERIPH_INSEL_REGWEN_52 @ 0xd0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_52

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_52

For MIO_PERIPH_INSEL52

PINMUX.MIO_PERIPH_INSEL_REGWEN_53 @ 0xd4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_53

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_53

For MIO_PERIPH_INSEL53

PINMUX.MIO_PERIPH_INSEL_REGWEN_54 @ 0xd8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_54

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_54

For MIO_PERIPH_INSEL54

PINMUX.MIO_PERIPH_INSEL_0 @ 0xdc

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_0

Bits

Type

Reset

Name

Description

5:0

0x0

IN_0

0: tie constantly to zero, 1: tie constantly to 1, >=2: MIO pads (i.e., add 2 to the native MIO pad index).

PINMUX.MIO_PERIPH_INSEL_1 @ 0xe0

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_1

Bits

Type

Reset

Name

Description

5:0

0x0

IN_1

For IN1

PINMUX.MIO_PERIPH_INSEL_2 @ 0xe4

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_2

Bits

Type

Reset

Name

Description

5:0

0x0

IN_2

For IN2

PINMUX.MIO_PERIPH_INSEL_3 @ 0xe8

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_3

Bits

Type

Reset

Name

Description

5:0

0x0

IN_3

For IN3

PINMUX.MIO_PERIPH_INSEL_4 @ 0xec

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_4

Bits

Type

Reset

Name

Description

5:0

0x0

IN_4

For IN4

PINMUX.MIO_PERIPH_INSEL_5 @ 0xf0

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_5

Bits

Type

Reset

Name

Description

5:0

0x0

IN_5

For IN5

PINMUX.MIO_PERIPH_INSEL_6 @ 0xf4

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_6

Bits

Type

Reset

Name

Description

5:0

0x0

IN_6

For IN6

PINMUX.MIO_PERIPH_INSEL_7 @ 0xf8

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_7

Bits

Type

Reset

Name

Description

5:0

0x0

IN_7

For IN7

PINMUX.MIO_PERIPH_INSEL_8 @ 0xfc

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_8

Bits

Type

Reset

Name

Description

5:0

0x0

IN_8

For IN8

PINMUX.MIO_PERIPH_INSEL_9 @ 0x100

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_9

Bits

Type

Reset

Name

Description

5:0

0x0

IN_9

For IN9

PINMUX.MIO_PERIPH_INSEL_10 @ 0x104

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_10

Bits

Type

Reset

Name

Description

5:0

0x0

IN_10

For IN10

PINMUX.MIO_PERIPH_INSEL_11 @ 0x108

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_11

Bits

Type

Reset

Name

Description

5:0

0x0

IN_11

For IN11

PINMUX.MIO_PERIPH_INSEL_12 @ 0x10c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_12

Bits

Type

Reset

Name

Description

5:0

0x0

IN_12

For IN12

PINMUX.MIO_PERIPH_INSEL_13 @ 0x110

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_13

Bits

Type

Reset

Name

Description

5:0

0x0

IN_13

For IN13

PINMUX.MIO_PERIPH_INSEL_14 @ 0x114

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_14

Bits

Type

Reset

Name

Description

5:0

0x0

IN_14

For IN14

PINMUX.MIO_PERIPH_INSEL_15 @ 0x118

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_15

Bits

Type

Reset

Name

Description

5:0

0x0

IN_15

For IN15

PINMUX.MIO_PERIPH_INSEL_16 @ 0x11c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_16

Bits

Type

Reset

Name

Description

5:0

0x0

IN_16

For IN16

PINMUX.MIO_PERIPH_INSEL_17 @ 0x120

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_17

Bits

Type

Reset

Name

Description

5:0

0x0

IN_17

For IN17

PINMUX.MIO_PERIPH_INSEL_18 @ 0x124

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_18

Bits

Type

Reset

Name

Description

5:0

0x0

IN_18

For IN18

PINMUX.MIO_PERIPH_INSEL_19 @ 0x128

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_19

Bits

Type

Reset

Name

Description

5:0

0x0

IN_19

For IN19

PINMUX.MIO_PERIPH_INSEL_20 @ 0x12c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_20

Bits

Type

Reset

Name

Description

5:0

0x0

IN_20

For IN20

PINMUX.MIO_PERIPH_INSEL_21 @ 0x130

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_21

Bits

Type

Reset

Name

Description

5:0

0x0

IN_21

For IN21

PINMUX.MIO_PERIPH_INSEL_22 @ 0x134

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_22

Bits

Type

Reset

Name

Description

5:0

0x0

IN_22

For IN22

PINMUX.MIO_PERIPH_INSEL_23 @ 0x138

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_23

Bits

Type

Reset

Name

Description

5:0

0x0

IN_23

For IN23

PINMUX.MIO_PERIPH_INSEL_24 @ 0x13c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_24

Bits

Type

Reset

Name

Description

5:0

0x0

IN_24

For IN24

PINMUX.MIO_PERIPH_INSEL_25 @ 0x140

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_25

Bits

Type

Reset

Name

Description

5:0

0x0

IN_25

For IN25

PINMUX.MIO_PERIPH_INSEL_26 @ 0x144

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_26

Bits

Type

Reset

Name

Description

5:0

0x0

IN_26

For IN26

PINMUX.MIO_PERIPH_INSEL_27 @ 0x148

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_27

Bits

Type

Reset

Name

Description

5:0

0x0

IN_27

For IN27

PINMUX.MIO_PERIPH_INSEL_28 @ 0x14c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_28

Bits

Type

Reset

Name

Description

5:0

0x0

IN_28

For IN28

PINMUX.MIO_PERIPH_INSEL_29 @ 0x150

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_29

Bits

Type

Reset

Name

Description

5:0

0x0

IN_29

For IN29

PINMUX.MIO_PERIPH_INSEL_30 @ 0x154

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_30

Bits

Type

Reset

Name

Description

5:0

0x0

IN_30

For IN30

PINMUX.MIO_PERIPH_INSEL_31 @ 0x158

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_31

Bits

Type

Reset

Name

Description

5:0

0x0

IN_31

For IN31

PINMUX.MIO_PERIPH_INSEL_32 @ 0x15c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_32

Bits

Type

Reset

Name

Description

5:0

0x0

IN_32

For IN32

PINMUX.MIO_PERIPH_INSEL_33 @ 0x160

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_33

Bits

Type

Reset

Name

Description

5:0

0x0

IN_33

For IN33

PINMUX.MIO_PERIPH_INSEL_34 @ 0x164

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_34

Bits

Type

Reset

Name

Description

5:0

0x0

IN_34

For IN34

PINMUX.MIO_PERIPH_INSEL_35 @ 0x168

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_35

Bits

Type

Reset

Name

Description

5:0

0x0

IN_35

For IN35

PINMUX.MIO_PERIPH_INSEL_36 @ 0x16c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_36

Bits

Type

Reset

Name

Description

5:0

0x0

IN_36

For IN36

PINMUX.MIO_PERIPH_INSEL_37 @ 0x170

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_37

Bits

Type

Reset

Name

Description

5:0

0x0

IN_37

For IN37

PINMUX.MIO_PERIPH_INSEL_38 @ 0x174

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_38

Bits

Type

Reset

Name

Description

5:0

0x0

IN_38

For IN38

PINMUX.MIO_PERIPH_INSEL_39 @ 0x178

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_39

Bits

Type

Reset

Name

Description

5:0

0x0

IN_39

For IN39

PINMUX.MIO_PERIPH_INSEL_40 @ 0x17c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_40

Bits

Type

Reset

Name

Description

5:0

0x0

IN_40

For IN40

PINMUX.MIO_PERIPH_INSEL_41 @ 0x180

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_41

Bits

Type

Reset

Name

Description

5:0

0x0

IN_41

For IN41

PINMUX.MIO_PERIPH_INSEL_42 @ 0x184

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_42

Bits

Type

Reset

Name

Description

5:0

0x0

IN_42

For IN42

PINMUX.MIO_PERIPH_INSEL_43 @ 0x188

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_43

Bits

Type

Reset

Name

Description

5:0

0x0

IN_43

For IN43

PINMUX.MIO_PERIPH_INSEL_44 @ 0x18c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_44

Bits

Type

Reset

Name

Description

5:0

0x0

IN_44

For IN44

PINMUX.MIO_PERIPH_INSEL_45 @ 0x190

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_45

Bits

Type

Reset

Name

Description

5:0

0x0

IN_45

For IN45

PINMUX.MIO_PERIPH_INSEL_46 @ 0x194

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_46

Bits

Type

Reset

Name

Description

5:0

0x0

IN_46

For IN46

PINMUX.MIO_PERIPH_INSEL_47 @ 0x198

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_47

Bits

Type

Reset

Name

Description

5:0

0x0

IN_47

For IN47

PINMUX.MIO_PERIPH_INSEL_48 @ 0x19c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_48

Bits

Type

Reset

Name

Description

5:0

0x0

IN_48

For IN48

PINMUX.MIO_PERIPH_INSEL_49 @ 0x1a0

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_49

Bits

Type

Reset

Name

Description

5:0

0x0

IN_49

For IN49

PINMUX.MIO_PERIPH_INSEL_50 @ 0x1a4

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_50

Bits

Type

Reset

Name

Description

5:0

0x0

IN_50

For IN50

PINMUX.MIO_PERIPH_INSEL_51 @ 0x1a8

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_51

Bits

Type

Reset

Name

Description

5:0

0x0

IN_51

For IN51

PINMUX.MIO_PERIPH_INSEL_52 @ 0x1ac

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_52

Bits

Type

Reset

Name

Description

5:0

0x0

IN_52

For IN52

PINMUX.MIO_PERIPH_INSEL_53 @ 0x1b0

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_53

Bits

Type

Reset

Name

Description

5:0

0x0

IN_53

For IN53

PINMUX.MIO_PERIPH_INSEL_54 @ 0x1b4

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_54

Bits

Type

Reset

Name

Description

5:0

0x0

IN_54

For IN54

PINMUX.MIO_OUTSEL_REGWEN_0 @ 0x1b8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_0

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_0

PINMUX.MIO_OUTSEL_REGWEN_1 @ 0x1bc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_1

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_1

For MIO_OUTSEL1

PINMUX.MIO_OUTSEL_REGWEN_2 @ 0x1c0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_2

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_2

For MIO_OUTSEL2

PINMUX.MIO_OUTSEL_REGWEN_3 @ 0x1c4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_3

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_3

For MIO_OUTSEL3

PINMUX.MIO_OUTSEL_REGWEN_4 @ 0x1c8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_4

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_4

For MIO_OUTSEL4

PINMUX.MIO_OUTSEL_REGWEN_5 @ 0x1cc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_5

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_5

For MIO_OUTSEL5

PINMUX.MIO_OUTSEL_REGWEN_6 @ 0x1d0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_6

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_6

For MIO_OUTSEL6

PINMUX.MIO_OUTSEL_REGWEN_7 @ 0x1d4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_7

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_7

For MIO_OUTSEL7

PINMUX.MIO_OUTSEL_REGWEN_8 @ 0x1d8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_8

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_8

For MIO_OUTSEL8

PINMUX.MIO_OUTSEL_REGWEN_9 @ 0x1dc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_9

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_9

For MIO_OUTSEL9

PINMUX.MIO_OUTSEL_REGWEN_10 @ 0x1e0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_10

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_10

For MIO_OUTSEL10

PINMUX.MIO_OUTSEL_REGWEN_11 @ 0x1e4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_11

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_11

For MIO_OUTSEL11

PINMUX.MIO_OUTSEL_REGWEN_12 @ 0x1e8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_12

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_12

For MIO_OUTSEL12

PINMUX.MIO_OUTSEL_REGWEN_13 @ 0x1ec

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_13

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_13

For MIO_OUTSEL13

PINMUX.MIO_OUTSEL_REGWEN_14 @ 0x1f0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_14

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_14

For MIO_OUTSEL14

PINMUX.MIO_OUTSEL_REGWEN_15 @ 0x1f4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_15

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_15

For MIO_OUTSEL15

PINMUX.MIO_OUTSEL_REGWEN_16 @ 0x1f8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_16

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_16

For MIO_OUTSEL16

PINMUX.MIO_OUTSEL_REGWEN_17 @ 0x1fc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_17

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_17

For MIO_OUTSEL17

PINMUX.MIO_OUTSEL_REGWEN_18 @ 0x200

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_18

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_18

For MIO_OUTSEL18

PINMUX.MIO_OUTSEL_REGWEN_19 @ 0x204

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_19

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_19

For MIO_OUTSEL19

PINMUX.MIO_OUTSEL_REGWEN_20 @ 0x208

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_20

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_20

For MIO_OUTSEL20

PINMUX.MIO_OUTSEL_REGWEN_21 @ 0x20c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_21

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_21

For MIO_OUTSEL21

PINMUX.MIO_OUTSEL_REGWEN_22 @ 0x210

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_22

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_22

For MIO_OUTSEL22

PINMUX.MIO_OUTSEL_REGWEN_23 @ 0x214

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_23

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_23

For MIO_OUTSEL23

PINMUX.MIO_OUTSEL_REGWEN_24 @ 0x218

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_24

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_24

For MIO_OUTSEL24

PINMUX.MIO_OUTSEL_REGWEN_25 @ 0x21c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_25

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_25

For MIO_OUTSEL25

PINMUX.MIO_OUTSEL_REGWEN_26 @ 0x220

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_26

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_26

For MIO_OUTSEL26

PINMUX.MIO_OUTSEL_REGWEN_27 @ 0x224

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_27

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_27

For MIO_OUTSEL27

PINMUX.MIO_OUTSEL_REGWEN_28 @ 0x228

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_28

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_28

For MIO_OUTSEL28

PINMUX.MIO_OUTSEL_REGWEN_29 @ 0x22c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_29

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_29

For MIO_OUTSEL29

PINMUX.MIO_OUTSEL_REGWEN_30 @ 0x230

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_30

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_30

For MIO_OUTSEL30

PINMUX.MIO_OUTSEL_REGWEN_31 @ 0x234

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_31

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_31

For MIO_OUTSEL31

PINMUX.MIO_OUTSEL_REGWEN_32 @ 0x238

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_32

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_32

For MIO_OUTSEL32

PINMUX.MIO_OUTSEL_REGWEN_33 @ 0x23c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_33

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_33

For MIO_OUTSEL33

PINMUX.MIO_OUTSEL_REGWEN_34 @ 0x240

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_34

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_34

For MIO_OUTSEL34

PINMUX.MIO_OUTSEL_REGWEN_35 @ 0x244

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_35

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_35

For MIO_OUTSEL35

PINMUX.MIO_OUTSEL_REGWEN_36 @ 0x248

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_36

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_36

For MIO_OUTSEL36

PINMUX.MIO_OUTSEL_REGWEN_37 @ 0x24c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_37

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_37

For MIO_OUTSEL37

PINMUX.MIO_OUTSEL_REGWEN_38 @ 0x250

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_38

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_38

For MIO_OUTSEL38

PINMUX.MIO_OUTSEL_REGWEN_39 @ 0x254

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_39

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_39

For MIO_OUTSEL39

PINMUX.MIO_OUTSEL_REGWEN_40 @ 0x258

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_40

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_40

For MIO_OUTSEL40

PINMUX.MIO_OUTSEL_REGWEN_41 @ 0x25c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_41

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_41

For MIO_OUTSEL41

PINMUX.MIO_OUTSEL_REGWEN_42 @ 0x260

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_42

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_42

For MIO_OUTSEL42

PINMUX.MIO_OUTSEL_REGWEN_43 @ 0x264

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_43

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_43

For MIO_OUTSEL43

PINMUX.MIO_OUTSEL_REGWEN_44 @ 0x268

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_44

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_44

For MIO_OUTSEL44

PINMUX.MIO_OUTSEL_REGWEN_45 @ 0x26c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_45

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_45

For MIO_OUTSEL45

PINMUX.MIO_OUTSEL_REGWEN_46 @ 0x270

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_46

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_46

For MIO_OUTSEL46

PINMUX.MIO_OUTSEL_0 @ 0x274

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_0

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_0

0: tie constantly to zero, 1: tie constantly to 1, 2: high-Z, >=3: peripheral outputs (i.e., add 3 to the native peripheral pad index).

PINMUX.MIO_OUTSEL_1 @ 0x278

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_1

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_1

For OUT1

PINMUX.MIO_OUTSEL_2 @ 0x27c

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_2

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_2

For OUT2

PINMUX.MIO_OUTSEL_3 @ 0x280

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_3

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_3

For OUT3

PINMUX.MIO_OUTSEL_4 @ 0x284

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_4

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_4

For OUT4

PINMUX.MIO_OUTSEL_5 @ 0x288

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_5

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_5

For OUT5

PINMUX.MIO_OUTSEL_6 @ 0x28c

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_6

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_6

For OUT6

PINMUX.MIO_OUTSEL_7 @ 0x290

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_7

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_7

For OUT7

PINMUX.MIO_OUTSEL_8 @ 0x294

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_8

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_8

For OUT8

PINMUX.MIO_OUTSEL_9 @ 0x298

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_9

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_9

For OUT9

PINMUX.MIO_OUTSEL_10 @ 0x29c

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_10

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_10

For OUT10

PINMUX.MIO_OUTSEL_11 @ 0x2a0

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_11

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_11

For OUT11

PINMUX.MIO_OUTSEL_12 @ 0x2a4

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_12

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_12

For OUT12

PINMUX.MIO_OUTSEL_13 @ 0x2a8

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_13

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_13

For OUT13

PINMUX.MIO_OUTSEL_14 @ 0x2ac

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_14

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_14

For OUT14

PINMUX.MIO_OUTSEL_15 @ 0x2b0

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_15

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_15

For OUT15

PINMUX.MIO_OUTSEL_16 @ 0x2b4

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_16

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_16

For OUT16

PINMUX.MIO_OUTSEL_17 @ 0x2b8

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_17

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_17

For OUT17

PINMUX.MIO_OUTSEL_18 @ 0x2bc

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_18

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_18

For OUT18

PINMUX.MIO_OUTSEL_19 @ 0x2c0

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_19

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_19

For OUT19

PINMUX.MIO_OUTSEL_20 @ 0x2c4

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_20

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_20

For OUT20

PINMUX.MIO_OUTSEL_21 @ 0x2c8

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_21

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_21

For OUT21

PINMUX.MIO_OUTSEL_22 @ 0x2cc

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_22

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_22

For OUT22

PINMUX.MIO_OUTSEL_23 @ 0x2d0

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_23

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_23

For OUT23

PINMUX.MIO_OUTSEL_24 @ 0x2d4

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_24

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_24

For OUT24

PINMUX.MIO_OUTSEL_25 @ 0x2d8

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_25

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_25

For OUT25

PINMUX.MIO_OUTSEL_26 @ 0x2dc

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_26

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_26

For OUT26

PINMUX.MIO_OUTSEL_27 @ 0x2e0

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_27

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_27

For OUT27

PINMUX.MIO_OUTSEL_28 @ 0x2e4

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_28

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_28

For OUT28

PINMUX.MIO_OUTSEL_29 @ 0x2e8

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_29

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_29

For OUT29

PINMUX.MIO_OUTSEL_30 @ 0x2ec

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_30

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_30

For OUT30

PINMUX.MIO_OUTSEL_31 @ 0x2f0

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_31

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_31

For OUT31

PINMUX.MIO_OUTSEL_32 @ 0x2f4

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_32

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_32

For OUT32

PINMUX.MIO_OUTSEL_33 @ 0x2f8

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_33

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_33

For OUT33

PINMUX.MIO_OUTSEL_34 @ 0x2fc

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_34

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_34

For OUT34

PINMUX.MIO_OUTSEL_35 @ 0x300

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_35

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_35

For OUT35

PINMUX.MIO_OUTSEL_36 @ 0x304

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_36

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_36

For OUT36

PINMUX.MIO_OUTSEL_37 @ 0x308

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_37

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_37

For OUT37

PINMUX.MIO_OUTSEL_38 @ 0x30c

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_38

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_38

For OUT38

PINMUX.MIO_OUTSEL_39 @ 0x310

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_39

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_39

For OUT39

PINMUX.MIO_OUTSEL_40 @ 0x314

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_40

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_40

For OUT40

PINMUX.MIO_OUTSEL_41 @ 0x318

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_41

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_41

For OUT41

PINMUX.MIO_OUTSEL_42 @ 0x31c

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_42

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_42

For OUT42

PINMUX.MIO_OUTSEL_43 @ 0x320

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_43

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_43

For OUT43

PINMUX.MIO_OUTSEL_44 @ 0x324

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_44

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_44

For OUT44

PINMUX.MIO_OUTSEL_45 @ 0x328

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_45

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_45

For OUT45

PINMUX.MIO_OUTSEL_46 @ 0x32c

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_46

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_46

For OUT46

PINMUX.MIO_PAD_ATTR_REGWEN_0 @ 0x330

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_0

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_0

PINMUX.MIO_PAD_ATTR_REGWEN_1 @ 0x334

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_1

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_1

For MIO_PAD1

PINMUX.MIO_PAD_ATTR_REGWEN_2 @ 0x338

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_2

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_2

For MIO_PAD2

PINMUX.MIO_PAD_ATTR_REGWEN_3 @ 0x33c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_3

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_3

For MIO_PAD3

PINMUX.MIO_PAD_ATTR_REGWEN_4 @ 0x340

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_4

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_4

For MIO_PAD4

PINMUX.MIO_PAD_ATTR_REGWEN_5 @ 0x344

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_5

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_5

For MIO_PAD5

PINMUX.MIO_PAD_ATTR_REGWEN_6 @ 0x348

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_6

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_6

For MIO_PAD6

PINMUX.MIO_PAD_ATTR_REGWEN_7 @ 0x34c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_7

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_7

For MIO_PAD7

PINMUX.MIO_PAD_ATTR_REGWEN_8 @ 0x350

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_8

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_8

For MIO_PAD8

PINMUX.MIO_PAD_ATTR_REGWEN_9 @ 0x354

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_9

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_9

For MIO_PAD9

PINMUX.MIO_PAD_ATTR_REGWEN_10 @ 0x358

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_10

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_10

For MIO_PAD10

PINMUX.MIO_PAD_ATTR_REGWEN_11 @ 0x35c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_11

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_11

For MIO_PAD11

PINMUX.MIO_PAD_ATTR_REGWEN_12 @ 0x360

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_12

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_12

For MIO_PAD12

PINMUX.MIO_PAD_ATTR_REGWEN_13 @ 0x364

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_13

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_13

For MIO_PAD13

PINMUX.MIO_PAD_ATTR_REGWEN_14 @ 0x368

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_14

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_14

For MIO_PAD14

PINMUX.MIO_PAD_ATTR_REGWEN_15 @ 0x36c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_15

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_15

For MIO_PAD15

PINMUX.MIO_PAD_ATTR_REGWEN_16 @ 0x370

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_16

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_16

For MIO_PAD16

PINMUX.MIO_PAD_ATTR_REGWEN_17 @ 0x374

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_17

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_17

For MIO_PAD17

PINMUX.MIO_PAD_ATTR_REGWEN_18 @ 0x378

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_18

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_18

For MIO_PAD18

PINMUX.MIO_PAD_ATTR_REGWEN_19 @ 0x37c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_19

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_19

For MIO_PAD19

PINMUX.MIO_PAD_ATTR_REGWEN_20 @ 0x380

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_20

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_20

For MIO_PAD20

PINMUX.MIO_PAD_ATTR_REGWEN_21 @ 0x384

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_21

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_21

For MIO_PAD21

PINMUX.MIO_PAD_ATTR_REGWEN_22 @ 0x388

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_22

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_22

For MIO_PAD22

PINMUX.MIO_PAD_ATTR_REGWEN_23 @ 0x38c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_23

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_23

For MIO_PAD23

PINMUX.MIO_PAD_ATTR_REGWEN_24 @ 0x390

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_24

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_24

For MIO_PAD24

PINMUX.MIO_PAD_ATTR_REGWEN_25 @ 0x394

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_25

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_25

For MIO_PAD25

PINMUX.MIO_PAD_ATTR_REGWEN_26 @ 0x398

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_26

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_26

For MIO_PAD26

PINMUX.MIO_PAD_ATTR_REGWEN_27 @ 0x39c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_27

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_27

For MIO_PAD27

PINMUX.MIO_PAD_ATTR_REGWEN_28 @ 0x3a0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_28

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_28

For MIO_PAD28

PINMUX.MIO_PAD_ATTR_REGWEN_29 @ 0x3a4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_29

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_29

For MIO_PAD29

PINMUX.MIO_PAD_ATTR_REGWEN_30 @ 0x3a8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_30

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_30

For MIO_PAD30

PINMUX.MIO_PAD_ATTR_REGWEN_31 @ 0x3ac

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_31

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_31

For MIO_PAD31

PINMUX.MIO_PAD_ATTR_REGWEN_32 @ 0x3b0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_32

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_32

For MIO_PAD32

PINMUX.MIO_PAD_ATTR_REGWEN_33 @ 0x3b4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_33

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_33

For MIO_PAD33

PINMUX.MIO_PAD_ATTR_REGWEN_34 @ 0x3b8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_34

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_34

For MIO_PAD34

PINMUX.MIO_PAD_ATTR_REGWEN_35 @ 0x3bc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_35

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_35

For MIO_PAD35

PINMUX.MIO_PAD_ATTR_REGWEN_36 @ 0x3c0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_36

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_36

For MIO_PAD36

PINMUX.MIO_PAD_ATTR_REGWEN_37 @ 0x3c4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_37

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_37

For MIO_PAD37

PINMUX.MIO_PAD_ATTR_REGWEN_38 @ 0x3c8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_38

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_38

For MIO_PAD38

PINMUX.MIO_PAD_ATTR_REGWEN_39 @ 0x3cc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_39

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_39

For MIO_PAD39

PINMUX.MIO_PAD_ATTR_REGWEN_40 @ 0x3d0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_40

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_40

For MIO_PAD40

PINMUX.MIO_PAD_ATTR_REGWEN_41 @ 0x3d4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_41

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_41

For MIO_PAD41

PINMUX.MIO_PAD_ATTR_REGWEN_42 @ 0x3d8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_42

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_42

For MIO_PAD42

PINMUX.MIO_PAD_ATTR_REGWEN_43 @ 0x3dc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_43

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_43

For MIO_PAD43

PINMUX.MIO_PAD_ATTR_REGWEN_44 @ 0x3e0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_44

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_44

For MIO_PAD44

PINMUX.MIO_PAD_ATTR_REGWEN_45 @ 0x3e4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_45

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_45

For MIO_PAD45

PINMUX.MIO_PAD_ATTR_REGWEN_46 @ 0x3e8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_46

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_46

For MIO_PAD46

PINMUX.MIO_PAD_ATTR_0 @ 0x3ec

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_0

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_0

Bit 0: input/output inversion, Bit 1: Virtual open drain enable. Bit 2: Pull enable. Bit 3: Pull select (0: pull down, 1: pull up). Bit 4: Keeper enable. Bit 5: Schmitt trigger enable. Bit 6: Open drain enable Bit 7/8: Slew rate (0x0: slowest, 0x3: fastest). Bit 9/12: Drive strength (0x0: weakest, 0xf: strongest).

PINMUX.MIO_PAD_ATTR_1 @ 0x3f0

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_1

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_1

For MIO_PAD1

PINMUX.MIO_PAD_ATTR_2 @ 0x3f4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_2

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_2

For MIO_PAD2

PINMUX.MIO_PAD_ATTR_3 @ 0x3f8

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_3

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_3

For MIO_PAD3

PINMUX.MIO_PAD_ATTR_4 @ 0x3fc

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_4

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_4

For MIO_PAD4

PINMUX.MIO_PAD_ATTR_5 @ 0x400

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_5

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_5

For MIO_PAD5

PINMUX.MIO_PAD_ATTR_6 @ 0x404

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_6

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_6

For MIO_PAD6

PINMUX.MIO_PAD_ATTR_7 @ 0x408

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_7

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_7

For MIO_PAD7

PINMUX.MIO_PAD_ATTR_8 @ 0x40c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_8

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_8

For MIO_PAD8

PINMUX.MIO_PAD_ATTR_9 @ 0x410

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_9

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_9

For MIO_PAD9

PINMUX.MIO_PAD_ATTR_10 @ 0x414

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_10

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_10

For MIO_PAD10

PINMUX.MIO_PAD_ATTR_11 @ 0x418

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_11

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_11

For MIO_PAD11

PINMUX.MIO_PAD_ATTR_12 @ 0x41c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_12

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_12

For MIO_PAD12

PINMUX.MIO_PAD_ATTR_13 @ 0x420

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_13

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_13

For MIO_PAD13

PINMUX.MIO_PAD_ATTR_14 @ 0x424

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_14

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_14

For MIO_PAD14

PINMUX.MIO_PAD_ATTR_15 @ 0x428

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_15

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_15

For MIO_PAD15

PINMUX.MIO_PAD_ATTR_16 @ 0x42c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_16

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_16

For MIO_PAD16

PINMUX.MIO_PAD_ATTR_17 @ 0x430

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_17

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_17

For MIO_PAD17

PINMUX.MIO_PAD_ATTR_18 @ 0x434

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_18

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_18

For MIO_PAD18

PINMUX.MIO_PAD_ATTR_19 @ 0x438

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_19

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_19

For MIO_PAD19

PINMUX.MIO_PAD_ATTR_20 @ 0x43c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_20

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_20

For MIO_PAD20

PINMUX.MIO_PAD_ATTR_21 @ 0x440

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_21

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_21

For MIO_PAD21

PINMUX.MIO_PAD_ATTR_22 @ 0x444

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_22

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_22

For MIO_PAD22

PINMUX.MIO_PAD_ATTR_23 @ 0x448

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_23

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_23

For MIO_PAD23

PINMUX.MIO_PAD_ATTR_24 @ 0x44c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_24

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_24

For MIO_PAD24

PINMUX.MIO_PAD_ATTR_25 @ 0x450

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_25

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_25

For MIO_PAD25

PINMUX.MIO_PAD_ATTR_26 @ 0x454

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_26

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_26

For MIO_PAD26

PINMUX.MIO_PAD_ATTR_27 @ 0x458

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_27

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_27

For MIO_PAD27

PINMUX.MIO_PAD_ATTR_28 @ 0x45c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_28

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_28

For MIO_PAD28

PINMUX.MIO_PAD_ATTR_29 @ 0x460

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_29

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_29

For MIO_PAD29

PINMUX.MIO_PAD_ATTR_30 @ 0x464

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_30

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_30

For MIO_PAD30

PINMUX.MIO_PAD_ATTR_31 @ 0x468

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_31

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_31

For MIO_PAD31

PINMUX.MIO_PAD_ATTR_32 @ 0x46c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_32

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_32

For MIO_PAD32

PINMUX.MIO_PAD_ATTR_33 @ 0x470

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_33

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_33

For MIO_PAD33

PINMUX.MIO_PAD_ATTR_34 @ 0x474

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_34

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_34

For MIO_PAD34

PINMUX.MIO_PAD_ATTR_35 @ 0x478

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_35

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_35

For MIO_PAD35

PINMUX.MIO_PAD_ATTR_36 @ 0x47c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_36

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_36

For MIO_PAD36

PINMUX.MIO_PAD_ATTR_37 @ 0x480

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_37

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_37

For MIO_PAD37

PINMUX.MIO_PAD_ATTR_38 @ 0x484

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_38

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_38

For MIO_PAD38

PINMUX.MIO_PAD_ATTR_39 @ 0x488

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_39

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_39

For MIO_PAD39

PINMUX.MIO_PAD_ATTR_40 @ 0x48c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_40

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_40

For MIO_PAD40

PINMUX.MIO_PAD_ATTR_41 @ 0x490

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_41

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_41

For MIO_PAD41

PINMUX.MIO_PAD_ATTR_42 @ 0x494

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_42

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_42

For MIO_PAD42

PINMUX.MIO_PAD_ATTR_43 @ 0x498

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_43

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_43

For MIO_PAD43

PINMUX.MIO_PAD_ATTR_44 @ 0x49c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_44

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_44

For MIO_PAD44

PINMUX.MIO_PAD_ATTR_45 @ 0x4a0

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_45

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_45

For MIO_PAD45

PINMUX.MIO_PAD_ATTR_46 @ 0x4a4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_46

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_46

For MIO_PAD46

PINMUX.DIO_PAD_ATTR_REGWEN_0 @ 0x4a8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_0

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_0

PINMUX.DIO_PAD_ATTR_REGWEN_1 @ 0x4ac

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_1

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_1

For DIO_PAD1

PINMUX.DIO_PAD_ATTR_REGWEN_2 @ 0x4b0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_2

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_2

For DIO_PAD2

PINMUX.DIO_PAD_ATTR_REGWEN_3 @ 0x4b4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_3

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_3

For DIO_PAD3

PINMUX.DIO_PAD_ATTR_REGWEN_4 @ 0x4b8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_4

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_4

For DIO_PAD4

PINMUX.DIO_PAD_ATTR_REGWEN_5 @ 0x4bc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_5

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_5

For DIO_PAD5

PINMUX.DIO_PAD_ATTR_REGWEN_6 @ 0x4c0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_6

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_6

For DIO_PAD6

PINMUX.DIO_PAD_ATTR_REGWEN_7 @ 0x4c4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_7

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_7

For DIO_PAD7

PINMUX.DIO_PAD_ATTR_REGWEN_8 @ 0x4c8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_8

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_8

For DIO_PAD8

PINMUX.DIO_PAD_ATTR_REGWEN_9 @ 0x4cc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_9

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_9

For DIO_PAD9

PINMUX.DIO_PAD_ATTR_REGWEN_10 @ 0x4d0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_10

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_10

For DIO_PAD10

PINMUX.DIO_PAD_ATTR_REGWEN_11 @ 0x4d4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_11

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_11

For DIO_PAD11

PINMUX.DIO_PAD_ATTR_REGWEN_12 @ 0x4d8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_12

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_12

For DIO_PAD12

PINMUX.DIO_PAD_ATTR_REGWEN_13 @ 0x4dc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_13

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_13

For DIO_PAD13

PINMUX.DIO_PAD_ATTR_REGWEN_14 @ 0x4e0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_14

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_14

For DIO_PAD14

PINMUX.DIO_PAD_ATTR_REGWEN_15 @ 0x4e4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_15

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_15

For DIO_PAD15

PINMUX.DIO_PAD_ATTR_REGWEN_16 @ 0x4e8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_16

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_16

For DIO_PAD16

PINMUX.DIO_PAD_ATTR_REGWEN_17 @ 0x4ec

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_17

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_17

For DIO_PAD17

PINMUX.DIO_PAD_ATTR_REGWEN_18 @ 0x4f0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_18

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_18

For DIO_PAD18

PINMUX.DIO_PAD_ATTR_REGWEN_19 @ 0x4f4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_19

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_19

For DIO_PAD19

PINMUX.DIO_PAD_ATTR_REGWEN_20 @ 0x4f8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_20

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_20

For DIO_PAD20

PINMUX.DIO_PAD_ATTR_REGWEN_21 @ 0x4fc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_21

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_21

For DIO_PAD21

PINMUX.DIO_PAD_ATTR_REGWEN_22 @ 0x500

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_22

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_22

For DIO_PAD22

PINMUX.DIO_PAD_ATTR_REGWEN_23 @ 0x504

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_23

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_23

For DIO_PAD23

PINMUX.DIO_PAD_ATTR_0 @ 0x508

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_0

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_0

PINMUX.DIO_PAD_ATTR_1 @ 0x50c

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_1

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_1

For DIO_PAD1

PINMUX.DIO_PAD_ATTR_2 @ 0x510

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_2

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_2

For DIO_PAD2

PINMUX.DIO_PAD_ATTR_3 @ 0x514

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_3

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_3

For DIO_PAD3

PINMUX.DIO_PAD_ATTR_4 @ 0x518

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_4

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_4

For DIO_PAD4

PINMUX.DIO_PAD_ATTR_5 @ 0x51c

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_5

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_5

For DIO_PAD5

PINMUX.DIO_PAD_ATTR_6 @ 0x520

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_6

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_6

For DIO_PAD6

PINMUX.DIO_PAD_ATTR_7 @ 0x524

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_7

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_7

For DIO_PAD7

PINMUX.DIO_PAD_ATTR_8 @ 0x528

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_8

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_8

For DIO_PAD8

PINMUX.DIO_PAD_ATTR_9 @ 0x52c

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_9

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_9

For DIO_PAD9

PINMUX.DIO_PAD_ATTR_10 @ 0x530

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_10

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_10

For DIO_PAD10

PINMUX.DIO_PAD_ATTR_11 @ 0x534

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_11

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_11

For DIO_PAD11

PINMUX.DIO_PAD_ATTR_12 @ 0x538

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_12

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_12

For DIO_PAD12

PINMUX.DIO_PAD_ATTR_13 @ 0x53c

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_13

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_13

For DIO_PAD13

PINMUX.DIO_PAD_ATTR_14 @ 0x540

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_14

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_14

For DIO_PAD14

PINMUX.DIO_PAD_ATTR_15 @ 0x544

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_15

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_15

For DIO_PAD15

PINMUX.DIO_PAD_ATTR_16 @ 0x548

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_16

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_16

For DIO_PAD16

PINMUX.DIO_PAD_ATTR_17 @ 0x54c

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_17

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_17

For DIO_PAD17

PINMUX.DIO_PAD_ATTR_18 @ 0x550

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_18

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_18

For DIO_PAD18

PINMUX.DIO_PAD_ATTR_19 @ 0x554

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_19

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_19

For DIO_PAD19

PINMUX.DIO_PAD_ATTR_20 @ 0x558

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_20

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_20

For DIO_PAD20

PINMUX.DIO_PAD_ATTR_21 @ 0x55c

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_21

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_21

For DIO_PAD21

PINMUX.DIO_PAD_ATTR_22 @ 0x560

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_22

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_22

For DIO_PAD22

PINMUX.DIO_PAD_ATTR_23 @ 0x564

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ATTR_23

Bits

Type

Reset

Name

Description

12:0

0x0

ATTR_23

For DIO_PAD23

PINMUX.MIO_PAD_SLEEP_STATUS_0 @ 0x568

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EN_31	EN_30	EN_29	EN_28	EN_27	EN_26	EN_25	EN_24	EN_23	EN_22	EN_21	EN_20	EN_19	EN_18	EN_17	EN_16
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EN_15	EN_14	EN_13	EN_12	EN_11	EN_10	EN_9	EN_8	EN_7	EN_6	EN_5	EN_4	EN_3	EN_2	EN_1	EN_0

Bits

Type

Reset

Name

Description

rw0c

0x0

EN_0

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

rw0c

0x0

EN_1

rw0c

0x0

EN_2

rw0c

0x0

EN_3

rw0c

0x0

EN_4

rw0c

0x0

EN_5

rw0c

0x0

EN_6

rw0c

0x0

EN_7

rw0c

0x0

EN_8

rw0c

0x0

EN_9

rw0c

0x0

EN_10

rw0c

0x0

EN_11

rw0c

0x0

EN_12

rw0c

0x0

EN_13

rw0c

0x0

EN_14

rw0c

0x0

EN_15

rw0c

0x0

EN_16

rw0c

0x0

EN_17

rw0c

0x0

EN_18

rw0c

0x0

EN_19

rw0c

0x0

EN_20

rw0c

0x0

EN_21

rw0c

0x0

EN_22

rw0c

0x0

EN_23

rw0c

0x0

EN_24

rw0c

0x0

EN_25

rw0c

0x0

EN_26

rw0c

0x0

EN_27

rw0c

0x0

EN_28

rw0c

0x0

EN_29

rw0c

0x0

EN_30

rw0c

0x0

EN_31

PINMUX.MIO_PAD_SLEEP_STATUS_1 @ 0x56c

Reset default = 0x0, mask 0x7fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	EN_46	EN_45	EN_44	EN_43	EN_42	EN_41	EN_40	EN_39	EN_38	EN_37	EN_36	EN_35	EN_34	EN_33	EN_32

Bits

Type

Reset

Name

Description

rw0c

0x0

EN_32

For MIO_PAD1

rw0c

0x0

EN_33

For MIO_PAD1

rw0c

0x0

EN_34

For MIO_PAD1

rw0c

0x0

EN_35

For MIO_PAD1

rw0c

0x0

EN_36

For MIO_PAD1

rw0c

0x0

EN_37

For MIO_PAD1

rw0c

0x0

EN_38

For MIO_PAD1

rw0c

0x0

EN_39

For MIO_PAD1

rw0c

0x0

EN_40

For MIO_PAD1

rw0c

0x0

EN_41

For MIO_PAD1

rw0c

0x0

EN_42

For MIO_PAD1

rw0c

0x0

EN_43

For MIO_PAD1

rw0c

0x0

EN_44

For MIO_PAD1

rw0c

0x0

EN_45

For MIO_PAD1

rw0c

0x0

EN_46

For MIO_PAD1

PINMUX.MIO_PAD_SLEEP_REGWEN_0 @ 0x570

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_0

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_0

PINMUX.MIO_PAD_SLEEP_REGWEN_1 @ 0x574

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_1

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_1

For MIO_PAD1

PINMUX.MIO_PAD_SLEEP_REGWEN_2 @ 0x578

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_2

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_2

For MIO_PAD2

PINMUX.MIO_PAD_SLEEP_REGWEN_3 @ 0x57c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_3

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_3

For MIO_PAD3

PINMUX.MIO_PAD_SLEEP_REGWEN_4 @ 0x580

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_4

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_4

For MIO_PAD4

PINMUX.MIO_PAD_SLEEP_REGWEN_5 @ 0x584

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_5

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_5

For MIO_PAD5

PINMUX.MIO_PAD_SLEEP_REGWEN_6 @ 0x588

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_6

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_6

For MIO_PAD6

PINMUX.MIO_PAD_SLEEP_REGWEN_7 @ 0x58c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_7

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_7

For MIO_PAD7

PINMUX.MIO_PAD_SLEEP_REGWEN_8 @ 0x590

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_8

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_8

For MIO_PAD8

PINMUX.MIO_PAD_SLEEP_REGWEN_9 @ 0x594

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_9

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_9

For MIO_PAD9

PINMUX.MIO_PAD_SLEEP_REGWEN_10 @ 0x598

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_10

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_10

For MIO_PAD10

PINMUX.MIO_PAD_SLEEP_REGWEN_11 @ 0x59c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_11

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_11

For MIO_PAD11

PINMUX.MIO_PAD_SLEEP_REGWEN_12 @ 0x5a0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_12

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_12

For MIO_PAD12

PINMUX.MIO_PAD_SLEEP_REGWEN_13 @ 0x5a4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_13

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_13

For MIO_PAD13

PINMUX.MIO_PAD_SLEEP_REGWEN_14 @ 0x5a8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_14

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_14

For MIO_PAD14

PINMUX.MIO_PAD_SLEEP_REGWEN_15 @ 0x5ac

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_15

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_15

For MIO_PAD15

PINMUX.MIO_PAD_SLEEP_REGWEN_16 @ 0x5b0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_16

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_16

For MIO_PAD16

PINMUX.MIO_PAD_SLEEP_REGWEN_17 @ 0x5b4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_17

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_17

For MIO_PAD17

PINMUX.MIO_PAD_SLEEP_REGWEN_18 @ 0x5b8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_18

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_18

For MIO_PAD18

PINMUX.MIO_PAD_SLEEP_REGWEN_19 @ 0x5bc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_19

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_19

For MIO_PAD19

PINMUX.MIO_PAD_SLEEP_REGWEN_20 @ 0x5c0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_20

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_20

For MIO_PAD20

PINMUX.MIO_PAD_SLEEP_REGWEN_21 @ 0x5c4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_21

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_21

For MIO_PAD21

PINMUX.MIO_PAD_SLEEP_REGWEN_22 @ 0x5c8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_22

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_22

For MIO_PAD22

PINMUX.MIO_PAD_SLEEP_REGWEN_23 @ 0x5cc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_23

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_23

For MIO_PAD23

PINMUX.MIO_PAD_SLEEP_REGWEN_24 @ 0x5d0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_24

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_24

For MIO_PAD24

PINMUX.MIO_PAD_SLEEP_REGWEN_25 @ 0x5d4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_25

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_25

For MIO_PAD25

PINMUX.MIO_PAD_SLEEP_REGWEN_26 @ 0x5d8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_26

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_26

For MIO_PAD26

PINMUX.MIO_PAD_SLEEP_REGWEN_27 @ 0x5dc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_27

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_27

For MIO_PAD27

PINMUX.MIO_PAD_SLEEP_REGWEN_28 @ 0x5e0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_28

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_28

For MIO_PAD28

PINMUX.MIO_PAD_SLEEP_REGWEN_29 @ 0x5e4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_29

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_29

For MIO_PAD29

PINMUX.MIO_PAD_SLEEP_REGWEN_30 @ 0x5e8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_30

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_30

For MIO_PAD30

PINMUX.MIO_PAD_SLEEP_REGWEN_31 @ 0x5ec

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_31

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_31

For MIO_PAD31

PINMUX.MIO_PAD_SLEEP_REGWEN_32 @ 0x5f0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_32

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_32

For MIO_PAD32

PINMUX.MIO_PAD_SLEEP_REGWEN_33 @ 0x5f4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_33

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_33

For MIO_PAD33

PINMUX.MIO_PAD_SLEEP_REGWEN_34 @ 0x5f8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_34

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_34

For MIO_PAD34

PINMUX.MIO_PAD_SLEEP_REGWEN_35 @ 0x5fc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_35

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_35

For MIO_PAD35

PINMUX.MIO_PAD_SLEEP_REGWEN_36 @ 0x600

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_36

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_36

For MIO_PAD36

PINMUX.MIO_PAD_SLEEP_REGWEN_37 @ 0x604

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_37

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_37

For MIO_PAD37

PINMUX.MIO_PAD_SLEEP_REGWEN_38 @ 0x608

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_38

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_38

For MIO_PAD38

PINMUX.MIO_PAD_SLEEP_REGWEN_39 @ 0x60c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_39

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_39

For MIO_PAD39

PINMUX.MIO_PAD_SLEEP_REGWEN_40 @ 0x610

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_40

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_40

For MIO_PAD40

PINMUX.MIO_PAD_SLEEP_REGWEN_41 @ 0x614

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_41

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_41

For MIO_PAD41

PINMUX.MIO_PAD_SLEEP_REGWEN_42 @ 0x618

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_42

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_42

For MIO_PAD42

PINMUX.MIO_PAD_SLEEP_REGWEN_43 @ 0x61c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_43

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_43

For MIO_PAD43

PINMUX.MIO_PAD_SLEEP_REGWEN_44 @ 0x620

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_44

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_44

For MIO_PAD44

PINMUX.MIO_PAD_SLEEP_REGWEN_45 @ 0x624

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_45

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_45

For MIO_PAD45

PINMUX.MIO_PAD_SLEEP_REGWEN_46 @ 0x628

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_46

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_46

For MIO_PAD46

PINMUX.MIO_PAD_SLEEP_EN_0 @ 0x62c

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_0

Bits

Type

Reset

Name

Description

0x0

EN_0

Deep sleep mode enable. If this bit is set to 1 the corresponding pad will enable the sleep behavior specified in !!MIO_PAD_SLEEP_MODE upon deep sleep entry, and the corresponding bit in !!MIO_PAD_SLEEP_STATUS will be set to 1. The pad remains in deep sleep mode until the corresponding bit in !!MIO_PAD_SLEEP_STATUS is cleared by SW. Note that if an always on peripheral is connected to a specific MIO pad, the corresponding !!MIO_PAD_SLEEP_EN bit should be set to 0.

PINMUX.MIO_PAD_SLEEP_EN_1 @ 0x630

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_1

Bits

Type

Reset

Name

Description

0x0

EN_1

For OUT1

PINMUX.MIO_PAD_SLEEP_EN_2 @ 0x634

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_2

Bits

Type

Reset

Name

Description

0x0

EN_2

For OUT2

PINMUX.MIO_PAD_SLEEP_EN_3 @ 0x638

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_3

Bits

Type

Reset

Name

Description

0x0

EN_3

For OUT3

PINMUX.MIO_PAD_SLEEP_EN_4 @ 0x63c

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_4

Bits

Type

Reset

Name

Description

0x0

EN_4

For OUT4

PINMUX.MIO_PAD_SLEEP_EN_5 @ 0x640

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_5

Bits

Type

Reset

Name

Description

0x0

EN_5

For OUT5

PINMUX.MIO_PAD_SLEEP_EN_6 @ 0x644

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_6

Bits

Type

Reset

Name

Description

0x0

EN_6

For OUT6

PINMUX.MIO_PAD_SLEEP_EN_7 @ 0x648

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_7

Bits

Type

Reset

Name

Description

0x0

EN_7

For OUT7

PINMUX.MIO_PAD_SLEEP_EN_8 @ 0x64c

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_8

Bits

Type

Reset

Name

Description

0x0

EN_8

For OUT8

PINMUX.MIO_PAD_SLEEP_EN_9 @ 0x650

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_9

Bits

Type

Reset

Name

Description

0x0

EN_9

For OUT9

PINMUX.MIO_PAD_SLEEP_EN_10 @ 0x654

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_10

Bits

Type

Reset

Name

Description

0x0

EN_10

For OUT10

PINMUX.MIO_PAD_SLEEP_EN_11 @ 0x658

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_11

Bits

Type

Reset

Name

Description

0x0

EN_11

For OUT11

PINMUX.MIO_PAD_SLEEP_EN_12 @ 0x65c

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_12

Bits

Type

Reset

Name

Description

0x0

EN_12

For OUT12

PINMUX.MIO_PAD_SLEEP_EN_13 @ 0x660

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_13

Bits

Type

Reset

Name

Description

0x0

EN_13

For OUT13

PINMUX.MIO_PAD_SLEEP_EN_14 @ 0x664

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_14

Bits

Type

Reset

Name

Description

0x0

EN_14

For OUT14

PINMUX.MIO_PAD_SLEEP_EN_15 @ 0x668

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_15

Bits

Type

Reset

Name

Description

0x0

EN_15

For OUT15

PINMUX.MIO_PAD_SLEEP_EN_16 @ 0x66c

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_16

Bits

Type

Reset

Name

Description

0x0

EN_16

For OUT16

PINMUX.MIO_PAD_SLEEP_EN_17 @ 0x670

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_17

Bits

Type

Reset

Name

Description

0x0

EN_17

For OUT17

PINMUX.MIO_PAD_SLEEP_EN_18 @ 0x674

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_18

Bits

Type

Reset

Name

Description

0x0

EN_18

For OUT18

PINMUX.MIO_PAD_SLEEP_EN_19 @ 0x678

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_19

Bits

Type

Reset

Name

Description

0x0

EN_19

For OUT19

PINMUX.MIO_PAD_SLEEP_EN_20 @ 0x67c

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_20

Bits

Type

Reset

Name

Description

0x0

EN_20

For OUT20

PINMUX.MIO_PAD_SLEEP_EN_21 @ 0x680

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_21

Bits

Type

Reset

Name

Description

0x0

EN_21

For OUT21

PINMUX.MIO_PAD_SLEEP_EN_22 @ 0x684

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_22

Bits

Type

Reset

Name

Description

0x0

EN_22

For OUT22

PINMUX.MIO_PAD_SLEEP_EN_23 @ 0x688

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_23

Bits

Type

Reset

Name

Description

0x0

EN_23

For OUT23

PINMUX.MIO_PAD_SLEEP_EN_24 @ 0x68c

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_24

Bits

Type

Reset

Name

Description

0x0

EN_24

For OUT24

PINMUX.MIO_PAD_SLEEP_EN_25 @ 0x690

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_25

Bits

Type

Reset

Name

Description

0x0

EN_25

For OUT25

PINMUX.MIO_PAD_SLEEP_EN_26 @ 0x694

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_26

Bits

Type

Reset

Name

Description

0x0

EN_26

For OUT26

PINMUX.MIO_PAD_SLEEP_EN_27 @ 0x698

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_27

Bits

Type

Reset

Name

Description

0x0

EN_27

For OUT27

PINMUX.MIO_PAD_SLEEP_EN_28 @ 0x69c

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_28

Bits

Type

Reset

Name

Description

0x0

EN_28

For OUT28

PINMUX.MIO_PAD_SLEEP_EN_29 @ 0x6a0

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_29

Bits

Type

Reset

Name

Description

0x0

EN_29

For OUT29

PINMUX.MIO_PAD_SLEEP_EN_30 @ 0x6a4

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_30

Bits

Type

Reset

Name

Description

0x0

EN_30

For OUT30

PINMUX.MIO_PAD_SLEEP_EN_31 @ 0x6a8

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_31

Bits

Type

Reset

Name

Description

0x0

EN_31

For OUT31

PINMUX.MIO_PAD_SLEEP_EN_32 @ 0x6ac

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_32

Bits

Type

Reset

Name

Description

0x0

EN_32

For OUT32

PINMUX.MIO_PAD_SLEEP_EN_33 @ 0x6b0

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_33

Bits

Type

Reset

Name

Description

0x0

EN_33

For OUT33

PINMUX.MIO_PAD_SLEEP_EN_34 @ 0x6b4

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_34

Bits

Type

Reset

Name

Description

0x0

EN_34

For OUT34

PINMUX.MIO_PAD_SLEEP_EN_35 @ 0x6b8

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_35

Bits

Type

Reset

Name

Description

0x0

EN_35

For OUT35

PINMUX.MIO_PAD_SLEEP_EN_36 @ 0x6bc

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_36

Bits

Type

Reset

Name

Description

0x0

EN_36

For OUT36

PINMUX.MIO_PAD_SLEEP_EN_37 @ 0x6c0

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_37

Bits

Type

Reset

Name

Description

0x0

EN_37

For OUT37

PINMUX.MIO_PAD_SLEEP_EN_38 @ 0x6c4

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_38

Bits

Type

Reset

Name

Description

0x0

EN_38

For OUT38

PINMUX.MIO_PAD_SLEEP_EN_39 @ 0x6c8

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_39

Bits

Type

Reset

Name

Description

0x0

EN_39

For OUT39

PINMUX.MIO_PAD_SLEEP_EN_40 @ 0x6cc

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_40

Bits

Type

Reset

Name

Description

0x0

EN_40

For OUT40

PINMUX.MIO_PAD_SLEEP_EN_41 @ 0x6d0

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_41

Bits

Type

Reset

Name

Description

0x0

EN_41

For OUT41

PINMUX.MIO_PAD_SLEEP_EN_42 @ 0x6d4

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_42

Bits

Type

Reset

Name

Description

0x0

EN_42

For OUT42

PINMUX.MIO_PAD_SLEEP_EN_43 @ 0x6d8

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_43

Bits

Type

Reset

Name

Description

0x0

EN_43

For OUT43

PINMUX.MIO_PAD_SLEEP_EN_44 @ 0x6dc

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_44

Bits

Type

Reset

Name

Description

0x0

EN_44

For OUT44

PINMUX.MIO_PAD_SLEEP_EN_45 @ 0x6e0

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_45

Bits

Type

Reset

Name

Description

0x0

EN_45

For OUT45

PINMUX.MIO_PAD_SLEEP_EN_46 @ 0x6e4

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_46

Bits

Type

Reset

Name

Description

0x0

EN_46

For OUT46

PINMUX.MIO_PAD_SLEEP_MODE_0 @ 0x6e8

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_0

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_0

Value to drive in deep sleep.

0	Tie-Low	The pad is driven actively to zero in deep sleep mode.
1	Tie-High	The pad is driven actively to one in deep sleep mode.
2	High-Z	The pad is left undriven in deep sleep mode. Note that the actual driving behavior during deep sleep will then depend on the pull-up/-down configuration of in !!MIO_PAD_ATTR.
3	Keep	Keep last driven value (including high-Z).

PINMUX.MIO_PAD_SLEEP_MODE_1 @ 0x6ec

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_1

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_1

For OUT1

PINMUX.MIO_PAD_SLEEP_MODE_2 @ 0x6f0

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_2

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_2

For OUT2

PINMUX.MIO_PAD_SLEEP_MODE_3 @ 0x6f4

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_3

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_3

For OUT3

PINMUX.MIO_PAD_SLEEP_MODE_4 @ 0x6f8

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_4

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_4

For OUT4

PINMUX.MIO_PAD_SLEEP_MODE_5 @ 0x6fc

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_5

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_5

For OUT5

PINMUX.MIO_PAD_SLEEP_MODE_6 @ 0x700

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_6

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_6

For OUT6

PINMUX.MIO_PAD_SLEEP_MODE_7 @ 0x704

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_7

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_7

For OUT7

PINMUX.MIO_PAD_SLEEP_MODE_8 @ 0x708

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_8

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_8

For OUT8

PINMUX.MIO_PAD_SLEEP_MODE_9 @ 0x70c

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_9

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_9

For OUT9

PINMUX.MIO_PAD_SLEEP_MODE_10 @ 0x710

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_10

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_10

For OUT10

PINMUX.MIO_PAD_SLEEP_MODE_11 @ 0x714

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_11

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_11

For OUT11

PINMUX.MIO_PAD_SLEEP_MODE_12 @ 0x718

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_12

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_12

For OUT12

PINMUX.MIO_PAD_SLEEP_MODE_13 @ 0x71c

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_13

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_13

For OUT13

PINMUX.MIO_PAD_SLEEP_MODE_14 @ 0x720

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_14

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_14

For OUT14

PINMUX.MIO_PAD_SLEEP_MODE_15 @ 0x724

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_15

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_15

For OUT15

PINMUX.MIO_PAD_SLEEP_MODE_16 @ 0x728

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_16

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_16

For OUT16

PINMUX.MIO_PAD_SLEEP_MODE_17 @ 0x72c

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_17

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_17

For OUT17

PINMUX.MIO_PAD_SLEEP_MODE_18 @ 0x730

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_18

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_18

For OUT18

PINMUX.MIO_PAD_SLEEP_MODE_19 @ 0x734

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_19

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_19

For OUT19

PINMUX.MIO_PAD_SLEEP_MODE_20 @ 0x738

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_20

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_20

For OUT20

PINMUX.MIO_PAD_SLEEP_MODE_21 @ 0x73c

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_21

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_21

For OUT21

PINMUX.MIO_PAD_SLEEP_MODE_22 @ 0x740

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_22

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_22

For OUT22

PINMUX.MIO_PAD_SLEEP_MODE_23 @ 0x744

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_23

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_23

For OUT23

PINMUX.MIO_PAD_SLEEP_MODE_24 @ 0x748

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_24

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_24

For OUT24

PINMUX.MIO_PAD_SLEEP_MODE_25 @ 0x74c

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_25

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_25

For OUT25

PINMUX.MIO_PAD_SLEEP_MODE_26 @ 0x750

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_26

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_26

For OUT26

PINMUX.MIO_PAD_SLEEP_MODE_27 @ 0x754

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_27

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_27

For OUT27

PINMUX.MIO_PAD_SLEEP_MODE_28 @ 0x758

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_28

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_28

For OUT28

PINMUX.MIO_PAD_SLEEP_MODE_29 @ 0x75c

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_29

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_29

For OUT29

PINMUX.MIO_PAD_SLEEP_MODE_30 @ 0x760

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_30

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_30

For OUT30

PINMUX.MIO_PAD_SLEEP_MODE_31 @ 0x764

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_31

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_31

For OUT31

PINMUX.MIO_PAD_SLEEP_MODE_32 @ 0x768

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_32

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_32

For OUT32

PINMUX.MIO_PAD_SLEEP_MODE_33 @ 0x76c

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_33

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_33

For OUT33

PINMUX.MIO_PAD_SLEEP_MODE_34 @ 0x770

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_34

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_34

For OUT34

PINMUX.MIO_PAD_SLEEP_MODE_35 @ 0x774

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_35

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_35

For OUT35

PINMUX.MIO_PAD_SLEEP_MODE_36 @ 0x778

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_36

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_36

For OUT36

PINMUX.MIO_PAD_SLEEP_MODE_37 @ 0x77c

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_37

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_37

For OUT37

PINMUX.MIO_PAD_SLEEP_MODE_38 @ 0x780

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_38

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_38

For OUT38

PINMUX.MIO_PAD_SLEEP_MODE_39 @ 0x784

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_39

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_39

For OUT39

PINMUX.MIO_PAD_SLEEP_MODE_40 @ 0x788

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_40

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_40

For OUT40

PINMUX.MIO_PAD_SLEEP_MODE_41 @ 0x78c

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_41

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_41

For OUT41

PINMUX.MIO_PAD_SLEEP_MODE_42 @ 0x790

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_42

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_42

For OUT42

PINMUX.MIO_PAD_SLEEP_MODE_43 @ 0x794

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_43

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_43

For OUT43

PINMUX.MIO_PAD_SLEEP_MODE_44 @ 0x798

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_44

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_44

For OUT44

PINMUX.MIO_PAD_SLEEP_MODE_45 @ 0x79c

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_45

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_45

For OUT45

PINMUX.MIO_PAD_SLEEP_MODE_46 @ 0x7a0

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_46

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_46

For OUT46

PINMUX.DIO_PAD_SLEEP_STATUS @ 0x7a4

Reset default = 0x0, mask 0xffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								EN_23	EN_22	EN_21	EN_20	EN_19	EN_18	EN_17	EN_16
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EN_15	EN_14	EN_13	EN_12	EN_11	EN_10	EN_9	EN_8	EN_7	EN_6	EN_5	EN_4	EN_3	EN_2	EN_1	EN_0

Bits

Type

Reset

Name

Description

rw0c

0x0

EN_0

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

rw0c

0x0

EN_1

rw0c

0x0

EN_2

rw0c

0x0

EN_3

rw0c

0x0

EN_4

rw0c

0x0

EN_5

rw0c

0x0

EN_6

rw0c

0x0

EN_7

rw0c

0x0

EN_8

rw0c

0x0

EN_9

rw0c

0x0

EN_10

rw0c

0x0

EN_11

rw0c

0x0

EN_12

rw0c

0x0

EN_13

rw0c

0x0

EN_14

rw0c

0x0

EN_15

rw0c

0x0

EN_16

rw0c

0x0

EN_17

rw0c

0x0

EN_18

rw0c

0x0

EN_19

rw0c

0x0

EN_20

rw0c

0x0

EN_21

rw0c

0x0

EN_22

rw0c

0x0

EN_23

PINMUX.DIO_PAD_SLEEP_REGWEN_0 @ 0x7a8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_0

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_0

PINMUX.DIO_PAD_SLEEP_REGWEN_1 @ 0x7ac

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_1

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_1

For DIO_PAD1

PINMUX.DIO_PAD_SLEEP_REGWEN_2 @ 0x7b0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_2

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_2

For DIO_PAD2

PINMUX.DIO_PAD_SLEEP_REGWEN_3 @ 0x7b4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_3

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_3

For DIO_PAD3

PINMUX.DIO_PAD_SLEEP_REGWEN_4 @ 0x7b8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_4

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_4

For DIO_PAD4

PINMUX.DIO_PAD_SLEEP_REGWEN_5 @ 0x7bc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_5

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_5

For DIO_PAD5

PINMUX.DIO_PAD_SLEEP_REGWEN_6 @ 0x7c0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_6

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_6

For DIO_PAD6

PINMUX.DIO_PAD_SLEEP_REGWEN_7 @ 0x7c4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_7

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_7

For DIO_PAD7

PINMUX.DIO_PAD_SLEEP_REGWEN_8 @ 0x7c8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_8

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_8

For DIO_PAD8

PINMUX.DIO_PAD_SLEEP_REGWEN_9 @ 0x7cc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_9

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_9

For DIO_PAD9

PINMUX.DIO_PAD_SLEEP_REGWEN_10 @ 0x7d0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_10

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_10

For DIO_PAD10

PINMUX.DIO_PAD_SLEEP_REGWEN_11 @ 0x7d4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_11

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_11

For DIO_PAD11

PINMUX.DIO_PAD_SLEEP_REGWEN_12 @ 0x7d8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_12

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_12

For DIO_PAD12

PINMUX.DIO_PAD_SLEEP_REGWEN_13 @ 0x7dc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_13

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_13

For DIO_PAD13

PINMUX.DIO_PAD_SLEEP_REGWEN_14 @ 0x7e0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_14

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_14

For DIO_PAD14

PINMUX.DIO_PAD_SLEEP_REGWEN_15 @ 0x7e4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_15

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_15

For DIO_PAD15

PINMUX.DIO_PAD_SLEEP_REGWEN_16 @ 0x7e8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_16

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_16

For DIO_PAD16

PINMUX.DIO_PAD_SLEEP_REGWEN_17 @ 0x7ec

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_17

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_17

For DIO_PAD17

PINMUX.DIO_PAD_SLEEP_REGWEN_18 @ 0x7f0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_18

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_18

For DIO_PAD18

PINMUX.DIO_PAD_SLEEP_REGWEN_19 @ 0x7f4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_19

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_19

For DIO_PAD19

PINMUX.DIO_PAD_SLEEP_REGWEN_20 @ 0x7f8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_20

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_20

For DIO_PAD20

PINMUX.DIO_PAD_SLEEP_REGWEN_21 @ 0x7fc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_21

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_21

For DIO_PAD21

PINMUX.DIO_PAD_SLEEP_REGWEN_22 @ 0x800

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_22

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_22

For DIO_PAD22

PINMUX.DIO_PAD_SLEEP_REGWEN_23 @ 0x804

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_23

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_23

For DIO_PAD23

PINMUX.DIO_PAD_SLEEP_EN_0 @ 0x808

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_0

Bits Type Reset Name Description

0x0

EN_0

Deep sleep mode enable. If this bit is set to 1 the corresponding pad will enable the sleep behavior specified in !!DIO_PAD_SLEEP_MODE upon deep sleep entry, and the corresponding bit in DIO_PAD_SLEEP_STATUS will be set to 1. The pad remains in deep sleep mode until the corresponding bit in DIO_PAD_SLEEP_STATUS is cleared by SW. Note that if an always on peripheral is connected to a specific DIO pad, the corresponding !!DIO_PAD_SLEEP_EN bit should be set to 0.

PINMUX.DIO_PAD_SLEEP_EN_1 @ 0x80c

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_1

Bits

Type

Reset

Name

Description

0x0

EN_1

For OUT1

PINMUX.DIO_PAD_SLEEP_EN_2 @ 0x810

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_2

Bits

Type

Reset

Name

Description

0x0

EN_2

For OUT2

PINMUX.DIO_PAD_SLEEP_EN_3 @ 0x814

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_3

Bits

Type

Reset

Name

Description

0x0

EN_3

For OUT3

PINMUX.DIO_PAD_SLEEP_EN_4 @ 0x818

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_4

Bits

Type

Reset

Name

Description

0x0

EN_4

For OUT4

PINMUX.DIO_PAD_SLEEP_EN_5 @ 0x81c

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_5

Bits

Type

Reset

Name

Description

0x0

EN_5

For OUT5

PINMUX.DIO_PAD_SLEEP_EN_6 @ 0x820

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_6

Bits

Type

Reset

Name

Description

0x0

EN_6

For OUT6

PINMUX.DIO_PAD_SLEEP_EN_7 @ 0x824

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_7

Bits

Type

Reset

Name

Description

0x0

EN_7

For OUT7

PINMUX.DIO_PAD_SLEEP_EN_8 @ 0x828

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_8

Bits

Type

Reset

Name

Description

0x0

EN_8

For OUT8

PINMUX.DIO_PAD_SLEEP_EN_9 @ 0x82c

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_9

Bits

Type

Reset

Name

Description

0x0

EN_9

For OUT9

PINMUX.DIO_PAD_SLEEP_EN_10 @ 0x830

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_10

Bits

Type

Reset

Name

Description

0x0

EN_10

For OUT10

PINMUX.DIO_PAD_SLEEP_EN_11 @ 0x834

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_11

Bits

Type

Reset

Name

Description

0x0

EN_11

For OUT11

PINMUX.DIO_PAD_SLEEP_EN_12 @ 0x838

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_12

Bits

Type

Reset

Name

Description

0x0

EN_12

For OUT12

PINMUX.DIO_PAD_SLEEP_EN_13 @ 0x83c

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_13

Bits

Type

Reset

Name

Description

0x0

EN_13

For OUT13

PINMUX.DIO_PAD_SLEEP_EN_14 @ 0x840

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_14

Bits

Type

Reset

Name

Description

0x0

EN_14

For OUT14

PINMUX.DIO_PAD_SLEEP_EN_15 @ 0x844

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_15

Bits

Type

Reset

Name

Description

0x0

EN_15

For OUT15

PINMUX.DIO_PAD_SLEEP_EN_16 @ 0x848

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_16

Bits

Type

Reset

Name

Description

0x0

EN_16

For OUT16

PINMUX.DIO_PAD_SLEEP_EN_17 @ 0x84c

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_17

Bits

Type

Reset

Name

Description

0x0

EN_17

For OUT17

PINMUX.DIO_PAD_SLEEP_EN_18 @ 0x850

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_18

Bits

Type

Reset

Name

Description

0x0

EN_18

For OUT18

PINMUX.DIO_PAD_SLEEP_EN_19 @ 0x854

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_19

Bits

Type

Reset

Name

Description

0x0

EN_19

For OUT19

PINMUX.DIO_PAD_SLEEP_EN_20 @ 0x858

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_20

Bits

Type

Reset

Name

Description

0x0

EN_20

For OUT20

PINMUX.DIO_PAD_SLEEP_EN_21 @ 0x85c

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_21

Bits

Type

Reset

Name

Description

0x0

EN_21

For OUT21

PINMUX.DIO_PAD_SLEEP_EN_22 @ 0x860

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_22

Bits

Type

Reset

Name

Description

0x0

EN_22

For OUT22

PINMUX.DIO_PAD_SLEEP_EN_23 @ 0x864

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_23

Bits

Type

Reset

Name

Description

0x0

EN_23

For OUT23

PINMUX.DIO_PAD_SLEEP_MODE_0 @ 0x868

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_0

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_0

Value to drive in deep sleep.

0	Tie-Low	The pad is driven actively to zero in deep sleep mode.
1	Tie-High	The pad is driven actively to one in deep sleep mode.
2	High-Z	The pad is left undriven in deep sleep mode. Note that the actual driving behavior during deep sleep will then depend on the pull-up/-down configuration of in !!DIO_PAD_ATTR.
3	Keep	Keep last driven value (including high-Z).

PINMUX.DIO_PAD_SLEEP_MODE_1 @ 0x86c

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_1

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_1

For OUT1

PINMUX.DIO_PAD_SLEEP_MODE_2 @ 0x870

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_2

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_2

For OUT2

PINMUX.DIO_PAD_SLEEP_MODE_3 @ 0x874

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_3

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_3

For OUT3

PINMUX.DIO_PAD_SLEEP_MODE_4 @ 0x878

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_4

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_4

For OUT4

PINMUX.DIO_PAD_SLEEP_MODE_5 @ 0x87c

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_5

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_5

For OUT5

PINMUX.DIO_PAD_SLEEP_MODE_6 @ 0x880

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_6

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_6

For OUT6

PINMUX.DIO_PAD_SLEEP_MODE_7 @ 0x884

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_7

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_7

For OUT7

PINMUX.DIO_PAD_SLEEP_MODE_8 @ 0x888

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_8

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_8

For OUT8

PINMUX.DIO_PAD_SLEEP_MODE_9 @ 0x88c

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_9

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_9

For OUT9

PINMUX.DIO_PAD_SLEEP_MODE_10 @ 0x890

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_10

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_10

For OUT10

PINMUX.DIO_PAD_SLEEP_MODE_11 @ 0x894

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_11

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_11

For OUT11

PINMUX.DIO_PAD_SLEEP_MODE_12 @ 0x898

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_12

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_12

For OUT12

PINMUX.DIO_PAD_SLEEP_MODE_13 @ 0x89c

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_13

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_13

For OUT13

PINMUX.DIO_PAD_SLEEP_MODE_14 @ 0x8a0

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_14

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_14

For OUT14

PINMUX.DIO_PAD_SLEEP_MODE_15 @ 0x8a4

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_15

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_15

For OUT15

PINMUX.DIO_PAD_SLEEP_MODE_16 @ 0x8a8

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_16

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_16

For OUT16

PINMUX.DIO_PAD_SLEEP_MODE_17 @ 0x8ac

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_17

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_17

For OUT17

PINMUX.DIO_PAD_SLEEP_MODE_18 @ 0x8b0

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_18

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_18

For OUT18

PINMUX.DIO_PAD_SLEEP_MODE_19 @ 0x8b4

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_19

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_19

For OUT19

PINMUX.DIO_PAD_SLEEP_MODE_20 @ 0x8b8

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_20

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_20

For OUT20

PINMUX.DIO_PAD_SLEEP_MODE_21 @ 0x8bc

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_21

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_21

For OUT21

PINMUX.DIO_PAD_SLEEP_MODE_22 @ 0x8c0

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_22

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_22

For OUT22

PINMUX.DIO_PAD_SLEEP_MODE_23 @ 0x8c4

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OUT_23

Bits

Type

Reset

Name

Description

1:0

0x2

OUT_23

For OUT23

PINMUX.WKUP_DETECTOR_REGWEN_0 @ 0x8c8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_0

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_0

Register write enable bit. If this is cleared to 0, the corresponding WKUP_DETECTOR configuration is not writable anymore.

PINMUX.WKUP_DETECTOR_REGWEN_1 @ 0x8cc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_1

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_1

For WKUP_DETECTOR1

PINMUX.WKUP_DETECTOR_REGWEN_2 @ 0x8d0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_2

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_2

For WKUP_DETECTOR2

PINMUX.WKUP_DETECTOR_REGWEN_3 @ 0x8d4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_3

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_3

For WKUP_DETECTOR3

PINMUX.WKUP_DETECTOR_REGWEN_4 @ 0x8d8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_4

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_4

For WKUP_DETECTOR4

PINMUX.WKUP_DETECTOR_REGWEN_5 @ 0x8dc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_5

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_5

For WKUP_DETECTOR5

PINMUX.WKUP_DETECTOR_REGWEN_6 @ 0x8e0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_6

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_6

For WKUP_DETECTOR6

PINMUX.WKUP_DETECTOR_REGWEN_7 @ 0x8e4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_7

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_7

For WKUP_DETECTOR7

PINMUX.WKUP_DETECTOR_EN_0 @ 0x8e8

Enables for the wakeup detectors.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_0

Bits

Type

Reset

Name

Description

0x0

EN_0

Setting this bit activates the corresponding wakeup detector. The behavior is as specified in !!WKUP_DETECTOR, !!WKUP_DETECTOR_CNT_TH and !!WKUP_DETECTOR_PADSEL.

PINMUX.WKUP_DETECTOR_EN_1 @ 0x8ec

Enables for the wakeup detectors.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_1

Bits

Type

Reset

Name

Description

0x0

EN_1

For DETECTOR1

PINMUX.WKUP_DETECTOR_EN_2 @ 0x8f0

Enables for the wakeup detectors.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_2

Bits

Type

Reset

Name

Description

0x0

EN_2

For DETECTOR2

PINMUX.WKUP_DETECTOR_EN_3 @ 0x8f4

Enables for the wakeup detectors.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_3

Bits

Type

Reset

Name

Description

0x0

EN_3

For DETECTOR3

PINMUX.WKUP_DETECTOR_EN_4 @ 0x8f8

Enables for the wakeup detectors.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_4

Bits

Type

Reset

Name

Description

0x0

EN_4

For DETECTOR4

PINMUX.WKUP_DETECTOR_EN_5 @ 0x8fc

Enables for the wakeup detectors.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_5

Bits

Type

Reset

Name

Description

0x0

EN_5

For DETECTOR5

PINMUX.WKUP_DETECTOR_EN_6 @ 0x900

Enables for the wakeup detectors.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_6

Bits

Type

Reset

Name

Description

0x0

EN_6

For DETECTOR6

PINMUX.WKUP_DETECTOR_EN_7 @ 0x904

Enables for the wakeup detectors.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_7

Bits

Type

Reset

Name

Description

0x0

EN_7

For DETECTOR7

PINMUX.WKUP_DETECTOR_0 @ 0x908

Configuration of wakeup condition detectors.

Reset default = 0x0, mask 0x1f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											MIODIO_0	FILTER_0	MODE_0

Bits

Type

Reset

Name

Description

2:0

0x0

MODE_0

Wakeup detection mode.

0	Posedge	Trigger a wakeup request when observing a positive edge.
1	Negedge	Trigger a wakeup request when observing a negative edge.
2	Edge	Trigger a wakeup request when observing an edge in any direction.
3	TimedHigh	Trigger a wakeup request when pin is driven HIGH for a certain amount of always-on clock cycles as configured in !!WKUP_DETECTOR_CNT_TH.
4	TimedLow	Trigger a wakeup request when pin is driven LOW for a certain amount of always-on clock cycles as configured in !!WKUP_DETECTOR_CNT_TH.

Other values are reserved.

0x0

FILTER_0

0: signal filter disabled, 1: signal filter enabled. the signal must be stable for 4 always-on clock cycles before the value is being forwarded. can be used for debouncing.

0x0

MIODIO_0

0: select index !!WKUP_DETECTOR_PADSEL from MIO pads, 1: select index !!WKUP_DETECTOR_PADSEL from DIO pads.

PINMUX.WKUP_DETECTOR_1 @ 0x90c

Configuration of wakeup condition detectors.

Reset default = 0x0, mask 0x1f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											MIODIO_1	FILTER_1	MODE_1

Bits

Type

Reset

Name

Description

2:0

0x0

MODE_1

For DETECTOR1

0x0

FILTER_1

For DETECTOR1

0x0

MIODIO_1

For DETECTOR1

PINMUX.WKUP_DETECTOR_2 @ 0x910

Configuration of wakeup condition detectors.

Reset default = 0x0, mask 0x1f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											MIODIO_2	FILTER_2	MODE_2

Bits

Type

Reset

Name

Description

2:0

0x0

MODE_2

For DETECTOR2

0x0

FILTER_2

For DETECTOR2

0x0

MIODIO_2

For DETECTOR2

PINMUX.WKUP_DETECTOR_3 @ 0x914

Configuration of wakeup condition detectors.

Reset default = 0x0, mask 0x1f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											MIODIO_3	FILTER_3	MODE_3

Bits

Type

Reset

Name

Description

2:0

0x0

MODE_3

For DETECTOR3

0x0

FILTER_3

For DETECTOR3

0x0

MIODIO_3

For DETECTOR3

PINMUX.WKUP_DETECTOR_4 @ 0x918

Configuration of wakeup condition detectors.

Reset default = 0x0, mask 0x1f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											MIODIO_4	FILTER_4	MODE_4

Bits

Type

Reset

Name

Description

2:0

0x0

MODE_4

For DETECTOR4

0x0

FILTER_4

For DETECTOR4

0x0

MIODIO_4

For DETECTOR4

PINMUX.WKUP_DETECTOR_5 @ 0x91c

Configuration of wakeup condition detectors.

Reset default = 0x0, mask 0x1f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											MIODIO_5	FILTER_5	MODE_5

Bits

Type

Reset

Name

Description

2:0

0x0

MODE_5

For DETECTOR5

0x0

FILTER_5

For DETECTOR5

0x0

MIODIO_5

For DETECTOR5

PINMUX.WKUP_DETECTOR_6 @ 0x920

Configuration of wakeup condition detectors.

Reset default = 0x0, mask 0x1f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											MIODIO_6	FILTER_6	MODE_6

Bits

Type

Reset

Name

Description

2:0

0x0

MODE_6

For DETECTOR6

0x0

FILTER_6

For DETECTOR6

0x0

MIODIO_6

For DETECTOR6

PINMUX.WKUP_DETECTOR_7 @ 0x924

Configuration of wakeup condition detectors.

Reset default = 0x0, mask 0x1f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											MIODIO_7	FILTER_7	MODE_7

Bits

Type

Reset

Name

Description

2:0

0x0

MODE_7

For DETECTOR7

0x0

FILTER_7

For DETECTOR7

0x0

MIODIO_7

For DETECTOR7

PINMUX.WKUP_DETECTOR_CNT_TH_0 @ 0x928

Counter thresholds for wakeup condition detectors.

Reset default = 0x0, mask 0xff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TH_0

Bits

Type

Reset

Name

Description

7:0

0x0

TH_0

Counter threshold for TimedLow and TimedHigh wakeup detector modes (see !!WKUP_DETECTOR). The threshold is in terms of always-on clock cycles.

PINMUX.WKUP_DETECTOR_CNT_TH_1 @ 0x92c

Counter thresholds for wakeup condition detectors.

Reset default = 0x0, mask 0xff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TH_1

Bits

Type

Reset

Name

Description

7:0

0x0

TH_1

For DETECTOR1

PINMUX.WKUP_DETECTOR_CNT_TH_2 @ 0x930

Counter thresholds for wakeup condition detectors.

Reset default = 0x0, mask 0xff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TH_2

Bits

Type

Reset

Name

Description

7:0

0x0

TH_2

For DETECTOR2

PINMUX.WKUP_DETECTOR_CNT_TH_3 @ 0x934

Counter thresholds for wakeup condition detectors.

Reset default = 0x0, mask 0xff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TH_3

Bits

Type

Reset

Name

Description

7:0

0x0

TH_3

For DETECTOR3

PINMUX.WKUP_DETECTOR_CNT_TH_4 @ 0x938

Counter thresholds for wakeup condition detectors.

Reset default = 0x0, mask 0xff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TH_4

Bits

Type

Reset

Name

Description

7:0

0x0

TH_4

For DETECTOR4

PINMUX.WKUP_DETECTOR_CNT_TH_5 @ 0x93c

Counter thresholds for wakeup condition detectors.

Reset default = 0x0, mask 0xff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TH_5

Bits

Type

Reset

Name

Description

7:0

0x0

TH_5

For DETECTOR5

PINMUX.WKUP_DETECTOR_CNT_TH_6 @ 0x940

Counter thresholds for wakeup condition detectors.

Reset default = 0x0, mask 0xff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TH_6

Bits

Type

Reset

Name

Description

7:0

0x0

TH_6

For DETECTOR6

PINMUX.WKUP_DETECTOR_CNT_TH_7 @ 0x944

Counter thresholds for wakeup condition detectors.

Reset default = 0x0, mask 0xff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TH_7

Bits

Type

Reset

Name

Description

7:0

0x0

TH_7

For DETECTOR7

PINMUX.WKUP_DETECTOR_PADSEL_0 @ 0x948

Pad selects for pad wakeup condition detectors.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										SEL_0

Bits

Type

Reset

Name

Description

5:0

0x0

SEL_0

Selects a specific MIO or DIO pad (depending on !!WKUP_DETECTOR configuration). In case of MIO, the pad select index is the same as used for !!PERIPH_INSEL, meaning that index 0 and 1 just select constant 0, and the MIO pads live at indices >= 2. In case of DIO pads, the pad select index corresponds 1:1 to the DIO pad to be selected.

PINMUX.WKUP_DETECTOR_PADSEL_1 @ 0x94c

Pad selects for pad wakeup condition detectors.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										SEL_1

Bits

Type

Reset

Name

Description

5:0

0x0

SEL_1

For DETECTOR1

PINMUX.WKUP_DETECTOR_PADSEL_2 @ 0x950

Pad selects for pad wakeup condition detectors.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										SEL_2

Bits

Type

Reset

Name

Description

5:0

0x0

SEL_2

For DETECTOR2

PINMUX.WKUP_DETECTOR_PADSEL_3 @ 0x954

Pad selects for pad wakeup condition detectors.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6