Pinmux Technical Specification

Overview

This document specifies the functionality of the pin multiplexer (pinmux) peripheral. This module conforms to the OpenTitan guideline for peripheral device functionality. See that document for integration overview within the broader OpenTitan top level system. The module provides a mechanism to reconfigure the peripheral-to-pin mapping at runtime, which greatly enhances the system flexibility. In addition to that, the pinmux also allows the user to control pad attributes (such as pull-up, pull-down, open-drain, drive-strength, keeper and inversion), and it contains features that facilitate low-power modes of the system. For example, the sleep behavior of each pad can be programmed individually, and the module contains additional pattern detectors that can listen on any IO and wake up the system if a specific pattern has been detected.

Features

  • Configurable number of chip bidirectional IOs

  • Configurable number of peripheral inputs and outputs

  • Programmable mapping from peripheral outputs (and output enables) to top-level outputs (and output enables)

  • Programmable mapping from top-level inputs to peripheral inputs

  • Programmable control of chip pad attributes like output drive-strength, pull-up, pull-down and virtual open-drain

  • Programmable pattern detectors to detect wakeup conditions during sleep mode

  • Programmable sleep mode behavior

  • Support for life-cycle-based JTAG (TAP) isolation and muxing

Theory of Operations

Block Diagram and Overview

The pinmux peripheral is a programmable module designed to wire arbitrary peripheral inputs and outputs to arbitrary multiplexable chip bidirectional pins. It gives much flexibility at the top level of the device, allowing most data pins to be flexibly wired and controlled by many peripherals. Even though the pinmux is referred to as one IP, it is logically split into two modules that are instantiated on the top-level and the chip-level, respectively, as can be seen in the block diagram below. The top-level module pinmux contains the CSRs accessible via the TL-UL interface, the main muxing matrix, retention registers, a set of programmable wakeup detectors, and the HW strap sampling and TAP / JTAG muxing logic. The chip-level module padring instantiates the bidirectional pads and connects the physical pad attributes.

Pinmux Block Diagram

MIO and DIO Signal Categories

The pinmux supports two different IO signal categories: Muxed IO (MIO) signals that are routed through the pinmux matrix, and dedicated IO (DIO) signals that bypass the pinmux matrix. This distinction is useful for accommodating IO signals that are timing critical or that must have a fixed IO mapping for another reason. Note that although DIO signals are not routed through the pinmux matrix, they are still connected to the retention logic and the wakeup detectors (see next section below).

The number of available peripheral IOs, pads, and their assignment to the MIO / DIO categories is done at design time as part of the top-level configuration. This configurability is achieved by representing inputs / outputs as packed arrays, in combination with the SystemVerilog parameters NPeriphIn, NPeriphOut, NMioPads and NDioPads. Note however that the register file is also affected by this configuration and needs to be regenerated for each design instance.

It is assumed that all available pins that the pinmux connects to are bidirectional, controlled by logic within this module. By default, all muxed peripheral inputs are tied to zero. Further, all output enables are set to zero, which essentially causes all pads to be in high-Z state after reset. In addition to wiring programmability, each muxed peripheral input can be set constantly to 0 or 1, and each muxed chip output can be set constantly to 0, 1 or high-Z.

See the muxing matrix section for more details about the mux implementation.

Retention and Wakeup Features

The retention logic allows SW to specify a certain behavior during sleep for each muxed and dedicated output. Legal behaviors are tie low, tie high, high-Z, keeping the previous state, or driving the current value (useful for peripherals that are always on).

The wakeup detectors can detect patterns such as rising / falling edges and pulses of a certain width up to 255 AON clock cycles. Each wakeup detector can listen on any one of the MIO / DIO signals that are routed through the pinmux, and if a pattern is detected, the power manager is informed of that event via a wakeup request.

The pinmux module itself is in the always-on (AON) power domain, and as such does not loose configuration state when a sleep power cycle is performed. However, only the wakeup detector logic will be actively clocked during sleep in order to save power.

See the retention logic and wakeup detectors sections for more details about the mux implementation.

Test and Debug Access

The hardware strap sampling and TAP isolation logic provides test and debug access to the chip during specific life cycle states. This mechanism is explained in more detail in the strap sampling and TAP isolation section.

Pad Attributes

Additional pad-specific features such as inversion, pull-up, pull-down, virtual open-drain, drive-strength and input/output inversion etc. can be exercise via the pad attribute CSRs. The pinmux module supports a comprehensive set of such pad attributes, but it is permissible that some of them may not be supported by the underlying pad implementation. For example, certain ASIC libraries may not provide open-drain outputs, and FPGAs typically do not allow all of these attributes to be programmed dynamically at runtime. See the generic pad wrapper section below for more details. Note that static pad attributes for FPGAs are currently not covered in this specification.

Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module PINMUX has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: clk_aon_i

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO: none

Inter-Module Signals: Reference

Inter-Module Signals
Port Name Package::Struct Type Act Width Description
lc_hw_debug_en lc_ctrl_pkg::lc_tx uni rcv 1
lc_dft_en lc_ctrl_pkg::lc_tx uni rcv 1
lc_jtag jtag_pkg::jtag req_rsp req 1
rv_jtag jtag_pkg::jtag req_rsp req 1
dft_jtag jtag_pkg::jtag req_rsp req 1
dft_strap_test pinmux_pkg::dft_strap_test_req uni req 1
dft_hold_tap_sel logic uni rcv 1
sleep_en logic uni rcv 1
strap_en logic uni rcv 1
pin_wkup_req logic uni req 1
usbdev_dppullup_en logic uni rcv 1
usbdev_dnpullup_en logic uni rcv 1
usb_dppullup_en logic uni req 1
usb_dnpullup_en logic uni req 1
usb_wkup_req logic uni req 1
usbdev_suspend_req logic uni rcv 1
usbdev_wake_ack logic uni rcv 1
usbdev_bus_reset logic uni req 1
usbdev_sense_lost logic uni req 1
usbdev_wake_detect_active logic uni req 1
tl tlul_pkg::tl req_rsp rsp 1

Interrupts: none

Security Alerts:

Alert NameDescription
fatal_fault

This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures:

Countermeasure IDDescription
PINMUX.BUS.INTEGRITY

End-to-end bus integrity scheme.

Parameters

The following table lists the main parameters used throughout the pinmux design. Note that the pinmux is generated based on the system configuration, and hence these parameters are placed into a package. The pinout and pinmux mappings are listed under Pinout and Pinmux Mapping for specific top-level configurations.

Parameter Description
NPeriphOut Number of peripheral outputs.
NPeriphIn Number of peripheral input.
NMioPads Number of muxed bidirectional pads.
NDioPads Number of dedicated pads.

Signals

The table below lists the pinmux signals. The number of dedicated and muxed IOs is parametric, and hence the signals are stacked in packed arrays.

Signal Direction Type Description
pin_wkup_req_o output logic Wakeup request from wakeup detectors, to the power manager, running on the AON clock.
usb_wkup_req_o output logic Wakeup request from USB wakeup detector, going to the power manager, running on the AON clock.
sleep_en_i input logic Level signal that is asserted when the power manager enters sleep.
strap_en_i input logic This signal is pulsed high by the power manager after reset in order to sample the HW straps.
lc_dft_en_i input lc_ctrl_pkg::lc_tx_t Test enable qualifier coming from life cycle controller, used for HW strap qualification.
lc_hw_debug_en_i input lc_ctrl_pkg::lc_tx_t Debug enable qualifier coming from life cycle controller, used for HW strap qualification.
dft_strap_test_o output pinmux_pkg::dft_strap_test_req_t Sampled DFT strap values, going to the DFT TAP.
dft_hold_tap_sel_i output logic TAP selection hold indication, asserted by the DFT TAP during boundary scan.
lc_jtag_o output jtag_pkg::jtag_req_t Qualified JTAG signals for life cycle controller TAP.
lc_jtag_i input jtag_pkg::jtag_rsp_t Qualified JTAG signals for life cycle controller TAP.
rv_jtag_o output jtag_pkg::jtag_req_t Qualified JTAG signals for RISC-V processor TAP.
rv_jtag_i input jtag_pkg::jtag_rsp_t Qualified JTAG signals for RISC-V processor TAP.
dft_jtag_o output jtag_pkg::jtag_req_t Qualified JTAG signals for DFT TAP.
dft_jtag_i input jtag_pkg::jtag_rsp_t Qualified JTAG signals for DFT TAP.
usb_out_of_rst_i input logic Indicates whether the USB has come out of reset, coming from the USB device.
usb_aon_wake_en_i input logic Enables the USB wakeup feature, coming from the USB device.
usb_aon_wake_ack_i input logic Acknowledges the USB wakeup request, coming from the USB device.
usb_suspend_i input logic Indicates whether USB is in suspended state, coming from the USB device.
usb_state_debug_o output usbdev_pkg::awk_state_t Debug information about the wake state, going to the USB device.
periph_to_mio_i[NPeriphOut-1:0] input packed logic Signals from NPeriphOut muxed peripheral outputs coming into the pinmux.
periph_to_mio_oe_i[NPeriphOut-1:0] input packed logic Signals from NPeriphOut muxed peripheral output enables coming into the pinmux.
mio_to_periph_o[NPeriphIn-1:0] output packed logic Signals to NPeriphIn muxed peripherals coming from the pinmux.
periph_to_dio_i[NDioPads-1:0] input packed logic Signals from NDioPads dedicated peripheral outputs coming into the pinmux.
periph_to_dio_oe_i[NDioPads-1:0] input packed logic Signals from NDioPads dedicated peripheral output enables coming into the pinmux.
dio_to_periph_o[NDioPads-1:0] output packed logic Signals to NDioPads dedicated peripherals coming from the pinmux.
mio_attr_o[NMioPads-1:0] output prim_pad_wrapper_pkg::pad_attr_t Packed array containing the pad attributes of all muxed IOs.
mio_out_o[NMioPads-1:0] output packed logic Signals to NMioPads bidirectional muxed pads as output data.
mio_oe_o[NMioPads-1:0] output packed logic Signals to NMioPads bidirectional muxed pads as output enables.
mio_in_i[NMioPads-1:0] input packed logic Signals from NMioPads bidirectional muxed pads as input data.
dio_attr_o[NDioPads-1:0] output prim_pad_wrapper_pkg::pad_attr_t Packed array containing the pad attributes of all dedicated IOs.
dio_out_o[NDioPads-1:0] output packed logic Signals to NDioPads bidirectional dedicated pads as output data.
dio_oe_o[NDioPads-1:0] output packed logic Signals to NDioPads bidirectional dedicated pads as output enables.
dio_in_i[NDioPads-1:0] input packed logic Signals from NDioPads bidirectional dedicated pads as input data.

Muxing Matrix

The diagram below shows connectivity between four arbitrary chip pins, named MIO0 .. MIO3, and several muxed peripheral inputs and outputs. This shows the connectivity available in all directions, as well as the control registers described later in this document. Two example peripherals (uart and spidev) are attached to the pinmux in this example, one with one input and one output, the other with three inputs and one output. The diagram also shows the padring module which instantiates the bidirectional chip pads with output enable control.

Pinmux Block Diagram

Note that apart from selecting a specific input pad, the periph_insel[*] signals can also be used to tie the peripheral input to 0 or 1. Likewise, the output select signals mio_outsel[*] can also be used to constantly drive an output pin to 0/1 or to put it into high-Z state (default). The output enable and the associated data signal (i.e. periph_to_mio and periph_to_mio_oe) are indexed with the same select signal to allow the peripheral hardware to determine the pad direction instead of demoting that control to SW.

Retention Logic

As illustrated in the picture above, all muxing matrix and DIO outputs are routed through the retention logic, which essentially consists of a set of multiplexors and two retention registers per output (one register is for the output data and one for the output enable). This multiplexor can be configured to be automatically activated upon sleep entry in order to either drive the output low, high, high-Z or to the last seen value (keep). If no sleep behavior is specified, the retention logic will continue to drive out the value coming from the peripheral side, which can be useful for peripherals that reside in the AON domain.

The sleep behavior of all outputs is activated in parallel via a trigger signal asserted by the power manager. Once activated, it is the task of SW to disable the sleep behavior for each individual pin when waking up from sleep. This ensures that the output values remain stable until the system and its peripherals have been re-initialized.

Wakeup Detectors

The pinmux contains eight programmable wakeup detector modules that can listen on any of the MIO or DIO pins. Each detector contains a debounce filter and an 8bit counter running on the AON clock domain. The detectors can be programmed via the WKUP_DETECTOR_0 and WKUP_DETECTOR_CNT_TH_0 registers to detect the following patterns:

  • rising edge
  • falling edge
  • rising or falling edge
  • positive pulse up to 255 AON clock cycles in length
  • negative pulse up to 255 AON clock cycles in length

Note that for all patterns listed above, the input signal is sampled with the AON clock. This means that the input signal needs to remain stable for at least one AON clock cycle after a level change for the detector to recognize the event (depending on the debounce filter configuration, the signal needs to remain stable for multiple clock cycles).

If a pattern is detected, the wakeup detector will send a wakeup request to the power manager, and the cause bit corresponding to that detector will be set in the WKUP_CAUSE register.

Note that the wkup detector should be disabled by setting WKUP_DETECTOR_EN_0 before changing the detection mode. The reason for that is that the pulse width counter is NOT cleared upon a mode change while the detector is enabled.

Strap Sampling and TAP Isolation

The pinmux contains a set of dedicated HW “straps”, which are essentially signals that are multiplexed onto fixed MIO pad locations. Depending on the life cycle state, these straps are either continuously sampled, or latched right after POR.

There are two groups of HW straps:

  1. Three DFT straps that determine the DFT mode. These bits are output via the dft_strap_test_o signal such that they can be routed to the tool-inserted DFT controller.
  2. Two TAP selection straps for determining which TAP should be multiplexed onto the JTAG IOs.

The conditions under which these two strap groups are sampled are listed in the tables below. Note that the HW straps can be used just like regular GPIOs once they have been sampled.

Strap Group \ Life Cycle State TEST_UNLOCKED* RMA DEV All Other States
DFT straps Once at boot Once at boot - -
TAP strap 0 Continuously Continuously Once at boot Once at boot
TAP strap 1 Continuously Continuously Once at boot -

Once at boot: Sampled once after life cycle initialization (sampling event is initiated by pwrmgr).

Continuously: Sampled continuously after life cycle initialization.

The TAP muxing logic is further qualified by the life cycle state in order to isolate the TAPs in certain life cycle states. The following table lists the TAP strap encoding and the life cycle states in which the associated TAPs can be selected and accessed.

TAP strap 1 TAP strap 0 Life Cycle State Selected TAP
0 0 All states -
0 1 All states Life Cycle
1 0 TEST_UNLOCKED*, RMA, DEV RISC-V
1 1 TEST_UNLOCKED*, RMA DFT

Note that the tool-inserted DFT controller may assert the dft_hold_tap_sel_i during a test (e.g. boundary scan) in which case the pinmux will temporarily pause sampling of the TAP selection straps.

Also, it should be noted that the pad attributes of all JTAG IOs will be gated to all-zero temporarily, while the JTAG is enabled (this does not affect the values in the CSRs). This is to ensure that any functional attributes like inversion or pull-ups / pull-downs do not interfere with the JTAG while it is in use.

For more information about the life cycle states, see Life Cycle Controller Specification and the Life Cycle Definition Table.

Generic Pad Wrapper

The generic pad wrapper is intended to abstract away implementation differences between the target technologies by providing a generic interface that is compatible with the padring module. It is the task of the RTL build flow to select the appropriate pad wrapper implementation.

A specific implementation of a pad wrapper may choose to instantiate a technology primitive (as it is common in ASIC flows), or it may choose to model the functionality behaviorally such that it can be inferred by the technology mapping tool (e.g., in the case of an FPGA target). It is permissible to omit the implementation of all IO attributes except input/output inversion.

The generic pad wrapper must expose the following IOs and parameters, even if they are not connected internally. In particular, the pad attribute struct attr_i must contain all fields listed below, even if not all attributes are supported (it is permissible to just leave them unconnected in the pad wrapper implementation).

Parameter Default Description
PadType BidirStd Pad variant to be instantiated (technology-specific)
ScanRole NoScan Scan role, can be NoScan, ScanIn or ScanOut

Note that PadType is a technology-specific parameter. The generic pad wrapper only implements variant BidirStd, but for other target technologies, this parameter can be used to select among a variety of different pad flavors.

The ScanRole parameter determines the behavior when scanmode is enabled. Depending on whether a given pad acts as a scan input or output, certain pad attributes and functionalities need to be bypassed. This parameter is typically only relevant for ASIC targets and therefore not modeled in the generic pad model.

Also note that the pad wrapper may implement a “virtual” open-drain termination, where standard bidirectional pads are employed, but instead of driving the output high for a logic 1 the pad is put into tristate mode.

Signal Direction Type Description
clk_scan_i input logic Scan clock of the pad
scanmode_i input logic Scan mode enable of the pad
pok_i input pad_pok_t Technology-specific power sequencing signals
inout_io inout wire Bidirectional inout of the pad
in_o output logic Input data signal
in_raw_o output logic Un-inverted input data signal
out_i input logic Output data signal
oe_i input logic Output data enable
attr_i[0] input logic Input/output inversion
attr_i[1] input logic Virtual open-drain enable
attr_i[2] input logic Pull enable
attr_i[3] input logic Pull select (0: pull-down, 1: pull-up)
attr_i[4] input logic Keeper enable
attr_i[5] input logic Schmitt trigger enable
attr_i[6] input logic Open drain enable
attr_i[8:7] input logic Slew rate (0x0: slowest, 0x3: fastest)
attr_i[12:9] input logic Drive strength (0x0: weakest, 0xf: strongest)

Note that the corresponding pad attribute registers MIO_PAD_ATTR_0 and DIO_PAD_ATTR_0 have “writes-any-reads-legal” (WARL) behavior (see also pad attributes).

Programmers Guide

Pad Attributes

Software should determine and program the pad attributes at startup, or reprogram the attributes when the functionality requirements change at runtime.

This can be achieved by writing to the MIO_PAD_ATTR_0 and DIO_PAD_ATTR_0 registers. Note that the IO attributes should be configured before enabling muxed IOs going through the pinmux matrix in order to avoid undesired electrical behavior and/or contention at the pads.

The pad attributes configuration can be locked down individually for each pad via the MIO_PAD_ATTR_REGWEN_0 and DIO_PAD_ATTR_REGWEN_0 registers. The configuration can then not be altered anymore until the next system reset.

The following pad attributes are supported by this register layout by default:

ATTR Bits Description Access
0 Input/output inversion WARL
1 Virtual open drain enable WARL
2 Pull enable WARL
3 Pull select (0: down, 1: up) WARL
4 Keeper enable WARL
5 Schmitt trigger enable WARL
6 Open drain enable WARL
8:7 Slew rate (0x0: slowest, 0x3: fastest) WARL
12:9 Drive strength (0x0: weakest, 0xf: strongest) WARL

Since some of the pad attributes may not be implemented, SW can probe this capability by writing the CSRs and read them back to determine whether the value was legal. This behavior is also referred to as “writes-any-reads-legal” or “WARL” in the RISC-V world. For example, certain pads may only support two drive-strength bits, instead of four. The unsupported drive-strength bits in the corresponding CSRs would then always read as zero, even if SW attempts to set them to 1.

Pinmux Configuration

Upon POR, the pinmux state is such that all MIO outputs are high-Z, and all MIO peripheral inputs are tied off to 0. Software should determine and program the pinmux mapping at startup, or reprogram it when the functionality requirements change at runtime. This can be achieved by writing the following values to the PERIPH_INSEL_0 and MIO_OUTSEL_0 registers.

periph_insel Value Selected Input Signal
0 Constant zero (default)
1 Constant one
2 + k Corresponding MIO input signal at index k

The global default at reset is 0, but the default of individual signals can be overridden at design time, if needed.

mio_outsel Value Selected Output signal
0 Constant zero (default)
1 Constant one
2 High-Z
3 + k Corresponding peripheral output signal at index k

The global default at reset is 2, but the default of individual signals can be overridden at design time, if needed.

Note that the pinmux configuration should be sequenced after any IO attribute-specific configuration in the MIO_PAD_ATTR_0 and DIO_PAD_ATTR_0 registers to avoid any unwanted electric behavior and/or contention. If needed, each select signal can be individually locked down via MIO_PERIPH_INSEL_REGWEN_0 or MIO_OUTSEL_REGWEN_0. The configuration can then not be altered anymore until the next system reset.

Sleep Features

The sleep behavior of each individual MIO or DIO can be defined via the ( MIO_PAD_SLEEP_EN_0, DIO_PAD_SLEEP_EN_0, MIO_PAD_SLEEP_MODE_0 and DIO_PAD_SLEEP_MODE_0) registers. Available sleep behaviors are:

dio/mio_pad_sleep_en Value dio/mio_pad_sleep_mode Value Sleep Behavior
0 - Drive (default)
1 0 Tie-low
1 1 Tie-high
1 2 High-Z
1 3 Keep last value

Note that if the behavior is set to “Drive”, the sleep mode will not be activated upon sleep entry. Rather, the retention logic continues to drive the value coming from the peripheral side. Also note that the sleep logic is located after the pinmux matrix, hence the sleep configuration is per MIO pad and not per MIO peripheral.

Before sleep entry, SW should configure the appropriate sleep behavior of all MIOs/DIOs via MIO_PAD_SLEEP_MODE_0, DIO_PAD_SLEEP_MODE_0. This configuration can be optionally locked down, in which case it cannot be modified again until POR. The configured behavior is then activated for all pads that have sleep mode set to enabled ( MIO_PAD_SLEEP_EN_0 and DIO_PAD_SLEEP_EN_0) at once by the power manager during the sleep entry sequence.

When exiting sleep, the task of disabling the sleep behavior is however up to SW. I.e., it must clear the per-pad sleep status bits in registers MIO_PAD_SLEEP_STATUS_0 and DIO_PAD_SLEEP_STATUS_0 that have been set upon sleep entry. The rationale for this is that it may not be desirable to disable sleep behavior on all pads at once due to some additional book keeping / re-initialization that needs to be performed while exiting sleep.

Wakeup Features

The pinmux contains eight wakeup detectors. These detectors can be individually enabled and disabled regardless of the sleep state. This ensures that SW can set them up before and disable them after sleep in order to ensure that no events are missed during sleep entry and exit.

For more information on the patterns supported by the wakeup detectors, see wakeup detectors.

A typical programming sequence for the wakeup detectors looks as follows:

  1. Before initiating any sleep mode, SW should configure the wakeup detectors appropriately and enable them via the WKUP_DETECTOR_0, WKUP_DETECTOR_CNT_TH_0 and WKUP_DETECTOR_PADSEL_0 registers.

  2. Optionally, lock the wakeup detector configuration via the WKUP_DETECTOR_REGWEN_0 registers.

  3. During sleep, the wakeup detectors will trigger a wakeup request if a matching pattern has been observed. A bit corresponding to the wakeup detector that has observed the pattern will be set in the WKUP_CAUSE register.

  4. When exiting sleep, SW should read the wake info register in the power manager to determine the reason(s) for the wakeup request.

  5. If the wakeup request was due to a pin wakeup pattern detector, SW should inspect the WKUP_CAUSE registers in order to determine the exact cause.

  6. SW should in any case disable the wakeup detectors and clear the WKUP_CAUSE registers once it is safe to do so (in order to not miss any events). Note that the WKUP_CAUSE registers reside in the slow AON clock domain, and hence clearing them takes a few uS to take effect. If needed, a SW readback can be performed to ensure that the clear operation has completed successfully.

Pinout and Pinmux Mapping

The tables below summarize the pinout and pinmux connectivity for certain top-level designs.

Top Earlgrey

Target Name #IO Banks #Muxed Pads #Direct Pads #Manual Pads #Total Pads Pinout / Pinmux Tables
ASIC 4 47 14 10 71 Pinout Table
CW310 4 47 14 15 76 Pinout Table

Device Interface Functions (DIFs)

To use this DIF, include the following C header:

#include "sw/device/lib/dif/dif_pinmux.h"

This header provides the following device interface functions:

Register Table

The register description below matches the instance in the Earl Grey top level design.

Similar register descriptions can be generated with different parameterizations.

Summary
Name Offset Length Description
PINMUX.ALERT_TEST 0x0 4

Alert Test Register

PINMUX.MIO_PERIPH_INSEL_REGWEN_0 0x4 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_1 0x8 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_2 0xc 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_3 0x10 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_4 0x14 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_5 0x18 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_6 0x1c 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_7 0x20 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_8 0x24 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_9 0x28 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_10 0x2c 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_11 0x30 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_12 0x34 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_13 0x38 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_14 0x3c 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_15 0x40 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_16 0x44 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_17 0x48 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_18 0x4c 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_19 0x50 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_20 0x54 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_21 0x58 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_22 0x5c 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_23 0x60 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_24 0x64 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_25 0x68 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_26 0x6c 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_27 0x70 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_28 0x74 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_29 0x78 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_30 0x7c 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_31 0x80 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_32 0x84 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_33 0x88 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_34 0x8c 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_35 0x90 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_36 0x94 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_37 0x98 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_38 0x9c 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_39 0xa0 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_40 0xa4 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_41 0xa8 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_42 0xac 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_43 0xb0 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_44 0xb4 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_45 0xb8 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_46 0xbc 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_47 0xc0 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_48 0xc4 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_49 0xc8 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_50 0xcc 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_51 0xd0 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_52 0xd4 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_53 0xd8 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_54 0xdc 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_55 0xe0 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_REGWEN_56 0xe4 4

Register write enable for MIO peripheral input selects.

PINMUX.MIO_PERIPH_INSEL_0 0xe8 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_1 0xec 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_2 0xf0 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_3 0xf4 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_4 0xf8 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_5 0xfc 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_6 0x100 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_7 0x104 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_8 0x108 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_9 0x10c 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_10 0x110 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_11 0x114 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_12 0x118 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_13 0x11c 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_14 0x120 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_15 0x124 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_16 0x128 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_17 0x12c 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_18 0x130 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_19 0x134 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_20 0x138 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_21 0x13c 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_22 0x140 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_23 0x144 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_24 0x148 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_25 0x14c 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_26 0x150 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_27 0x154 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_28 0x158 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_29 0x15c 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_30 0x160 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_31 0x164 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_32 0x168 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_33 0x16c 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_34 0x170 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_35 0x174 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_36 0x178 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_37 0x17c 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_38 0x180 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_39 0x184 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_40 0x188 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_41 0x18c 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_42 0x190 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_43 0x194 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_44 0x198 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_45 0x19c 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_46 0x1a0 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_47 0x1a4 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_48 0x1a8 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_49 0x1ac 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_50 0x1b0 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_51 0x1b4 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_52 0x1b8 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_53 0x1bc 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_54 0x1c0 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_55 0x1c4 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_PERIPH_INSEL_56 0x1c8 4

For each peripheral input, this selects the muxable pad input.

PINMUX.MIO_OUTSEL_REGWEN_0 0x1cc 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_1 0x1d0 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_2 0x1d4 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_3 0x1d8 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_4 0x1dc 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_5 0x1e0 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_6 0x1e4 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_7 0x1e8 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_8 0x1ec 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_9 0x1f0 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_10 0x1f4 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_11 0x1f8 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_12 0x1fc 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_13 0x200 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_14 0x204 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_15 0x208 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_16 0x20c 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_17 0x210 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_18 0x214 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_19 0x218 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_20 0x21c 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_21 0x220 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_22 0x224 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_23 0x228 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_24 0x22c 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_25 0x230 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_26 0x234 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_27 0x238 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_28 0x23c 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_29 0x240 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_30 0x244 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_31 0x248 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_32 0x24c 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_33 0x250 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_34 0x254 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_35 0x258 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_36 0x25c 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_37 0x260 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_38 0x264 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_39 0x268 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_40 0x26c 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_41 0x270 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_42 0x274 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_43 0x278 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_44 0x27c 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_45 0x280 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_REGWEN_46 0x284 4

Register write enable for MIO output selects.

PINMUX.MIO_OUTSEL_0 0x288 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_1 0x28c 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_2 0x290 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_3 0x294 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_4 0x298 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_5 0x29c 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_6 0x2a0 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_7 0x2a4 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_8 0x2a8 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_9 0x2ac 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_10 0x2b0 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_11 0x2b4 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_12 0x2b8 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_13 0x2bc 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_14 0x2c0 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_15 0x2c4 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_16 0x2c8 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_17 0x2cc 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_18 0x2d0 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_19 0x2d4 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_20 0x2d8 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_21 0x2dc 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_22 0x2e0 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_23 0x2e4 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_24 0x2e8 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_25 0x2ec 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_26 0x2f0 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_27 0x2f4 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_28 0x2f8 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_29 0x2fc 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_30 0x300 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_31 0x304 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_32 0x308 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_33 0x30c 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_34 0x310 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_35 0x314 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_36 0x318 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_37 0x31c 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_38 0x320 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_39 0x324 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_40 0x328 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_41 0x32c 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_42 0x330 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_43 0x334 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_44 0x338 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_45 0x33c 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_OUTSEL_46 0x340 4

For each muxable pad, this selects the peripheral output.

PINMUX.MIO_PAD_ATTR_REGWEN_0 0x344 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_1 0x348 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_2 0x34c 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_3 0x350 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_4 0x354 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_5 0x358 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_6 0x35c 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_7 0x360 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_8 0x364 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_9 0x368 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_10 0x36c 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_11 0x370 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_12 0x374 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_13 0x378 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_14 0x37c 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_15 0x380 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_16 0x384 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_17 0x388 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_18 0x38c 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_19 0x390 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_20 0x394 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_21 0x398 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_22 0x39c 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_23 0x3a0 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_24 0x3a4 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_25 0x3a8 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_26 0x3ac 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_27 0x3b0 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_28 0x3b4 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_29 0x3b8 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_30 0x3bc 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_31 0x3c0 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_32 0x3c4 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_33 0x3c8 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_34 0x3cc 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_35 0x3d0 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_36 0x3d4 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_37 0x3d8 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_38 0x3dc 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_39 0x3e0 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_40 0x3e4 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_41 0x3e8 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_42 0x3ec 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_43 0x3f0 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_44 0x3f4 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_45 0x3f8 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_REGWEN_46 0x3fc 4

Register write enable for MIO PAD attributes.

PINMUX.MIO_PAD_ATTR_0 0x400 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_1 0x404 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_2 0x408 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_3 0x40c 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_4 0x410 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_5 0x414 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_6 0x418 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_7 0x41c 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_8 0x420 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_9 0x424 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_10 0x428 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_11 0x42c 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_12 0x430 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_13 0x434 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_14 0x438 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_15 0x43c 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_16 0x440 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_17 0x444 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_18 0x448 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_19 0x44c 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_20 0x450 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_21 0x454 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_22 0x458 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_23 0x45c 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_24 0x460 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_25 0x464 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_26 0x468 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_27 0x46c 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_28 0x470 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_29 0x474 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_30 0x478 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_31 0x47c 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_32 0x480 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_33 0x484 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_34 0x488 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_35 0x48c 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_36 0x490 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_37 0x494 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_38 0x498 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_39 0x49c 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_40 0x4a0 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_41 0x4a4 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_42 0x4a8 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_43 0x4ac 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_44 0x4b0 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_45 0x4b4 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_ATTR_46 0x4b8 4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.DIO_PAD_ATTR_REGWEN_0 0x4bc 4

Register write enable for DIO PAD attributes.

PINMUX.DIO_PAD_ATTR_REGWEN_1 0x4c0 4

Register write enable for DIO PAD attributes.

PINMUX.DIO_PAD_ATTR_REGWEN_2 0x4c4 4

Register write enable for DIO PAD attributes.

PINMUX.DIO_PAD_ATTR_REGWEN_3 0x4c8 4

Register write enable for DIO PAD attributes.

PINMUX.DIO_PAD_ATTR_REGWEN_4 0x4cc 4

Register write enable for DIO PAD attributes.

PINMUX.DIO_PAD_ATTR_REGWEN_5 0x4d0 4

Register write enable for DIO PAD attributes.

PINMUX.DIO_PAD_ATTR_REGWEN_6 0x4d4 4

Register write enable for DIO PAD attributes.

PINMUX.DIO_PAD_ATTR_REGWEN_7 0x4d8 4

Register write enable for DIO PAD attributes.

PINMUX.DIO_PAD_ATTR_REGWEN_8 0x4dc 4

Register write enable for DIO PAD attributes.

PINMUX.DIO_PAD_ATTR_REGWEN_9 0x4e0 4

Register write enable for DIO PAD attributes.

PINMUX.DIO_PAD_ATTR_REGWEN_10 0x4e4 4

Register write enable for DIO PAD attributes.

PINMUX.DIO_PAD_ATTR_REGWEN_11 0x4e8 4

Register write enable for DIO PAD attributes.

PINMUX.DIO_PAD_ATTR_REGWEN_12 0x4ec 4

Register write enable for DIO PAD attributes.

PINMUX.DIO_PAD_ATTR_REGWEN_13 0x4f0 4

Register write enable for DIO PAD attributes.

PINMUX.DIO_PAD_ATTR_REGWEN_14 0x4f4 4

Register write enable for DIO PAD attributes.

PINMUX.DIO_PAD_ATTR_REGWEN_15 0x4f8 4

Register write enable for DIO PAD attributes.

PINMUX.DIO_PAD_ATTR_0 0x4fc 4

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.DIO_PAD_ATTR_1 0x500 4

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.DIO_PAD_ATTR_2 0x504 4

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.DIO_PAD_ATTR_3 0x508 4

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.DIO_PAD_ATTR_4 0x50c 4

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.DIO_PAD_ATTR_5 0x510 4

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.DIO_PAD_ATTR_6 0x514 4

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.DIO_PAD_ATTR_7 0x518 4

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.DIO_PAD_ATTR_8 0x51c 4

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.DIO_PAD_ATTR_9 0x520 4

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.DIO_PAD_ATTR_10 0x524 4

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.DIO_PAD_ATTR_11 0x528 4

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.DIO_PAD_ATTR_12 0x52c 4

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.DIO_PAD_ATTR_13 0x530 4

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.DIO_PAD_ATTR_14 0x534 4

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.DIO_PAD_ATTR_15 0x538 4

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

PINMUX.MIO_PAD_SLEEP_STATUS_0 0x53c 4

Register indicating whether the corresponding pad is in sleep mode.

PINMUX.MIO_PAD_SLEEP_STATUS_1 0x540 4

Register indicating whether the corresponding pad is in sleep mode.

PINMUX.MIO_PAD_SLEEP_REGWEN_0 0x544 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_1 0x548 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_2 0x54c 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_3 0x550 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_4 0x554 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_5 0x558 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_6 0x55c 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_7 0x560 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_8 0x564 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_9 0x568 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_10 0x56c 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_11 0x570 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_12 0x574 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_13 0x578 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_14 0x57c 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_15 0x580 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_16 0x584 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_17 0x588 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_18 0x58c 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_19 0x590 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_20 0x594 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_21 0x598 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_22 0x59c 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_23 0x5a0 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_24 0x5a4 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_25 0x5a8 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_26 0x5ac 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_27 0x5b0 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_28 0x5b4 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_29 0x5b8 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_30 0x5bc 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_31 0x5c0 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_32 0x5c4 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_33 0x5c8 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_34 0x5cc 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_35 0x5d0 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_36 0x5d4 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_37 0x5d8 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_38 0x5dc 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_39 0x5e0 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_40 0x5e4 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_41 0x5e8 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_42 0x5ec 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_43 0x5f0 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_44 0x5f4 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_45 0x5f8 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_REGWEN_46 0x5fc 4

Register write enable for MIO sleep value configuration.

PINMUX.MIO_PAD_SLEEP_EN_0 0x600 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_1 0x604 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_2 0x608 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_3 0x60c 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_4 0x610 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_5 0x614 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_6 0x618 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_7 0x61c 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_8 0x620 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_9 0x624 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_10 0x628 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_11 0x62c 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_12 0x630 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_13 0x634 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_14 0x638 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_15 0x63c 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_16 0x640 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_17 0x644 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_18 0x648 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_19 0x64c 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_20 0x650 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_21 0x654 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_22 0x658 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_23 0x65c 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_24 0x660 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_25 0x664 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_26 0x668 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_27 0x66c 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_28 0x670 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_29 0x674 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_30 0x678 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_31 0x67c 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_32 0x680 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_33 0x684 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_34 0x688 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_35 0x68c 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_36 0x690 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_37 0x694 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_38 0x698 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_39 0x69c 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_40 0x6a0 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_41 0x6a4 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_42 0x6a8 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_43 0x6ac 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_44 0x6b0 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_45 0x6b4 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_EN_46 0x6b8 4

Enables the sleep mode of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_0 0x6bc 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_1 0x6c0 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_2 0x6c4 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_3 0x6c8 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_4 0x6cc 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_5 0x6d0 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_6 0x6d4 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_7 0x6d8 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_8 0x6dc 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_9 0x6e0 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_10 0x6e4 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_11 0x6e8 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_12 0x6ec 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_13 0x6f0 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_14 0x6f4 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_15 0x6f8 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_16 0x6fc 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_17 0x700 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_18 0x704 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_19 0x708 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_20 0x70c 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_21 0x710 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_22 0x714 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_23 0x718 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_24 0x71c 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_25 0x720 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_26 0x724 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_27 0x728 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_28 0x72c 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_29 0x730 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_30 0x734 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_31 0x738 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_32 0x73c 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_33 0x740 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_34 0x744 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_35 0x748 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_36 0x74c 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_37 0x750 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_38 0x754 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_39 0x758 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_40 0x75c 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_41 0x760 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_42 0x764 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_43 0x768 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_44 0x76c 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_45 0x770 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.MIO_PAD_SLEEP_MODE_46 0x774 4

Defines sleep behavior of the corresponding muxed pad.

PINMUX.DIO_PAD_SLEEP_STATUS 0x778 4

Register indicating whether the corresponding pad is in sleep mode.

PINMUX.DIO_PAD_SLEEP_REGWEN_0 0x77c 4

Register write enable for DIO sleep value configuration.

PINMUX.DIO_PAD_SLEEP_REGWEN_1 0x780 4

Register write enable for DIO sleep value configuration.

PINMUX.DIO_PAD_SLEEP_REGWEN_2 0x784 4

Register write enable for DIO sleep value configuration.

PINMUX.DIO_PAD_SLEEP_REGWEN_3 0x788 4

Register write enable for DIO sleep value configuration.

PINMUX.DIO_PAD_SLEEP_REGWEN_4 0x78c 4

Register write enable for DIO sleep value configuration.

PINMUX.DIO_PAD_SLEEP_REGWEN_5 0x790 4

Register write enable for DIO sleep value configuration.

PINMUX.DIO_PAD_SLEEP_REGWEN_6 0x794 4

Register write enable for DIO sleep value configuration.

PINMUX.DIO_PAD_SLEEP_REGWEN_7 0x798 4

Register write enable for DIO sleep value configuration.

PINMUX.DIO_PAD_SLEEP_REGWEN_8 0x79c 4

Register write enable for DIO sleep value configuration.

PINMUX.DIO_PAD_SLEEP_REGWEN_9 0x7a0 4

Register write enable for DIO sleep value configuration.

PINMUX.DIO_PAD_SLEEP_REGWEN_10 0x7a4 4

Register write enable for DIO sleep value configuration.

PINMUX.DIO_PAD_SLEEP_REGWEN_11 0x7a8 4

Register write enable for DIO sleep value configuration.

PINMUX.DIO_PAD_SLEEP_REGWEN_12 0x7ac 4

Register write enable for DIO sleep value configuration.

PINMUX.DIO_PAD_SLEEP_REGWEN_13 0x7b0 4

Register write enable for DIO sleep value configuration.

PINMUX.DIO_PAD_SLEEP_REGWEN_14 0x7b4 4

Register write enable for DIO sleep value configuration.

PINMUX.DIO_PAD_SLEEP_REGWEN_15 0x7b8 4

Register write enable for DIO sleep value configuration.

PINMUX.DIO_PAD_SLEEP_EN_0 0x7bc 4

Enables the sleep mode of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_EN_1 0x7c0 4

Enables the sleep mode of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_EN_2 0x7c4 4

Enables the sleep mode of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_EN_3 0x7c8 4

Enables the sleep mode of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_EN_4 0x7cc 4

Enables the sleep mode of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_EN_5 0x7d0 4

Enables the sleep mode of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_EN_6 0x7d4 4

Enables the sleep mode of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_EN_7 0x7d8 4

Enables the sleep mode of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_EN_8 0x7dc 4

Enables the sleep mode of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_EN_9 0x7e0 4

Enables the sleep mode of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_EN_10 0x7e4 4

Enables the sleep mode of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_EN_11 0x7e8 4

Enables the sleep mode of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_EN_12 0x7ec 4

Enables the sleep mode of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_EN_13 0x7f0 4

Enables the sleep mode of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_EN_14 0x7f4 4

Enables the sleep mode of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_EN_15 0x7f8 4

Enables the sleep mode of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_MODE_0 0x7fc 4

Defines sleep behavior of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_MODE_1 0x800 4

Defines sleep behavior of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_MODE_2 0x804 4

Defines sleep behavior of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_MODE_3 0x808 4

Defines sleep behavior of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_MODE_4 0x80c 4

Defines sleep behavior of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_MODE_5 0x810 4

Defines sleep behavior of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_MODE_6 0x814 4

Defines sleep behavior of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_MODE_7 0x818 4

Defines sleep behavior of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_MODE_8 0x81c 4

Defines sleep behavior of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_MODE_9 0x820 4

Defines sleep behavior of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_MODE_10 0x824 4

Defines sleep behavior of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_MODE_11 0x828 4

Defines sleep behavior of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_MODE_12 0x82c 4

Defines sleep behavior of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_MODE_13 0x830 4

Defines sleep behavior of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_MODE_14 0x834 4

Defines sleep behavior of the corresponding dedicated pad.

PINMUX.DIO_PAD_SLEEP_MODE_15 0x838 4

Defines sleep behavior of the corresponding dedicated pad.

PINMUX.WKUP_DETECTOR_REGWEN_0 0x83c 4

Register write enable for wakeup detectors.

PINMUX.WKUP_DETECTOR_REGWEN_1 0x840 4

Register write enable for wakeup detectors.

PINMUX.WKUP_DETECTOR_REGWEN_2 0x844 4

Register write enable for wakeup detectors.

PINMUX.WKUP_DETECTOR_REGWEN_3 0x848 4

Register write enable for wakeup detectors.

PINMUX.WKUP_DETECTOR_REGWEN_4 0x84c 4

Register write enable for wakeup detectors.

PINMUX.WKUP_DETECTOR_REGWEN_5 0x850 4

Register write enable for wakeup detectors.

PINMUX.WKUP_DETECTOR_REGWEN_6 0x854 4

Register write enable for wakeup detectors.

PINMUX.WKUP_DETECTOR_REGWEN_7 0x858 4

Register write enable for wakeup detectors.

PINMUX.WKUP_DETECTOR_EN_0 0x85c 4

Enables for the wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

PINMUX.WKUP_DETECTOR_EN_1 0x860 4

Enables for the wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

PINMUX.WKUP_DETECTOR_EN_2 0x864 4

Enables for the wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

PINMUX.WKUP_DETECTOR_EN_3 0x868 4

Enables for the wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

PINMUX.WKUP_DETECTOR_EN_4 0x86c 4

Enables for the wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

PINMUX.WKUP_DETECTOR_EN_5 0x870 4

Enables for the wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

PINMUX.WKUP_DETECTOR_EN_6 0x874 4

Enables for the wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

PINMUX.WKUP_DETECTOR_EN_7 0x878 4

Enables for the wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

PINMUX.WKUP_DETECTOR_0 0x87c 4

Configuration of wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

PINMUX.WKUP_DETECTOR_1 0x880 4

Configuration of wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

PINMUX.WKUP_DETECTOR_2 0x884 4

Configuration of wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

PINMUX.WKUP_DETECTOR_3 0x888 4

Configuration of wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

PINMUX.WKUP_DETECTOR_4 0x88c 4

Configuration of wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

PINMUX.WKUP_DETECTOR_5 0x890 4

Configuration of wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

PINMUX.WKUP_DETECTOR_6 0x894 4

Configuration of wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

PINMUX.WKUP_DETECTOR_7 0x898 4

Configuration of wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

PINMUX.WKUP_DETECTOR_CNT_TH_0 0x89c 4

Counter thresholds for wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

PINMUX.WKUP_DETECTOR_CNT_TH_1 0x8a0 4

Counter thresholds for wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

PINMUX.WKUP_DETECTOR_CNT_TH_2 0x8a4 4

Counter thresholds for wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

PINMUX.WKUP_DETECTOR_CNT_TH_3 0x8a8 4

Counter thresholds for wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

PINMUX.WKUP_DETECTOR_CNT_TH_4 0x8ac 4

Counter thresholds for wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

PINMUX.WKUP_DETECTOR_CNT_TH_5 0x8b0 4

Counter thresholds for wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

PINMUX.WKUP_DETECTOR_CNT_TH_6 0x8b4 4

Counter thresholds for wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

PINMUX.WKUP_DETECTOR_CNT_TH_7 0x8b8 4

Counter thresholds for wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

PINMUX.WKUP_DETECTOR_PADSEL_0 0x8bc 4

Pad selects for pad wakeup condition detectors. This register is NOT synced to the AON domain since the muxing mechanism is implemented in the same way as the pinmux muxing matrix.

PINMUX.WKUP_DETECTOR_PADSEL_1 0x8c0 4

Pad selects for pad wakeup condition detectors. This register is NOT synced to the AON domain since the muxing mechanism is implemented in the same way as the pinmux muxing matrix.

PINMUX.WKUP_DETECTOR_PADSEL_2 0x8c4 4

Pad selects for pad wakeup condition detectors. This register is NOT synced to the AON domain since the muxing mechanism is implemented in the same way as the pinmux muxing matrix.

PINMUX.WKUP_DETECTOR_PADSEL_3 0x8c8 4

Pad selects for pad wakeup condition detectors. This register is NOT synced to the AON domain since the muxing mechanism is implemented in the same way as the pinmux muxing matrix.

PINMUX.WKUP_DETECTOR_PADSEL_4 0x8cc 4

Pad selects for pad wakeup condition detectors. This register is NOT synced to the AON domain since the muxing mechanism is implemented in the same way as the pinmux muxing matrix.

PINMUX.WKUP_DETECTOR_PADSEL_5 0x8d0 4

Pad selects for pad wakeup condition detectors. This register is NOT synced to the AON domain since the muxing mechanism is implemented in the same way as the pinmux muxing matrix.

PINMUX.WKUP_DETECTOR_PADSEL_6 0x8d4 4

Pad selects for pad wakeup condition detectors. This register is NOT synced to the AON domain since the muxing mechanism is implemented in the same way as the pinmux muxing matrix.

PINMUX.WKUP_DETECTOR_PADSEL_7 0x8d8 4

Pad selects for pad wakeup condition detectors. This register is NOT synced to the AON domain since the muxing mechanism is implemented in the same way as the pinmux muxing matrix.

PINMUX.WKUP_CAUSE 0x8dc 4

Cause registers for wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

PINMUX.ALERT_TEST @ 0x0

Alert Test Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  fatal_fault
BitsTypeResetNameDescription
0wo0x0fatal_fault

Write 1 to trigger one alert event of this kind.


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_0
BitsTypeResetNameDescription
0rw0c0x1EN_0

Register write enable bit. If this is cleared to 0, the corresponding MIO_PERIPH_INSEL is not writable anymore.


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  EN_1
BitsTypeResetNameDescription
0rw0c0x1EN_1

For MIO_PERIPH_INSEL1


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_2
BitsTypeResetNameDescription
0rw0c0x1EN_2

For MIO_PERIPH_INSEL2


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_3
BitsTypeResetNameDescription
0rw0c0x1EN_3

For MIO_PERIPH_INSEL3


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_4
BitsTypeResetNameDescription
0rw0c0x1EN_4

For MIO_PERIPH_INSEL4


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_5
BitsTypeResetNameDescription
0rw0c0x1EN_5

For MIO_PERIPH_INSEL5


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_6
BitsTypeResetNameDescription
0rw0c0x1EN_6

For MIO_PERIPH_INSEL6


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_7
BitsTypeResetNameDescription
0rw0c0x1EN_7

For MIO_PERIPH_INSEL7


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_8
BitsTypeResetNameDescription
0rw0c0x1EN_8

For MIO_PERIPH_INSEL8


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_9
BitsTypeResetNameDescription
0rw0c0x1EN_9

For MIO_PERIPH_INSEL9


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_10
BitsTypeResetNameDescription
0rw0c0x1EN_10

For MIO_PERIPH_INSEL10


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_11
BitsTypeResetNameDescription
0rw0c0x1EN_11

For MIO_PERIPH_INSEL11


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_12
BitsTypeResetNameDescription
0rw0c0x1EN_12

For MIO_PERIPH_INSEL12


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_13
BitsTypeResetNameDescription
0rw0c0x1EN_13

For MIO_PERIPH_INSEL13


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_14
BitsTypeResetNameDescription
0rw0c0x1EN_14

For MIO_PERIPH_INSEL14


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_15
BitsTypeResetNameDescription
0rw0c0x1EN_15

For MIO_PERIPH_INSEL15


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_16
BitsTypeResetNameDescription
0rw0c0x1EN_16

For MIO_PERIPH_INSEL16


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_17
BitsTypeResetNameDescription
0rw0c0x1EN_17

For MIO_PERIPH_INSEL17


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_18
BitsTypeResetNameDescription
0rw0c0x1EN_18

For MIO_PERIPH_INSEL18


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_19
BitsTypeResetNameDescription
0rw0c0x1EN_19

For MIO_PERIPH_INSEL19


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_20
BitsTypeResetNameDescription
0rw0c0x1EN_20

For MIO_PERIPH_INSEL20


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_21
BitsTypeResetNameDescription
0rw0c0x1EN_21

For MIO_PERIPH_INSEL21


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_22
BitsTypeResetNameDescription
0rw0c0x1EN_22

For MIO_PERIPH_INSEL22


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_23
BitsTypeResetNameDescription
0rw0c0x1EN_23

For MIO_PERIPH_INSEL23


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_24
BitsTypeResetNameDescription
0rw0c0x1EN_24

For MIO_PERIPH_INSEL24


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_25
BitsTypeResetNameDescription
0rw0c0x1EN_25

For MIO_PERIPH_INSEL25


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_26
BitsTypeResetNameDescription
0rw0c0x1EN_26

For MIO_PERIPH_INSEL26


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_27
BitsTypeResetNameDescription
0rw0c0x1EN_27

For MIO_PERIPH_INSEL27


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_28
BitsTypeResetNameDescription
0rw0c0x1EN_28

For MIO_PERIPH_INSEL28


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_29
BitsTypeResetNameDescription
0rw0c0x1EN_29

For MIO_PERIPH_INSEL29


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_30
BitsTypeResetNameDescription
0rw0c0x1EN_30

For MIO_PERIPH_INSEL30


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_31
BitsTypeResetNameDescription
0rw0c0x1EN_31

For MIO_PERIPH_INSEL31


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_32
BitsTypeResetNameDescription
0rw0c0x1EN_32

For MIO_PERIPH_INSEL32


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_33
BitsTypeResetNameDescription
0rw0c0x1EN_33

For MIO_PERIPH_INSEL33


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_34
BitsTypeResetNameDescription
0rw0c0x1EN_34

For MIO_PERIPH_INSEL34


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_35
BitsTypeResetNameDescription
0rw0c0x1EN_35

For MIO_PERIPH_INSEL35


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_36
BitsTypeResetNameDescription
0rw0c0x1EN_36

For MIO_PERIPH_INSEL36


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_37
BitsTypeResetNameDescription
0rw0c0x1EN_37

For MIO_PERIPH_INSEL37


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_38
BitsTypeResetNameDescription
0rw0c0x1EN_38

For MIO_PERIPH_INSEL38


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_39
BitsTypeResetNameDescription
0rw0c0x1EN_39

For MIO_PERIPH_INSEL39


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_40
BitsTypeResetNameDescription
0rw0c0x1EN_40

For MIO_PERIPH_INSEL40


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_41
BitsTypeResetNameDescription
0rw0c0x1EN_41

For MIO_PERIPH_INSEL41


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_42
BitsTypeResetNameDescription
0rw0c0x1EN_42

For MIO_PERIPH_INSEL42


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_43
BitsTypeResetNameDescription
0rw0c0x1EN_43

For MIO_PERIPH_INSEL43


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_44
BitsTypeResetNameDescription
0rw0c0x1EN_44

For MIO_PERIPH_INSEL44


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_45
BitsTypeResetNameDescription
0rw0c0x1EN_45

For MIO_PERIPH_INSEL45


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_46
BitsTypeResetNameDescription
0rw0c0x1EN_46

For MIO_PERIPH_INSEL46


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_47
BitsTypeResetNameDescription
0rw0c0x1EN_47

For MIO_PERIPH_INSEL47


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_48
BitsTypeResetNameDescription
0rw0c0x1EN_48

For MIO_PERIPH_INSEL48


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_49
BitsTypeResetNameDescription
0rw0c0x1EN_49

For MIO_PERIPH_INSEL49


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_50
BitsTypeResetNameDescription
0rw0c0x1EN_50

For MIO_PERIPH_INSEL50


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_51
BitsTypeResetNameDescription
0rw0c0x1EN_51

For MIO_PERIPH_INSEL51


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_52
BitsTypeResetNameDescription
0rw0c0x1EN_52

For MIO_PERIPH_INSEL52


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_53
BitsTypeResetNameDescription
0rw0c0x1EN_53

For MIO_PERIPH_INSEL53


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_54
BitsTypeResetNameDescription
0rw0c0x1EN_54

For MIO_PERIPH_INSEL54


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_55
BitsTypeResetNameDescription
0rw0c0x1EN_55

For MIO_PERIPH_INSEL55


Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_56
BitsTypeResetNameDescription
0rw0c0x1EN_56

For MIO_PERIPH_INSEL56


PINMUX.MIO_PERIPH_INSEL_0 @ 0xe8

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_0
31302928272625242322212019181716
 
1514131211109876543210
  IN_0
BitsTypeResetNameDescription
5:0rw0x0IN_0

0: tie constantly to zero, 1: tie constantly to 1,

=2: MIO pads (i.e., add 2 to the native MIO pad index).


PINMUX.MIO_PERIPH_INSEL_1 @ 0xec

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_1
31302928272625242322212019181716
 
1514131211109876543210
  IN_1
BitsTypeResetNameDescription
5:0rw0x0IN_1

For IN1


PINMUX.MIO_PERIPH_INSEL_2 @ 0xf0

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_2
31302928272625242322212019181716
 
1514131211109876543210
  IN_2
BitsTypeResetNameDescription
5:0rw0x0IN_2

For IN2


PINMUX.MIO_PERIPH_INSEL_3 @ 0xf4

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_3
31302928272625242322212019181716
 
1514131211109876543210
  IN_3
BitsTypeResetNameDescription
5:0rw0x0IN_3

For IN3


PINMUX.MIO_PERIPH_INSEL_4 @ 0xf8

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_4
31302928272625242322212019181716
 
1514131211109876543210
  IN_4
BitsTypeResetNameDescription
5:0rw0x0IN_4

For IN4


PINMUX.MIO_PERIPH_INSEL_5 @ 0xfc

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_5
31302928272625242322212019181716
 
1514131211109876543210
  IN_5
BitsTypeResetNameDescription
5:0rw0x0IN_5

For IN5


PINMUX.MIO_PERIPH_INSEL_6 @ 0x100

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_6
31302928272625242322212019181716
 
1514131211109876543210
  IN_6
BitsTypeResetNameDescription
5:0rw0x0IN_6

For IN6


PINMUX.MIO_PERIPH_INSEL_7 @ 0x104

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_7
31302928272625242322212019181716
 
1514131211109876543210
  IN_7
BitsTypeResetNameDescription
5:0rw0x0IN_7

For IN7


PINMUX.MIO_PERIPH_INSEL_8 @ 0x108

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_8
31302928272625242322212019181716
 
1514131211109876543210
  IN_8
BitsTypeResetNameDescription
5:0rw0x0IN_8

For IN8


PINMUX.MIO_PERIPH_INSEL_9 @ 0x10c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_9
31302928272625242322212019181716
 
1514131211109876543210
  IN_9
BitsTypeResetNameDescription
5:0rw0x0IN_9

For IN9


PINMUX.MIO_PERIPH_INSEL_10 @ 0x110

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_10
31302928272625242322212019181716
 
1514131211109876543210
  IN_10
BitsTypeResetNameDescription
5:0rw0x0IN_10

For IN10


PINMUX.MIO_PERIPH_INSEL_11 @ 0x114

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_11
31302928272625242322212019181716
 
1514131211109876543210
  IN_11
BitsTypeResetNameDescription
5:0rw0x0IN_11

For IN11


PINMUX.MIO_PERIPH_INSEL_12 @ 0x118

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_12
31302928272625242322212019181716
 
1514131211109876543210
  IN_12
BitsTypeResetNameDescription
5:0rw0x0IN_12

For IN12


PINMUX.MIO_PERIPH_INSEL_13 @ 0x11c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_13
31302928272625242322212019181716
 
1514131211109876543210
  IN_13
BitsTypeResetNameDescription
5:0rw0x0IN_13

For IN13


PINMUX.MIO_PERIPH_INSEL_14 @ 0x120

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_14
31302928272625242322212019181716
 
1514131211109876543210
  IN_14
BitsTypeResetNameDescription
5:0rw0x0IN_14

For IN14


PINMUX.MIO_PERIPH_INSEL_15 @ 0x124

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_15
31302928272625242322212019181716
 
1514131211109876543210
  IN_15
BitsTypeResetNameDescription
5:0rw0x0IN_15

For IN15


PINMUX.MIO_PERIPH_INSEL_16 @ 0x128

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_16
31302928272625242322212019181716
 
1514131211109876543210
  IN_16
BitsTypeResetNameDescription
5:0rw0x0IN_16

For IN16


PINMUX.MIO_PERIPH_INSEL_17 @ 0x12c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_17
31302928272625242322212019181716
 
1514131211109876543210
  IN_17
BitsTypeResetNameDescription
5:0rw0x0IN_17

For IN17


PINMUX.MIO_PERIPH_INSEL_18 @ 0x130

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_18
31302928272625242322212019181716
 
1514131211109876543210
  IN_18
BitsTypeResetNameDescription
5:0rw0x0IN_18

For IN18


PINMUX.MIO_PERIPH_INSEL_19 @ 0x134

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_19
31302928272625242322212019181716
 
1514131211109876543210
  IN_19
BitsTypeResetNameDescription
5:0rw0x0IN_19

For IN19


PINMUX.MIO_PERIPH_INSEL_20 @ 0x138

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_20
31302928272625242322212019181716
 
1514131211109876543210
  IN_20
BitsTypeResetNameDescription
5:0rw0x0IN_20

For IN20


PINMUX.MIO_PERIPH_INSEL_21 @ 0x13c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_21
31302928272625242322212019181716
 
1514131211109876543210
  IN_21
BitsTypeResetNameDescription
5:0rw0x0IN_21

For IN21


PINMUX.MIO_PERIPH_INSEL_22 @ 0x140

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_22
31302928272625242322212019181716
 
1514131211109876543210
  IN_22
BitsTypeResetNameDescription
5:0rw0x0IN_22

For IN22


PINMUX.MIO_PERIPH_INSEL_23 @ 0x144

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_23
31302928272625242322212019181716
 
1514131211109876543210
  IN_23
BitsTypeResetNameDescription
5:0rw0x0IN_23

For IN23


PINMUX.MIO_PERIPH_INSEL_24 @ 0x148

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_24
31302928272625242322212019181716
 
1514131211109876543210
  IN_24
BitsTypeResetNameDescription
5:0rw0x0IN_24

For IN24


PINMUX.MIO_PERIPH_INSEL_25 @ 0x14c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_25
31302928272625242322212019181716
 
1514131211109876543210
  IN_25
BitsTypeResetNameDescription
5:0rw0x0IN_25

For IN25


PINMUX.MIO_PERIPH_INSEL_26 @ 0x150

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_26
31302928272625242322212019181716
 
1514131211109876543210
  IN_26
BitsTypeResetNameDescription
5:0rw0x0IN_26

For IN26


PINMUX.MIO_PERIPH_INSEL_27 @ 0x154

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_27
31302928272625242322212019181716
 
1514131211109876543210
  IN_27
BitsTypeResetNameDescription
5:0rw0x0IN_27

For IN27


PINMUX.MIO_PERIPH_INSEL_28 @ 0x158

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_28
31302928272625242322212019181716
 
1514131211109876543210
  IN_28
BitsTypeResetNameDescription
5:0rw0x0IN_28

For IN28


PINMUX.MIO_PERIPH_INSEL_29 @ 0x15c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_29
31302928272625242322212019181716
 
1514131211109876543210
  IN_29
BitsTypeResetNameDescription
5:0rw0x0IN_29

For IN29


PINMUX.MIO_PERIPH_INSEL_30 @ 0x160

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_30
31302928272625242322212019181716
 
1514131211109876543210
  IN_30
BitsTypeResetNameDescription
5:0rw0x0IN_30

For IN30


PINMUX.MIO_PERIPH_INSEL_31 @ 0x164

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_31
31302928272625242322212019181716
 
1514131211109876543210
  IN_31
BitsTypeResetNameDescription
5:0rw0x0IN_31

For IN31


PINMUX.MIO_PERIPH_INSEL_32 @ 0x168

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_32
31302928272625242322212019181716
 
1514131211109876543210
  IN_32
BitsTypeResetNameDescription
5:0rw0x0IN_32

For IN32


PINMUX.MIO_PERIPH_INSEL_33 @ 0x16c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_33
31302928272625242322212019181716
 
1514131211109876543210
  IN_33
BitsTypeResetNameDescription
5:0rw0x0IN_33

For IN33


PINMUX.MIO_PERIPH_INSEL_34 @ 0x170

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_34
31302928272625242322212019181716
 
1514131211109876543210
  IN_34
BitsTypeResetNameDescription
5:0rw0x0IN_34

For IN34


PINMUX.MIO_PERIPH_INSEL_35 @ 0x174

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_35
31302928272625242322212019181716
 
1514131211109876543210
  IN_35
BitsTypeResetNameDescription
5:0rw0x0IN_35

For IN35


PINMUX.MIO_PERIPH_INSEL_36 @ 0x178

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_36
31302928272625242322212019181716
 
1514131211109876543210
  IN_36
BitsTypeResetNameDescription
5:0rw0x0IN_36

For IN36


PINMUX.MIO_PERIPH_INSEL_37 @ 0x17c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_37
31302928272625242322212019181716
 
1514131211109876543210
  IN_37
BitsTypeResetNameDescription
5:0rw0x0IN_37

For IN37


PINMUX.MIO_PERIPH_INSEL_38 @ 0x180

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_38
31302928272625242322212019181716
 
1514131211109876543210
  IN_38
BitsTypeResetNameDescription
5:0rw0x0IN_38

For IN38


PINMUX.MIO_PERIPH_INSEL_39 @ 0x184

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_39
31302928272625242322212019181716
 
1514131211109876543210
  IN_39
BitsTypeResetNameDescription
5:0rw0x0IN_39

For IN39


PINMUX.MIO_PERIPH_INSEL_40 @ 0x188

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_40
31302928272625242322212019181716
 
1514131211109876543210
  IN_40
BitsTypeResetNameDescription
5:0rw0x0IN_40

For IN40


PINMUX.MIO_PERIPH_INSEL_41 @ 0x18c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_41
31302928272625242322212019181716
 
1514131211109876543210
  IN_41
BitsTypeResetNameDescription
5:0rw0x0IN_41

For IN41


PINMUX.MIO_PERIPH_INSEL_42 @ 0x190

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_42
31302928272625242322212019181716
 
1514131211109876543210
  IN_42
BitsTypeResetNameDescription
5:0rw0x0IN_42

For IN42


PINMUX.MIO_PERIPH_INSEL_43 @ 0x194

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_43
31302928272625242322212019181716
 
1514131211109876543210
  IN_43
BitsTypeResetNameDescription
5:0rw0x0IN_43

For IN43


PINMUX.MIO_PERIPH_INSEL_44 @ 0x198

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_44
31302928272625242322212019181716
 
1514131211109876543210
  IN_44
BitsTypeResetNameDescription
5:0rw0x0IN_44

For IN44


PINMUX.MIO_PERIPH_INSEL_45 @ 0x19c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_45
31302928272625242322212019181716
 
1514131211109876543210
  IN_45
BitsTypeResetNameDescription
5:0rw0x0IN_45

For IN45


PINMUX.MIO_PERIPH_INSEL_46 @ 0x1a0

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_46
31302928272625242322212019181716
 
1514131211109876543210
  IN_46
BitsTypeResetNameDescription
5:0rw0x0IN_46

For IN46


PINMUX.MIO_PERIPH_INSEL_47 @ 0x1a4

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_47
31302928272625242322212019181716
 
1514131211109876543210
  IN_47
BitsTypeResetNameDescription
5:0rw0x0IN_47

For IN47


PINMUX.MIO_PERIPH_INSEL_48 @ 0x1a8

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_48
31302928272625242322212019181716
 
1514131211109876543210
  IN_48
BitsTypeResetNameDescription
5:0rw0x0IN_48

For IN48


PINMUX.MIO_PERIPH_INSEL_49 @ 0x1ac

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_49
31302928272625242322212019181716
 
1514131211109876543210
  IN_49
BitsTypeResetNameDescription
5:0rw0x0IN_49

For IN49


PINMUX.MIO_PERIPH_INSEL_50 @ 0x1b0

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_50
31302928272625242322212019181716
 
1514131211109876543210
  IN_50
BitsTypeResetNameDescription
5:0rw0x0IN_50

For IN50


PINMUX.MIO_PERIPH_INSEL_51 @ 0x1b4

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_51
31302928272625242322212019181716
 
1514131211109876543210
  IN_51
BitsTypeResetNameDescription
5:0rw0x0IN_51

For IN51


PINMUX.MIO_PERIPH_INSEL_52 @ 0x1b8

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_52
31302928272625242322212019181716
 
1514131211109876543210
  IN_52
BitsTypeResetNameDescription
5:0rw0x0IN_52

For IN52


PINMUX.MIO_PERIPH_INSEL_53 @ 0x1bc

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_53
31302928272625242322212019181716
 
1514131211109876543210
  IN_53
BitsTypeResetNameDescription
5:0rw0x0IN_53

For IN53


PINMUX.MIO_PERIPH_INSEL_54 @ 0x1c0

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_54
31302928272625242322212019181716
 
1514131211109876543210
  IN_54
BitsTypeResetNameDescription
5:0rw0x0IN_54

For IN54


PINMUX.MIO_PERIPH_INSEL_55 @ 0x1c4

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_55
31302928272625242322212019181716
 
1514131211109876543210
  IN_55
BitsTypeResetNameDescription
5:0rw0x0IN_55

For IN55


PINMUX.MIO_PERIPH_INSEL_56 @ 0x1c8

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_56
31302928272625242322212019181716
 
1514131211109876543210
  IN_56
BitsTypeResetNameDescription
5:0rw0x0IN_56

For IN56


PINMUX.MIO_OUTSEL_REGWEN_0 @ 0x1cc

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_0
BitsTypeResetNameDescription
0rw0c0x1EN_0

Register write enable bit. If this is cleared to 0, the corresponding MIO_OUTSEL is not writable anymore.


PINMUX.MIO_OUTSEL_REGWEN_1 @ 0x1d0

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_1
BitsTypeResetNameDescription
0rw0c0x1EN_1

For MIO_OUTSEL1


PINMUX.MIO_OUTSEL_REGWEN_2 @ 0x1d4

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_2
BitsTypeResetNameDescription
0rw0c0x1EN_2

For MIO_OUTSEL2


PINMUX.MIO_OUTSEL_REGWEN_3 @ 0x1d8

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_3
BitsTypeResetNameDescription
0rw0c0x1EN_3

For MIO_OUTSEL3


PINMUX.MIO_OUTSEL_REGWEN_4 @ 0x1dc

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_4
BitsTypeResetNameDescription
0rw0c0x1EN_4

For MIO_OUTSEL4


PINMUX.MIO_OUTSEL_REGWEN_5 @ 0x1e0

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_5
BitsTypeResetNameDescription
0rw0c0x1EN_5

For MIO_OUTSEL5


PINMUX.MIO_OUTSEL_REGWEN_6 @ 0x1e4

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_6
BitsTypeResetNameDescription
0rw0c0x1EN_6

For MIO_OUTSEL6


PINMUX.MIO_OUTSEL_REGWEN_7 @ 0x1e8

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_7
BitsTypeResetNameDescription
0rw0c0x1EN_7

For MIO_OUTSEL7


PINMUX.MIO_OUTSEL_REGWEN_8 @ 0x1ec

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_8
BitsTypeResetNameDescription
0rw0c0x1EN_8

For MIO_OUTSEL8


PINMUX.MIO_OUTSEL_REGWEN_9 @ 0x1f0

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_9
BitsTypeResetNameDescription
0rw0c0x1EN_9

For MIO_OUTSEL9


PINMUX.MIO_OUTSEL_REGWEN_10 @ 0x1f4

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_10
BitsTypeResetNameDescription
0rw0c0x1EN_10

For MIO_OUTSEL10


PINMUX.MIO_OUTSEL_REGWEN_11 @ 0x1f8

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_11
BitsTypeResetNameDescription
0rw0c0x1EN_11

For MIO_OUTSEL11


PINMUX.MIO_OUTSEL_REGWEN_12 @ 0x1fc

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_12
BitsTypeResetNameDescription
0rw0c0x1EN_12

For MIO_OUTSEL12


PINMUX.MIO_OUTSEL_REGWEN_13 @ 0x200

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_13
BitsTypeResetNameDescription
0rw0c0x1EN_13

For MIO_OUTSEL13


PINMUX.MIO_OUTSEL_REGWEN_14 @ 0x204

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_14
BitsTypeResetNameDescription
0rw0c0x1EN_14

For MIO_OUTSEL14


PINMUX.MIO_OUTSEL_REGWEN_15 @ 0x208

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_15
BitsTypeResetNameDescription
0rw0c0x1EN_15

For MIO_OUTSEL15


PINMUX.MIO_OUTSEL_REGWEN_16 @ 0x20c

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_16
BitsTypeResetNameDescription
0rw0c0x1EN_16

For MIO_OUTSEL16


PINMUX.MIO_OUTSEL_REGWEN_17 @ 0x210

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_17
BitsTypeResetNameDescription
0rw0c0x1EN_17

For MIO_OUTSEL17


PINMUX.MIO_OUTSEL_REGWEN_18 @ 0x214

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_18
BitsTypeResetNameDescription
0rw0c0x1EN_18

For MIO_OUTSEL18


PINMUX.MIO_OUTSEL_REGWEN_19 @ 0x218

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_19
BitsTypeResetNameDescription
0rw0c0x1EN_19

For MIO_OUTSEL19


PINMUX.MIO_OUTSEL_REGWEN_20 @ 0x21c

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_20
BitsTypeResetNameDescription
0rw0c0x1EN_20

For MIO_OUTSEL20


PINMUX.MIO_OUTSEL_REGWEN_21 @ 0x220

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_21
BitsTypeResetNameDescription
0rw0c0x1EN_21

For MIO_OUTSEL21


PINMUX.MIO_OUTSEL_REGWEN_22 @ 0x224

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_22
BitsTypeResetNameDescription
0rw0c0x1EN_22

For MIO_OUTSEL22


PINMUX.MIO_OUTSEL_REGWEN_23 @ 0x228

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_23
BitsTypeResetNameDescription
0rw0c0x1EN_23

For MIO_OUTSEL23


PINMUX.MIO_OUTSEL_REGWEN_24 @ 0x22c

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_24
BitsTypeResetNameDescription
0rw0c0x1EN_24

For MIO_OUTSEL24


PINMUX.MIO_OUTSEL_REGWEN_25 @ 0x230

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_25
BitsTypeResetNameDescription
0rw0c0x1EN_25

For MIO_OUTSEL25


PINMUX.MIO_OUTSEL_REGWEN_26 @ 0x234

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_26
BitsTypeResetNameDescription
0rw0c0x1EN_26

For MIO_OUTSEL26


PINMUX.MIO_OUTSEL_REGWEN_27 @ 0x238

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_27
BitsTypeResetNameDescription
0rw0c0x1EN_27

For MIO_OUTSEL27


PINMUX.MIO_OUTSEL_REGWEN_28 @ 0x23c

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_28
BitsTypeResetNameDescription
0rw0c0x1EN_28

For MIO_OUTSEL28


PINMUX.MIO_OUTSEL_REGWEN_29 @ 0x240

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_29
BitsTypeResetNameDescription
0rw0c0x1EN_29

For MIO_OUTSEL29


PINMUX.MIO_OUTSEL_REGWEN_30 @ 0x244

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_30
BitsTypeResetNameDescription
0rw0c0x1EN_30

For MIO_OUTSEL30


PINMUX.MIO_OUTSEL_REGWEN_31 @ 0x248

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_31
BitsTypeResetNameDescription
0rw0c0x1EN_31

For MIO_OUTSEL31


PINMUX.MIO_OUTSEL_REGWEN_32 @ 0x24c

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_32
BitsTypeResetNameDescription
0rw0c0x1EN_32

For MIO_OUTSEL32


PINMUX.MIO_OUTSEL_REGWEN_33 @ 0x250

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_33
BitsTypeResetNameDescription
0rw0c0x1EN_33

For MIO_OUTSEL33


PINMUX.MIO_OUTSEL_REGWEN_34 @ 0x254

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_34
BitsTypeResetNameDescription
0rw0c0x1EN_34

For MIO_OUTSEL34


PINMUX.MIO_OUTSEL_REGWEN_35 @ 0x258

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_35
BitsTypeResetNameDescription
0rw0c0x1EN_35

For MIO_OUTSEL35


PINMUX.MIO_OUTSEL_REGWEN_36 @ 0x25c

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_36
BitsTypeResetNameDescription
0rw0c0x1EN_36

For MIO_OUTSEL36


PINMUX.MIO_OUTSEL_REGWEN_37 @ 0x260

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_37
BitsTypeResetNameDescription
0rw0c0x1EN_37

For MIO_OUTSEL37


PINMUX.MIO_OUTSEL_REGWEN_38 @ 0x264

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_38
BitsTypeResetNameDescription
0rw0c0x1EN_38

For MIO_OUTSEL38


PINMUX.MIO_OUTSEL_REGWEN_39 @ 0x268

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_39
BitsTypeResetNameDescription
0rw0c0x1EN_39

For MIO_OUTSEL39


PINMUX.MIO_OUTSEL_REGWEN_40 @ 0x26c

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_40
BitsTypeResetNameDescription
0rw0c0x1EN_40

For MIO_OUTSEL40


PINMUX.MIO_OUTSEL_REGWEN_41 @ 0x270

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_41
BitsTypeResetNameDescription
0rw0c0x1EN_41

For MIO_OUTSEL41


PINMUX.MIO_OUTSEL_REGWEN_42 @ 0x274

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_42
BitsTypeResetNameDescription
0rw0c0x1EN_42

For MIO_OUTSEL42


PINMUX.MIO_OUTSEL_REGWEN_43 @ 0x278

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_43
BitsTypeResetNameDescription
0rw0c0x1EN_43

For MIO_OUTSEL43


PINMUX.MIO_OUTSEL_REGWEN_44 @ 0x27c

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_44
BitsTypeResetNameDescription
0rw0c0x1EN_44

For MIO_OUTSEL44


PINMUX.MIO_OUTSEL_REGWEN_45 @ 0x280

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_45
BitsTypeResetNameDescription
0rw0c0x1EN_45

For MIO_OUTSEL45


PINMUX.MIO_OUTSEL_REGWEN_46 @ 0x284

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_46
BitsTypeResetNameDescription
0rw0c0x1EN_46

For MIO_OUTSEL46


PINMUX.MIO_OUTSEL_0 @ 0x288

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_0
31302928272625242322212019181716
 
1514131211109876543210
  OUT_0
BitsTypeResetNameDescription
6:0rw0x2OUT_0

0: tie constantly to zero, 1: tie constantly to 1, 2: high-Z,

=3: peripheral outputs (i.e., add 3 to the native peripheral pad index).


PINMUX.MIO_OUTSEL_1 @ 0x28c

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_1
31302928272625242322212019181716
 
1514131211109876543210
  OUT_1
BitsTypeResetNameDescription
6:0rw0x2OUT_1

For OUT1


PINMUX.MIO_OUTSEL_2 @ 0x290

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_2
31302928272625242322212019181716
 
1514131211109876543210
  OUT_2
BitsTypeResetNameDescription
6:0rw0x2OUT_2

For OUT2


PINMUX.MIO_OUTSEL_3 @ 0x294

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_3
31302928272625242322212019181716
 
1514131211109876543210
  OUT_3
BitsTypeResetNameDescription
6:0rw0x2OUT_3

For OUT3


PINMUX.MIO_OUTSEL_4 @ 0x298

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_4
31302928272625242322212019181716
 
1514131211109876543210
  OUT_4
BitsTypeResetNameDescription
6:0rw0x2OUT_4

For OUT4


PINMUX.MIO_OUTSEL_5 @ 0x29c

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_5
31302928272625242322212019181716
 
1514131211109876543210
  OUT_5
BitsTypeResetNameDescription
6:0rw0x2OUT_5

For OUT5


PINMUX.MIO_OUTSEL_6 @ 0x2a0

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_6
31302928272625242322212019181716
 
1514131211109876543210
  OUT_6
BitsTypeResetNameDescription
6:0rw0x2OUT_6

For OUT6


PINMUX.MIO_OUTSEL_7 @ 0x2a4

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_7
31302928272625242322212019181716
 
1514131211109876543210
  OUT_7
BitsTypeResetNameDescription
6:0rw0x2OUT_7

For OUT7


PINMUX.MIO_OUTSEL_8 @ 0x2a8

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_8
31302928272625242322212019181716
 
1514131211109876543210
  OUT_8
BitsTypeResetNameDescription
6:0rw0x2OUT_8

For OUT8


PINMUX.MIO_OUTSEL_9 @ 0x2ac

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_9
31302928272625242322212019181716
 
1514131211109876543210
  OUT_9
BitsTypeResetNameDescription
6:0rw0x2OUT_9

For OUT9


PINMUX.MIO_OUTSEL_10 @ 0x2b0

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_10
31302928272625242322212019181716
 
1514131211109876543210
  OUT_10
BitsTypeResetNameDescription
6:0rw0x2OUT_10

For OUT10


PINMUX.MIO_OUTSEL_11 @ 0x2b4

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_11
31302928272625242322212019181716
 
1514131211109876543210
  OUT_11
BitsTypeResetNameDescription
6:0rw0x2OUT_11

For OUT11


PINMUX.MIO_OUTSEL_12 @ 0x2b8

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_12
31302928272625242322212019181716
 
1514131211109876543210
  OUT_12
BitsTypeResetNameDescription
6:0rw0x2OUT_12

For OUT12


PINMUX.MIO_OUTSEL_13 @ 0x2bc

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_13
31302928272625242322212019181716
 
1514131211109876543210
  OUT_13
BitsTypeResetNameDescription
6:0rw0x2OUT_13

For OUT13


PINMUX.MIO_OUTSEL_14 @ 0x2c0

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_14
31302928272625242322212019181716
 
1514131211109876543210
  OUT_14
BitsTypeResetNameDescription
6:0rw0x2OUT_14

For OUT14


PINMUX.MIO_OUTSEL_15 @ 0x2c4

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_15
31302928272625242322212019181716
 
1514131211109876543210
  OUT_15
BitsTypeResetNameDescription
6:0rw0x2OUT_15

For OUT15


PINMUX.MIO_OUTSEL_16 @ 0x2c8

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_16
31302928272625242322212019181716
 
1514131211109876543210
  OUT_16
BitsTypeResetNameDescription
6:0rw0x2OUT_16

For OUT16


PINMUX.MIO_OUTSEL_17 @ 0x2cc

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_17
31302928272625242322212019181716
 
1514131211109876543210
  OUT_17
BitsTypeResetNameDescription
6:0rw0x2OUT_17

For OUT17


PINMUX.MIO_OUTSEL_18 @ 0x2d0

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_18
31302928272625242322212019181716
 
1514131211109876543210
  OUT_18
BitsTypeResetNameDescription
6:0rw0x2OUT_18

For OUT18


PINMUX.MIO_OUTSEL_19 @ 0x2d4

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_19
31302928272625242322212019181716
 
1514131211109876543210
  OUT_19
BitsTypeResetNameDescription
6:0rw0x2OUT_19

For OUT19


PINMUX.MIO_OUTSEL_20 @ 0x2d8

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_20
31302928272625242322212019181716
 
1514131211109876543210
  OUT_20
BitsTypeResetNameDescription
6:0rw0x2OUT_20

For OUT20


PINMUX.MIO_OUTSEL_21 @ 0x2dc

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_21
31302928272625242322212019181716
 
1514131211109876543210
  OUT_21
BitsTypeResetNameDescription
6:0rw0x2OUT_21

For OUT21


PINMUX.MIO_OUTSEL_22 @ 0x2e0

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_22
31302928272625242322212019181716
 
1514131211109876543210
  OUT_22
BitsTypeResetNameDescription
6:0rw0x2OUT_22

For OUT22


PINMUX.MIO_OUTSEL_23 @ 0x2e4

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_23
31302928272625242322212019181716
 
1514131211109876543210
  OUT_23
BitsTypeResetNameDescription
6:0rw0x2OUT_23

For OUT23


PINMUX.MIO_OUTSEL_24 @ 0x2e8

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_24
31302928272625242322212019181716
 
1514131211109876543210
  OUT_24
BitsTypeResetNameDescription
6:0rw0x2OUT_24

For OUT24


PINMUX.MIO_OUTSEL_25 @ 0x2ec

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_25
31302928272625242322212019181716
 
1514131211109876543210
  OUT_25
BitsTypeResetNameDescription
6:0rw0x2OUT_25

For OUT25


PINMUX.MIO_OUTSEL_26 @ 0x2f0

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_26
31302928272625242322212019181716
 
1514131211109876543210
  OUT_26
BitsTypeResetNameDescription
6:0rw0x2OUT_26

For OUT26


PINMUX.MIO_OUTSEL_27 @ 0x2f4

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_27
31302928272625242322212019181716
 
1514131211109876543210
  OUT_27
BitsTypeResetNameDescription
6:0rw0x2OUT_27

For OUT27


PINMUX.MIO_OUTSEL_28 @ 0x2f8

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_28
31302928272625242322212019181716
 
1514131211109876543210
  OUT_28
BitsTypeResetNameDescription
6:0rw0x2OUT_28

For OUT28


PINMUX.MIO_OUTSEL_29 @ 0x2fc

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_29
31302928272625242322212019181716
 
1514131211109876543210
  OUT_29
BitsTypeResetNameDescription
6:0rw0x2OUT_29

For OUT29


PINMUX.MIO_OUTSEL_30 @ 0x300

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_30
31302928272625242322212019181716
 
1514131211109876543210
  OUT_30
BitsTypeResetNameDescription
6:0rw0x2OUT_30

For OUT30


PINMUX.MIO_OUTSEL_31 @ 0x304

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_31
31302928272625242322212019181716
 
1514131211109876543210
  OUT_31
BitsTypeResetNameDescription
6:0rw0x2OUT_31

For OUT31


PINMUX.MIO_OUTSEL_32 @ 0x308

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_32
31302928272625242322212019181716
 
1514131211109876543210
  OUT_32
BitsTypeResetNameDescription
6:0rw0x2OUT_32

For OUT32


PINMUX.MIO_OUTSEL_33 @ 0x30c

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_33
31302928272625242322212019181716
 
1514131211109876543210
  OUT_33
BitsTypeResetNameDescription
6:0rw0x2OUT_33

For OUT33


PINMUX.MIO_OUTSEL_34 @ 0x310

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_34
31302928272625242322212019181716
 
1514131211109876543210
  OUT_34
BitsTypeResetNameDescription
6:0rw0x2OUT_34

For OUT34


PINMUX.MIO_OUTSEL_35 @ 0x314

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_35
31302928272625242322212019181716
 
1514131211109876543210
  OUT_35
BitsTypeResetNameDescription
6:0rw0x2OUT_35

For OUT35


PINMUX.MIO_OUTSEL_36 @ 0x318

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_36
31302928272625242322212019181716
 
1514131211109876543210
  OUT_36
BitsTypeResetNameDescription
6:0rw0x2OUT_36

For OUT36


PINMUX.MIO_OUTSEL_37 @ 0x31c

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_37
31302928272625242322212019181716
 
1514131211109876543210
  OUT_37
BitsTypeResetNameDescription
6:0rw0x2OUT_37

For OUT37


PINMUX.MIO_OUTSEL_38 @ 0x320

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_38
31302928272625242322212019181716
 
1514131211109876543210
  OUT_38
BitsTypeResetNameDescription
6:0rw0x2OUT_38

For OUT38


PINMUX.MIO_OUTSEL_39 @ 0x324

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_39
31302928272625242322212019181716
 
1514131211109876543210
  OUT_39
BitsTypeResetNameDescription
6:0rw0x2OUT_39

For OUT39


PINMUX.MIO_OUTSEL_40 @ 0x328

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_40
31302928272625242322212019181716
 
1514131211109876543210
  OUT_40
BitsTypeResetNameDescription
6:0rw0x2OUT_40

For OUT40


PINMUX.MIO_OUTSEL_41 @ 0x32c

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_41
31302928272625242322212019181716
 
1514131211109876543210
  OUT_41
BitsTypeResetNameDescription
6:0rw0x2OUT_41

For OUT41


PINMUX.MIO_OUTSEL_42 @ 0x330

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_42
31302928272625242322212019181716
 
1514131211109876543210
  OUT_42
BitsTypeResetNameDescription
6:0rw0x2OUT_42

For OUT42


PINMUX.MIO_OUTSEL_43 @ 0x334

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_43
31302928272625242322212019181716
 
1514131211109876543210
  OUT_43
BitsTypeResetNameDescription
6:0rw0x2OUT_43

For OUT43


PINMUX.MIO_OUTSEL_44 @ 0x338

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_44
31302928272625242322212019181716
 
1514131211109876543210
  OUT_44
BitsTypeResetNameDescription
6:0rw0x2OUT_44

For OUT44


PINMUX.MIO_OUTSEL_45 @ 0x33c

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_45
31302928272625242322212019181716
 
1514131211109876543210
  OUT_45
BitsTypeResetNameDescription
6:0rw0x2OUT_45

For OUT45


PINMUX.MIO_OUTSEL_46 @ 0x340

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_46
31302928272625242322212019181716
 
1514131211109876543210
  OUT_46
BitsTypeResetNameDescription
6:0rw0x2OUT_46

For OUT46


PINMUX.MIO_PAD_ATTR_REGWEN_0 @ 0x344

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_0
BitsTypeResetNameDescription
0rw0c0x1EN_0

Register write enable bit. If this is cleared to 0, the corresponding !!MIO_PAD_ATTR is not writable anymore.


PINMUX.MIO_PAD_ATTR_REGWEN_1 @ 0x348

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_1
BitsTypeResetNameDescription
0rw0c0x1EN_1

For MIO_PAD1


PINMUX.MIO_PAD_ATTR_REGWEN_2 @ 0x34c

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_2
BitsTypeResetNameDescription
0rw0c0x1EN_2

For MIO_PAD2


PINMUX.MIO_PAD_ATTR_REGWEN_3 @ 0x350

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_3
BitsTypeResetNameDescription
0rw0c0x1EN_3

For MIO_PAD3


PINMUX.MIO_PAD_ATTR_REGWEN_4 @ 0x354

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_4
BitsTypeResetNameDescription
0rw0c0x1EN_4

For MIO_PAD4


PINMUX.MIO_PAD_ATTR_REGWEN_5 @ 0x358

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_5
BitsTypeResetNameDescription
0rw0c0x1EN_5

For MIO_PAD5


PINMUX.MIO_PAD_ATTR_REGWEN_6 @ 0x35c

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_6
BitsTypeResetNameDescription
0rw0c0x1EN_6

For MIO_PAD6


PINMUX.MIO_PAD_ATTR_REGWEN_7 @ 0x360

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_7
BitsTypeResetNameDescription
0rw0c0x1EN_7

For MIO_PAD7


PINMUX.MIO_PAD_ATTR_REGWEN_8 @ 0x364

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_8
BitsTypeResetNameDescription
0rw0c0x1EN_8

For MIO_PAD8


PINMUX.MIO_PAD_ATTR_REGWEN_9 @ 0x368

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_9
BitsTypeResetNameDescription
0rw0c0x1EN_9

For MIO_PAD9


PINMUX.MIO_PAD_ATTR_REGWEN_10 @ 0x36c

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_10
BitsTypeResetNameDescription
0rw0c0x1EN_10

For MIO_PAD10


PINMUX.MIO_PAD_ATTR_REGWEN_11 @ 0x370

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_11
BitsTypeResetNameDescription
0rw0c0x1EN_11

For MIO_PAD11


PINMUX.MIO_PAD_ATTR_REGWEN_12 @ 0x374

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_12
BitsTypeResetNameDescription
0rw0c0x1EN_12

For MIO_PAD12


PINMUX.MIO_PAD_ATTR_REGWEN_13 @ 0x378

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_13
BitsTypeResetNameDescription
0rw0c0x1EN_13

For MIO_PAD13


PINMUX.MIO_PAD_ATTR_REGWEN_14 @ 0x37c

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_14
BitsTypeResetNameDescription
0rw0c0x1EN_14

For MIO_PAD14


PINMUX.MIO_PAD_ATTR_REGWEN_15 @ 0x380

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_15
BitsTypeResetNameDescription
0rw0c0x1EN_15

For MIO_PAD15


PINMUX.MIO_PAD_ATTR_REGWEN_16 @ 0x384

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_16
BitsTypeResetNameDescription
0rw0c0x1EN_16

For MIO_PAD16


PINMUX.MIO_PAD_ATTR_REGWEN_17 @ 0x388

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_17
BitsTypeResetNameDescription
0rw0c0x1EN_17

For MIO_PAD17


PINMUX.MIO_PAD_ATTR_REGWEN_18 @ 0x38c

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_18
BitsTypeResetNameDescription
0rw0c0x1EN_18

For MIO_PAD18


PINMUX.MIO_PAD_ATTR_REGWEN_19 @ 0x390

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_19
BitsTypeResetNameDescription
0rw0c0x1EN_19

For MIO_PAD19


PINMUX.MIO_PAD_ATTR_REGWEN_20 @ 0x394

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_20
BitsTypeResetNameDescription
0rw0c0x1EN_20

For MIO_PAD20


PINMUX.MIO_PAD_ATTR_REGWEN_21 @ 0x398

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_21
BitsTypeResetNameDescription
0rw0c0x1EN_21

For MIO_PAD21


PINMUX.MIO_PAD_ATTR_REGWEN_22 @ 0x39c

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_22
BitsTypeResetNameDescription
0rw0c0x1EN_22

For MIO_PAD22


PINMUX.MIO_PAD_ATTR_REGWEN_23 @ 0x3a0

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_23
BitsTypeResetNameDescription
0rw0c0x1EN_23

For MIO_PAD23


PINMUX.MIO_PAD_ATTR_REGWEN_24 @ 0x3a4

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_24
BitsTypeResetNameDescription
0rw0c0x1EN_24

For MIO_PAD24


PINMUX.MIO_PAD_ATTR_REGWEN_25 @ 0x3a8

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_25
BitsTypeResetNameDescription
0rw0c0x1EN_25

For MIO_PAD25


PINMUX.MIO_PAD_ATTR_REGWEN_26 @ 0x3ac

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_26
BitsTypeResetNameDescription
0rw0c0x1EN_26

For MIO_PAD26


PINMUX.MIO_PAD_ATTR_REGWEN_27 @ 0x3b0

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_27
BitsTypeResetNameDescription
0rw0c0x1EN_27

For MIO_PAD27


PINMUX.MIO_PAD_ATTR_REGWEN_28 @ 0x3b4

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_28
BitsTypeResetNameDescription
0rw0c0x1EN_28

For MIO_PAD28


PINMUX.MIO_PAD_ATTR_REGWEN_29 @ 0x3b8

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_29
BitsTypeResetNameDescription
0rw0c0x1EN_29

For MIO_PAD29


PINMUX.MIO_PAD_ATTR_REGWEN_30 @ 0x3bc

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_30
BitsTypeResetNameDescription
0rw0c0x1EN_30

For MIO_PAD30


PINMUX.MIO_PAD_ATTR_REGWEN_31 @ 0x3c0

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_31
BitsTypeResetNameDescription
0rw0c0x1EN_31

For MIO_PAD31


PINMUX.MIO_PAD_ATTR_REGWEN_32 @ 0x3c4

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_32
BitsTypeResetNameDescription
0rw0c0x1EN_32

For MIO_PAD32


PINMUX.MIO_PAD_ATTR_REGWEN_33 @ 0x3c8

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_33
BitsTypeResetNameDescription
0rw0c0x1EN_33

For MIO_PAD33


PINMUX.MIO_PAD_ATTR_REGWEN_34 @ 0x3cc

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_34
BitsTypeResetNameDescription
0rw0c0x1EN_34

For MIO_PAD34


PINMUX.MIO_PAD_ATTR_REGWEN_35 @ 0x3d0

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_35
BitsTypeResetNameDescription
0rw0c0x1EN_35

For MIO_PAD35


PINMUX.MIO_PAD_ATTR_REGWEN_36 @ 0x3d4

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_36
BitsTypeResetNameDescription
0rw0c0x1EN_36

For MIO_PAD36


PINMUX.MIO_PAD_ATTR_REGWEN_37 @ 0x3d8

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_37
BitsTypeResetNameDescription
0rw0c0x1EN_37

For MIO_PAD37


PINMUX.MIO_PAD_ATTR_REGWEN_38 @ 0x3dc

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_38
BitsTypeResetNameDescription
0rw0c0x1EN_38

For MIO_PAD38


PINMUX.MIO_PAD_ATTR_REGWEN_39 @ 0x3e0

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_39
BitsTypeResetNameDescription
0rw0c0x1EN_39

For MIO_PAD39


PINMUX.MIO_PAD_ATTR_REGWEN_40 @ 0x3e4

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_40
BitsTypeResetNameDescription
0rw0c0x1EN_40

For MIO_PAD40


PINMUX.MIO_PAD_ATTR_REGWEN_41 @ 0x3e8

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_41
BitsTypeResetNameDescription
0rw0c0x1EN_41

For MIO_PAD41


PINMUX.MIO_PAD_ATTR_REGWEN_42 @ 0x3ec

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_42
BitsTypeResetNameDescription
0rw0c0x1EN_42

For MIO_PAD42


PINMUX.MIO_PAD_ATTR_REGWEN_43 @ 0x3f0

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_43
BitsTypeResetNameDescription
0rw0c0x1EN_43

For MIO_PAD43


PINMUX.MIO_PAD_ATTR_REGWEN_44 @ 0x3f4

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_44
BitsTypeResetNameDescription
0rw0c0x1EN_44

For MIO_PAD44


PINMUX.MIO_PAD_ATTR_REGWEN_45 @ 0x3f8

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_45
BitsTypeResetNameDescription
0rw0c0x1EN_45

For MIO_PAD45


PINMUX.MIO_PAD_ATTR_REGWEN_46 @ 0x3fc

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_46
BitsTypeResetNameDescription
0rw0c0x1EN_46

For MIO_PAD46


PINMUX.MIO_PAD_ATTR_0 @ 0x400

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_0
31302928272625242322212019181716
  drive_strength_0   slew_rate_0
1514131211109876543210
  od_en_0 schmitt_en_0 keeper_en_0 pull_select_0 pull_en_0 virtual_od_en_0 invert_0
BitsTypeResetNameDescription
0rw0x0invert_0

Invert input and output levels.

1rw0x0virtual_od_en_0

Enable virtual open drain.

2rw0x0pull_en_0

Enable pull-up or pull-down resistor.

3rw0x0pull_select_0

Pull select (0: pull-down, 1: pull-up).

0x0pull_down

Select the pull-down resistor.

0x1pull_up

Select the pull-up resistor.

4rw0x0keeper_en_0

Enable pull-up or pull-down resistor.

5rw0x0schmitt_en_0

Enable the schmitt trigger.

6rw0x0od_en_0

Enable open drain.

15:7Reserved
17:16rw0x0slew_rate_0

Slew rate (0x0: slowest, 0x3: fastest).

19:18Reserved
23:20rw0x0drive_strength_0

Drive strength (0x0: weakest, 0xf: strongest)


PINMUX.MIO_PAD_ATTR_1 @ 0x404

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_1
31302928272625242322212019181716
  drive_strength_1   slew_rate_1
1514131211109876543210
  od_en_1 schmitt_en_1 keeper_en_1 pull_select_1 pull_en_1 virtual_od_en_1 invert_1
BitsTypeResetNameDescription
0rw0x0invert_1

For MIO_PAD1

1rw0x0virtual_od_en_1

For MIO_PAD1

2rw0x0pull_en_1

For MIO_PAD1

3rw0x0pull_select_1

For MIO_PAD1

4rw0x0keeper_en_1

For MIO_PAD1

5rw0x0schmitt_en_1

For MIO_PAD1

6rw0x0od_en_1

For MIO_PAD1

15:7Reserved
17:16rw0x0slew_rate_1

For MIO_PAD1

19:18Reserved
23:20rw0x0drive_strength_1

For MIO_PAD1


PINMUX.MIO_PAD_ATTR_2 @ 0x408

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_2
31302928272625242322212019181716
  drive_strength_2   slew_rate_2
1514131211109876543210
  od_en_2 schmitt_en_2 keeper_en_2 pull_select_2 pull_en_2 virtual_od_en_2 invert_2
BitsTypeResetNameDescription
0rw0x0invert_2

For MIO_PAD2

1rw0x0virtual_od_en_2

For MIO_PAD2

2rw0x0pull_en_2

For MIO_PAD2

3rw0x0pull_select_2

For MIO_PAD2

4rw0x0keeper_en_2

For MIO_PAD2

5rw0x0schmitt_en_2

For MIO_PAD2

6rw0x0od_en_2

For MIO_PAD2

15:7Reserved
17:16rw0x0slew_rate_2

For MIO_PAD2

19:18Reserved
23:20rw0x0drive_strength_2

For MIO_PAD2


PINMUX.MIO_PAD_ATTR_3 @ 0x40c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_3
31302928272625242322212019181716
  drive_strength_3   slew_rate_3
1514131211109876543210
  od_en_3 schmitt_en_3 keeper_en_3 pull_select_3 pull_en_3 virtual_od_en_3 invert_3
BitsTypeResetNameDescription
0rw0x0invert_3

For MIO_PAD3

1rw0x0virtual_od_en_3

For MIO_PAD3

2rw0x0pull_en_3

For MIO_PAD3

3rw0x0pull_select_3

For MIO_PAD3

4rw0x0keeper_en_3

For MIO_PAD3

5rw0x0schmitt_en_3

For MIO_PAD3

6rw0x0od_en_3

For MIO_PAD3

15:7Reserved
17:16rw0x0slew_rate_3

For MIO_PAD3

19:18Reserved
23:20rw0x0drive_strength_3

For MIO_PAD3


PINMUX.MIO_PAD_ATTR_4 @ 0x410

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_4
31302928272625242322212019181716
  drive_strength_4   slew_rate_4
1514131211109876543210
  od_en_4 schmitt_en_4 keeper_en_4 pull_select_4 pull_en_4 virtual_od_en_4 invert_4
BitsTypeResetNameDescription
0rw0x0invert_4

For MIO_PAD4

1rw0x0virtual_od_en_4

For MIO_PAD4

2rw0x0pull_en_4

For MIO_PAD4

3rw0x0pull_select_4

For MIO_PAD4

4rw0x0keeper_en_4

For MIO_PAD4

5rw0x0schmitt_en_4

For MIO_PAD4

6rw0x0od_en_4

For MIO_PAD4

15:7Reserved
17:16rw0x0slew_rate_4

For MIO_PAD4

19:18Reserved
23:20rw0x0drive_strength_4

For MIO_PAD4


PINMUX.MIO_PAD_ATTR_5 @ 0x414

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_5
31302928272625242322212019181716
  drive_strength_5   slew_rate_5
1514131211109876543210
  od_en_5 schmitt_en_5 keeper_en_5 pull_select_5 pull_en_5 virtual_od_en_5 invert_5
BitsTypeResetNameDescription
0rw0x0invert_5

For MIO_PAD5

1rw0x0virtual_od_en_5

For MIO_PAD5

2rw0x0pull_en_5

For MIO_PAD5

3rw0x0pull_select_5

For MIO_PAD5

4rw0x0keeper_en_5

For MIO_PAD5

5rw0x0schmitt_en_5

For MIO_PAD5

6rw0x0od_en_5

For MIO_PAD5

15:7Reserved
17:16rw0x0slew_rate_5

For MIO_PAD5

19:18Reserved
23:20rw0x0drive_strength_5

For MIO_PAD5


PINMUX.MIO_PAD_ATTR_6 @ 0x418

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_6
31302928272625242322212019181716
  drive_strength_6   slew_rate_6
1514131211109876543210
  od_en_6 schmitt_en_6 keeper_en_6 pull_select_6 pull_en_6 virtual_od_en_6 invert_6
BitsTypeResetNameDescription
0rw0x0invert_6

For MIO_PAD6

1rw0x0virtual_od_en_6

For MIO_PAD6

2rw0x0pull_en_6

For MIO_PAD6

3rw0x0pull_select_6

For MIO_PAD6

4rw0x0keeper_en_6

For MIO_PAD6

5rw0x0schmitt_en_6

For MIO_PAD6

6rw0x0od_en_6

For MIO_PAD6

15:7Reserved
17:16rw0x0slew_rate_6

For MIO_PAD6

19:18Reserved
23:20rw0x0drive_strength_6

For MIO_PAD6


PINMUX.MIO_PAD_ATTR_7 @ 0x41c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_7
31302928272625242322212019181716
  drive_strength_7   slew_rate_7
1514131211109876543210
  od_en_7 schmitt_en_7 keeper_en_7 pull_select_7 pull_en_7 virtual_od_en_7 invert_7
BitsTypeResetNameDescription
0rw0x0invert_7

For MIO_PAD7

1rw0x0virtual_od_en_7

For MIO_PAD7

2rw0x0pull_en_7

For MIO_PAD7

3rw0x0pull_select_7

For MIO_PAD7

4rw0x0keeper_en_7

For MIO_PAD7

5rw0x0schmitt_en_7

For MIO_PAD7

6rw0x0od_en_7

For MIO_PAD7

15:7Reserved
17:16rw0x0slew_rate_7

For MIO_PAD7

19:18Reserved
23:20rw0x0drive_strength_7

For MIO_PAD7


PINMUX.MIO_PAD_ATTR_8 @ 0x420

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_8
31302928272625242322212019181716
  drive_strength_8   slew_rate_8
1514131211109876543210
  od_en_8 schmitt_en_8 keeper_en_8 pull_select_8 pull_en_8 virtual_od_en_8 invert_8
BitsTypeResetNameDescription
0rw0x0invert_8

For MIO_PAD8

1rw0x0virtual_od_en_8

For MIO_PAD8

2rw0x0pull_en_8

For MIO_PAD8

3rw0x0pull_select_8

For MIO_PAD8

4rw0x0keeper_en_8

For MIO_PAD8

5rw0x0schmitt_en_8

For MIO_PAD8

6rw0x0od_en_8

For MIO_PAD8

15:7Reserved
17:16rw0x0slew_rate_8

For MIO_PAD8

19:18Reserved
23:20rw0x0drive_strength_8

For MIO_PAD8


PINMUX.MIO_PAD_ATTR_9 @ 0x424

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_9
31302928272625242322212019181716
  drive_strength_9   slew_rate_9
1514131211109876543210
  od_en_9 schmitt_en_9 keeper_en_9 pull_select_9 pull_en_9 virtual_od_en_9 invert_9
BitsTypeResetNameDescription
0rw0x0invert_9

For MIO_PAD9

1rw0x0virtual_od_en_9

For MIO_PAD9

2rw0x0pull_en_9

For MIO_PAD9

3rw0x0pull_select_9

For MIO_PAD9

4rw0x0keeper_en_9

For MIO_PAD9

5rw0x0schmitt_en_9

For MIO_PAD9

6rw0x0od_en_9

For MIO_PAD9

15:7Reserved
17:16rw0x0slew_rate_9

For MIO_PAD9

19:18Reserved
23:20rw0x0drive_strength_9

For MIO_PAD9


PINMUX.MIO_PAD_ATTR_10 @ 0x428

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_10
31302928272625242322212019181716
  drive_strength_10   slew_rate_10
1514131211109876543210
  od_en_10 schmitt_en_10 keeper_en_10 pull_select_10 pull_en_10 virtual_od_en_10 invert_10
BitsTypeResetNameDescription
0rw0x0invert_10

For MIO_PAD10

1rw0x0virtual_od_en_10

For MIO_PAD10

2rw0x0pull_en_10

For MIO_PAD10

3rw0x0pull_select_10

For MIO_PAD10

4rw0x0keeper_en_10

For MIO_PAD10

5rw0x0schmitt_en_10

For MIO_PAD10

6rw0x0od_en_10

For MIO_PAD10

15:7Reserved
17:16rw0x0slew_rate_10

For MIO_PAD10

19:18Reserved
23:20rw0x0drive_strength_10

For MIO_PAD10


PINMUX.MIO_PAD_ATTR_11 @ 0x42c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_11
31302928272625242322212019181716
  drive_strength_11   slew_rate_11
1514131211109876543210
  od_en_11 schmitt_en_11 keeper_en_11 pull_select_11 pull_en_11 virtual_od_en_11 invert_11
BitsTypeResetNameDescription
0rw0x0invert_11

For MIO_PAD11

1rw0x0virtual_od_en_11

For MIO_PAD11

2rw0x0pull_en_11

For MIO_PAD11

3rw0x0pull_select_11

For MIO_PAD11

4rw0x0keeper_en_11

For MIO_PAD11

5rw0x0schmitt_en_11

For MIO_PAD11

6rw0x0od_en_11

For MIO_PAD11

15:7Reserved
17:16rw0x0slew_rate_11

For MIO_PAD11

19:18Reserved
23:20rw0x0drive_strength_11

For MIO_PAD11


PINMUX.MIO_PAD_ATTR_12 @ 0x430

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_12
31302928272625242322212019181716
  drive_strength_12   slew_rate_12
1514131211109876543210
  od_en_12 schmitt_en_12 keeper_en_12 pull_select_12 pull_en_12 virtual_od_en_12 invert_12
BitsTypeResetNameDescription
0rw0x0invert_12

For MIO_PAD12

1rw0x0virtual_od_en_12

For MIO_PAD12

2rw0x0pull_en_12

For MIO_PAD12

3rw0x0pull_select_12

For MIO_PAD12

4rw0x0keeper_en_12

For MIO_PAD12

5rw0x0schmitt_en_12

For MIO_PAD12

6rw0x0od_en_12

For MIO_PAD12

15:7Reserved
17:16rw0x0slew_rate_12

For MIO_PAD12

19:18Reserved
23:20rw0x0drive_strength_12

For MIO_PAD12


PINMUX.MIO_PAD_ATTR_13 @ 0x434

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_13
31302928272625242322212019181716
  drive_strength_13   slew_rate_13
1514131211109876543210
  od_en_13 schmitt_en_13 keeper_en_13 pull_select_13 pull_en_13 virtual_od_en_13 invert_13
BitsTypeResetNameDescription
0rw0x0invert_13

For MIO_PAD13

1rw0x0virtual_od_en_13

For MIO_PAD13

2rw0x0pull_en_13

For MIO_PAD13

3rw0x0pull_select_13

For MIO_PAD13

4rw0x0keeper_en_13

For MIO_PAD13

5rw0x0schmitt_en_13

For MIO_PAD13

6rw0x0od_en_13

For MIO_PAD13

15:7Reserved
17:16rw0x0slew_rate_13

For MIO_PAD13

19:18Reserved
23:20rw0x0drive_strength_13

For MIO_PAD13


PINMUX.MIO_PAD_ATTR_14 @ 0x438

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_14
31302928272625242322212019181716
  drive_strength_14   slew_rate_14
1514131211109876543210
  od_en_14 schmitt_en_14 keeper_en_14 pull_select_14 pull_en_14 virtual_od_en_14 invert_14
BitsTypeResetNameDescription
0rw0x0invert_14

For MIO_PAD14

1rw0x0virtual_od_en_14

For MIO_PAD14

2rw0x0pull_en_14

For MIO_PAD14

3rw0x0pull_select_14

For MIO_PAD14

4rw0x0keeper_en_14

For MIO_PAD14

5rw0x0schmitt_en_14

For MIO_PAD14

6rw0x0od_en_14

For MIO_PAD14

15:7Reserved
17:16rw0x0slew_rate_14

For MIO_PAD14

19:18Reserved
23:20rw0x0drive_strength_14

For MIO_PAD14


PINMUX.MIO_PAD_ATTR_15 @ 0x43c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_15
31302928272625242322212019181716
  drive_strength_15   slew_rate_15
1514131211109876543210
  od_en_15 schmitt_en_15 keeper_en_15 pull_select_15 pull_en_15 virtual_od_en_15 invert_15
BitsTypeResetNameDescription
0rw0x0invert_15

For MIO_PAD15

1rw0x0virtual_od_en_15

For MIO_PAD15

2rw0x0pull_en_15

For MIO_PAD15

3rw0x0pull_select_15

For MIO_PAD15

4rw0x0keeper_en_15

For MIO_PAD15

5rw0x0schmitt_en_15

For MIO_PAD15

6rw0x0od_en_15

For MIO_PAD15

15:7Reserved
17:16rw0x0slew_rate_15

For MIO_PAD15

19:18Reserved
23:20rw0x0drive_strength_15

For MIO_PAD15


PINMUX.MIO_PAD_ATTR_16 @ 0x440

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_16
31302928272625242322212019181716
  drive_strength_16   slew_rate_16
1514131211109876543210
  od_en_16 schmitt_en_16 keeper_en_16 pull_select_16 pull_en_16 virtual_od_en_16 invert_16
BitsTypeResetNameDescription
0rw0x0invert_16

For MIO_PAD16

1rw0x0virtual_od_en_16

For MIO_PAD16

2rw0x0pull_en_16

For MIO_PAD16

3rw0x0pull_select_16

For MIO_PAD16

4rw0x0keeper_en_16

For MIO_PAD16

5rw0x0schmitt_en_16

For MIO_PAD16

6rw0x0od_en_16

For MIO_PAD16

15:7Reserved
17:16rw0x0slew_rate_16

For MIO_PAD16

19:18Reserved
23:20rw0x0drive_strength_16

For MIO_PAD16


PINMUX.MIO_PAD_ATTR_17 @ 0x444

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_17
31302928272625242322212019181716
  drive_strength_17   slew_rate_17
1514131211109876543210
  od_en_17 schmitt_en_17 keeper_en_17 pull_select_17 pull_en_17 virtual_od_en_17 invert_17
BitsTypeResetNameDescription
0rw0x0invert_17

For MIO_PAD17

1rw0x0virtual_od_en_17

For MIO_PAD17

2rw0x0pull_en_17

For MIO_PAD17

3rw0x0pull_select_17

For MIO_PAD17

4rw0x0keeper_en_17

For MIO_PAD17

5rw0x0schmitt_en_17

For MIO_PAD17

6rw0x0od_en_17

For MIO_PAD17

15:7Reserved
17:16rw0x0slew_rate_17

For MIO_PAD17

19:18Reserved
23:20rw0x0drive_strength_17

For MIO_PAD17


PINMUX.MIO_PAD_ATTR_18 @ 0x448

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_18
31302928272625242322212019181716
  drive_strength_18   slew_rate_18
1514131211109876543210
  od_en_18 schmitt_en_18 keeper_en_18 pull_select_18 pull_en_18 virtual_od_en_18 invert_18
BitsTypeResetNameDescription
0rw0x0invert_18

For MIO_PAD18

1rw0x0virtual_od_en_18

For MIO_PAD18

2rw0x0pull_en_18

For MIO_PAD18

3rw0x0pull_select_18

For MIO_PAD18

4rw0x0keeper_en_18

For MIO_PAD18

5rw0x0schmitt_en_18

For MIO_PAD18

6rw0x0od_en_18

For MIO_PAD18

15:7Reserved
17:16rw0x0slew_rate_18

For MIO_PAD18

19:18Reserved
23:20rw0x0drive_strength_18

For MIO_PAD18


PINMUX.MIO_PAD_ATTR_19 @ 0x44c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_19
31302928272625242322212019181716
  drive_strength_19   slew_rate_19
1514131211109876543210
  od_en_19 schmitt_en_19 keeper_en_19 pull_select_19 pull_en_19 virtual_od_en_19 invert_19
BitsTypeResetNameDescription
0rw0x0invert_19

For MIO_PAD19

1rw0x0virtual_od_en_19

For MIO_PAD19

2rw0x0pull_en_19

For MIO_PAD19

3rw0x0pull_select_19

For MIO_PAD19

4rw0x0keeper_en_19

For MIO_PAD19

5rw0x0schmitt_en_19

For MIO_PAD19

6rw0x0od_en_19

For MIO_PAD19

15:7Reserved
17:16rw0x0slew_rate_19

For MIO_PAD19

19:18Reserved
23:20rw0x0drive_strength_19

For MIO_PAD19


PINMUX.MIO_PAD_ATTR_20 @ 0x450

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_20
31302928272625242322212019181716
  drive_strength_20   slew_rate_20
1514131211109876543210
  od_en_20 schmitt_en_20 keeper_en_20 pull_select_20 pull_en_20 virtual_od_en_20 invert_20
BitsTypeResetNameDescription
0rw0x0invert_20

For MIO_PAD20

1rw0x0virtual_od_en_20

For MIO_PAD20

2rw0x0pull_en_20

For MIO_PAD20

3rw0x0pull_select_20

For MIO_PAD20

4rw0x0keeper_en_20

For MIO_PAD20

5rw0x0schmitt_en_20

For MIO_PAD20

6rw0x0od_en_20

For MIO_PAD20

15:7Reserved
17:16rw0x0slew_rate_20

For MIO_PAD20

19:18Reserved
23:20rw0x0drive_strength_20

For MIO_PAD20


PINMUX.MIO_PAD_ATTR_21 @ 0x454

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_21
31302928272625242322212019181716
  drive_strength_21   slew_rate_21
1514131211109876543210
  od_en_21 schmitt_en_21 keeper_en_21 pull_select_21 pull_en_21 virtual_od_en_21 invert_21
BitsTypeResetNameDescription
0rw0x0invert_21

For MIO_PAD21

1rw0x0virtual_od_en_21

For MIO_PAD21

2rw0x0pull_en_21

For MIO_PAD21

3rw0x0pull_select_21

For MIO_PAD21

4rw0x0keeper_en_21

For MIO_PAD21

5rw0x0schmitt_en_21

For MIO_PAD21

6rw0x0od_en_21

For MIO_PAD21

15:7Reserved
17:16rw0x0slew_rate_21

For MIO_PAD21

19:18Reserved
23:20rw0x0drive_strength_21

For MIO_PAD21


PINMUX.MIO_PAD_ATTR_22 @ 0x458

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_22
31302928272625242322212019181716
  drive_strength_22   slew_rate_22
1514131211109876543210
  od_en_22 schmitt_en_22 keeper_en_22 pull_select_22 pull_en_22 virtual_od_en_22 invert_22
BitsTypeResetNameDescription
0rw0x0invert_22

For MIO_PAD22

1rw0x0virtual_od_en_22

For MIO_PAD22

2rw0x0pull_en_22

For MIO_PAD22

3rw0x0pull_select_22

For MIO_PAD22

4rw0x0keeper_en_22

For MIO_PAD22

5rw0x0schmitt_en_22

For MIO_PAD22

6rw0x0od_en_22

For MIO_PAD22

15:7Reserved
17:16rw0x0slew_rate_22

For MIO_PAD22

19:18Reserved
23:20rw0x0drive_strength_22

For MIO_PAD22


PINMUX.MIO_PAD_ATTR_23 @ 0x45c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_23
31302928272625242322212019181716
  drive_strength_23   slew_rate_23
1514131211109876543210
  od_en_23 schmitt_en_23 keeper_en_23 pull_select_23 pull_en_23 virtual_od_en_23 invert_23
BitsTypeResetNameDescription
0rw0x0invert_23

For MIO_PAD23

1rw0x0virtual_od_en_23

For MIO_PAD23

2rw0x0pull_en_23

For MIO_PAD23

3rw0x0pull_select_23

For MIO_PAD23

4rw0x0keeper_en_23

For MIO_PAD23

5rw0x0schmitt_en_23

For MIO_PAD23

6rw0x0od_en_23

For MIO_PAD23

15:7Reserved
17:16rw0x0slew_rate_23

For MIO_PAD23

19:18Reserved
23:20rw0x0drive_strength_23

For MIO_PAD23


PINMUX.MIO_PAD_ATTR_24 @ 0x460

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_24
31302928272625242322212019181716
  drive_strength_24   slew_rate_24
1514131211109876543210
  od_en_24 schmitt_en_24 keeper_en_24 pull_select_24 pull_en_24 virtual_od_en_24 invert_24
BitsTypeResetNameDescription
0rw0x0invert_24

For MIO_PAD24

1rw0x0virtual_od_en_24

For MIO_PAD24

2rw0x0pull_en_24

For MIO_PAD24

3rw0x0pull_select_24

For MIO_PAD24

4rw0x0keeper_en_24

For MIO_PAD24

5rw0x0schmitt_en_24

For MIO_PAD24

6rw0x0od_en_24

For MIO_PAD24

15:7Reserved
17:16rw0x0slew_rate_24

For MIO_PAD24

19:18Reserved
23:20rw0x0drive_strength_24

For MIO_PAD24


PINMUX.MIO_PAD_ATTR_25 @ 0x464

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_25
31302928272625242322212019181716
  drive_strength_25   slew_rate_25
1514131211109876543210
  od_en_25 schmitt_en_25 keeper_en_25 pull_select_25 pull_en_25 virtual_od_en_25 invert_25
BitsTypeResetNameDescription
0rw0x0invert_25

For MIO_PAD25

1rw0x0virtual_od_en_25

For MIO_PAD25

2rw0x0pull_en_25

For MIO_PAD25

3rw0x0pull_select_25

For MIO_PAD25

4rw0x0keeper_en_25

For MIO_PAD25

5rw0x0schmitt_en_25

For MIO_PAD25

6rw0x0od_en_25

For MIO_PAD25

15:7Reserved
17:16rw0x0slew_rate_25

For MIO_PAD25

19:18Reserved
23:20rw0x0drive_strength_25

For MIO_PAD25


PINMUX.MIO_PAD_ATTR_26 @ 0x468

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_26
31302928272625242322212019181716
  drive_strength_26   slew_rate_26
1514131211109876543210
  od_en_26 schmitt_en_26 keeper_en_26 pull_select_26 pull_en_26 virtual_od_en_26 invert_26
BitsTypeResetNameDescription
0rw0x0invert_26

For MIO_PAD26

1rw0x0virtual_od_en_26

For MIO_PAD26

2rw0x0pull_en_26

For MIO_PAD26

3rw0x0pull_select_26

For MIO_PAD26

4rw0x0keeper_en_26

For MIO_PAD26

5rw0x0schmitt_en_26

For MIO_PAD26

6rw0x0od_en_26

For MIO_PAD26

15:7Reserved
17:16rw0x0slew_rate_26

For MIO_PAD26

19:18Reserved
23:20rw0x0drive_strength_26

For MIO_PAD26


PINMUX.MIO_PAD_ATTR_27 @ 0x46c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_27
31302928272625242322212019181716
  drive_strength_27   slew_rate_27
1514131211109876543210
  od_en_27 schmitt_en_27 keeper_en_27 pull_select_27 pull_en_27 virtual_od_en_27 invert_27
BitsTypeResetNameDescription
0rw0x0invert_27

For MIO_PAD27

1rw0x0virtual_od_en_27

For MIO_PAD27

2rw0x0pull_en_27

For MIO_PAD27

3rw0x0pull_select_27

For MIO_PAD27

4rw0x0keeper_en_27

For MIO_PAD27

5rw0x0schmitt_en_27

For MIO_PAD27

6rw0x0od_en_27

For MIO_PAD27

15:7Reserved
17:16rw0x0slew_rate_27

For MIO_PAD27

19:18Reserved
23:20rw0x0drive_strength_27

For MIO_PAD27


PINMUX.MIO_PAD_ATTR_28 @ 0x470

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_28
31302928272625242322212019181716
  drive_strength_28   slew_rate_28
1514131211109876543210
  od_en_28 schmitt_en_28 keeper_en_28 pull_select_28 pull_en_28 virtual_od_en_28 invert_28
BitsTypeResetNameDescription
0rw0x0invert_28

For MIO_PAD28

1rw0x0virtual_od_en_28

For MIO_PAD28

2rw0x0pull_en_28

For MIO_PAD28

3rw0x0pull_select_28

For MIO_PAD28

4rw0x0keeper_en_28

For MIO_PAD28

5rw0x0schmitt_en_28

For MIO_PAD28

6rw0x0od_en_28

For MIO_PAD28

15:7Reserved
17:16rw0x0slew_rate_28

For MIO_PAD28

19:18Reserved
23:20rw0x0drive_strength_28

For MIO_PAD28


PINMUX.MIO_PAD_ATTR_29 @ 0x474

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_29
31302928272625242322212019181716
  drive_strength_29   slew_rate_29
1514131211109876543210
  od_en_29 schmitt_en_29 keeper_en_29 pull_select_29 pull_en_29 virtual_od_en_29 invert_29
BitsTypeResetNameDescription
0rw0x0invert_29

For MIO_PAD29

1rw0x0virtual_od_en_29

For MIO_PAD29

2rw0x0pull_en_29

For MIO_PAD29

3rw0x0pull_select_29

For MIO_PAD29

4rw0x0keeper_en_29

For MIO_PAD29

5rw0x0schmitt_en_29

For MIO_PAD29

6rw0x0od_en_29

For MIO_PAD29

15:7Reserved
17:16rw0x0slew_rate_29

For MIO_PAD29

19:18Reserved
23:20rw0x0drive_strength_29

For MIO_PAD29


PINMUX.MIO_PAD_ATTR_30 @ 0x478

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_30
31302928272625242322212019181716
  drive_strength_30   slew_rate_30
1514131211109876543210
  od_en_30 schmitt_en_30 keeper_en_30 pull_select_30 pull_en_30 virtual_od_en_30 invert_30
BitsTypeResetNameDescription
0rw0x0invert_30

For MIO_PAD30

1rw0x0virtual_od_en_30

For MIO_PAD30

2rw0x0pull_en_30

For MIO_PAD30

3rw0x0pull_select_30

For MIO_PAD30

4rw0x0keeper_en_30

For MIO_PAD30

5rw0x0schmitt_en_30

For MIO_PAD30

6rw0x0od_en_30

For MIO_PAD30

15:7Reserved
17:16rw0x0slew_rate_30

For MIO_PAD30

19:18Reserved
23:20rw0x0drive_strength_30

For MIO_PAD30


PINMUX.MIO_PAD_ATTR_31 @ 0x47c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_31
31302928272625242322212019181716
  drive_strength_31   slew_rate_31
1514131211109876543210
  od_en_31 schmitt_en_31 keeper_en_31 pull_select_31 pull_en_31 virtual_od_en_31 invert_31
BitsTypeResetNameDescription
0rw0x0invert_31

For MIO_PAD31

1rw0x0virtual_od_en_31

For MIO_PAD31

2rw0x0pull_en_31

For MIO_PAD31

3rw0x0pull_select_31

For MIO_PAD31

4rw0x0keeper_en_31

For MIO_PAD31

5rw0x0schmitt_en_31

For MIO_PAD31

6rw0x0od_en_31

For MIO_PAD31

15:7Reserved
17:16rw0x0slew_rate_31

For MIO_PAD31

19:18Reserved
23:20rw0x0drive_strength_31

For MIO_PAD31


PINMUX.MIO_PAD_ATTR_32 @ 0x480

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_32
31302928272625242322212019181716
  drive_strength_32   slew_rate_32
1514131211109876543210
  od_en_32 schmitt_en_32 keeper_en_32 pull_select_32 pull_en_32 virtual_od_en_32 invert_32
BitsTypeResetNameDescription
0rw0x0invert_32

For MIO_PAD32

1rw0x0virtual_od_en_32

For MIO_PAD32

2rw0x0pull_en_32

For MIO_PAD32

3rw0x0pull_select_32

For MIO_PAD32

4rw0x0keeper_en_32

For MIO_PAD32

5rw0x0schmitt_en_32

For MIO_PAD32

6rw0x0od_en_32

For MIO_PAD32

15:7Reserved
17:16rw0x0slew_rate_32

For MIO_PAD32

19:18Reserved
23:20rw0x0drive_strength_32

For MIO_PAD32


PINMUX.MIO_PAD_ATTR_33 @ 0x484

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_33
31302928272625242322212019181716
  drive_strength_33   slew_rate_33
1514131211109876543210
  od_en_33 schmitt_en_33 keeper_en_33 pull_select_33 pull_en_33 virtual_od_en_33 invert_33
BitsTypeResetNameDescription
0rw0x0invert_33

For MIO_PAD33

1rw0x0virtual_od_en_33

For MIO_PAD33

2rw0x0pull_en_33

For MIO_PAD33

3rw0x0pull_select_33

For MIO_PAD33

4rw0x0keeper_en_33

For MIO_PAD33

5rw0x0schmitt_en_33

For MIO_PAD33

6rw0x0od_en_33

For MIO_PAD33

15:7Reserved
17:16rw0x0slew_rate_33

For MIO_PAD33

19:18Reserved
23:20rw0x0drive_strength_33

For MIO_PAD33


PINMUX.MIO_PAD_ATTR_34 @ 0x488

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_34
31302928272625242322212019181716
  drive_strength_34   slew_rate_34
1514131211109876543210
  od_en_34 schmitt_en_34 keeper_en_34 pull_select_34 pull_en_34 virtual_od_en_34 invert_34
BitsTypeResetNameDescription
0rw0x0invert_34

For MIO_PAD34

1rw0x0virtual_od_en_34

For MIO_PAD34

2rw0x0pull_en_34

For MIO_PAD34

3rw0x0pull_select_34

For MIO_PAD34

4rw0x0keeper_en_34

For MIO_PAD34

5rw0x0schmitt_en_34

For MIO_PAD34

6rw0x0od_en_34

For MIO_PAD34

15:7Reserved
17:16rw0x0slew_rate_34

For MIO_PAD34

19:18Reserved
23:20rw0x0drive_strength_34

For MIO_PAD34


PINMUX.MIO_PAD_ATTR_35 @ 0x48c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_35
31302928272625242322212019181716
  drive_strength_35   slew_rate_35
1514131211109876543210
  od_en_35 schmitt_en_35 keeper_en_35 pull_select_35 pull_en_35 virtual_od_en_35 invert_35
BitsTypeResetNameDescription
0rw0x0invert_35

For MIO_PAD35

1rw0x0virtual_od_en_35

For MIO_PAD35

2rw0x0pull_en_35

For MIO_PAD35

3rw0x0pull_select_35

For MIO_PAD35

4rw0x0keeper_en_35

For MIO_PAD35

5rw0x0schmitt_en_35

For MIO_PAD35

6rw0x0od_en_35

For MIO_PAD35

15:7Reserved
17:16rw0x0slew_rate_35

For MIO_PAD35

19:18Reserved
23:20rw0x0drive_strength_35

For MIO_PAD35


PINMUX.MIO_PAD_ATTR_36 @ 0x490

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_36
31302928272625242322212019181716
  drive_strength_36   slew_rate_36
1514131211109876543210
  od_en_36 schmitt_en_36 keeper_en_36 pull_select_36 pull_en_36 virtual_od_en_36 invert_36
BitsTypeResetNameDescription
0rw0x0invert_36

For MIO_PAD36

1rw0x0virtual_od_en_36

For MIO_PAD36

2rw0x0pull_en_36

For MIO_PAD36

3rw0x0pull_select_36

For MIO_PAD36

4rw0x0keeper_en_36

For MIO_PAD36

5rw0x0schmitt_en_36

For MIO_PAD36

6rw0x0od_en_36

For MIO_PAD36

15:7Reserved
17:16rw0x0slew_rate_36

For MIO_PAD36

19:18Reserved
23:20rw0x0drive_strength_36

For MIO_PAD36


PINMUX.MIO_PAD_ATTR_37 @ 0x494

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_37
31302928272625242322212019181716
  drive_strength_37   slew_rate_37
1514131211109876543210
  od_en_37 schmitt_en_37 keeper_en_37 pull_select_37 pull_en_37 virtual_od_en_37 invert_37
BitsTypeResetNameDescription
0rw0x0invert_37

For MIO_PAD37

1rw0x0virtual_od_en_37

For MIO_PAD37

2rw0x0pull_en_37

For MIO_PAD37

3rw0x0pull_select_37

For MIO_PAD37

4rw0x0keeper_en_37

For MIO_PAD37

5rw0x0schmitt_en_37

For MIO_PAD37

6rw0x0od_en_37

For MIO_PAD37

15:7Reserved
17:16rw0x0slew_rate_37

For MIO_PAD37

19:18Reserved
23:20rw0x0drive_strength_37

For MIO_PAD37


PINMUX.MIO_PAD_ATTR_38 @ 0x498

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_38
31302928272625242322212019181716
  drive_strength_38   slew_rate_38
1514131211109876543210
  od_en_38 schmitt_en_38 keeper_en_38 pull_select_38 pull_en_38 virtual_od_en_38 invert_38
BitsTypeResetNameDescription
0rw0x0invert_38

For MIO_PAD38

1rw0x0virtual_od_en_38

For MIO_PAD38

2rw0x0pull_en_38

For MIO_PAD38

3rw0x0pull_select_38

For MIO_PAD38

4rw0x0keeper_en_38

For MIO_PAD38

5rw0x0schmitt_en_38

For MIO_PAD38

6rw0x0od_en_38

For MIO_PAD38

15:7Reserved
17:16rw0x0slew_rate_38

For MIO_PAD38

19:18Reserved
23:20rw0x0drive_strength_38

For MIO_PAD38


PINMUX.MIO_PAD_ATTR_39 @ 0x49c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_39
31302928272625242322212019181716
  drive_strength_39   slew_rate_39
1514131211109876543210
  od_en_39 schmitt_en_39 keeper_en_39 pull_select_39 pull_en_39 virtual_od_en_39 invert_39
BitsTypeResetNameDescription
0rw0x0invert_39

For MIO_PAD39

1rw0x0virtual_od_en_39

For MIO_PAD39

2rw0x0pull_en_39

For MIO_PAD39

3rw0x0pull_select_39

For MIO_PAD39

4rw0x0keeper_en_39

For MIO_PAD39

5rw0x0schmitt_en_39

For MIO_PAD39

6rw0x0od_en_39

For MIO_PAD39

15:7Reserved
17:16rw0x0slew_rate_39

For MIO_PAD39

19:18Reserved
23:20rw0x0drive_strength_39

For MIO_PAD39


PINMUX.MIO_PAD_ATTR_40 @ 0x4a0

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_40
31302928272625242322212019181716
  drive_strength_40   slew_rate_40
1514131211109876543210
  od_en_40 schmitt_en_40 keeper_en_40 pull_select_40 pull_en_40 virtual_od_en_40 invert_40
BitsTypeResetNameDescription
0rw0x0invert_40

For MIO_PAD40

1rw0x0virtual_od_en_40

For MIO_PAD40

2rw0x0pull_en_40

For MIO_PAD40

3rw0x0pull_select_40

For MIO_PAD40

4rw0x0keeper_en_40

For MIO_PAD40

5rw0x0schmitt_en_40

For MIO_PAD40

6rw0x0od_en_40

For MIO_PAD40

15:7Reserved
17:16rw0x0slew_rate_40

For MIO_PAD40

19:18Reserved
23:20rw0x0drive_strength_40

For MIO_PAD40


PINMUX.MIO_PAD_ATTR_41 @ 0x4a4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_41
31302928272625242322212019181716
  drive_strength_41   slew_rate_41
1514131211109876543210
  od_en_41 schmitt_en_41 keeper_en_41 pull_select_41 pull_en_41 virtual_od_en_41 invert_41
BitsTypeResetNameDescription
0rw0x0invert_41

For MIO_PAD41

1rw0x0virtual_od_en_41

For MIO_PAD41

2rw0x0pull_en_41

For MIO_PAD41

3rw0x0pull_select_41

For MIO_PAD41

4rw0x0keeper_en_41

For MIO_PAD41

5rw0x0schmitt_en_41

For MIO_PAD41

6rw0x0od_en_41

For MIO_PAD41

15:7Reserved
17:16rw0x0slew_rate_41

For MIO_PAD41

19:18Reserved
23:20rw0x0drive_strength_41

For MIO_PAD41


PINMUX.MIO_PAD_ATTR_42 @ 0x4a8

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_42
31302928272625242322212019181716
  drive_strength_42   slew_rate_42
1514131211109876543210
  od_en_42 schmitt_en_42 keeper_en_42 pull_select_42 pull_en_42 virtual_od_en_42 invert_42
BitsTypeResetNameDescription
0rw0x0invert_42

For MIO_PAD42

1rw0x0virtual_od_en_42

For MIO_PAD42

2rw0x0pull_en_42

For MIO_PAD42

3rw0x0pull_select_42

For MIO_PAD42

4rw0x0keeper_en_42

For MIO_PAD42

5rw0x0schmitt_en_42

For MIO_PAD42

6rw0x0od_en_42

For MIO_PAD42

15:7Reserved
17:16rw0x0slew_rate_42

For MIO_PAD42

19:18Reserved
23:20rw0x0drive_strength_42

For MIO_PAD42


PINMUX.MIO_PAD_ATTR_43 @ 0x4ac

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_43
31302928272625242322212019181716
  drive_strength_43   slew_rate_43
1514131211109876543210
  od_en_43 schmitt_en_43 keeper_en_43 pull_select_43 pull_en_43 virtual_od_en_43 invert_43
BitsTypeResetNameDescription
0rw0x0invert_43

For MIO_PAD43

1rw0x0virtual_od_en_43

For MIO_PAD43

2rw0x0pull_en_43

For MIO_PAD43

3rw0x0pull_select_43

For MIO_PAD43

4rw0x0keeper_en_43

For MIO_PAD43

5rw0x0schmitt_en_43

For MIO_PAD43

6rw0x0od_en_43

For MIO_PAD43

15:7Reserved
17:16rw0x0slew_rate_43

For MIO_PAD43

19:18Reserved
23:20rw0x0drive_strength_43

For MIO_PAD43


PINMUX.MIO_PAD_ATTR_44 @ 0x4b0

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_44
31302928272625242322212019181716
  drive_strength_44   slew_rate_44
1514131211109876543210
  od_en_44 schmitt_en_44 keeper_en_44 pull_select_44 pull_en_44 virtual_od_en_44 invert_44
BitsTypeResetNameDescription
0rw0x0invert_44

For MIO_PAD44

1rw0x0virtual_od_en_44

For MIO_PAD44

2rw0x0pull_en_44

For MIO_PAD44

3rw0x0pull_select_44

For MIO_PAD44

4rw0x0keeper_en_44

For MIO_PAD44

5rw0x0schmitt_en_44

For MIO_PAD44

6rw0x0od_en_44

For MIO_PAD44

15:7Reserved
17:16rw0x0slew_rate_44

For MIO_PAD44

19:18Reserved
23:20rw0x0drive_strength_44

For MIO_PAD44


PINMUX.MIO_PAD_ATTR_45 @ 0x4b4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_45
31302928272625242322212019181716
  drive_strength_45   slew_rate_45
1514131211109876543210
  od_en_45 schmitt_en_45 keeper_en_45 pull_select_45 pull_en_45 virtual_od_en_45 invert_45
BitsTypeResetNameDescription
0rw0x0invert_45

For MIO_PAD45

1rw0x0virtual_od_en_45

For MIO_PAD45

2rw0x0pull_en_45

For MIO_PAD45

3rw0x0pull_select_45

For MIO_PAD45

4rw0x0keeper_en_45

For MIO_PAD45

5rw0x0schmitt_en_45

For MIO_PAD45

6rw0x0od_en_45

For MIO_PAD45

15:7Reserved
17:16rw0x0slew_rate_45

For MIO_PAD45

19:18Reserved
23:20rw0x0drive_strength_45

For MIO_PAD45


PINMUX.MIO_PAD_ATTR_46 @ 0x4b8

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = MIO_PAD_ATTR_REGWEN_46
31302928272625242322212019181716
  drive_strength_46   slew_rate_46
1514131211109876543210
  od_en_46 schmitt_en_46 keeper_en_46 pull_select_46 pull_en_46 virtual_od_en_46 invert_46
BitsTypeResetNameDescription
0rw0x0invert_46

For MIO_PAD46

1rw0x0virtual_od_en_46

For MIO_PAD46

2rw0x0pull_en_46

For MIO_PAD46

3rw0x0pull_select_46

For MIO_PAD46

4rw0x0keeper_en_46

For MIO_PAD46

5rw0x0schmitt_en_46

For MIO_PAD46

6rw0x0od_en_46

For MIO_PAD46

15:7Reserved
17:16rw0x0slew_rate_46

For MIO_PAD46

19:18Reserved
23:20rw0x0drive_strength_46

For MIO_PAD46


PINMUX.DIO_PAD_ATTR_REGWEN_0 @ 0x4bc

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_0
BitsTypeResetNameDescription
0rw0c0x1EN_0

Register write enable bit. If this is cleared to 0, the corresponding !!DIO_PAD_ATTR is not writable anymore.


PINMUX.DIO_PAD_ATTR_REGWEN_1 @ 0x4c0

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_1
BitsTypeResetNameDescription
0rw0c0x1EN_1

For DIO_PAD1


PINMUX.DIO_PAD_ATTR_REGWEN_2 @ 0x4c4

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_2
BitsTypeResetNameDescription
0rw0c0x1EN_2

For DIO_PAD2


PINMUX.DIO_PAD_ATTR_REGWEN_3 @ 0x4c8

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_3
BitsTypeResetNameDescription
0rw0c0x1EN_3

For DIO_PAD3


PINMUX.DIO_PAD_ATTR_REGWEN_4 @ 0x4cc

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_4
BitsTypeResetNameDescription
0rw0c0x1EN_4

For DIO_PAD4


PINMUX.DIO_PAD_ATTR_REGWEN_5 @ 0x4d0

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_5
BitsTypeResetNameDescription
0rw0c0x1EN_5

For DIO_PAD5


PINMUX.DIO_PAD_ATTR_REGWEN_6 @ 0x4d4

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_6
BitsTypeResetNameDescription
0rw0c0x1EN_6

For DIO_PAD6


PINMUX.DIO_PAD_ATTR_REGWEN_7 @ 0x4d8

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_7
BitsTypeResetNameDescription
0rw0c0x1EN_7

For DIO_PAD7


PINMUX.DIO_PAD_ATTR_REGWEN_8 @ 0x4dc

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_8
BitsTypeResetNameDescription
0rw0c0x1EN_8

For DIO_PAD8


PINMUX.DIO_PAD_ATTR_REGWEN_9 @ 0x4e0

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_9
BitsTypeResetNameDescription
0rw0c0x1EN_9

For DIO_PAD9


PINMUX.DIO_PAD_ATTR_REGWEN_10 @ 0x4e4

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_10
BitsTypeResetNameDescription
0rw0c0x1EN_10

For DIO_PAD10


PINMUX.DIO_PAD_ATTR_REGWEN_11 @ 0x4e8

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_11
BitsTypeResetNameDescription
0rw0c0x1EN_11

For DIO_PAD11


PINMUX.DIO_PAD_ATTR_REGWEN_12 @ 0x4ec

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_12
BitsTypeResetNameDescription
0rw0c0x1EN_12

For DIO_PAD12


PINMUX.DIO_PAD_ATTR_REGWEN_13 @ 0x4f0

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_13
BitsTypeResetNameDescription
0rw0c0x1EN_13

For DIO_PAD13


PINMUX.DIO_PAD_ATTR_REGWEN_14 @ 0x4f4

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_14
BitsTypeResetNameDescription
0rw0c0x1EN_14

For DIO_PAD14


PINMUX.DIO_PAD_ATTR_REGWEN_15 @ 0x4f8

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_15
BitsTypeResetNameDescription
0rw0c0x1EN_15

For DIO_PAD15


PINMUX.DIO_PAD_ATTR_0 @ 0x4fc

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = DIO_PAD_ATTR_REGWEN_0
31302928272625242322212019181716
  drive_strength_0   slew_rate_0
1514131211109876543210
  od_en_0 schmitt_en_0 keeper_en_0 pull_select_0 pull_en_0 virtual_od_en_0 invert_0
BitsTypeResetNameDescription
0rw0x0invert_0

Invert input and output levels.

1rw0x0virtual_od_en_0

Enable virtual open drain.

2rw0x0pull_en_0

Enable pull-up or pull-down resistor.

3rw0x0pull_select_0

Pull select (0: pull-down, 1: pull-up).

0x0pull_down

Select the pull-down resistor.

0x1pull_up

Select the pull-up resistor.

4rw0x0keeper_en_0

Enable pull-up or pull-down resistor.

5rw0x0schmitt_en_0

Enable the schmitt trigger.

6rw0x0od_en_0

Enable open drain.

15:7Reserved
17:16rw0x0slew_rate_0

Slew rate (0x0: slowest, 0x3: fastest).

19:18Reserved
23:20rw0x0drive_strength_0

Drive strength (0x0: weakest, 0xf: strongest)


PINMUX.DIO_PAD_ATTR_1 @ 0x500

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = DIO_PAD_ATTR_REGWEN_1
31302928272625242322212019181716
  drive_strength_1   slew_rate_1
1514131211109876543210
  od_en_1 schmitt_en_1 keeper_en_1 pull_select_1 pull_en_1 virtual_od_en_1 invert_1
BitsTypeResetNameDescription
0rw0x0invert_1

For DIO_PAD1

1rw0x0virtual_od_en_1

For DIO_PAD1

2rw0x0pull_en_1

For DIO_PAD1

3rw0x0pull_select_1

For DIO_PAD1

4rw0x0keeper_en_1

For DIO_PAD1

5rw0x0schmitt_en_1

For DIO_PAD1

6rw0x0od_en_1

For DIO_PAD1

15:7Reserved
17:16rw0x0slew_rate_1

For DIO_PAD1

19:18Reserved
23:20rw0x0drive_strength_1

For DIO_PAD1


PINMUX.DIO_PAD_ATTR_2 @ 0x504

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = DIO_PAD_ATTR_REGWEN_2
31302928272625242322212019181716
  drive_strength_2   slew_rate_2
1514131211109876543210
  od_en_2 schmitt_en_2 keeper_en_2 pull_select_2 pull_en_2 virtual_od_en_2 invert_2
BitsTypeResetNameDescription
0rw0x0invert_2

For DIO_PAD2

1rw0x0virtual_od_en_2

For DIO_PAD2

2rw0x0pull_en_2

For DIO_PAD2

3rw0x0pull_select_2

For DIO_PAD2

4rw0x0keeper_en_2

For DIO_PAD2

5rw0x0schmitt_en_2

For DIO_PAD2

6rw0x0od_en_2

For DIO_PAD2

15:7Reserved
17:16rw0x0slew_rate_2

For DIO_PAD2

19:18Reserved
23:20rw0x0drive_strength_2

For DIO_PAD2


PINMUX.DIO_PAD_ATTR_3 @ 0x508

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = DIO_PAD_ATTR_REGWEN_3
31302928272625242322212019181716
  drive_strength_3   slew_rate_3
1514131211109876543210
  od_en_3 schmitt_en_3 keeper_en_3 pull_select_3 pull_en_3 virtual_od_en_3 invert_3
BitsTypeResetNameDescription
0rw0x0invert_3

For DIO_PAD3

1rw0x0virtual_od_en_3

For DIO_PAD3

2rw0x0pull_en_3

For DIO_PAD3

3rw0x0pull_select_3

For DIO_PAD3

4rw0x0keeper_en_3

For DIO_PAD3

5rw0x0schmitt_en_3

For DIO_PAD3

6rw0x0od_en_3

For DIO_PAD3

15:7Reserved
17:16rw0x0slew_rate_3

For DIO_PAD3

19:18Reserved
23:20rw0x0drive_strength_3

For DIO_PAD3


PINMUX.DIO_PAD_ATTR_4 @ 0x50c

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = DIO_PAD_ATTR_REGWEN_4
31302928272625242322212019181716
  drive_strength_4   slew_rate_4
1514131211109876543210
  od_en_4 schmitt_en_4 keeper_en_4 pull_select_4 pull_en_4 virtual_od_en_4 invert_4
BitsTypeResetNameDescription
0rw0x0invert_4

For DIO_PAD4

1rw0x0virtual_od_en_4

For DIO_PAD4

2rw0x0pull_en_4

For DIO_PAD4

3rw0x0pull_select_4

For DIO_PAD4

4rw0x0keeper_en_4

For DIO_PAD4

5rw0x0schmitt_en_4

For DIO_PAD4

6rw0x0od_en_4

For DIO_PAD4

15:7Reserved
17:16rw0x0slew_rate_4

For DIO_PAD4

19:18Reserved
23:20rw0x0drive_strength_4

For DIO_PAD4


PINMUX.DIO_PAD_ATTR_5 @ 0x510

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = DIO_PAD_ATTR_REGWEN_5
31302928272625242322212019181716
  drive_strength_5   slew_rate_5
1514131211109876543210
  od_en_5 schmitt_en_5 keeper_en_5 pull_select_5 pull_en_5 virtual_od_en_5 invert_5
BitsTypeResetNameDescription
0rw0x0invert_5

For DIO_PAD5

1rw0x0virtual_od_en_5

For DIO_PAD5

2rw0x0pull_en_5

For DIO_PAD5

3rw0x0pull_select_5

For DIO_PAD5

4rw0x0keeper_en_5

For DIO_PAD5

5rw0x0schmitt_en_5

For DIO_PAD5

6rw0x0od_en_5

For DIO_PAD5

15:7Reserved
17:16rw0x0slew_rate_5

For DIO_PAD5

19:18Reserved
23:20rw0x0drive_strength_5

For DIO_PAD5


PINMUX.DIO_PAD_ATTR_6 @ 0x514

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = DIO_PAD_ATTR_REGWEN_6
31302928272625242322212019181716
  drive_strength_6   slew_rate_6
1514131211109876543210
  od_en_6 schmitt_en_6 keeper_en_6 pull_select_6 pull_en_6 virtual_od_en_6 invert_6
BitsTypeResetNameDescription
0rw0x0invert_6

For DIO_PAD6

1rw0x0virtual_od_en_6

For DIO_PAD6

2rw0x0pull_en_6

For DIO_PAD6

3rw0x0pull_select_6

For DIO_PAD6

4rw0x0keeper_en_6

For DIO_PAD6

5rw0x0schmitt_en_6

For DIO_PAD6

6rw0x0od_en_6

For DIO_PAD6

15:7Reserved
17:16rw0x0slew_rate_6

For DIO_PAD6

19:18Reserved
23:20rw0x0drive_strength_6

For DIO_PAD6


PINMUX.DIO_PAD_ATTR_7 @ 0x518

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = DIO_PAD_ATTR_REGWEN_7
31302928272625242322212019181716
  drive_strength_7   slew_rate_7
1514131211109876543210
  od_en_7 schmitt_en_7 keeper_en_7 pull_select_7 pull_en_7 virtual_od_en_7 invert_7
BitsTypeResetNameDescription
0rw0x0invert_7

For DIO_PAD7

1rw0x0virtual_od_en_7

For DIO_PAD7

2rw0x0pull_en_7

For DIO_PAD7

3rw0x0pull_select_7

For DIO_PAD7

4rw0x0keeper_en_7

For DIO_PAD7

5rw0x0schmitt_en_7

For DIO_PAD7

6rw0x0od_en_7

For DIO_PAD7

15:7Reserved
17:16rw0x0slew_rate_7

For DIO_PAD7

19:18Reserved
23:20rw0x0drive_strength_7

For DIO_PAD7


PINMUX.DIO_PAD_ATTR_8 @ 0x51c

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = DIO_PAD_ATTR_REGWEN_8
31302928272625242322212019181716
  drive_strength_8   slew_rate_8
1514131211109876543210
  od_en_8 schmitt_en_8 keeper_en_8 pull_select_8 pull_en_8 virtual_od_en_8 invert_8
BitsTypeResetNameDescription
0rw0x0invert_8

For DIO_PAD8

1rw0x0virtual_od_en_8

For DIO_PAD8

2rw0x0pull_en_8

For DIO_PAD8

3rw0x0pull_select_8

For DIO_PAD8

4rw0x0keeper_en_8

For DIO_PAD8

5rw0x0schmitt_en_8

For DIO_PAD8

6rw0x0od_en_8

For DIO_PAD8

15:7Reserved
17:16rw0x0slew_rate_8

For DIO_PAD8

19:18Reserved
23:20rw0x0drive_strength_8

For DIO_PAD8


PINMUX.DIO_PAD_ATTR_9 @ 0x520

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = DIO_PAD_ATTR_REGWEN_9
31302928272625242322212019181716
  drive_strength_9   slew_rate_9
1514131211109876543210
  od_en_9 schmitt_en_9 keeper_en_9 pull_select_9 pull_en_9 virtual_od_en_9 invert_9
BitsTypeResetNameDescription
0rw0x0invert_9

For DIO_PAD9

1rw0x0virtual_od_en_9

For DIO_PAD9

2rw0x0pull_en_9

For DIO_PAD9

3rw0x0pull_select_9

For DIO_PAD9

4rw0x0keeper_en_9

For DIO_PAD9

5rw0x0schmitt_en_9

For DIO_PAD9

6rw0x0od_en_9

For DIO_PAD9

15:7Reserved
17:16rw0x0slew_rate_9

For DIO_PAD9

19:18Reserved
23:20rw0x0drive_strength_9

For DIO_PAD9


PINMUX.DIO_PAD_ATTR_10 @ 0x524

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = DIO_PAD_ATTR_REGWEN_10
31302928272625242322212019181716
  drive_strength_10   slew_rate_10
1514131211109876543210
  od_en_10 schmitt_en_10 keeper_en_10 pull_select_10 pull_en_10 virtual_od_en_10 invert_10
BitsTypeResetNameDescription
0rw0x0invert_10

For DIO_PAD10

1rw0x0virtual_od_en_10

For DIO_PAD10

2rw0x0pull_en_10

For DIO_PAD10

3rw0x0pull_select_10

For DIO_PAD10

4rw0x0keeper_en_10

For DIO_PAD10

5rw0x0schmitt_en_10

For DIO_PAD10

6rw0x0od_en_10

For DIO_PAD10

15:7Reserved
17:16rw0x0slew_rate_10

For DIO_PAD10

19:18Reserved
23:20rw0x0drive_strength_10

For DIO_PAD10


PINMUX.DIO_PAD_ATTR_11 @ 0x528

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = DIO_PAD_ATTR_REGWEN_11
31302928272625242322212019181716
  drive_strength_11   slew_rate_11
1514131211109876543210
  od_en_11 schmitt_en_11 keeper_en_11 pull_select_11 pull_en_11 virtual_od_en_11 invert_11
BitsTypeResetNameDescription
0rw0x0invert_11

For DIO_PAD11

1rw0x0virtual_od_en_11

For DIO_PAD11

2rw0x0pull_en_11

For DIO_PAD11

3rw0x0pull_select_11

For DIO_PAD11

4rw0x0keeper_en_11

For DIO_PAD11

5rw0x0schmitt_en_11

For DIO_PAD11

6rw0x0od_en_11

For DIO_PAD11

15:7Reserved
17:16rw0x0slew_rate_11

For DIO_PAD11

19:18Reserved
23:20rw0x0drive_strength_11

For DIO_PAD11


PINMUX.DIO_PAD_ATTR_12 @ 0x52c

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = DIO_PAD_ATTR_REGWEN_12
31302928272625242322212019181716
  drive_strength_12   slew_rate_12
1514131211109876543210
  od_en_12 schmitt_en_12 keeper_en_12 pull_select_12 pull_en_12 virtual_od_en_12 invert_12
BitsTypeResetNameDescription
0rw0x0invert_12

For DIO_PAD12

1rw0x0virtual_od_en_12

For DIO_PAD12

2rw0x0pull_en_12

For DIO_PAD12

3rw0x0pull_select_12

For DIO_PAD12

4rw0x0keeper_en_12

For DIO_PAD12

5rw0x0schmitt_en_12

For DIO_PAD12

6rw0x0od_en_12

For DIO_PAD12

15:7Reserved
17:16rw0x0slew_rate_12

For DIO_PAD12

19:18Reserved
23:20rw0x0drive_strength_12

For DIO_PAD12


PINMUX.DIO_PAD_ATTR_13 @ 0x530

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = DIO_PAD_ATTR_REGWEN_13
31302928272625242322212019181716
  drive_strength_13   slew_rate_13
1514131211109876543210
  od_en_13 schmitt_en_13 keeper_en_13 pull_select_13 pull_en_13 virtual_od_en_13 invert_13
BitsTypeResetNameDescription
0rw0x0invert_13

For DIO_PAD13

1rw0x0virtual_od_en_13

For DIO_PAD13

2rw0x0pull_en_13

For DIO_PAD13

3rw0x0pull_select_13

For DIO_PAD13

4rw0x0keeper_en_13

For DIO_PAD13

5rw0x0schmitt_en_13

For DIO_PAD13

6rw0x0od_en_13

For DIO_PAD13

15:7Reserved
17:16rw0x0slew_rate_13

For DIO_PAD13

19:18Reserved
23:20rw0x0drive_strength_13

For DIO_PAD13


PINMUX.DIO_PAD_ATTR_14 @ 0x534

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = DIO_PAD_ATTR_REGWEN_14
31302928272625242322212019181716
  drive_strength_14   slew_rate_14
1514131211109876543210
  od_en_14 schmitt_en_14 keeper_en_14 pull_select_14 pull_en_14 virtual_od_en_14 invert_14
BitsTypeResetNameDescription
0rw0x0invert_14

For DIO_PAD14

1rw0x0virtual_od_en_14

For DIO_PAD14

2rw0x0pull_en_14

For DIO_PAD14

3rw0x0pull_select_14

For DIO_PAD14

4rw0x0keeper_en_14

For DIO_PAD14

5rw0x0schmitt_en_14

For DIO_PAD14

6rw0x0od_en_14

For DIO_PAD14

15:7Reserved
17:16rw0x0slew_rate_14

For DIO_PAD14

19:18Reserved
23:20rw0x0drive_strength_14

For DIO_PAD14


PINMUX.DIO_PAD_ATTR_15 @ 0x538

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f
Register enable = DIO_PAD_ATTR_REGWEN_15
31302928272625242322212019181716
  drive_strength_15   slew_rate_15
1514131211109876543210
  od_en_15 schmitt_en_15 keeper_en_15 pull_select_15 pull_en_15 virtual_od_en_15 invert_15
BitsTypeResetNameDescription
0rw0x0invert_15

For DIO_PAD15

1rw0x0virtual_od_en_15

For DIO_PAD15

2rw0x0pull_en_15

For DIO_PAD15

3rw0x0pull_select_15

For DIO_PAD15

4rw0x0keeper_en_15

For DIO_PAD15

5rw0x0schmitt_en_15

For DIO_PAD15

6rw0x0od_en_15

For DIO_PAD15

15:7Reserved
17:16rw0x0slew_rate_15

For DIO_PAD15

19:18Reserved
23:20rw0x0drive_strength_15

For DIO_PAD15


PINMUX.MIO_PAD_SLEEP_STATUS_0 @ 0x53c

Register indicating whether the corresponding pad is in sleep mode.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
EN_31 EN_30 EN_29 EN_28 EN_27 EN_26 EN_25 EN_24 EN_23 EN_22 EN_21 EN_20 EN_19 EN_18 EN_17 EN_16
1514131211109876543210
EN_15 EN_14 EN_13 EN_12 EN_11 EN_10 EN_9 EN_8 EN_7 EN_6 EN_5 EN_4 EN_3 EN_2 EN_1 EN_0
BitsTypeResetNameDescription
0rw0c0x0EN_0

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

1rw0c0x0EN_1

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

2rw0c0x0EN_2

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

3rw0c0x0EN_3

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

4rw0c0x0EN_4

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

5rw0c0x0EN_5

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

6rw0c0x0EN_6

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

7rw0c0x0EN_7

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

8rw0c0x0EN_8

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

9rw0c0x0EN_9

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

10rw0c0x0EN_10

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

11rw0c0x0EN_11

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

12rw0c0x0EN_12

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

13rw0c0x0EN_13

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

14rw0c0x0EN_14

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

15rw0c0x0EN_15

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

16rw0c0x0EN_16

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

17rw0c0x0EN_17

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

18rw0c0x0EN_18

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

19rw0c0x0EN_19

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

20rw0c0x0EN_20

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

21rw0c0x0EN_21

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

22rw0c0x0EN_22

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

23rw0c0x0EN_23

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

24rw0c0x0EN_24

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

25rw0c0x0EN_25

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

26rw0c0x0EN_26

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

27rw0c0x0EN_27

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

28rw0c0x0EN_28

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

29rw0c0x0EN_29

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

30rw0c0x0EN_30

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

31rw0c0x0EN_31

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.


PINMUX.MIO_PAD_SLEEP_STATUS_1 @ 0x540

Register indicating whether the corresponding pad is in sleep mode.

Reset default = 0x0, mask 0x7fff
31302928272625242322212019181716
 
1514131211109876543210
  EN_46 EN_45 EN_44 EN_43 EN_42 EN_41 EN_40 EN_39 EN_38 EN_37 EN_36 EN_35 EN_34 EN_33 EN_32
BitsTypeResetNameDescription
0rw0c0x0EN_32

For MIO_PAD1

1rw0c0x0EN_33

For MIO_PAD1

2rw0c0x0EN_34

For MIO_PAD1

3rw0c0x0EN_35

For MIO_PAD1

4rw0c0x0EN_36

For MIO_PAD1

5rw0c0x0EN_37

For MIO_PAD1

6rw0c0x0EN_38

For MIO_PAD1

7rw0c0x0EN_39

For MIO_PAD1

8rw0c0x0EN_40

For MIO_PAD1

9rw0c0x0EN_41

For MIO_PAD1

10rw0c0x0EN_42

For MIO_PAD1

11rw0c0x0EN_43

For MIO_PAD1

12rw0c0x0EN_44

For MIO_PAD1

13rw0c0x0EN_45

For MIO_PAD1

14rw0c0x0EN_46

For MIO_PAD1


PINMUX.MIO_PAD_SLEEP_REGWEN_0 @ 0x544

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_0
BitsTypeResetNameDescription
0rw0c0x1EN_0

Register write enable bit. If this is cleared to 0, the corresponding !!MIO_OUT_SLEEP_MODE is not writable anymore.


PINMUX.MIO_PAD_SLEEP_REGWEN_1 @ 0x548

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_1
BitsTypeResetNameDescription
0rw0c0x1EN_1

For MIO_PAD1


PINMUX.MIO_PAD_SLEEP_REGWEN_2 @ 0x54c

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_2
BitsTypeResetNameDescription
0rw0c0x1EN_2

For MIO_PAD2


PINMUX.MIO_PAD_SLEEP_REGWEN_3 @ 0x550

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_3
BitsTypeResetNameDescription
0rw0c0x1EN_3

For MIO_PAD3


PINMUX.MIO_PAD_SLEEP_REGWEN_4 @ 0x554

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_4
BitsTypeResetNameDescription
0rw0c0x1EN_4

For MIO_PAD4


PINMUX.MIO_PAD_SLEEP_REGWEN_5 @ 0x558

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_5
BitsTypeResetNameDescription
0rw0c0x1EN_5

For MIO_PAD5


PINMUX.MIO_PAD_SLEEP_REGWEN_6 @ 0x55c

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_6
BitsTypeResetNameDescription
0rw0c0x1EN_6

For MIO_PAD6


PINMUX.MIO_PAD_SLEEP_REGWEN_7 @ 0x560

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_7
BitsTypeResetNameDescription
0rw0c0x1EN_7

For MIO_PAD7


PINMUX.MIO_PAD_SLEEP_REGWEN_8 @ 0x564

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_8
BitsTypeResetNameDescription
0rw0c0x1EN_8

For MIO_PAD8


PINMUX.MIO_PAD_SLEEP_REGWEN_9 @ 0x568

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_9
BitsTypeResetNameDescription
0rw0c0x1EN_9

For MIO_PAD9


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_10
BitsTypeResetNameDescription
0rw0c0x1EN_10

For MIO_PAD10


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_11
BitsTypeResetNameDescription
0rw0c0x1EN_11

For MIO_PAD11


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_12
BitsTypeResetNameDescription
0rw0c0x1EN_12

For MIO_PAD12


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_13
BitsTypeResetNameDescription
0rw0c0x1EN_13

For MIO_PAD13


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_14
BitsTypeResetNameDescription
0rw0c0x1EN_14

For MIO_PAD14


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_15
BitsTypeResetNameDescription
0rw0c0x1EN_15

For MIO_PAD15


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_16
BitsTypeResetNameDescription
0rw0c0x1EN_16

For MIO_PAD16


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_17
BitsTypeResetNameDescription
0rw0c0x1EN_17

For MIO_PAD17


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_18
BitsTypeResetNameDescription
0rw0c0x1EN_18

For MIO_PAD18


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_19
BitsTypeResetNameDescription
0rw0c0x1EN_19

For MIO_PAD19


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_20
BitsTypeResetNameDescription
0rw0c0x1EN_20

For MIO_PAD20


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_21
BitsTypeResetNameDescription
0rw0c0x1EN_21

For MIO_PAD21


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_22
BitsTypeResetNameDescription
0rw0c0x1EN_22

For MIO_PAD22


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_23
BitsTypeResetNameDescription
0rw0c0x1EN_23

For MIO_PAD23


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_24
BitsTypeResetNameDescription
0rw0c0x1EN_24

For MIO_PAD24


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_25
BitsTypeResetNameDescription
0rw0c0x1EN_25

For MIO_PAD25


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_26
BitsTypeResetNameDescription
0rw0c0x1EN_26

For MIO_PAD26


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_27
BitsTypeResetNameDescription
0rw0c0x1EN_27

For MIO_PAD27


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_28
BitsTypeResetNameDescription
0rw0c0x1EN_28

For MIO_PAD28


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_29
BitsTypeResetNameDescription
0rw0c0x1EN_29

For MIO_PAD29


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_30
BitsTypeResetNameDescription
0rw0c0x1EN_30

For MIO_PAD30


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_31
BitsTypeResetNameDescription
0rw0c0x1EN_31

For MIO_PAD31


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_32
BitsTypeResetNameDescription
0rw0c0x1EN_32

For MIO_PAD32


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_33
BitsTypeResetNameDescription
0rw0c0x1EN_33

For MIO_PAD33


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_34
BitsTypeResetNameDescription
0rw0c0x1EN_34

For MIO_PAD34


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_35
BitsTypeResetNameDescription
0rw0c0x1EN_35

For MIO_PAD35


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_36
BitsTypeResetNameDescription
0rw0c0x1EN_36

For MIO_PAD36


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_37
BitsTypeResetNameDescription
0rw0c0x1EN_37

For MIO_PAD37


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_38
BitsTypeResetNameDescription
0rw0c0x1EN_38

For MIO_PAD38


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_39
BitsTypeResetNameDescription
0rw0c0x1EN_39

For MIO_PAD39


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_40
BitsTypeResetNameDescription
0rw0c0x1EN_40

For MIO_PAD40


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
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  EN_41
BitsTypeResetNameDescription
0rw0c0x1EN_41

For MIO_PAD41


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
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  EN_42
BitsTypeResetNameDescription
0rw0c0x1EN_42

For MIO_PAD42


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
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  EN_43
BitsTypeResetNameDescription
0rw0c0x1EN_43

For MIO_PAD43


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
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  EN_44
BitsTypeResetNameDescription
0rw0c0x1EN_44

For MIO_PAD44


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
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  EN_45
BitsTypeResetNameDescription
0rw0c0x1EN_45

For MIO_PAD45


Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
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  EN_46
BitsTypeResetNameDescription
0rw0c0x1EN_46

For MIO_PAD46


PINMUX.MIO_PAD_SLEEP_EN_0 @ 0x600

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_0
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  EN_0
BitsTypeResetNameDescription
0rw0x0EN_0

Deep sleep mode enable. If this bit is set to 1 the corresponding pad will enable the sleep behavior specified in !!MIO_PAD_SLEEP_MODE upon deep sleep entry, and the corresponding bit in !!MIO_PAD_SLEEP_STATUS will be set to 1. The pad remains in deep sleep mode until the corresponding bit in !!MIO_PAD_SLEEP_STATUS is cleared by SW. Note that if an always on peripheral is connected to a specific MIO pad, the corresponding !!MIO_PAD_SLEEP_EN bit should be set to 0.


PINMUX.MIO_PAD_SLEEP_EN_1 @ 0x604

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_1
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  EN_1
BitsTypeResetNameDescription
0rw0x0EN_1

For OUT1


PINMUX.MIO_PAD_SLEEP_EN_2 @ 0x608

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_2
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  EN_2
BitsTypeResetNameDescription
0rw0x0EN_2

For OUT2


PINMUX.MIO_PAD_SLEEP_EN_3 @ 0x60c

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_3
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  EN_3
BitsTypeResetNameDescription
0rw0x0EN_3

For OUT3


PINMUX.MIO_PAD_SLEEP_EN_4 @ 0x610

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_4
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  EN_4
BitsTypeResetNameDescription
0rw0x0EN_4

For OUT4


PINMUX.MIO_PAD_SLEEP_EN_5 @ 0x614

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_5
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  EN_5
BitsTypeResetNameDescription
0rw0x0EN_5

For OUT5


PINMUX.MIO_PAD_SLEEP_EN_6 @ 0x618

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_6
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  EN_6
BitsTypeResetNameDescription
0rw0x0EN_6

For OUT6


PINMUX.MIO_PAD_SLEEP_EN_7 @ 0x61c

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_7
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  EN_7
BitsTypeResetNameDescription
0rw0x0EN_7

For OUT7


PINMUX.MIO_PAD_SLEEP_EN_8 @ 0x620

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_8
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  EN_8
BitsTypeResetNameDescription
0rw0x0EN_8

For OUT8


PINMUX.MIO_PAD_SLEEP_EN_9 @ 0x624

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_9
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  EN_9
BitsTypeResetNameDescription
0rw0x0EN_9

For OUT9


PINMUX.MIO_PAD_SLEEP_EN_10 @ 0x628

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_10
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  EN_10
BitsTypeResetNameDescription
0rw0x0EN_10

For OUT10


PINMUX.MIO_PAD_SLEEP_EN_11 @ 0x62c

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_11
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  EN_11
BitsTypeResetNameDescription
0rw0x0EN_11

For OUT11


PINMUX.MIO_PAD_SLEEP_EN_12 @ 0x630

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_12
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  EN_12
BitsTypeResetNameDescription
0rw0x0EN_12

For OUT12


PINMUX.MIO_PAD_SLEEP_EN_13 @ 0x634

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_13
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  EN_13
BitsTypeResetNameDescription
0rw0x0EN_13

For OUT13


PINMUX.MIO_PAD_SLEEP_EN_14 @ 0x638

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_14
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  EN_14
BitsTypeResetNameDescription
0rw0x0EN_14

For OUT14


PINMUX.MIO_PAD_SLEEP_EN_15 @ 0x63c

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_15
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  EN_15
BitsTypeResetNameDescription
0rw0x0EN_15

For OUT15


PINMUX.MIO_PAD_SLEEP_EN_16 @ 0x640

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_16
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