Pinmux Technical Specification

Overview

This document specifies the functionality of the pin multiplexer (pinmux) peripheral. This module conforms to the OpenTitan guideline for peripheral device functionality.. See that document for integration overview within the broader OpenTitan top level system. The module provides a mechanism to reconfigure the peripheral-to-pin mapping at runtime, which greatly enhances the system flexibility. This IP is closely related to the padctrl instance which provides additional control of pad attributes (pull-up, pull-down, open drain, drive strength, keeper and inversion). See that spec for more information.

Features

  • Configurable number of chip bidirectional pins

  • Configurable number of peripheral inputs and outputs

  • Programmable mapping from peripheral outputs (and output enables) to top-level outputs (and output enables)

  • Programmable mapping from top-level inputs to peripheral inputs

Description

The pinmux peripheral is a programmable module designed to wire arbitrary peripheral inputs and outputs to arbitrary multiplexable chip bidirectional pins. It gives much flexibility at the top level of the device, allowing most data pins to be flexibly wired and controlled by many peripherals. It is assumed that all available pins that the pinmux connects to are bidirectional, controlled by logic within this module. This document does not define how these are connected to pads at the toplevel, since that is governed by the padctrl IP that spec. However, some discussion is shared in a later section.

The number of available peripheral IOs and muxed IOs is configurable, in other words modifiable at design time. This configurability is implemented by representing inputs / outputs as packed arrays, in combination with the SystemVerilog parameters NPeriphIn, NPeriphOut and NMioPads. Note however that the register file is also affected by this configuration and needs to be regenerated for each design instance.

The assignment of which peripheral output goes to the output data signal of which chip pin is programmable, in other words, modifiable by software at run time. Similarly the assignment of which peripheral input is driven by which chip input is programmable. By default, all peripheral inputs are tied to zero or one (this default is design-time programmable via the InputDefault parameter). Further, all output enables are set to zero, which essentially causes all pads to be in high-Z state after reset.

In addition to wiring programmability, each peripheral input can be set constantly to 0 or 1, and each chip output can be set constantly to 0, 1 or high-Z. Additional features such as output keeper or inversion are not provided by the pinmux since they are implemented in the padctrl IP which operates at the chip-level. This separation of physical pad attributes and logical wiring makes it possible to place the pads into an always-on domain without restricting possible power-down modes of the pinmux. One could imagine this to be a useful feature if a deep sleep mode were implemented in future; chip outputs could hold their output values and not be affected by internal power loss.

Theory of Operations

The pin multiplexor module intends to give maximum flexibility of peripheral and chip wiring to the software running on the device. The assumption is that the wiring is done once at the initialization of the application based upon usage of the device within the broader system. How this wiring is most effectively done is outside the scope of this document, but a section below briefly discusses use cases.

Block Diagram

The diagram below shows connectivity between four arbitrary chip pins, named MIO_00 .. MIO_03, and several peripheral inputs and outputs. This shows the connectivity available in all directions, as well as the control registers described later in this document. Two example peripherals (uart and spidev) are attached to the pinmux in this example, one with one input and one output, the other with three inputs and one output. The diagram also shows the padring module (from the padctrl IP) which instantiates the bidirectional chip pads with output enable control.

Pinmux Block Diagram

Note that apart from selecting a specific input pad, the periph_insel[*] signals can also be used to tie the peripheral input to 0 or 1. Likewise, the output select signals mio_outsel[*] can also be used to constantly drive an output pin to 0/1 or to put it into high-Z state (default). The output enable and the associated data signal (i.e. periph_to_mio and periph_to_mio_oe) are indexed with the same select signal to allow the peripheral hardware to determine the pad direction instead of demoting that control to software.

Additional details about the signal names and parameters are given in the sections below.

Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module PINMUX has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks:

Bus Device Interface: tlul

Bus Host Interface:

Peripheral Pins for Chip IO: none

Interrupts: none

Security Alerts:

Alert NameDescription

Parameters

The following table lists the main parameters used throughout the pinmux design. Note that the pinmux is generated based on the system configuration, and hence these parameters are placed into a package as “localparams”.

Localparam Default (Max) Top Earlgrey Description
NPeriphOut 16 (-) 32 Number of peripheral outputs.
NPeriphIn 16 (-) 32 Number of peripheral input.
NMioPads 8 (-) 32 Number of muxed bidirectional pads (depending on padctrl setup).

Additional IOs

The table below lists the pinmux signals. The number of IOs is parametric, and hence the signals are stacked in packed arrays.

Signal Direction Type Description
periph_to_mio_i[NPeriphOut-1:0] input packed logic Signals from NPeriphOut peripheral outputs coming into the pinmux.
periph_to_mio_oe_i[NPeriphOut-1:0] input packed logic Signals from NPeriphOut peripheral output enables coming into the pinmux.
mio_to_periph_o[NPeriphIn-1:0] output packed logic Signals to NPeriphIn peripherals coming from the pinmux.
mio_out_o[NMioPads-1:0] output packed logic Signals to NMioPads bidirectional pads as output data.
mio_oe_o[NMioPads-1:0] output packed logic Signals to NMioPads bidirectional pads as output enables.
mio_in_i[NMioPads-1:0] input packed logic Signals from NMioPads bidirectional pads as input data.

Programmers Guide

Software should determine and program the pinmux mapping at startup, or reprogram it when the functionality requirements change at runtime. This can be achieved by writing the following values to the PERIPH_INSEL and MIO_OUTSEL registers. Note that the pinmux configuration should be sequenced after any IO attribute-specific configuration in the padctrl module to avoid any unwanted electric behavior and/or contention.

periph_insel Value Selected Input Signal
0 Constant zero
1 Constant one
2 + k Corresponding MIO input signal at index k

The global default at reset is 0, but the default of individual signals can be overridden at design time, if needed.

mio_outsel Value Selected Output signal
0 Constant zero
1 Constant one
2 High-Z
3 + k Corresponding peripheral output signal at index k

The global default at reset is 2, but the default of individual signals can be overridden at design time, if needed.

The pinmux configuration can be locked down by writing 0 to register REGEN. The configuration can then not be altered anymore unless the system is reset.

Register Table

The register description below matches the instance in the Earl Grey top level design.

Similar register descriptions can be generated with different parameterizations.

PINMUX.REGEN @ + 0x0
Register write enable for all control registers.
Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  wen
BitsTypeResetNameDescription
0rw0c0x1wenWhen true, all configuration registers can be modified. When false, they become read-only. Defaults true, write zero to clear.


PINMUX.PERIPH_INSEL_0 @ + 0x4
Mux select for peripheral inputs.
Reset default = 0x0, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  IN_4 IN_3 IN_2...
1514131211109876543210
...IN_2 IN_1 IN_0
BitsTypeResetNameDescription
5:0rw0x0IN_00: tie constantly to zero, 1: tie constantly to 1, >=2: MIO pads (i.e., add 2 to the native MIO pad index).
11:6rw0x0IN_1For IN1
17:12rw0x0IN_2For IN2
23:18rw0x0IN_3For IN3
29:24rw0x0IN_4For IN4


PINMUX.PERIPH_INSEL_1 @ + 0x8
Mux select for peripheral inputs.
Reset default = 0x0, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  IN_9 IN_8 IN_7...
1514131211109876543210
...IN_7 IN_6 IN_5
BitsTypeResetNameDescription
5:0rw0x0IN_5For IN5
11:6rw0x0IN_6For IN6
17:12rw0x0IN_7For IN7
23:18rw0x0IN_8For IN8
29:24rw0x0IN_9For IN9


PINMUX.PERIPH_INSEL_2 @ + 0xc
Mux select for peripheral inputs.
Reset default = 0x0, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  IN_14 IN_13 IN_12...
1514131211109876543210
...IN_12 IN_11 IN_10
BitsTypeResetNameDescription
5:0rw0x0IN_10For IN10
11:6rw0x0IN_11For IN11
17:12rw0x0IN_12For IN12
23:18rw0x0IN_13For IN13
29:24rw0x0IN_14For IN14


PINMUX.PERIPH_INSEL_3 @ + 0x10
Mux select for peripheral inputs.
Reset default = 0x0, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  IN_19 IN_18 IN_17...
1514131211109876543210
...IN_17 IN_16 IN_15
BitsTypeResetNameDescription
5:0rw0x0IN_15For IN15
11:6rw0x0IN_16For IN16
17:12rw0x0IN_17For IN17
23:18rw0x0IN_18For IN18
29:24rw0x0IN_19For IN19


PINMUX.PERIPH_INSEL_4 @ + 0x14
Mux select for peripheral inputs.
Reset default = 0x0, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  IN_24 IN_23 IN_22...
1514131211109876543210
...IN_22 IN_21 IN_20
BitsTypeResetNameDescription
5:0rw0x0IN_20For IN20
11:6rw0x0IN_21For IN21
17:12rw0x0IN_22For IN22
23:18rw0x0IN_23For IN23
29:24rw0x0IN_24For IN24


PINMUX.PERIPH_INSEL_5 @ + 0x18
Mux select for peripheral inputs.
Reset default = 0x0, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  IN_29 IN_28 IN_27...
1514131211109876543210
...IN_27 IN_26 IN_25
BitsTypeResetNameDescription
5:0rw0x0IN_25For IN25
11:6rw0x0IN_26For IN26
17:12rw0x0IN_27For IN27
23:18rw0x0IN_28For IN28
29:24rw0x0IN_29For IN29


PINMUX.PERIPH_INSEL_6 @ + 0x1c
Mux select for peripheral inputs.
Reset default = 0x0, mask 0xfff
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  IN_31 IN_30
BitsTypeResetNameDescription
5:0rw0x0IN_30For IN30
11:6rw0x0IN_31For IN31


PINMUX.MIO_OUTSEL_0 @ + 0x20
Mux select for MIO outputs.
Reset default = 0x2082082, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  OUT_4 OUT_3 OUT_2...
1514131211109876543210
...OUT_2 OUT_1 OUT_0
BitsTypeResetNameDescription
5:0rw0x2OUT_00: tie constantly to zero, 1: tie constantly to 1, 2: high-Z, >=3: peripheral outputs (i.e., add 3 to the native peripheral pad index).
11:6rw0x2OUT_1For OUT1
17:12rw0x2OUT_2For OUT2
23:18rw0x2OUT_3For OUT3
29:24rw0x2OUT_4For OUT4


PINMUX.MIO_OUTSEL_1 @ + 0x24
Mux select for MIO outputs.
Reset default = 0x2082082, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  OUT_9 OUT_8 OUT_7...
1514131211109876543210
...OUT_7 OUT_6 OUT_5
BitsTypeResetNameDescription
5:0rw0x2OUT_5For OUT5
11:6rw0x2OUT_6For OUT6
17:12rw0x2OUT_7For OUT7
23:18rw0x2OUT_8For OUT8
29:24rw0x2OUT_9For OUT9


PINMUX.MIO_OUTSEL_2 @ + 0x28
Mux select for MIO outputs.
Reset default = 0x2082082, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  OUT_14 OUT_13 OUT_12...
1514131211109876543210
...OUT_12 OUT_11 OUT_10
BitsTypeResetNameDescription
5:0rw0x2OUT_10For OUT10
11:6rw0x2OUT_11For OUT11
17:12rw0x2OUT_12For OUT12
23:18rw0x2OUT_13For OUT13
29:24rw0x2OUT_14For OUT14


PINMUX.MIO_OUTSEL_3 @ + 0x2c
Mux select for MIO outputs.
Reset default = 0x2082082, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  OUT_19 OUT_18 OUT_17...
1514131211109876543210
...OUT_17 OUT_16 OUT_15
BitsTypeResetNameDescription
5:0rw0x2OUT_15For OUT15
11:6rw0x2OUT_16For OUT16
17:12rw0x2OUT_17For OUT17
23:18rw0x2OUT_18For OUT18
29:24rw0x2OUT_19For OUT19


PINMUX.MIO_OUTSEL_4 @ + 0x30
Mux select for MIO outputs.
Reset default = 0x2082082, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  OUT_24 OUT_23 OUT_22...
1514131211109876543210
...OUT_22 OUT_21 OUT_20
BitsTypeResetNameDescription
5:0rw0x2OUT_20For OUT20
11:6rw0x2OUT_21For OUT21
17:12rw0x2OUT_22For OUT22
23:18rw0x2OUT_23For OUT23
29:24rw0x2OUT_24For OUT24


PINMUX.MIO_OUTSEL_5 @ + 0x34
Mux select for MIO outputs.
Reset default = 0x2082082, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  OUT_29 OUT_28 OUT_27...
1514131211109876543210
...OUT_27 OUT_26 OUT_25
BitsTypeResetNameDescription
5:0rw0x2OUT_25For OUT25
11:6rw0x2OUT_26For OUT26
17:12rw0x2OUT_27For OUT27
23:18rw0x2OUT_28For OUT28
29:24rw0x2OUT_29For OUT29


PINMUX.MIO_OUTSEL_6 @ + 0x38
Mux select for MIO outputs.
Reset default = 0x82, mask 0xfff
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  OUT_31 OUT_30
BitsTypeResetNameDescription
5:0rw0x2OUT_30For OUT30
11:6rw0x2OUT_31For OUT31


PINMUX.MIO_OUT_SLEEP_VAL_0 @ + 0x3c
Defines sleep behavior of muxed output or inout. Note that the MIO output will only switch into sleep mode if the the corresponding !!MIO_OUTSEL is either set to 0-2, or if !!MIO_OUTSEL selects a peripheral output that can go into sleep. If an always on peripheral is selected with !!MIO_OUTSEL, the !!MIO_OUT_SLEEP_VAL configuration has no effect.
Reset default = 0xaaaaaaaa, mask 0xffffffff
Register enable = REGEN
31302928272625242322212019181716
OUT_15 OUT_14 OUT_13 OUT_12 OUT_11 OUT_10 OUT_9 OUT_8
1514131211109876543210
OUT_7 OUT_6 OUT_5 OUT_4 OUT_3 OUT_2 OUT_1 OUT_0
BitsTypeResetNameDescription
1:0rw0x2OUT_0Value to drive in deep sleep.
0Tie-LowThe pin is driven actively to zero in deep sleep mode.
1Tie-HighThe pin is driven actively to one in deep sleep mode.
2High-ZThe pin is left undriven in deep sleep mode. Note that the actual driving behavior during deep sleep will then depend on the pull-up/-down configuration of padctrl.
3KeepKeep last driven value (including high-Z).
3:2rw0x2OUT_1For OUT1
5:4rw0x2OUT_2For OUT2
7:6rw0x2OUT_3For OUT3
9:8rw0x2OUT_4For OUT4
11:10rw0x2OUT_5For OUT5
13:12rw0x2OUT_6For OUT6
15:14rw0x2OUT_7For OUT7
17:16rw0x2OUT_8For OUT8
19:18rw0x2OUT_9For OUT9
21:20rw0x2OUT_10For OUT10
23:22rw0x2OUT_11For OUT11
25:24rw0x2OUT_12For OUT12
27:26rw0x2OUT_13For OUT13
29:28rw0x2OUT_14For OUT14
31:30rw0x2OUT_15For OUT15


PINMUX.MIO_OUT_SLEEP_VAL_1 @ + 0x40
Defines sleep behavior of muxed output or inout. Note that the MIO output will only switch into sleep mode if the the corresponding !!MIO_OUTSEL is either set to 0-2, or if !!MIO_OUTSEL selects a peripheral output that can go into sleep. If an always on peripheral is selected with !!MIO_OUTSEL, the !!MIO_OUT_SLEEP_VAL configuration has no effect.
Reset default = 0xaaaaaaaa, mask 0xffffffff
Register enable = REGEN
31302928272625242322212019181716
OUT_31 OUT_30 OUT_29 OUT_28 OUT_27 OUT_26 OUT_25 OUT_24
1514131211109876543210
OUT_23 OUT_22 OUT_21 OUT_20 OUT_19 OUT_18 OUT_17 OUT_16
BitsTypeResetNameDescription
1:0rw0x2OUT_16For OUT16
3:2rw0x2OUT_17For OUT17
5:4rw0x2OUT_18For OUT18
7:6rw0x2OUT_19For OUT19
9:8rw0x2OUT_20For OUT20
11:10rw0x2OUT_21For OUT21
13:12rw0x2OUT_22For OUT22
15:14rw0x2OUT_23For OUT23
17:16rw0x2OUT_24For OUT24
19:18rw0x2OUT_25For OUT25
21:20rw0x2OUT_26For OUT26
23:22rw0x2OUT_27For OUT27
25:24rw0x2OUT_28For OUT28
27:26rw0x2OUT_29For OUT29
29:28rw0x2OUT_30For OUT30
31:30rw0x2OUT_31For OUT31


PINMUX.DIO_OUT_SLEEP_VAL @ + 0x44
Defines sleep behavior of dedicated output or inout. Note this register has WARL behavior since the sleep value settings are meaningless for always-on and input-only DIOs. For these DIOs, this register always reads 0.
Reset default = 0x2aaaaaaa, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  OUT_14 OUT_13 OUT_12 OUT_11 OUT_10 OUT_9 OUT_8
1514131211109876543210
OUT_7 OUT_6 OUT_5 OUT_4 OUT_3 OUT_2 OUT_1 OUT_0
BitsTypeResetNameDescription
1:0rw0x2OUT_0Value to drive in deep sleep.
0Tie-LowThe pin is driven actively to zero in deep sleep mode.
1Tie-HighThe pin is driven actively to one in deep sleep mode.
2High-ZThe pin is left undriven in deep sleep mode. Note that the actual driving behavior during deep sleep will then depend on the pull-up/-down configuration of padctrl.
3KeepKeep last driven value (including high-Z).
3:2rw0x2OUT_1For OUT1
5:4rw0x2OUT_2For OUT2
7:6rw0x2OUT_3For OUT3
9:8rw0x2OUT_4For OUT4
11:10rw0x2OUT_5For OUT5
13:12rw0x2OUT_6For OUT6
15:14rw0x2OUT_7For OUT7
17:16rw0x2OUT_8For OUT8
19:18rw0x2OUT_9For OUT9
21:20rw0x2OUT_10For OUT10
23:22rw0x2OUT_11For OUT11
25:24rw0x2OUT_12For OUT12
27:26rw0x2OUT_13For OUT13
29:28rw0x2OUT_14For OUT14


PINMUX.WKUP_DETECTOR_EN @ + 0x48
Enables for the wakeup detectors.
Reset default = 0x0, mask 0xff
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  EN_7 EN_6 EN_5 EN_4 EN_3 EN_2 EN_1 EN_0
BitsTypeResetNameDescription
0:0rw0x0EN_0Setting this bit activates the corresponding wakeup detector. The behavior is as specified in !!WKUP_DETECTOR, !!WKUP_DETECTOR_CNT_TH and !!WKUP_DETECTOR_PADSEL.
1:1rw0x0EN_1For DETECTOR1
2:2rw0x0EN_2For DETECTOR2
3:3rw0x0EN_3For DETECTOR3
4:4rw0x0EN_4For DETECTOR4
5:5rw0x0EN_5For DETECTOR5
6:6rw0x0EN_6For DETECTOR6
7:7rw0x0EN_7For DETECTOR7


PINMUX.WKUP_DETECTOR_0 @ + 0x4c
Configuration of wakeup condition detectors.
Reset default = 0x0, mask 0x1f
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  MIODIO_0 FILTER_0 MODE_0
BitsTypeResetNameDescription
2:0rw0x0MODE_0Wakeup detection mode.
0DisabledPin wakeup detector is disabled.
1NegedgeTrigger a wakeup request when observing a negative edge.
2PosedgeTrigger a wakeup request when observing a positive edge.
3EdgeTrigger a wakeup request when observing an edge in any direction.
4TimedLowTrigger a wakeup request when pin is driven LOW for a certain amount of always-on clock cycles as configured in !!WKUP_DETECTOR_CNT_TH.
5TimedHighTrigger a wakeup request when pin is driven HIGH for a certain amount of always-on clock cycles as configured in !!WKUP_DETECTOR_CNT_TH.
Other values are reserved.
3rw0x0FILTER_00: signal filter disabled, 1: signal filter enabled. the signal must be stable for 4 always-on clock cycles before the value is being forwarded. can be used for debouncing.
4rw0x0MIODIO_00: select index !!WKUP_DETECTOR_PADSEL from MIO pads, 1: select index !!WKUP_DETECTOR_PADSEL from DIO pads.


PINMUX.WKUP_DETECTOR_1 @ + 0x50
Configuration of wakeup condition detectors.
Reset default = 0x0, mask 0x1f
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  MIODIO_1 FILTER_1 MODE_1
BitsTypeResetNameDescription
2:0rw0x0MODE_1For DETECTOR1
3rw0x0FILTER_1For DETECTOR1
4rw0x0MIODIO_1For DETECTOR1


PINMUX.WKUP_DETECTOR_2 @ + 0x54
Configuration of wakeup condition detectors.
Reset default = 0x0, mask 0x1f
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  MIODIO_2 FILTER_2 MODE_2
BitsTypeResetNameDescription
2:0rw0x0MODE_2For DETECTOR2
3rw0x0FILTER_2For DETECTOR2
4rw0x0MIODIO_2For DETECTOR2


PINMUX.WKUP_DETECTOR_3 @ + 0x58
Configuration of wakeup condition detectors.
Reset default = 0x0, mask 0x1f
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  MIODIO_3 FILTER_3 MODE_3
BitsTypeResetNameDescription
2:0rw0x0MODE_3For DETECTOR3
3rw0x0FILTER_3For DETECTOR3
4rw0x0MIODIO_3For DETECTOR3


PINMUX.WKUP_DETECTOR_4 @ + 0x5c
Configuration of wakeup condition detectors.
Reset default = 0x0, mask 0x1f
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  MIODIO_4 FILTER_4 MODE_4
BitsTypeResetNameDescription
2:0rw0x0MODE_4For DETECTOR4
3rw0x0FILTER_4For DETECTOR4
4rw0x0MIODIO_4For DETECTOR4


PINMUX.WKUP_DETECTOR_5 @ + 0x60
Configuration of wakeup condition detectors.
Reset default = 0x0, mask 0x1f
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  MIODIO_5 FILTER_5 MODE_5
BitsTypeResetNameDescription
2:0rw0x0MODE_5For DETECTOR5
3rw0x0FILTER_5For DETECTOR5
4rw0x0MIODIO_5For DETECTOR5


PINMUX.WKUP_DETECTOR_6 @ + 0x64
Configuration of wakeup condition detectors.
Reset default = 0x0, mask 0x1f
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  MIODIO_6 FILTER_6 MODE_6
BitsTypeResetNameDescription
2:0rw0x0MODE_6For DETECTOR6
3rw0x0FILTER_6For DETECTOR6
4rw0x0MIODIO_6For DETECTOR6


PINMUX.WKUP_DETECTOR_7 @ + 0x68
Configuration of wakeup condition detectors.
Reset default = 0x0, mask 0x1f
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  MIODIO_7 FILTER_7 MODE_7
BitsTypeResetNameDescription
2:0rw0x0MODE_7For DETECTOR7
3rw0x0FILTER_7For DETECTOR7
4rw0x0MIODIO_7For DETECTOR7


PINMUX.WKUP_DETECTOR_CNT_TH_0 @ + 0x6c
Counter thresholds for wakeup condition detectors.
Reset default = 0x0, mask 0xffffffff
Register enable = REGEN
31302928272625242322212019181716
TH_3 TH_2
1514131211109876543210
TH_1 TH_0
BitsTypeResetNameDescription
7:0rw0x0TH_0Counter threshold for TimedLow and TimedHigh wakeup detector modes (see !!WKUP_DETECTOR). The threshold is in terms of always-on clock cycles.
15:8rw0x0TH_1For DETECTOR1
23:16rw0x0TH_2For DETECTOR2
31:24rw0x0TH_3For DETECTOR3


PINMUX.WKUP_DETECTOR_CNT_TH_1 @ + 0x70
Counter thresholds for wakeup condition detectors.
Reset default = 0x0, mask 0xffffffff
Register enable = REGEN
31302928272625242322212019181716
TH_7 TH_6
1514131211109876543210
TH_5 TH_4
BitsTypeResetNameDescription
7:0rw0x0TH_4For DETECTOR4
15:8rw0x0TH_5For DETECTOR5
23:16rw0x0TH_6For DETECTOR6
31:24rw0x0TH_7For DETECTOR7


PINMUX.WKUP_DETECTOR_PADSEL_0 @ + 0x74
Pad selects for pad wakeup condition detectors.
Reset default = 0x0, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  SEL_5 SEL_4 SEL_3...
1514131211109876543210
...SEL_3 SEL_2 SEL_1 SEL_0
BitsTypeResetNameDescription
4:0rw0x0SEL_0Selects a specific MIO or DIO pad (depending on !!WKUP_DETECTOR configuration). In case of MIO, the pad select index is the same as used for !!PERIPH_INSEL, meaning that index 0 and 1 just select constant 0, and the MIO pads live at indices >= 2. In case of DIO pads, the pad select index corresponds 1:1 to the DIO pad to be selected.
9:5rw0x0SEL_1For DETECTOR1
14:10rw0x0SEL_2For DETECTOR2
19:15rw0x0SEL_3For DETECTOR3
24:20rw0x0SEL_4For DETECTOR4
29:25rw0x0SEL_5For DETECTOR5


PINMUX.WKUP_DETECTOR_PADSEL_1 @ + 0x78
Pad selects for pad wakeup condition detectors.
Reset default = 0x0, mask 0x3ff
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  SEL_7 SEL_6
BitsTypeResetNameDescription
4:0rw0x0SEL_6For DETECTOR6
9:5rw0x0SEL_7For DETECTOR7


PINMUX.WKUP_CAUSE @ + 0x7c
Cause registers for wakeup detectors.
Reset default = 0x0, mask 0xff
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  CAUSE_7 CAUSE_6 CAUSE_5 CAUSE_4 CAUSE_3 CAUSE_2 CAUSE_1 CAUSE_0
BitsTypeResetNameDescription
0rw0c0x0CAUSE_0Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear.
1rw0c0x0CAUSE_1For DETECTOR1
2rw0c0x0CAUSE_2For DETECTOR2
3rw0c0x0CAUSE_3For DETECTOR3
4rw0c0x0CAUSE_4For DETECTOR4
5rw0c0x0CAUSE_5For DETECTOR5
6rw0c0x0CAUSE_6For DETECTOR6
7rw0c0x0CAUSE_7For DETECTOR7