Pinmux Technical Specification

Overview

This document specifies the functionality of the pin multiplexer (pinmux) peripheral. This module conforms to the OpenTitan guideline for peripheral device functionality.. See that document for integration overview within the broader OpenTitan top level system. The module provides a mechanism to reconfigure the peripheral-to-pin mapping at runtime, which greatly enhances the system flexibility. This IP is closely related to the padctrl instance which provides additional control of pad attributes (pull-up, pull-down, open drain, drive strength, keeper and inversion). See that spec for more information.

Features

  • Configurable number of chip bidirectional pins

  • Configurable number of peripheral inputs and outputs

  • Programmable mapping from peripheral outputs (and output enables) to top-level outputs (and output enables)

  • Programmable mapping from top-level inputs to peripheral inputs

Description

The pinmux peripheral is a programmable module designed to wire arbitrary peripheral inputs and outputs to arbitrary multiplexable chip bidirectional pins. It gives much flexibility at the top level of the device, allowing most data pins to be flexibly wired and controlled by many peripherals. It is assumed that all available pins that the pinmux connects to are bidirectional, controlled by logic within this module. This document does not define how these are connected to pads at the toplevel, since that is governed by the padctrl IP that spec. However, some discussion is shared in a later section.

The number of available peripheral IOs and muxed IOs is configurable, in other words modifiable at design time. This configurability is implemented by representing inputs / outputs as packed arrays, in combination with the SystemVerilog parameters NPeriphIn, NPeriphOut and NMioPads. Note however that the register file is also affected by this configuration and needs to be regenerated for each design instance.

The assignment of which peripheral output goes to the output data signal of which chip pin is programmable, in other words, modifiable by software at run time. Similarly the assignment of which peripheral input is driven by which chip input is programmable. By default, all peripheral inputs are tied to zero or one (this default is design-time programmable via the InputDefault parameter). Further, all output enables are set to zero, which essentially causes all pads to be in high-Z state after reset.

In addition to wiring programmability, each peripheral input can be set constantly to 0 or 1, and each chip output can be set constantly to 0, 1 or high-Z. Additional features such as output keeper or inversion are not provided by the pinmux since they are implemented in the padctrl IP which operates at the chip-level. This separation of physical pad attributes and logical wiring makes it possible to place the pads into an always-on domain without restricting possible power-down modes of the pinmux. One could imagine this to be a useful feature if a deep sleep mode were implemented in future; chip outputs could hold their output values and not be affected by internal power loss.

Theory of Operations

The pin multiplexor module intends to give maximum flexibility of peripheral and chip wiring to the software running on the device. The assumption is that the wiring is done once at the initialization of the application based upon usage of the device within the broader system. How this wiring is most effectively done is outside the scope of this document, but a section below briefly discusses use cases.

Block Diagram

The diagram below shows connectivity between four arbitrary chip pins, named MIO_00 .. MIO_03, and several peripheral inputs and outputs. This shows the connectivity available in all directions, as well as the control registers described later in this document. Two example peripherals (uart and spidev) are attached to the pinmux in this example, one with one input and one output, the other with three inputs and one output. The diagram also shows the padring module (from the padctrl IP) which instantiates the bidirectional chip pads with output enable control.

Pinmux Block Diagram

Note that apart from selecting a specific input pad, the periph_insel[*] signals can also be used to tie the peripheral input to 0 or 1. Likewise, the output select signals mio_outsel[*] can also be used to constantly drive an output pin to 0/1 or to put it into high-Z state (default). The output enable and the associated data signal (i.e. periph_to_mio and periph_to_mio_oe) are indexed with the same select signal to allow the peripheral hardware to determine the pad direction instead of demoting that control to software.

Additional details about the signal names and parameters are given in the sections below.

Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module PINMUX has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks:

Bus Device Interface: tlul

Bus Host Interface: none

Peripheral Pins for Chip IO: none

Interrupts: none

Security Alerts: none

Parameters

The following table lists the main parameters used throughout the pinmux design. Note that the pinmux is generated based on the system configuration, and hence these parameters are placed into a package as “localparams”.

Localparam Default (Max) Top Earlgrey Description
NPeriphOut 16 (-) 32 Number of peripheral outputs.
NPeriphIn 16 (-) 32 Number of peripheral input.
NMioPads 8 (-) 32 Number of muxed bidirectional pads (depending on padctrl setup).

Additional IOs

The table below lists the pinmux signals. The number of IOs is parametric, and hence the signals are stacked in packed arrays.

Signal Direction Type Description
periph_to_mio_i[NPeriphOut-1:0] input packed logic Signals from NPeriphOut peripheral outputs coming into the pinmux.
periph_to_mio_oe_i[NPeriphOut-1:0] input packed logic Signals from NPeriphOut peripheral output enables coming into the pinmux.
mio_to_periph_o[NPeriphIn-1:0] output packed logic Signals to NPeriphIn peripherals coming from the pinmux.
mio_out_o[NMioPads-1:0] output packed logic Signals to NMioPads bidirectional pads as output data.
mio_oe_o[NMioPads-1:0] output packed logic Signals to NMioPads bidirectional pads as output enables.
mio_in_i[NMioPads-1:0] input packed logic Signals from NMioPads bidirectional pads as input data.

Programmers Guide

Software should determine and program the pinmux mapping at startup, or reprogram it when the functionality requirements change at runtime. This can be achieved by writing the following values to the PERIPH_INSEL and MIO_OUTSEL registers. Note that the pinmux configuration should be sequenced after any IO attribute-specific configuration in the padctrl module to avoid any unwanted electric behavior and/or contention.

periph_insel Value Selected Input Signal
0 Constant zero
1 Constant one
2 + k Corresponding MIO input signal at index k

The global default at reset is 0, but the default of individual signals can be overridden at design time, if needed.

mio_outsel Value Selected Output signal
0 Constant zero
1 Constant one
2 High-Z
3 + k Corresponding peripheral output signal at index k

The global default at reset is 2, but the default of individual signals can be overridden at design time, if needed.

The pinmux configuration can be locked down by writing 0 to register REGEN. The configuration can then not be altered anymore unless the system is reset.

Register Table

The register description below matches the instance in the Earl Grey top level design.

Similar register descriptions can be generated with different parameterizations.

PINMUX.REGEN @ + 0x0
Register write enable for all control registers.
Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  wen
BitsTypeResetNameDescription
0rw0c0x1wenWhen true, all configuration registers can be modified. When false, they become read-only. Defaults true, write zero to clear.


PINMUX.PERIPH_INSEL0 @ + 0x4
Mux select for peripheral inputs.
Reset default = 0x0, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  IN4 IN3 IN2...
1514131211109876543210
...IN2 IN1 IN0
BitsTypeResetNameDescription
5:0rw0x0IN00: tie constantly to zero, 1: tie constantly to 1, >=2: MIO pads (i.e., add 2 to the native MIO pad index). for IN0
29:6for IN1..IN4


PINMUX.PERIPH_INSEL1 @ + 0x8
Mux select for peripheral inputs.
Reset default = 0x0, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  IN9 IN8 IN7...
1514131211109876543210
...IN7 IN6 IN5
BitsTypeResetNameDescription
5:0rw0x0IN50: tie constantly to zero, 1: tie constantly to 1, >=2: MIO pads (i.e., add 2 to the native MIO pad index). for IN5
29:6for IN6..IN9


PINMUX.PERIPH_INSEL2 @ + 0xc
Mux select for peripheral inputs.
Reset default = 0x0, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  IN14 IN13 IN12...
1514131211109876543210
...IN12 IN11 IN10
BitsTypeResetNameDescription
5:0rw0x0IN100: tie constantly to zero, 1: tie constantly to 1, >=2: MIO pads (i.e., add 2 to the native MIO pad index). for IN10
29:6for IN11..IN14


PINMUX.PERIPH_INSEL3 @ + 0x10
Mux select for peripheral inputs.
Reset default = 0x0, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  IN19 IN18 IN17...
1514131211109876543210
...IN17 IN16 IN15
BitsTypeResetNameDescription
5:0rw0x0IN150: tie constantly to zero, 1: tie constantly to 1, >=2: MIO pads (i.e., add 2 to the native MIO pad index). for IN15
29:6for IN16..IN19


PINMUX.PERIPH_INSEL4 @ + 0x14
Mux select for peripheral inputs.
Reset default = 0x0, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  IN24 IN23 IN22...
1514131211109876543210
...IN22 IN21 IN20
BitsTypeResetNameDescription
5:0rw0x0IN200: tie constantly to zero, 1: tie constantly to 1, >=2: MIO pads (i.e., add 2 to the native MIO pad index). for IN20
29:6for IN21..IN24


PINMUX.PERIPH_INSEL5 @ + 0x18
Mux select for peripheral inputs.
Reset default = 0x0, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  IN29 IN28 IN27...
1514131211109876543210
...IN27 IN26 IN25
BitsTypeResetNameDescription
5:0rw0x0IN250: tie constantly to zero, 1: tie constantly to 1, >=2: MIO pads (i.e., add 2 to the native MIO pad index). for IN25
29:6for IN26..IN29


PINMUX.PERIPH_INSEL6 @ + 0x1c
Mux select for peripheral inputs.
Reset default = 0x0, mask 0xfff
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  IN31 IN30
BitsTypeResetNameDescription
5:0rw0x0IN300: tie constantly to zero, 1: tie constantly to 1, >=2: MIO pads (i.e., add 2 to the native MIO pad index). for IN30
11:6for IN31


PINMUX.MIO_OUTSEL0 @ + 0x20
Mux select for MIO outputs.
Reset default = 0x2082082, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  OUT4 OUT3 OUT2...
1514131211109876543210
...OUT2 OUT1 OUT0
BitsTypeResetNameDescription
5:0rw0x2OUT00: tie constantly to zero, 1: tie constantly to 1, 2: high-Z, >=3: peripheral outputs (i.e., add 3 to the native peripheral pad index). for OUT0
29:6for OUT1..OUT4


PINMUX.MIO_OUTSEL1 @ + 0x24
Mux select for MIO outputs.
Reset default = 0x2082082, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  OUT9 OUT8 OUT7...
1514131211109876543210
...OUT7 OUT6 OUT5
BitsTypeResetNameDescription
5:0rw0x2OUT50: tie constantly to zero, 1: tie constantly to 1, 2: high-Z, >=3: peripheral outputs (i.e., add 3 to the native peripheral pad index). for OUT5
29:6for OUT6..OUT9


PINMUX.MIO_OUTSEL2 @ + 0x28
Mux select for MIO outputs.
Reset default = 0x2082082, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  OUT14 OUT13 OUT12...
1514131211109876543210
...OUT12 OUT11 OUT10
BitsTypeResetNameDescription
5:0rw0x2OUT100: tie constantly to zero, 1: tie constantly to 1, 2: high-Z, >=3: peripheral outputs (i.e., add 3 to the native peripheral pad index). for OUT10
29:6for OUT11..OUT14


PINMUX.MIO_OUTSEL3 @ + 0x2c
Mux select for MIO outputs.
Reset default = 0x2082082, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  OUT19 OUT18 OUT17...
1514131211109876543210
...OUT17 OUT16 OUT15
BitsTypeResetNameDescription
5:0rw0x2OUT150: tie constantly to zero, 1: tie constantly to 1, 2: high-Z, >=3: peripheral outputs (i.e., add 3 to the native peripheral pad index). for OUT15
29:6for OUT16..OUT19


PINMUX.MIO_OUTSEL4 @ + 0x30
Mux select for MIO outputs.
Reset default = 0x2082082, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  OUT24 OUT23 OUT22...
1514131211109876543210
...OUT22 OUT21 OUT20
BitsTypeResetNameDescription
5:0rw0x2OUT200: tie constantly to zero, 1: tie constantly to 1, 2: high-Z, >=3: peripheral outputs (i.e., add 3 to the native peripheral pad index). for OUT20
29:6for OUT21..OUT24


PINMUX.MIO_OUTSEL5 @ + 0x34
Mux select for MIO outputs.
Reset default = 0x2082082, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  OUT29 OUT28 OUT27...
1514131211109876543210
...OUT27 OUT26 OUT25
BitsTypeResetNameDescription
5:0rw0x2OUT250: tie constantly to zero, 1: tie constantly to 1, 2: high-Z, >=3: peripheral outputs (i.e., add 3 to the native peripheral pad index). for OUT25
29:6for OUT26..OUT29


PINMUX.MIO_OUTSEL6 @ + 0x38
Mux select for MIO outputs.
Reset default = 0x82, mask 0xfff
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  OUT31 OUT30
BitsTypeResetNameDescription
5:0rw0x2OUT300: tie constantly to zero, 1: tie constantly to 1, 2: high-Z, >=3: peripheral outputs (i.e., add 3 to the native peripheral pad index). for OUT30
11:6for OUT31


PINMUX.MIO_OUT_SLEEP_VAL0 @ + 0x3c
Defines sleep behavior of muxed output or inout. Note that the MIO output will only switch into sleep mode if the the corresponding MIO_OUTSEL is either set to 0-2, or if MIO_OUTSEL selects a peripheral output that can go into sleep. If an always on peripheral is selected with MIO_OUTSEL, the MIO_OUT_SLEEP_VAL configuration has no effect.
Reset default = 0xaaaaaaaa, mask 0xffffffff
Register enable = REGEN
31302928272625242322212019181716
OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8
1514131211109876543210
OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0
BitsTypeResetNameDescription
1:0rw0x2OUT0Value to drive in deep sleep. for OUT0
0Tie-LowThe pin is driven actively to zero in deep sleep mode.
1Tie-HighThe pin is driven actively to one in deep sleep mode.
2High-ZThe pin is left undriven in deep sleep mode. Note that the actual driving behavior during deep sleep will then depend on the pull-up/-down configuration of padctrl.
3KeepKeep last driven value (including high-Z).
31:2for OUT1..OUT15


PINMUX.MIO_OUT_SLEEP_VAL1 @ + 0x40
Defines sleep behavior of muxed output or inout. Note that the MIO output will only switch into sleep mode if the the corresponding MIO_OUTSEL is either set to 0-2, or if MIO_OUTSEL selects a peripheral output that can go into sleep. If an always on peripheral is selected with MIO_OUTSEL, the MIO_OUT_SLEEP_VAL configuration has no effect.
Reset default = 0xaaaaaaaa, mask 0xffffffff
Register enable = REGEN
31302928272625242322212019181716
OUT31 OUT30 OUT29 OUT28 OUT27 OUT26 OUT25 OUT24
1514131211109876543210
OUT23 OUT22 OUT21 OUT20 OUT19 OUT18 OUT17 OUT16
BitsTypeResetNameDescription
1:0rw0x2OUT16Value to drive in deep sleep. for OUT16
0Tie-LowThe pin is driven actively to zero in deep sleep mode.
1Tie-HighThe pin is driven actively to one in deep sleep mode.
2High-ZThe pin is left undriven in deep sleep mode. Note that the actual driving behavior during deep sleep will then depend on the pull-up/-down configuration of padctrl.
3KeepKeep last driven value (including high-Z).
31:2for OUT17..OUT31


PINMUX.DIO_OUT_SLEEP_VAL @ + 0x44
Defines sleep behavior of dedicated output or inout. Note this register has WARL behavior since the sleep value settings are meaningless for always-on and input-only DIOs. For these DIOs, this register always reads 0.
Reset default = 0x2aaaaaaa, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8
1514131211109876543210
OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0
BitsTypeResetNameDescription
1:0rw0x2OUT0Value to drive in deep sleep. for OUT0
0Tie-LowThe pin is driven actively to zero in deep sleep mode.
1Tie-HighThe pin is driven actively to one in deep sleep mode.
2High-ZThe pin is left undriven in deep sleep mode. Note that the actual driving behavior during deep sleep will then depend on the pull-up/-down configuration of padctrl.
3KeepKeep last driven value (including high-Z).
29:2for OUT1..OUT14


PINMUX.WKUP_DETECTOR_EN @ + 0x48
Enables for the wakeup detectors.
Reset default = 0x0, mask 0xff
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
BitsTypeResetNameDescription
0:0rw0x0EN0Setting this bit activates the corresponding wakeup detector. The behavior is as specified in WKUP_DETECTOR, WKUP_DETECTOR_CNT_TH and WKUP_DETECTOR_PADSEL. for DETECTOR0
7:1for DETECTOR1..DETECTOR7


PINMUX.WKUP_DETECTOR0 @ + 0x4c
Configuration of wakeup condition detectors.
Reset default = 0x0, mask 0x1f
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  MIODIO0 FILTER0 MODE0
BitsTypeResetNameDescription
2:0rw0x0MODE0Wakeup detection mode. for DETECTOR0
0DisabledPin wakeup detector is disabled.
1NegedgeTrigger a wakeup request when observing a negative edge.
2PosedgeTrigger a wakeup request when observing a positive edge.
3EdgeTrigger a wakeup request when observing an edge in any direction.
4TimedLowTrigger a wakeup request when pin is driven LOW for a certain amount of always-on clock cycles as configured in WKUP_DETECTOR_CNT_TH.
5TimedHighTrigger a wakeup request when pin is driven HIGH for a certain amount of always-on clock cycles as configured in WKUP_DETECTOR_CNT_TH.
Other values are reserved.
3rw0x0FILTER00: signal filter disabled, 1: signal filter enabled. the signal must be stable for 4 always-on clock cycles before the value is being forwarded. can be used for debouncing. for DETECTOR0
4rw0x0MIODIO00: select index WKUP_DETECTOR_PADSEL from MIO pads, 1: select index WKUP_DETECTOR_PADSEL from DIO pads. for DETECTOR0


PINMUX.WKUP_DETECTOR1 @ + 0x50
Configuration of wakeup condition detectors.
Reset default = 0x0, mask 0x1f
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  MIODIO1 FILTER1 MODE1
BitsTypeResetNameDescription
2:0rw0x0MODE1Wakeup detection mode. for DETECTOR1
0DisabledPin wakeup detector is disabled.
1NegedgeTrigger a wakeup request when observing a negative edge.
2PosedgeTrigger a wakeup request when observing a positive edge.
3EdgeTrigger a wakeup request when observing an edge in any direction.
4TimedLowTrigger a wakeup request when pin is driven LOW for a certain amount of always-on clock cycles as configured in WKUP_DETECTOR_CNT_TH.
5TimedHighTrigger a wakeup request when pin is driven HIGH for a certain amount of always-on clock cycles as configured in WKUP_DETECTOR_CNT_TH.
Other values are reserved.
3rw0x0FILTER10: signal filter disabled, 1: signal filter enabled. the signal must be stable for 4 always-on clock cycles before the value is being forwarded. can be used for debouncing. for DETECTOR1
4rw0x0MIODIO10: select index WKUP_DETECTOR_PADSEL from MIO pads, 1: select index WKUP_DETECTOR_PADSEL from DIO pads. for DETECTOR1


PINMUX.WKUP_DETECTOR2 @ + 0x54
Configuration of wakeup condition detectors.
Reset default = 0x0, mask 0x1f
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  MIODIO2 FILTER2 MODE2
BitsTypeResetNameDescription
2:0rw0x0MODE2Wakeup detection mode. for DETECTOR2
0DisabledPin wakeup detector is disabled.
1NegedgeTrigger a wakeup request when observing a negative edge.
2PosedgeTrigger a wakeup request when observing a positive edge.
3EdgeTrigger a wakeup request when observing an edge in any direction.
4TimedLowTrigger a wakeup request when pin is driven LOW for a certain amount of always-on clock cycles as configured in WKUP_DETECTOR_CNT_TH.
5TimedHighTrigger a wakeup request when pin is driven HIGH for a certain amount of always-on clock cycles as configured in WKUP_DETECTOR_CNT_TH.
Other values are reserved.
3rw0x0FILTER20: signal filter disabled, 1: signal filter enabled. the signal must be stable for 4 always-on clock cycles before the value is being forwarded. can be used for debouncing. for DETECTOR2
4rw0x0MIODIO20: select index WKUP_DETECTOR_PADSEL from MIO pads, 1: select index WKUP_DETECTOR_PADSEL from DIO pads. for DETECTOR2


PINMUX.WKUP_DETECTOR3 @ + 0x58
Configuration of wakeup condition detectors.
Reset default = 0x0, mask 0x1f
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  MIODIO3 FILTER3 MODE3
BitsTypeResetNameDescription
2:0rw0x0MODE3Wakeup detection mode. for DETECTOR3
0DisabledPin wakeup detector is disabled.
1NegedgeTrigger a wakeup request when observing a negative edge.
2PosedgeTrigger a wakeup request when observing a positive edge.
3EdgeTrigger a wakeup request when observing an edge in any direction.
4TimedLowTrigger a wakeup request when pin is driven LOW for a certain amount of always-on clock cycles as configured in WKUP_DETECTOR_CNT_TH.
5TimedHighTrigger a wakeup request when pin is driven HIGH for a certain amount of always-on clock cycles as configured in WKUP_DETECTOR_CNT_TH.
Other values are reserved.
3rw0x0FILTER30: signal filter disabled, 1: signal filter enabled. the signal must be stable for 4 always-on clock cycles before the value is being forwarded. can be used for debouncing. for DETECTOR3
4rw0x0MIODIO30: select index WKUP_DETECTOR_PADSEL from MIO pads, 1: select index WKUP_DETECTOR_PADSEL from DIO pads. for DETECTOR3


PINMUX.WKUP_DETECTOR4 @ + 0x5c
Configuration of wakeup condition detectors.
Reset default = 0x0, mask 0x1f
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  MIODIO4 FILTER4 MODE4
BitsTypeResetNameDescription
2:0rw0x0MODE4Wakeup detection mode. for DETECTOR4
0DisabledPin wakeup detector is disabled.
1NegedgeTrigger a wakeup request when observing a negative edge.
2PosedgeTrigger a wakeup request when observing a positive edge.
3EdgeTrigger a wakeup request when observing an edge in any direction.
4TimedLowTrigger a wakeup request when pin is driven LOW for a certain amount of always-on clock cycles as configured in WKUP_DETECTOR_CNT_TH.
5TimedHighTrigger a wakeup request when pin is driven HIGH for a certain amount of always-on clock cycles as configured in WKUP_DETECTOR_CNT_TH.
Other values are reserved.
3rw0x0FILTER40: signal filter disabled, 1: signal filter enabled. the signal must be stable for 4 always-on clock cycles before the value is being forwarded. can be used for debouncing. for DETECTOR4
4rw0x0MIODIO40: select index WKUP_DETECTOR_PADSEL from MIO pads, 1: select index WKUP_DETECTOR_PADSEL from DIO pads. for DETECTOR4


PINMUX.WKUP_DETECTOR5 @ + 0x60
Configuration of wakeup condition detectors.
Reset default = 0x0, mask 0x1f
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  MIODIO5 FILTER5 MODE5
BitsTypeResetNameDescription
2:0rw0x0MODE5Wakeup detection mode. for DETECTOR5
0DisabledPin wakeup detector is disabled.
1NegedgeTrigger a wakeup request when observing a negative edge.
2PosedgeTrigger a wakeup request when observing a positive edge.
3EdgeTrigger a wakeup request when observing an edge in any direction.
4TimedLowTrigger a wakeup request when pin is driven LOW for a certain amount of always-on clock cycles as configured in WKUP_DETECTOR_CNT_TH.
5TimedHighTrigger a wakeup request when pin is driven HIGH for a certain amount of always-on clock cycles as configured in WKUP_DETECTOR_CNT_TH.
Other values are reserved.
3rw0x0FILTER50: signal filter disabled, 1: signal filter enabled. the signal must be stable for 4 always-on clock cycles before the value is being forwarded. can be used for debouncing. for DETECTOR5
4rw0x0MIODIO50: select index WKUP_DETECTOR_PADSEL from MIO pads, 1: select index WKUP_DETECTOR_PADSEL from DIO pads. for DETECTOR5


PINMUX.WKUP_DETECTOR6 @ + 0x64
Configuration of wakeup condition detectors.
Reset default = 0x0, mask 0x1f
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  MIODIO6 FILTER6 MODE6
BitsTypeResetNameDescription
2:0rw0x0MODE6Wakeup detection mode. for DETECTOR6
0DisabledPin wakeup detector is disabled.
1NegedgeTrigger a wakeup request when observing a negative edge.
2PosedgeTrigger a wakeup request when observing a positive edge.
3EdgeTrigger a wakeup request when observing an edge in any direction.
4TimedLowTrigger a wakeup request when pin is driven LOW for a certain amount of always-on clock cycles as configured in WKUP_DETECTOR_CNT_TH.
5TimedHighTrigger a wakeup request when pin is driven HIGH for a certain amount of always-on clock cycles as configured in WKUP_DETECTOR_CNT_TH.
Other values are reserved.
3rw0x0FILTER60: signal filter disabled, 1: signal filter enabled. the signal must be stable for 4 always-on clock cycles before the value is being forwarded. can be used for debouncing. for DETECTOR6
4rw0x0MIODIO60: select index WKUP_DETECTOR_PADSEL from MIO pads, 1: select index WKUP_DETECTOR_PADSEL from DIO pads. for DETECTOR6


PINMUX.WKUP_DETECTOR7 @ + 0x68
Configuration of wakeup condition detectors.
Reset default = 0x0, mask 0x1f
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  MIODIO7 FILTER7 MODE7
BitsTypeResetNameDescription
2:0rw0x0MODE7Wakeup detection mode. for DETECTOR7
0DisabledPin wakeup detector is disabled.
1NegedgeTrigger a wakeup request when observing a negative edge.
2PosedgeTrigger a wakeup request when observing a positive edge.
3EdgeTrigger a wakeup request when observing an edge in any direction.
4TimedLowTrigger a wakeup request when pin is driven LOW for a certain amount of always-on clock cycles as configured in WKUP_DETECTOR_CNT_TH.
5TimedHighTrigger a wakeup request when pin is driven HIGH for a certain amount of always-on clock cycles as configured in WKUP_DETECTOR_CNT_TH.
Other values are reserved.
3rw0x0FILTER70: signal filter disabled, 1: signal filter enabled. the signal must be stable for 4 always-on clock cycles before the value is being forwarded. can be used for debouncing. for DETECTOR7
4rw0x0MIODIO70: select index WKUP_DETECTOR_PADSEL from MIO pads, 1: select index WKUP_DETECTOR_PADSEL from DIO pads. for DETECTOR7


PINMUX.WKUP_DETECTOR_CNT_TH0 @ + 0x6c
Counter thresholds for wakeup condition detectors.
Reset default = 0x0, mask 0xffffffff
Register enable = REGEN
31302928272625242322212019181716
TH3 TH2
1514131211109876543210
TH1 TH0
BitsTypeResetNameDescription
7:0rw0x0TH0Counter threshold for TimedLow and TimedHigh wakeup detector modes (see WKUP_DETECTOR). The threshold is in terms of always-on clock cycles. for DETECTOR0
31:8for DETECTOR1..DETECTOR3


PINMUX.WKUP_DETECTOR_CNT_TH1 @ + 0x70
Counter thresholds for wakeup condition detectors.
Reset default = 0x0, mask 0xffffffff
Register enable = REGEN
31302928272625242322212019181716
TH7 TH6
1514131211109876543210
TH5 TH4
BitsTypeResetNameDescription
7:0rw0x0TH4Counter threshold for TimedLow and TimedHigh wakeup detector modes (see WKUP_DETECTOR). The threshold is in terms of always-on clock cycles. for DETECTOR4
31:8for DETECTOR5..DETECTOR7


PINMUX.WKUP_DETECTOR_PADSEL0 @ + 0x74
Pad selects for pad wakeup condition detectors.
Reset default = 0x0, mask 0x3fffffff
Register enable = REGEN
31302928272625242322212019181716
  SEL5 SEL4 SEL3...
1514131211109876543210
...SEL3 SEL2 SEL1 SEL0
BitsTypeResetNameDescription
4:0rw0x0SEL0Selects a specific MIO or DIO pad (depending on WKUP_DETECTOR configuration). In case of MIO, the pad select index is the same as used for PERIPH_INSEL, meaning that index 0 and 1 just select constant 0, and the MIO pads live at indices >= 2. In case of DIO pads, the pad select index corresponds 1:1 to the DIO pad to be selected. for DETECTOR0
29:5for DETECTOR1..DETECTOR5


PINMUX.WKUP_DETECTOR_PADSEL1 @ + 0x78
Pad selects for pad wakeup condition detectors.
Reset default = 0x0, mask 0x3ff
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  SEL7 SEL6
BitsTypeResetNameDescription
4:0rw0x0SEL6Selects a specific MIO or DIO pad (depending on WKUP_DETECTOR configuration). In case of MIO, the pad select index is the same as used for PERIPH_INSEL, meaning that index 0 and 1 just select constant 0, and the MIO pads live at indices >= 2. In case of DIO pads, the pad select index corresponds 1:1 to the DIO pad to be selected. for DETECTOR6
9:5for DETECTOR7


PINMUX.WKUP_CAUSE @ + 0x7c
Cause registers for wakeup detectors.
Reset default = 0x0, mask 0xff
Register enable = REGEN
31302928272625242322212019181716
 
1514131211109876543210
  CAUSE7 CAUSE6 CAUSE5 CAUSE4 CAUSE3 CAUSE2 CAUSE1 CAUSE0
BitsTypeResetNameDescription
0rw0c0x0CAUSE0Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear. for DETECTOR0
7:1for DETECTOR1..DETECTOR7