Pinmux Technical Specification

Overview

This document specifies the functionality of the pin multiplexer (pinmux) peripheral. This module conforms to the OpenTitan guideline for peripheral device functionality. See that document for integration overview within the broader OpenTitan top level system. The module provides a mechanism to reconfigure the peripheral-to-pin mapping at runtime, which greatly enhances the system flexibility. In addition to that, the pinmux also allows the user to control pad attributes (such as pull-up, pull-down, open-drain, drive-strength, keeper and inversion), and it contains features that facilitate low-power modes of the system. For example, the deep sleep behavior of each pad can programmed individually, and the module contains additional pattern detectors that can listen on any IO and wake up the system if a specific pattern has been detected.

Features

  • Configurable number of chip bidirectional IOs

  • Configurable number of peripheral inputs and outputs

  • Programmable mapping from peripheral outputs (and output enables) to top-level outputs (and output enables)

  • Programmable mapping from top-level inputs to peripheral inputs

  • Programmable control of chip pad attributes like output drive-strength, pull-up, pull-down and virtual open-drain

  • Programmable pattern detectors to detect wakeup conditions during sleep mode

  • Programmable sleep mode behavior

  • Support for life-cycle-based JTAG (TAP) isolation and muxing

Theory of Operations

Block Diagram and Overview

The pinmux peripheral is a programmable module designed to wire arbitrary peripheral inputs and outputs to arbitrary multiplexable chip bidirectional pins. It gives much flexibility at the top level of the device, allowing most data pins to be flexibly wired and controlled by many peripherals. Even though the pinmux is referred to as one IP, it is logically split into two modules that are instantiated on the top-level and the chip-level, respectively, as can be seen in the block diagram below. The top-level module pinmux contains the CSRs accessible via the TL-UL interface, the main muxing matrix, retention registers, a set of programmable wakeup detectors, and the HW strap sampling and TAP / JTAG muxing logic. The chip-level module padring instantiates the bidirectional pads and connects the physical pad attributes.

Pinmux Block Diagram

MIO and DIO Signal Categories

The pinmux supports two different IO signal categories: Muxed IO (MIO) signals that are routed through the pinmux matrix, and dedicated IO (DIO) signals that bypass the pinmux matrix. This distinction is useful for accommodating IO signals that are timing critical or that must have a fixed IO mapping for another reason. Note that although DIO signals are not routed through the pinmux matrix, they are still connected to the retention logic and the wakeup detectors (see next section below).

The number of available peripheral IOs, pads, and their assignment to the MIO / DIO categories is done at design time as part of the top-level configuration. This configurability is achieved by representing inputs / outputs as packed arrays, in combination with the SystemVerilog parameters NPeriphIn, NPeriphOut, NMioPads and NDioPads. Note however that the register file is also affected by this configuration and needs to be regenerated for each design instance.

It is assumed that all available pins that the pinmux connects to are bidirectional, controlled by logic within this module. By default, all muxed peripheral inputs are tied to zero. Further, all output enables are set to zero, which essentially causes all pads to be in high-Z state after reset. In addition to wiring programmability, each muxed peripheral input can be set constantly to 0 or 1, and each muxed chip output can be set constantly to 0, 1 or high-Z.

See the muxing matrix section for more details about the mux implementation.

Retention and Wakeup Features

The retention logic allows SW to specify a certain behavior during deep sleep for each muxed and dedicated output. Legal behaviors are tie low, tie high, high-Z, keeping the previous state, or driving the current value (useful for peripherals that are always on).

The wakeup detectors can detect patterns such as rising / falling edges and pulses of a certain width up to 255 AON clock cycles. Each wakeup detector can listen on any one of the MIO / DIO signals that are routed through the pinmux, and if a pattern is detected, the power manager is informed of that event via a wakeup request.

The pinmux module itself is in the always-on (AON) power domain, and as such does not loose configuration state when a deep sleep power cycle is performed. However, only the wakeup detector logic will be actively clocked during deep sleep in order to save power.

See the retention logic and wakeup detectors sections for more details about the mux implementation.

Test and Debug Access

The hardware strap sampling and TAP isolation logic provides test and debug access to the chip during specific life cycle states. This mechanism is explained in more detail in the strap sampling and TAP isolation section.

Pad Attributes

Additional pad-specific features such as inversion, pull-up, pull-down, virtual open-drain, drive-strength and input/output inversion etc. can be exercise via the pad attribute CSRs. The pinmux module supports a comprehensive set of such pad attributes, but it is permissible that some of them may not be supported by the underlying pad implementation. For example, certain ASIC libraries may not provide open-drain outputs, and FPGAs typically do not allow all of these attributes to be programmed dynamically at runtime. See the generic pad wrapper section below for more details. Note that static pad attributes for FPGAs are currently not covered in this specification.

Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module PINMUX has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: clk_aon_i

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO: none

Interrupts: none

Security Alerts:

Alert NameDescription
fatal_fault

This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Parameters

The following table lists the main parameters used throughout the pinmux design. Note that the pinmux is generated based on the system configuration, and hence these parameters are placed into a package. The pinout and pinmux mappings are listed under TODO for specific top-level configurations.

Parameter Description
NPeriphOut Number of peripheral outputs.
NPeriphIn Number of peripheral input.
NMioPads Number of muxed bidirectional pads.
NDioPads Number of dedicated pads.

Signals

The table below lists the pinmux signals. The number of dedicated and muxed IOs is parametric, and hence the signals are stacked in packed arrays.

Signal Direction Type Description
aon_wkup_req_o output logic Wakeup request from wakeup detectors, to the power manager, running on the AON clock.
usb_wkup_req_o output logic Wakeup request from USB wakeup detector, going to the power manager, running on the AON clock.
sleep_en_i input logic Level signal that is asserted when the power manager enters deep sleep.
strap_en_i input logic This signal is pulsed high by the power manager after reset in order to sample the HW straps.
lc_dft_en_i input lc_ctrl_pkg::lc_tx_t Test enable qualifier coming from life cycle controller, used for HW strap qualification.
lc_hw_debug_en_i input lc_ctrl_pkg::lc_tx_t Debug enable qualifier coming from life cycle controller, used for HW strap qualification.
dft_strap_test_o output pinmux_pkg::dft_strap_test_req_t Sampled DFT strap values, going to the DFT TAP.
dft_hold_tap_sel_i output logic TAP selection hold indication, asserted by the DFT TAP during boundary scan.
lc_jtag_o output jtag_pkg::jtag_req_t Qualified JTAG signals for life cycle controller TAP.
lc_jtag_i input jtag_pkg::jtag_rsp_t Qualified JTAG signals for life cycle controller TAP.
rv_jtag_o output jtag_pkg::jtag_req_t Qualified JTAG signals for RISC-V processor TAP.
rv_jtag_i input jtag_pkg::jtag_rsp_t Qualified JTAG signals for RISC-V processor TAP.
dft_jtag_o output jtag_pkg::jtag_req_t Qualified JTAG signals for DFT TAP.
dft_jtag_i input jtag_pkg::jtag_rsp_t Qualified JTAG signals for DFT TAP.
usb_out_of_rst_i input logic Indicates whether the USB has come out of reset, coming from the USB device.
usb_aon_wake_en_i input logic Enables the USB wakeup feature, coming from the USB device.
usb_aon_wake_ack_i input logic Acknowledges the USB wakeup request, coming from the USB device.
usb_suspend_i input logic Indicates whether USB is in suspended state, coming from the USB device.
usb_state_debug_o output usbdev_pkg::awk_state_t Debug information about the wake state, going to the USB device.
periph_to_mio_i[NPeriphOut-1:0] input packed logic Signals from NPeriphOut muxed peripheral outputs coming into the pinmux.
periph_to_mio_oe_i[NPeriphOut-1:0] input packed logic Signals from NPeriphOut muxed peripheral output enables coming into the pinmux.
mio_to_periph_o[NPeriphIn-1:0] output packed logic Signals to NPeriphIn muxed peripherals coming from the pinmux.
periph_to_dio_i[NDioPads-1:0] input packed logic Signals from NDioPads dedicated peripheral outputs coming into the pinmux.
periph_to_dio_oe_i[NDioPads-1:0] input packed logic Signals from NDioPads dedicated peripheral output enables coming into the pinmux.
dio_to_periph_o[NDioPads-1:0] output packed logic Signals to NDioPads dedicated peripherals coming from the pinmux.
mio_attr_o[NMioPads-1:0] output prim_pad_wrapper_pkg::pad_attr_t Packed array containing the pad attributes of all muxed IOs.
mio_out_o[NMioPads-1:0] output packed logic Signals to NMioPads bidirectional muxed pads as output data.
mio_oe_o[NMioPads-1:0] output packed logic Signals to NMioPads bidirectional muxed pads as output enables.
mio_in_i[NMioPads-1:0] input packed logic Signals from NMioPads bidirectional muxed pads as input data.
dio_attr_o[NDioPads-1:0] output prim_pad_wrapper_pkg::pad_attr_t Packed array containing the pad attributes of all dedicated IOs.
dio_out_o[NDioPads-1:0] output packed logic Signals to NDioPads bidirectional dedicated pads as output data.
dio_oe_o[NDioPads-1:0] output packed logic Signals to NDioPads bidirectional dedicated pads as output enables.
dio_in_i[NDioPads-1:0] input packed logic Signals from NDioPads bidirectional dedicated pads as input data.

Muxing Matrix

The diagram below shows connectivity between four arbitrary chip pins, named MIO0 .. MIO3, and several muxed peripheral inputs and outputs. This shows the connectivity available in all directions, as well as the control registers described later in this document. Two example peripherals (uart and spidev) are attached to the pinmux in this example, one with one input and one output, the other with three inputs and one output. The diagram also shows the padring module which instantiates the bidirectional chip pads with output enable control.

Pinmux Block Diagram

Note that apart from selecting a specific input pad, the periph_insel[*] signals can also be used to tie the peripheral input to 0 or 1. Likewise, the output select signals mio_outsel[*] can also be used to constantly drive an output pin to 0/1 or to put it into high-Z state (default). The output enable and the associated data signal (i.e. periph_to_mio and periph_to_mio_oe) are indexed with the same select signal to allow the peripheral hardware to determine the pad direction instead of demoting that control to SW.

Retention Logic

As illustrated in the picture above, all muxing matrix and DIO outputs are routed through the retention logic, which essentially consists of a set of multiplexors and two retention registers per output (one register is for the output data and one for the output enable). This multiplexor can be configured to be automatically activated upon deep sleep entry in order to either drive the output low, high, high-Z or to the last seen value (keep). If no sleep behavior is specified, the retention logic will continue to drive out the value coming from the peripheral side, which can be useful for peripherals that reside in the AON domain.

The sleep behavior of all outputs is activated in parallel via a trigger signal asserted by the power manager. Once activated, it is the task of SW to disable the sleep behavior for each individual pin when waking up from deep sleep. This ensures that the output values remain stable until the system and its peripherals have been re-initialized.

Wakeup Detectors

The pinmux contains eight programmable wakeup detector modules that can listen on any of the MIO or DIO pins. Each detector contains a debounce filter and an 8bit counter running on the AON clock domain. The detectors can be programmed via the WKUP_DETECTOR_0 and WKUP_DETECTOR_CNT_TH_0 registers to detect the following patterns:

  • rising edge
  • falling edge
  • rising or falling edge
  • positive pulse up to 255 AON clock cycles in length
  • negative pulse up to 255 AON clock cycles in length

Note that for all patterns listed above, the input signal is sampled with the AON clock. This means that the input signal needs to remain stable for at least one AON clock cycle after a level change for the detector to recognize the event (depending on the debounce filter configuration, the signal needs to remain stable for multiple clock cycles).

If a pattern is detected, the wakeup detector will send a wakeup request to the power manager, and the cause bit corresponding to that detector will be set in the WKUP_CAUSE register.

Strap Sampling and TAP Isolation

The pinmux contains a set of dedicated HW “straps”, which are essentially signals that are multiplexed onto fixed MIO pad locations. Depending on the life cycle state, these straps are either continuously sampled, or latched right after POR.

There are two groups of HW straps:

  1. Three DFT straps that determine the DFT mode. These bits are output via the dft_strap_test_o signal such that they can be routed to the tool-inserted DFT controller.
  2. Two TAP selection straps for determining which TAP should be multiplexed onto the JTAG IOs.

The conditions under which these two strap groups are sampled are listed in the tables below. Note that the HW straps can be used just like regular GPIOs once they have been sampled.

Strap Group \ Life Cycle State TEST_UNLOCKED* RMA DEV All Other States
DFT straps Once at boot Once at boot - -
TAP strap 0 Continuously Continuously Once at boot Once at boot
TAP strap 1 Continuously Continuously Once at boot -

Once at boot: Sampled once after life cycle initialization (sampling event is initiated by pwrmgr).

Continously: Sampled continuously after life cycle initialization.

The TAP muxing logic is further qualified by the life cycle state in order to isolate the TAPs in certain life cycle states. The following table lists the TAP strap encoding and the life cycle states in which the associated TAPs can be selected and accessed.

TAP strap 1 TAP strap 0 Life Cycle State Selected TAP
0 0 All states -
0 1 All states Life Cycle
1 0 TEST_UNLOCKED*, RMA, DEV RISC-V
1 1 TEST_UNLOCKED*, RMA DFT

Note that the tool-inserted DFT controller may assert the dft_hold_tap_sel_i during a test (e.g. boundary scan) in which case the pinmux will temporarily pause sampling of the TAP selection straps.

For more information about the life cycle states, see Life Cycle Controller Specification and the Life Cycle Definition Table.

Generic Pad Wrapper

The generic pad wrapper is intended to abstract away implementation differences between the target technologies by providing a generic interface that is compatible with the padring module. It is the task of the RTL build flow to select the appropriate pad wrapper implementation.

A specific implementation of a pad wrapper may choose to instantiate a technology primitive (as it is common in ASIC flows), or it may choose to model the functionality behaviorally such that it can be inferred by the technology mapping tool (e.g., in the case of an FPGA target). It is permissible to omit the implementation of all IO attributes except input/output inversion.

The generic pad wrapper must expose the following IOs and parameters, even if they are not connected internally. In particular, the pad attribute struct attr_i must contain all fields listed below, even if not all attributes are supported (it is permissible to just leave them unconnected in the pad wrapper implementation).

Parameter Default Description
PadType BidirStd Pad variant to be instantiated (technology-specific)
ScanRole NoScan Scan role, can be NoScan, ScanIn or ScanOut

Note that PadType is a technology-specific parameter. The generic pad wrapper only implements variant BidirStd, but for other target technologies, this parameter can be used to select among a variety of different pad flavors.

The ScanRole parameter determines the behavior when scanmode is enabled. Depending on whether a given pad acts as a scan input or output, certain pad attributes and functionalities need to be bypassed. This parameter is typically only relevant for ASIC targets and therefore not modeled in the generic pad model.

Also note that the pad wrapper may implement a “virtual” open-drain termination, where standard bidirectional pads are employed, but instead of driving the output high for a logic 1 the pad is put into tristate mode.

Signal Direction Type Description
clk_scan_i input logic Scan clock of the pad
scanmode_i input logic Scan mode enable of the pad
pok_i input pad_pok_t Technology-specific power sequencing signals
inout_io inout wire Bidirectional inout of the pad
in_o output logic Input data signal
in_raw_o output logic Un-inverted input data signal
out_i input logic Output data signal
oe_i input logic Output data enable
attr_i[0] input logic Input/output inversion
attr_i[1] input logic Virtual open-drain enable
attr_i[2] input logic Pull enable
attr_i[3] input logic Pull select (0: pull-down, 1: pull-up)
attr_i[4] input logic Keeper enable
attr_i[5] input logic Schmitt trigger enable
attr_i[6] input logic Open drain enable enable
attr_i[8:7] input logic Slew rate (0x0: slowest, 0x3: fastest)
attr_i[12:9] input logic Drive strength (0x0: weakest, 0xf: strongest)

Note that the corresponding pad attribute registers MIO_PAD_ATTR_0 and DIO_PAD_ATTR_0 have “writes-any-reads-legal” (WARL) behavior (see also pad attributes).

Programmers Guide

Pad Attributes

Software should determine and program the pad attributes at startup, or reprogram the attributes when the functionality requirements change at runtime.

This can be achieved by writing to the MIO_PAD_ATTR_0 and DIO_PAD_ATTR_0 registers. Note that the IO attributes should be configured before enabling muxed IOs going through the pinmux matrix in order to avoid undesired electrical behavior and/or contention at the pads.

The pad attributes configuration can be locked down individually for each pad via the MIO_PAD_ATTR_REGWEN_0 and DIO_PAD_ATTR_REGWEN_0 registers. The configuration can then not be altered anymore until the next system reset.

The following pad attributes are supported by this register layout by default:

ATTR Bits Description Access
0 Input/output inversion RW
1 Open drain enable RW
2 Pull enable WARL
3 Pull select (0: down, 1: up) WARL
4 Keeper enable WARL
5 Schmitt trigger enable WARL
6 Open drain enable enable WARL
8:7 Slew rate (0x0: slowest, 0x3: fastest) WARL
12:9 Drive strength (0x0: weakest, 0xf: strongest) WARL

Since some of the pad attributes may not be implemented, SW can probe this capability by writing the CSRs and read them back to determine whether the value was legal. This behavior is also referred to as “writes-any-reads-legal” or “WARL” in the RISC-V world. For example, certain pads may only support two drive-strength bits, instead of four. The unsupported drive-strength bits in the corresponding CSRs would then always read as zero, even if SW attempts to set them to 1.

Pinmux Configuration

Upon POR, the pinmux state is such that all MIO outputs are high-Z, and all MIO peripheral inputs are tied off to 0. Software should determine and program the pinmux mapping at startup, or reprogram it when the functionality requirements change at runtime. This can be achieved by writing the following values to the PERIPH_INSEL_0 and MIO_OUTSEL_0 registers.

periph_insel Value Selected Input Signal
0 Constant zero (default)
1 Constant one
2 + k Corresponding MIO input signal at index k

The global default at reset is 0, but the default of individual signals can be overridden at design time, if needed.

mio_outsel Value Selected Output signal
0 Constant zero (default)
1 Constant one
2 High-Z
3 + k Corresponding peripheral output signal at index k

The global default at reset is 2, but the default of individual signals can be overridden at design time, if needed.

Note that the pinmux configuration should be sequenced after any IO attribute-specific configuration in the MIO_PAD_ATTR_0 and DIO_PAD_ATTR_0 registers to avoid any unwanted electric behavior and/or contention. If needed, each select signal can be individually locked down via MIO_PERIPH_INSEL_REGWEN_0 or MIO_OUTSEL_REGWEN_0. The configuration can then not be altered anymore until the next system reset.

Deep Sleep Features

The deep sleep behavior of each individual MIO or DIO can be defined via the (MIO_PAD_SLEEP_EN_0, DIO_PAD_SLEEP_EN_0, MIO_PAD_SLEEP_MODE_0 and DIO_PAD_SLEEP_MODE_0) registers. Available sleep behaviors are:

dio/mio_pad_sleep_en Value dio/mio_pad_sleep_mode Value Sleep Behavior
0 - Drive (default)
1 0 Tie-low
1 1 Tie-high
1 2 High-Z
1 3 Keep last value

Note that if the behavior is set to “Drive”, the sleep mode will not be activated upon deep sleep entry. Rather, the retention logic continues to drive the value coming from the peripheral side. Also note that the sleep logic is located after the pinmux matrix, hence the sleep configuration is per MIO pad and not per MIO peripheral.

Before sleep entry, SW should configure the appropriate sleep behavior of all MIOs/DIOs via MIO_PAD_SLEEP_MODE_0, DIO_PAD_SLEEP_MODE_0. This configuration can be optionally locked down, in which case it cannot be modified again until POR. The configured behavior is then activated for all pads that have sleep mode set to enabled (MIO_PAD_SLEEP_EN_0 and DIO_PAD_SLEEP_EN_0) at once by the power manager during the sleep entry sequence.

When exiting sleep, the task of disabling the sleep behavior is however up to SW. I.e., it must clear the per-pad sleep status bits in registers MIO_PAD_SLEEP_STATUS_0 and DIO_PAD_SLEEP_STATUS_0 that have been set upon sleep entry. The rationale for this is that it may not be desirable to disable sleep behavior on all pads at once due to some additional book keeping / re-initialization that needs to be performed while exiting sleep.

Wakeup Features

The pinmux contains eight wakeup detectors. These detectors can be individually enabled and disabled regardless of the sleep state. This ensures that SW can set them up before and disable them after sleep in order to ensure that no events are missed during sleep entry and exit.

For more information on the patterns supported by the wakeup detectors, see wakeup detectors.

A typical programming sequence for the wakeup detectors looks as follows:

  1. Before initiating any sleep mode, SW should configure the wakeup detectors appropriately and enable them via the WKUP_DETECTOR_0, WKUP_DETECTOR_CNT_TH_0 and WKUP_DETECTOR_PADSEL_0 registers.

  2. Optionally, lock the wakeup detector configuration via the WKUP_DETECTOR_REGWEN_0 registers.

  3. During sleep, the wakeup detectors will trigger a wakep request if a matching pattern has been observed. A bit corresponding to the wakeup detector that has observed the pattern will be set in the WKUP_CAUSE register.

  4. When exiting sleep, SW should read the wake info register in the power manager to determine the reason(s) for the wakeup request.

  5. If the wakeup request was due to a pin wakeup pattern detector, SW should inspect the WKUP_CAUSE registers in order to determine the exact cause.

  6. SW should in any case disable the wakeup detectors and clear the WKUP_CAUSE registers once it is safe to do so (in order to not miss any events). Note that the WKUP_CAUSE registers reside in the slow AON clock domain, and hence clearing them takes a few uS to take effect. If needed, a SW readback can be performed to ensure that the clear operation has completed successfully.

Pinout and Pinmux Mapping

The tables below summarize the pinout and pinmux connectivity for certain top-level designs.

Top Earlgrey

Target Name #IO Banks #Muxed Pads #Direct Pads #Manual Pads #Total Pads Pinout / Pinmux Tables
ASIC 4 47 14 9 70 Pinout Table
CW310 4 29 4 18 51 Pinout Table
NEXYSVIDEO 4 29 4 16 49 Pinout Table

Register Table

The register description below matches the instance in the Earl Grey top level design.

Similar register descriptions can be generated with different parameterizations.

PINMUX.ALERT_TEST @ 0x0

Alert Test Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
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  fatal_fault
BitsTypeResetNameDescription
0wo0x0fatal_fault

Write 1 to trigger one alert event of this kind.


PINMUX.MIO_PERIPH_INSEL_REGWEN_0 @ 0x4

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
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  EN_0
BitsTypeResetNameDescription
0rw0c0x1EN_0

Register write enable bit. If this is cleared to 0, the corresponding MIO_PERIPH_INSEL is not writable anymore.


PINMUX.MIO_PERIPH_INSEL_REGWEN_1 @ 0x8

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  EN_1
BitsTypeResetNameDescription
0rw0c0x1EN_1

For MIO_PERIPH_INSEL1


PINMUX.MIO_PERIPH_INSEL_REGWEN_2 @ 0xc

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  EN_2
BitsTypeResetNameDescription
0rw0c0x1EN_2

For MIO_PERIPH_INSEL2


PINMUX.MIO_PERIPH_INSEL_REGWEN_3 @ 0x10

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  EN_3
BitsTypeResetNameDescription
0rw0c0x1EN_3

For MIO_PERIPH_INSEL3


PINMUX.MIO_PERIPH_INSEL_REGWEN_4 @ 0x14

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  EN_4
BitsTypeResetNameDescription
0rw0c0x1EN_4

For MIO_PERIPH_INSEL4


PINMUX.MIO_PERIPH_INSEL_REGWEN_5 @ 0x18

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  EN_5
BitsTypeResetNameDescription
0rw0c0x1EN_5

For MIO_PERIPH_INSEL5


PINMUX.MIO_PERIPH_INSEL_REGWEN_6 @ 0x1c

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  EN_6
BitsTypeResetNameDescription
0rw0c0x1EN_6

For MIO_PERIPH_INSEL6


PINMUX.MIO_PERIPH_INSEL_REGWEN_7 @ 0x20

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  EN_7
BitsTypeResetNameDescription
0rw0c0x1EN_7

For MIO_PERIPH_INSEL7


PINMUX.MIO_PERIPH_INSEL_REGWEN_8 @ 0x24

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  EN_8
BitsTypeResetNameDescription
0rw0c0x1EN_8

For MIO_PERIPH_INSEL8


PINMUX.MIO_PERIPH_INSEL_REGWEN_9 @ 0x28

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  EN_9
BitsTypeResetNameDescription
0rw0c0x1EN_9

For MIO_PERIPH_INSEL9


PINMUX.MIO_PERIPH_INSEL_REGWEN_10 @ 0x2c

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  EN_10
BitsTypeResetNameDescription
0rw0c0x1EN_10

For MIO_PERIPH_INSEL10


PINMUX.MIO_PERIPH_INSEL_REGWEN_11 @ 0x30

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  EN_11
BitsTypeResetNameDescription
0rw0c0x1EN_11

For MIO_PERIPH_INSEL11


PINMUX.MIO_PERIPH_INSEL_REGWEN_12 @ 0x34

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_12
BitsTypeResetNameDescription
0rw0c0x1EN_12

For MIO_PERIPH_INSEL12


PINMUX.MIO_PERIPH_INSEL_REGWEN_13 @ 0x38

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  EN_13
BitsTypeResetNameDescription
0rw0c0x1EN_13

For MIO_PERIPH_INSEL13


PINMUX.MIO_PERIPH_INSEL_REGWEN_14 @ 0x3c

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_14
BitsTypeResetNameDescription
0rw0c0x1EN_14

For MIO_PERIPH_INSEL14


PINMUX.MIO_PERIPH_INSEL_REGWEN_15 @ 0x40

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_15
BitsTypeResetNameDescription
0rw0c0x1EN_15

For MIO_PERIPH_INSEL15


PINMUX.MIO_PERIPH_INSEL_REGWEN_16 @ 0x44

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_16
BitsTypeResetNameDescription
0rw0c0x1EN_16

For MIO_PERIPH_INSEL16


PINMUX.MIO_PERIPH_INSEL_REGWEN_17 @ 0x48

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_17
BitsTypeResetNameDescription
0rw0c0x1EN_17

For MIO_PERIPH_INSEL17


PINMUX.MIO_PERIPH_INSEL_REGWEN_18 @ 0x4c

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_18
BitsTypeResetNameDescription
0rw0c0x1EN_18

For MIO_PERIPH_INSEL18


PINMUX.MIO_PERIPH_INSEL_REGWEN_19 @ 0x50

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_19
BitsTypeResetNameDescription
0rw0c0x1EN_19

For MIO_PERIPH_INSEL19


PINMUX.MIO_PERIPH_INSEL_REGWEN_20 @ 0x54

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_20
BitsTypeResetNameDescription
0rw0c0x1EN_20

For MIO_PERIPH_INSEL20


PINMUX.MIO_PERIPH_INSEL_REGWEN_21 @ 0x58

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_21
BitsTypeResetNameDescription
0rw0c0x1EN_21

For MIO_PERIPH_INSEL21


PINMUX.MIO_PERIPH_INSEL_REGWEN_22 @ 0x5c

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_22
BitsTypeResetNameDescription
0rw0c0x1EN_22

For MIO_PERIPH_INSEL22


PINMUX.MIO_PERIPH_INSEL_REGWEN_23 @ 0x60

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_23
BitsTypeResetNameDescription
0rw0c0x1EN_23

For MIO_PERIPH_INSEL23


PINMUX.MIO_PERIPH_INSEL_REGWEN_24 @ 0x64

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_24
BitsTypeResetNameDescription
0rw0c0x1EN_24

For MIO_PERIPH_INSEL24


PINMUX.MIO_PERIPH_INSEL_REGWEN_25 @ 0x68

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_25
BitsTypeResetNameDescription
0rw0c0x1EN_25

For MIO_PERIPH_INSEL25


PINMUX.MIO_PERIPH_INSEL_REGWEN_26 @ 0x6c

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_26
BitsTypeResetNameDescription
0rw0c0x1EN_26

For MIO_PERIPH_INSEL26


PINMUX.MIO_PERIPH_INSEL_REGWEN_27 @ 0x70

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_27
BitsTypeResetNameDescription
0rw0c0x1EN_27

For MIO_PERIPH_INSEL27


PINMUX.MIO_PERIPH_INSEL_REGWEN_28 @ 0x74

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_28
BitsTypeResetNameDescription
0rw0c0x1EN_28

For MIO_PERIPH_INSEL28


PINMUX.MIO_PERIPH_INSEL_REGWEN_29 @ 0x78

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_29
BitsTypeResetNameDescription
0rw0c0x1EN_29

For MIO_PERIPH_INSEL29


PINMUX.MIO_PERIPH_INSEL_REGWEN_30 @ 0x7c

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_30
BitsTypeResetNameDescription
0rw0c0x1EN_30

For MIO_PERIPH_INSEL30


PINMUX.MIO_PERIPH_INSEL_REGWEN_31 @ 0x80

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_31
BitsTypeResetNameDescription
0rw0c0x1EN_31

For MIO_PERIPH_INSEL31


PINMUX.MIO_PERIPH_INSEL_REGWEN_32 @ 0x84

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_32
BitsTypeResetNameDescription
0rw0c0x1EN_32

For MIO_PERIPH_INSEL32


PINMUX.MIO_PERIPH_INSEL_REGWEN_33 @ 0x88

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_33
BitsTypeResetNameDescription
0rw0c0x1EN_33

For MIO_PERIPH_INSEL33


PINMUX.MIO_PERIPH_INSEL_REGWEN_34 @ 0x8c

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_34
BitsTypeResetNameDescription
0rw0c0x1EN_34

For MIO_PERIPH_INSEL34


PINMUX.MIO_PERIPH_INSEL_REGWEN_35 @ 0x90

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_35
BitsTypeResetNameDescription
0rw0c0x1EN_35

For MIO_PERIPH_INSEL35


PINMUX.MIO_PERIPH_INSEL_REGWEN_36 @ 0x94

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_36
BitsTypeResetNameDescription
0rw0c0x1EN_36

For MIO_PERIPH_INSEL36


PINMUX.MIO_PERIPH_INSEL_REGWEN_37 @ 0x98

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_37
BitsTypeResetNameDescription
0rw0c0x1EN_37

For MIO_PERIPH_INSEL37


PINMUX.MIO_PERIPH_INSEL_REGWEN_38 @ 0x9c

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_38
BitsTypeResetNameDescription
0rw0c0x1EN_38

For MIO_PERIPH_INSEL38


PINMUX.MIO_PERIPH_INSEL_REGWEN_39 @ 0xa0

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_39
BitsTypeResetNameDescription
0rw0c0x1EN_39

For MIO_PERIPH_INSEL39


PINMUX.MIO_PERIPH_INSEL_REGWEN_40 @ 0xa4

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_40
BitsTypeResetNameDescription
0rw0c0x1EN_40

For MIO_PERIPH_INSEL40


PINMUX.MIO_PERIPH_INSEL_REGWEN_41 @ 0xa8

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_41
BitsTypeResetNameDescription
0rw0c0x1EN_41

For MIO_PERIPH_INSEL41


PINMUX.MIO_PERIPH_INSEL_REGWEN_42 @ 0xac

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_42
BitsTypeResetNameDescription
0rw0c0x1EN_42

For MIO_PERIPH_INSEL42


PINMUX.MIO_PERIPH_INSEL_REGWEN_43 @ 0xb0

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_43
BitsTypeResetNameDescription
0rw0c0x1EN_43

For MIO_PERIPH_INSEL43


PINMUX.MIO_PERIPH_INSEL_REGWEN_44 @ 0xb4

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_44
BitsTypeResetNameDescription
0rw0c0x1EN_44

For MIO_PERIPH_INSEL44


PINMUX.MIO_PERIPH_INSEL_REGWEN_45 @ 0xb8

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_45
BitsTypeResetNameDescription
0rw0c0x1EN_45

For MIO_PERIPH_INSEL45


PINMUX.MIO_PERIPH_INSEL_REGWEN_46 @ 0xbc

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_46
BitsTypeResetNameDescription
0rw0c0x1EN_46

For MIO_PERIPH_INSEL46


PINMUX.MIO_PERIPH_INSEL_REGWEN_47 @ 0xc0

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_47
BitsTypeResetNameDescription
0rw0c0x1EN_47

For MIO_PERIPH_INSEL47


PINMUX.MIO_PERIPH_INSEL_REGWEN_48 @ 0xc4

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_48
BitsTypeResetNameDescription
0rw0c0x1EN_48

For MIO_PERIPH_INSEL48


PINMUX.MIO_PERIPH_INSEL_REGWEN_49 @ 0xc8

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_49
BitsTypeResetNameDescription
0rw0c0x1EN_49

For MIO_PERIPH_INSEL49


PINMUX.MIO_PERIPH_INSEL_REGWEN_50 @ 0xcc

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_50
BitsTypeResetNameDescription
0rw0c0x1EN_50

For MIO_PERIPH_INSEL50


PINMUX.MIO_PERIPH_INSEL_REGWEN_51 @ 0xd0

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_51
BitsTypeResetNameDescription
0rw0c0x1EN_51

For MIO_PERIPH_INSEL51


PINMUX.MIO_PERIPH_INSEL_REGWEN_52 @ 0xd4

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_52
BitsTypeResetNameDescription
0rw0c0x1EN_52

For MIO_PERIPH_INSEL52


PINMUX.MIO_PERIPH_INSEL_REGWEN_53 @ 0xd8

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_53
BitsTypeResetNameDescription
0rw0c0x1EN_53

For MIO_PERIPH_INSEL53


PINMUX.MIO_PERIPH_INSEL_REGWEN_54 @ 0xdc

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_54
BitsTypeResetNameDescription
0rw0c0x1EN_54

For MIO_PERIPH_INSEL54


PINMUX.MIO_PERIPH_INSEL_REGWEN_55 @ 0xe0

Register write enable for MIO peripheral input selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_55
BitsTypeResetNameDescription
0rw0c0x1EN_55

For MIO_PERIPH_INSEL55


PINMUX.MIO_PERIPH_INSEL_0 @ 0xe4

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_0
31302928272625242322212019181716
 
1514131211109876543210
  IN_0
BitsTypeResetNameDescription
5:0rw0x0IN_0

0: tie constantly to zero, 1: tie constantly to 1, >=2: MIO pads (i.e., add 2 to the native MIO pad index).


PINMUX.MIO_PERIPH_INSEL_1 @ 0xe8

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_1
31302928272625242322212019181716
 
1514131211109876543210
  IN_1
BitsTypeResetNameDescription
5:0rw0x0IN_1

For IN1


PINMUX.MIO_PERIPH_INSEL_2 @ 0xec

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_2
31302928272625242322212019181716
 
1514131211109876543210
  IN_2
BitsTypeResetNameDescription
5:0rw0x0IN_2

For IN2


PINMUX.MIO_PERIPH_INSEL_3 @ 0xf0

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_3
31302928272625242322212019181716
 
1514131211109876543210
  IN_3
BitsTypeResetNameDescription
5:0rw0x0IN_3

For IN3


PINMUX.MIO_PERIPH_INSEL_4 @ 0xf4

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_4
31302928272625242322212019181716
 
1514131211109876543210
  IN_4
BitsTypeResetNameDescription
5:0rw0x0IN_4

For IN4


PINMUX.MIO_PERIPH_INSEL_5 @ 0xf8

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_5
31302928272625242322212019181716
 
1514131211109876543210
  IN_5
BitsTypeResetNameDescription
5:0rw0x0IN_5

For IN5


PINMUX.MIO_PERIPH_INSEL_6 @ 0xfc

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_6
31302928272625242322212019181716
 
1514131211109876543210
  IN_6
BitsTypeResetNameDescription
5:0rw0x0IN_6

For IN6


PINMUX.MIO_PERIPH_INSEL_7 @ 0x100

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_7
31302928272625242322212019181716
 
1514131211109876543210
  IN_7
BitsTypeResetNameDescription
5:0rw0x0IN_7

For IN7


PINMUX.MIO_PERIPH_INSEL_8 @ 0x104

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_8
31302928272625242322212019181716
 
1514131211109876543210
  IN_8
BitsTypeResetNameDescription
5:0rw0x0IN_8

For IN8


PINMUX.MIO_PERIPH_INSEL_9 @ 0x108

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_9
31302928272625242322212019181716
 
1514131211109876543210
  IN_9
BitsTypeResetNameDescription
5:0rw0x0IN_9

For IN9


PINMUX.MIO_PERIPH_INSEL_10 @ 0x10c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_10
31302928272625242322212019181716
 
1514131211109876543210
  IN_10
BitsTypeResetNameDescription
5:0rw0x0IN_10

For IN10


PINMUX.MIO_PERIPH_INSEL_11 @ 0x110

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_11
31302928272625242322212019181716
 
1514131211109876543210
  IN_11
BitsTypeResetNameDescription
5:0rw0x0IN_11

For IN11


PINMUX.MIO_PERIPH_INSEL_12 @ 0x114

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_12
31302928272625242322212019181716
 
1514131211109876543210
  IN_12
BitsTypeResetNameDescription
5:0rw0x0IN_12

For IN12


PINMUX.MIO_PERIPH_INSEL_13 @ 0x118

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_13
31302928272625242322212019181716
 
1514131211109876543210
  IN_13
BitsTypeResetNameDescription
5:0rw0x0IN_13

For IN13


PINMUX.MIO_PERIPH_INSEL_14 @ 0x11c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_14
31302928272625242322212019181716
 
1514131211109876543210
  IN_14
BitsTypeResetNameDescription
5:0rw0x0IN_14

For IN14


PINMUX.MIO_PERIPH_INSEL_15 @ 0x120

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_15
31302928272625242322212019181716
 
1514131211109876543210
  IN_15
BitsTypeResetNameDescription
5:0rw0x0IN_15

For IN15


PINMUX.MIO_PERIPH_INSEL_16 @ 0x124

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_16
31302928272625242322212019181716
 
1514131211109876543210
  IN_16
BitsTypeResetNameDescription
5:0rw0x0IN_16

For IN16


PINMUX.MIO_PERIPH_INSEL_17 @ 0x128

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_17
31302928272625242322212019181716
 
1514131211109876543210
  IN_17
BitsTypeResetNameDescription
5:0rw0x0IN_17

For IN17


PINMUX.MIO_PERIPH_INSEL_18 @ 0x12c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_18
31302928272625242322212019181716
 
1514131211109876543210
  IN_18
BitsTypeResetNameDescription
5:0rw0x0IN_18

For IN18


PINMUX.MIO_PERIPH_INSEL_19 @ 0x130

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_19
31302928272625242322212019181716
 
1514131211109876543210
  IN_19
BitsTypeResetNameDescription
5:0rw0x0IN_19

For IN19


PINMUX.MIO_PERIPH_INSEL_20 @ 0x134

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_20
31302928272625242322212019181716
 
1514131211109876543210
  IN_20
BitsTypeResetNameDescription
5:0rw0x0IN_20

For IN20


PINMUX.MIO_PERIPH_INSEL_21 @ 0x138

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_21
31302928272625242322212019181716
 
1514131211109876543210
  IN_21
BitsTypeResetNameDescription
5:0rw0x0IN_21

For IN21


PINMUX.MIO_PERIPH_INSEL_22 @ 0x13c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_22
31302928272625242322212019181716
 
1514131211109876543210
  IN_22
BitsTypeResetNameDescription
5:0rw0x0IN_22

For IN22


PINMUX.MIO_PERIPH_INSEL_23 @ 0x140

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_23
31302928272625242322212019181716
 
1514131211109876543210
  IN_23
BitsTypeResetNameDescription
5:0rw0x0IN_23

For IN23


PINMUX.MIO_PERIPH_INSEL_24 @ 0x144

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_24
31302928272625242322212019181716
 
1514131211109876543210
  IN_24
BitsTypeResetNameDescription
5:0rw0x0IN_24

For IN24


PINMUX.MIO_PERIPH_INSEL_25 @ 0x148

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_25
31302928272625242322212019181716
 
1514131211109876543210
  IN_25
BitsTypeResetNameDescription
5:0rw0x0IN_25

For IN25


PINMUX.MIO_PERIPH_INSEL_26 @ 0x14c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_26
31302928272625242322212019181716
 
1514131211109876543210
  IN_26
BitsTypeResetNameDescription
5:0rw0x0IN_26

For IN26


PINMUX.MIO_PERIPH_INSEL_27 @ 0x150

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_27
31302928272625242322212019181716
 
1514131211109876543210
  IN_27
BitsTypeResetNameDescription
5:0rw0x0IN_27

For IN27


PINMUX.MIO_PERIPH_INSEL_28 @ 0x154

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_28
31302928272625242322212019181716
 
1514131211109876543210
  IN_28
BitsTypeResetNameDescription
5:0rw0x0IN_28

For IN28


PINMUX.MIO_PERIPH_INSEL_29 @ 0x158

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_29
31302928272625242322212019181716
 
1514131211109876543210
  IN_29
BitsTypeResetNameDescription
5:0rw0x0IN_29

For IN29


PINMUX.MIO_PERIPH_INSEL_30 @ 0x15c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_30
31302928272625242322212019181716
 
1514131211109876543210
  IN_30
BitsTypeResetNameDescription
5:0rw0x0IN_30

For IN30


PINMUX.MIO_PERIPH_INSEL_31 @ 0x160

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_31
31302928272625242322212019181716
 
1514131211109876543210
  IN_31
BitsTypeResetNameDescription
5:0rw0x0IN_31

For IN31


PINMUX.MIO_PERIPH_INSEL_32 @ 0x164

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_32
31302928272625242322212019181716
 
1514131211109876543210
  IN_32
BitsTypeResetNameDescription
5:0rw0x0IN_32

For IN32


PINMUX.MIO_PERIPH_INSEL_33 @ 0x168

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_33
31302928272625242322212019181716
 
1514131211109876543210
  IN_33
BitsTypeResetNameDescription
5:0rw0x0IN_33

For IN33


PINMUX.MIO_PERIPH_INSEL_34 @ 0x16c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_34
31302928272625242322212019181716
 
1514131211109876543210
  IN_34
BitsTypeResetNameDescription
5:0rw0x0IN_34

For IN34


PINMUX.MIO_PERIPH_INSEL_35 @ 0x170

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_35
31302928272625242322212019181716
 
1514131211109876543210
  IN_35
BitsTypeResetNameDescription
5:0rw0x0IN_35

For IN35


PINMUX.MIO_PERIPH_INSEL_36 @ 0x174

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_36
31302928272625242322212019181716
 
1514131211109876543210
  IN_36
BitsTypeResetNameDescription
5:0rw0x0IN_36

For IN36


PINMUX.MIO_PERIPH_INSEL_37 @ 0x178

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_37
31302928272625242322212019181716
 
1514131211109876543210
  IN_37
BitsTypeResetNameDescription
5:0rw0x0IN_37

For IN37


PINMUX.MIO_PERIPH_INSEL_38 @ 0x17c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_38
31302928272625242322212019181716
 
1514131211109876543210
  IN_38
BitsTypeResetNameDescription
5:0rw0x0IN_38

For IN38


PINMUX.MIO_PERIPH_INSEL_39 @ 0x180

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_39
31302928272625242322212019181716
 
1514131211109876543210
  IN_39
BitsTypeResetNameDescription
5:0rw0x0IN_39

For IN39


PINMUX.MIO_PERIPH_INSEL_40 @ 0x184

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_40
31302928272625242322212019181716
 
1514131211109876543210
  IN_40
BitsTypeResetNameDescription
5:0rw0x0IN_40

For IN40


PINMUX.MIO_PERIPH_INSEL_41 @ 0x188

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_41
31302928272625242322212019181716
 
1514131211109876543210
  IN_41
BitsTypeResetNameDescription
5:0rw0x0IN_41

For IN41


PINMUX.MIO_PERIPH_INSEL_42 @ 0x18c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_42
31302928272625242322212019181716
 
1514131211109876543210
  IN_42
BitsTypeResetNameDescription
5:0rw0x0IN_42

For IN42


PINMUX.MIO_PERIPH_INSEL_43 @ 0x190

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_43
31302928272625242322212019181716
 
1514131211109876543210
  IN_43
BitsTypeResetNameDescription
5:0rw0x0IN_43

For IN43


PINMUX.MIO_PERIPH_INSEL_44 @ 0x194

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_44
31302928272625242322212019181716
 
1514131211109876543210
  IN_44
BitsTypeResetNameDescription
5:0rw0x0IN_44

For IN44


PINMUX.MIO_PERIPH_INSEL_45 @ 0x198

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_45
31302928272625242322212019181716
 
1514131211109876543210
  IN_45
BitsTypeResetNameDescription
5:0rw0x0IN_45

For IN45


PINMUX.MIO_PERIPH_INSEL_46 @ 0x19c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_46
31302928272625242322212019181716
 
1514131211109876543210
  IN_46
BitsTypeResetNameDescription
5:0rw0x0IN_46

For IN46


PINMUX.MIO_PERIPH_INSEL_47 @ 0x1a0

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_47
31302928272625242322212019181716
 
1514131211109876543210
  IN_47
BitsTypeResetNameDescription
5:0rw0x0IN_47

For IN47


PINMUX.MIO_PERIPH_INSEL_48 @ 0x1a4

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_48
31302928272625242322212019181716
 
1514131211109876543210
  IN_48
BitsTypeResetNameDescription
5:0rw0x0IN_48

For IN48


PINMUX.MIO_PERIPH_INSEL_49 @ 0x1a8

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_49
31302928272625242322212019181716
 
1514131211109876543210
  IN_49
BitsTypeResetNameDescription
5:0rw0x0IN_49

For IN49


PINMUX.MIO_PERIPH_INSEL_50 @ 0x1ac

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_50
31302928272625242322212019181716
 
1514131211109876543210
  IN_50
BitsTypeResetNameDescription
5:0rw0x0IN_50

For IN50


PINMUX.MIO_PERIPH_INSEL_51 @ 0x1b0

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_51
31302928272625242322212019181716
 
1514131211109876543210
  IN_51
BitsTypeResetNameDescription
5:0rw0x0IN_51

For IN51


PINMUX.MIO_PERIPH_INSEL_52 @ 0x1b4

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_52
31302928272625242322212019181716
 
1514131211109876543210
  IN_52
BitsTypeResetNameDescription
5:0rw0x0IN_52

For IN52


PINMUX.MIO_PERIPH_INSEL_53 @ 0x1b8

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_53
31302928272625242322212019181716
 
1514131211109876543210
  IN_53
BitsTypeResetNameDescription
5:0rw0x0IN_53

For IN53


PINMUX.MIO_PERIPH_INSEL_54 @ 0x1bc

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_54
31302928272625242322212019181716
 
1514131211109876543210
  IN_54
BitsTypeResetNameDescription
5:0rw0x0IN_54

For IN54


PINMUX.MIO_PERIPH_INSEL_55 @ 0x1c0

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f
Register enable = MIO_PERIPH_INSEL_REGWEN_55
31302928272625242322212019181716
 
1514131211109876543210
  IN_55
BitsTypeResetNameDescription
5:0rw0x0IN_55

For IN55


PINMUX.MIO_OUTSEL_REGWEN_0 @ 0x1c4

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_0
BitsTypeResetNameDescription
0rw0c0x1EN_0

Register write enable bit. If this is cleared to 0, the corresponding MIO_OUTSEL is not writable anymore.


PINMUX.MIO_OUTSEL_REGWEN_1 @ 0x1c8

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_1
BitsTypeResetNameDescription
0rw0c0x1EN_1

For MIO_OUTSEL1


PINMUX.MIO_OUTSEL_REGWEN_2 @ 0x1cc

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_2
BitsTypeResetNameDescription
0rw0c0x1EN_2

For MIO_OUTSEL2


PINMUX.MIO_OUTSEL_REGWEN_3 @ 0x1d0

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_3
BitsTypeResetNameDescription
0rw0c0x1EN_3

For MIO_OUTSEL3


PINMUX.MIO_OUTSEL_REGWEN_4 @ 0x1d4

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_4
BitsTypeResetNameDescription
0rw0c0x1EN_4

For MIO_OUTSEL4


PINMUX.MIO_OUTSEL_REGWEN_5 @ 0x1d8

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_5
BitsTypeResetNameDescription
0rw0c0x1EN_5

For MIO_OUTSEL5


PINMUX.MIO_OUTSEL_REGWEN_6 @ 0x1dc

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_6
BitsTypeResetNameDescription
0rw0c0x1EN_6

For MIO_OUTSEL6


PINMUX.MIO_OUTSEL_REGWEN_7 @ 0x1e0

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_7
BitsTypeResetNameDescription
0rw0c0x1EN_7

For MIO_OUTSEL7


PINMUX.MIO_OUTSEL_REGWEN_8 @ 0x1e4

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_8
BitsTypeResetNameDescription
0rw0c0x1EN_8

For MIO_OUTSEL8


PINMUX.MIO_OUTSEL_REGWEN_9 @ 0x1e8

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_9
BitsTypeResetNameDescription
0rw0c0x1EN_9

For MIO_OUTSEL9


PINMUX.MIO_OUTSEL_REGWEN_10 @ 0x1ec

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_10
BitsTypeResetNameDescription
0rw0c0x1EN_10

For MIO_OUTSEL10


PINMUX.MIO_OUTSEL_REGWEN_11 @ 0x1f0

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_11
BitsTypeResetNameDescription
0rw0c0x1EN_11

For MIO_OUTSEL11


PINMUX.MIO_OUTSEL_REGWEN_12 @ 0x1f4

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_12
BitsTypeResetNameDescription
0rw0c0x1EN_12

For MIO_OUTSEL12


PINMUX.MIO_OUTSEL_REGWEN_13 @ 0x1f8

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_13
BitsTypeResetNameDescription
0rw0c0x1EN_13

For MIO_OUTSEL13


PINMUX.MIO_OUTSEL_REGWEN_14 @ 0x1fc

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_14
BitsTypeResetNameDescription
0rw0c0x1EN_14

For MIO_OUTSEL14


PINMUX.MIO_OUTSEL_REGWEN_15 @ 0x200

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_15
BitsTypeResetNameDescription
0rw0c0x1EN_15

For MIO_OUTSEL15


PINMUX.MIO_OUTSEL_REGWEN_16 @ 0x204

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_16
BitsTypeResetNameDescription
0rw0c0x1EN_16

For MIO_OUTSEL16


PINMUX.MIO_OUTSEL_REGWEN_17 @ 0x208

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_17
BitsTypeResetNameDescription
0rw0c0x1EN_17

For MIO_OUTSEL17


PINMUX.MIO_OUTSEL_REGWEN_18 @ 0x20c

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_18
BitsTypeResetNameDescription
0rw0c0x1EN_18

For MIO_OUTSEL18


PINMUX.MIO_OUTSEL_REGWEN_19 @ 0x210

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_19
BitsTypeResetNameDescription
0rw0c0x1EN_19

For MIO_OUTSEL19


PINMUX.MIO_OUTSEL_REGWEN_20 @ 0x214

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_20
BitsTypeResetNameDescription
0rw0c0x1EN_20

For MIO_OUTSEL20


PINMUX.MIO_OUTSEL_REGWEN_21 @ 0x218

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_21
BitsTypeResetNameDescription
0rw0c0x1EN_21

For MIO_OUTSEL21


PINMUX.MIO_OUTSEL_REGWEN_22 @ 0x21c

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_22
BitsTypeResetNameDescription
0rw0c0x1EN_22

For MIO_OUTSEL22


PINMUX.MIO_OUTSEL_REGWEN_23 @ 0x220

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_23
BitsTypeResetNameDescription
0rw0c0x1EN_23

For MIO_OUTSEL23


PINMUX.MIO_OUTSEL_REGWEN_24 @ 0x224

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_24
BitsTypeResetNameDescription
0rw0c0x1EN_24

For MIO_OUTSEL24


PINMUX.MIO_OUTSEL_REGWEN_25 @ 0x228

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_25
BitsTypeResetNameDescription
0rw0c0x1EN_25

For MIO_OUTSEL25


PINMUX.MIO_OUTSEL_REGWEN_26 @ 0x22c

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_26
BitsTypeResetNameDescription
0rw0c0x1EN_26

For MIO_OUTSEL26


PINMUX.MIO_OUTSEL_REGWEN_27 @ 0x230

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_27
BitsTypeResetNameDescription
0rw0c0x1EN_27

For MIO_OUTSEL27


PINMUX.MIO_OUTSEL_REGWEN_28 @ 0x234

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_28
BitsTypeResetNameDescription
0rw0c0x1EN_28

For MIO_OUTSEL28


PINMUX.MIO_OUTSEL_REGWEN_29 @ 0x238

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_29
BitsTypeResetNameDescription
0rw0c0x1EN_29

For MIO_OUTSEL29


PINMUX.MIO_OUTSEL_REGWEN_30 @ 0x23c

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_30
BitsTypeResetNameDescription
0rw0c0x1EN_30

For MIO_OUTSEL30


PINMUX.MIO_OUTSEL_REGWEN_31 @ 0x240

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_31
BitsTypeResetNameDescription
0rw0c0x1EN_31

For MIO_OUTSEL31


PINMUX.MIO_OUTSEL_REGWEN_32 @ 0x244

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_32
BitsTypeResetNameDescription
0rw0c0x1EN_32

For MIO_OUTSEL32


PINMUX.MIO_OUTSEL_REGWEN_33 @ 0x248

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_33
BitsTypeResetNameDescription
0rw0c0x1EN_33

For MIO_OUTSEL33


PINMUX.MIO_OUTSEL_REGWEN_34 @ 0x24c

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_34
BitsTypeResetNameDescription
0rw0c0x1EN_34

For MIO_OUTSEL34


PINMUX.MIO_OUTSEL_REGWEN_35 @ 0x250

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_35
BitsTypeResetNameDescription
0rw0c0x1EN_35

For MIO_OUTSEL35


PINMUX.MIO_OUTSEL_REGWEN_36 @ 0x254

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  EN_36
BitsTypeResetNameDescription
0rw0c0x1EN_36

For MIO_OUTSEL36


PINMUX.MIO_OUTSEL_REGWEN_37 @ 0x258

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_37
BitsTypeResetNameDescription
0rw0c0x1EN_37

For MIO_OUTSEL37


PINMUX.MIO_OUTSEL_REGWEN_38 @ 0x25c

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  EN_38
BitsTypeResetNameDescription
0rw0c0x1EN_38

For MIO_OUTSEL38


PINMUX.MIO_OUTSEL_REGWEN_39 @ 0x260

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  EN_39
BitsTypeResetNameDescription
0rw0c0x1EN_39

For MIO_OUTSEL39


PINMUX.MIO_OUTSEL_REGWEN_40 @ 0x264

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  EN_40
BitsTypeResetNameDescription
0rw0c0x1EN_40

For MIO_OUTSEL40


PINMUX.MIO_OUTSEL_REGWEN_41 @ 0x268

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  EN_41
BitsTypeResetNameDescription
0rw0c0x1EN_41

For MIO_OUTSEL41


PINMUX.MIO_OUTSEL_REGWEN_42 @ 0x26c

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_42
BitsTypeResetNameDescription
0rw0c0x1EN_42

For MIO_OUTSEL42


PINMUX.MIO_OUTSEL_REGWEN_43 @ 0x270

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  EN_43
BitsTypeResetNameDescription
0rw0c0x1EN_43

For MIO_OUTSEL43


PINMUX.MIO_OUTSEL_REGWEN_44 @ 0x274

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_44
BitsTypeResetNameDescription
0rw0c0x1EN_44

For MIO_OUTSEL44


PINMUX.MIO_OUTSEL_REGWEN_45 @ 0x278

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_45
BitsTypeResetNameDescription
0rw0c0x1EN_45

For MIO_OUTSEL45


PINMUX.MIO_OUTSEL_REGWEN_46 @ 0x27c

Register write enable for MIO output selects.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  EN_46
BitsTypeResetNameDescription
0rw0c0x1EN_46

For MIO_OUTSEL46


PINMUX.MIO_OUTSEL_0 @ 0x280

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_0
31302928272625242322212019181716
 
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  OUT_0
BitsTypeResetNameDescription
6:0rw0x2OUT_0

0: tie constantly to zero, 1: tie constantly to 1, 2: high-Z, >=3: peripheral outputs (i.e., add 3 to the native peripheral pad index).


PINMUX.MIO_OUTSEL_1 @ 0x284

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_1
31302928272625242322212019181716
 
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  OUT_1
BitsTypeResetNameDescription
6:0rw0x2OUT_1

For OUT1


PINMUX.MIO_OUTSEL_2 @ 0x288

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_2
31302928272625242322212019181716
 
1514131211109876543210
  OUT_2
BitsTypeResetNameDescription
6:0rw0x2OUT_2

For OUT2


PINMUX.MIO_OUTSEL_3 @ 0x28c

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_3
31302928272625242322212019181716
 
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  OUT_3
BitsTypeResetNameDescription
6:0rw0x2OUT_3

For OUT3


PINMUX.MIO_OUTSEL_4 @ 0x290

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_4
31302928272625242322212019181716
 
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  OUT_4
BitsTypeResetNameDescription
6:0rw0x2OUT_4

For OUT4


PINMUX.MIO_OUTSEL_5 @ 0x294

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_5
31302928272625242322212019181716
 
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  OUT_5
BitsTypeResetNameDescription
6:0rw0x2OUT_5

For OUT5


PINMUX.MIO_OUTSEL_6 @ 0x298

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_6
31302928272625242322212019181716
 
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  OUT_6
BitsTypeResetNameDescription
6:0rw0x2OUT_6

For OUT6


PINMUX.MIO_OUTSEL_7 @ 0x29c

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_7
31302928272625242322212019181716
 
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  OUT_7
BitsTypeResetNameDescription
6:0rw0x2OUT_7

For OUT7


PINMUX.MIO_OUTSEL_8 @ 0x2a0

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_8
31302928272625242322212019181716
 
1514131211109876543210
  OUT_8
BitsTypeResetNameDescription
6:0rw0x2OUT_8

For OUT8


PINMUX.MIO_OUTSEL_9 @ 0x2a4

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_9
31302928272625242322212019181716
 
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  OUT_9
BitsTypeResetNameDescription
6:0rw0x2OUT_9

For OUT9


PINMUX.MIO_OUTSEL_10 @ 0x2a8

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_10
31302928272625242322212019181716
 
1514131211109876543210
  OUT_10
BitsTypeResetNameDescription
6:0rw0x2OUT_10

For OUT10


PINMUX.MIO_OUTSEL_11 @ 0x2ac

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_11
31302928272625242322212019181716
 
1514131211109876543210
  OUT_11
BitsTypeResetNameDescription
6:0rw0x2OUT_11

For OUT11


PINMUX.MIO_OUTSEL_12 @ 0x2b0

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_12
31302928272625242322212019181716
 
1514131211109876543210
  OUT_12
BitsTypeResetNameDescription
6:0rw0x2OUT_12

For OUT12


PINMUX.MIO_OUTSEL_13 @ 0x2b4

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_13
31302928272625242322212019181716
 
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  OUT_13
BitsTypeResetNameDescription
6:0rw0x2OUT_13

For OUT13


PINMUX.MIO_OUTSEL_14 @ 0x2b8

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_14
31302928272625242322212019181716
 
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  OUT_14
BitsTypeResetNameDescription
6:0rw0x2OUT_14

For OUT14


PINMUX.MIO_OUTSEL_15 @ 0x2bc

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_15
31302928272625242322212019181716
 
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  OUT_15
BitsTypeResetNameDescription
6:0rw0x2OUT_15

For OUT15


PINMUX.MIO_OUTSEL_16 @ 0x2c0

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_16
31302928272625242322212019181716
 
1514131211109876543210
  OUT_16
BitsTypeResetNameDescription
6:0rw0x2OUT_16

For OUT16


PINMUX.MIO_OUTSEL_17 @ 0x2c4

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_17
31302928272625242322212019181716
 
1514131211109876543210
  OUT_17
BitsTypeResetNameDescription
6:0rw0x2OUT_17

For OUT17


PINMUX.MIO_OUTSEL_18 @ 0x2c8

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_18
31302928272625242322212019181716
 
1514131211109876543210
  OUT_18
BitsTypeResetNameDescription
6:0rw0x2OUT_18

For OUT18


PINMUX.MIO_OUTSEL_19 @ 0x2cc

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_19
31302928272625242322212019181716
 
1514131211109876543210
  OUT_19
BitsTypeResetNameDescription
6:0rw0x2OUT_19

For OUT19


PINMUX.MIO_OUTSEL_20 @ 0x2d0

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_20
31302928272625242322212019181716
 
1514131211109876543210
  OUT_20
BitsTypeResetNameDescription
6:0rw0x2OUT_20

For OUT20


PINMUX.MIO_OUTSEL_21 @ 0x2d4

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_21
31302928272625242322212019181716
 
1514131211109876543210
  OUT_21
BitsTypeResetNameDescription
6:0rw0x2OUT_21

For OUT21


PINMUX.MIO_OUTSEL_22 @ 0x2d8

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_22
31302928272625242322212019181716
 
1514131211109876543210
  OUT_22
BitsTypeResetNameDescription
6:0rw0x2OUT_22

For OUT22


PINMUX.MIO_OUTSEL_23 @ 0x2dc

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_23
31302928272625242322212019181716
 
1514131211109876543210
  OUT_23
BitsTypeResetNameDescription
6:0rw0x2OUT_23

For OUT23


PINMUX.MIO_OUTSEL_24 @ 0x2e0

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_24
31302928272625242322212019181716
 
1514131211109876543210
  OUT_24
BitsTypeResetNameDescription
6:0rw0x2OUT_24

For OUT24


PINMUX.MIO_OUTSEL_25 @ 0x2e4

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_25
31302928272625242322212019181716
 
1514131211109876543210
  OUT_25
BitsTypeResetNameDescription
6:0rw0x2OUT_25

For OUT25


PINMUX.MIO_OUTSEL_26 @ 0x2e8

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_26
31302928272625242322212019181716
 
1514131211109876543210
  OUT_26
BitsTypeResetNameDescription
6:0rw0x2OUT_26

For OUT26


PINMUX.MIO_OUTSEL_27 @ 0x2ec

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_27
31302928272625242322212019181716
 
1514131211109876543210
  OUT_27
BitsTypeResetNameDescription
6:0rw0x2OUT_27

For OUT27


PINMUX.MIO_OUTSEL_28 @ 0x2f0

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_28
31302928272625242322212019181716
 
1514131211109876543210
  OUT_28
BitsTypeResetNameDescription
6:0rw0x2OUT_28

For OUT28


PINMUX.MIO_OUTSEL_29 @ 0x2f4

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_29
31302928272625242322212019181716
 
1514131211109876543210
  OUT_29
BitsTypeResetNameDescription
6:0rw0x2OUT_29

For OUT29


PINMUX.MIO_OUTSEL_30 @ 0x2f8

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_30
31302928272625242322212019181716
 
1514131211109876543210
  OUT_30
BitsTypeResetNameDescription
6:0rw0x2OUT_30

For OUT30


PINMUX.MIO_OUTSEL_31 @ 0x2fc

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_31
31302928272625242322212019181716
 
1514131211109876543210
  OUT_31
BitsTypeResetNameDescription
6:0rw0x2OUT_31

For OUT31


PINMUX.MIO_OUTSEL_32 @ 0x300

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_32
31302928272625242322212019181716
 
1514131211109876543210
  OUT_32
BitsTypeResetNameDescription
6:0rw0x2OUT_32

For OUT32


PINMUX.MIO_OUTSEL_33 @ 0x304

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_33
31302928272625242322212019181716
 
1514131211109876543210
  OUT_33
BitsTypeResetNameDescription
6:0rw0x2OUT_33

For OUT33


PINMUX.MIO_OUTSEL_34 @ 0x308

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_34
31302928272625242322212019181716
 
1514131211109876543210
  OUT_34
BitsTypeResetNameDescription
6:0rw0x2OUT_34

For OUT34


PINMUX.MIO_OUTSEL_35 @ 0x30c

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_35
31302928272625242322212019181716
 
1514131211109876543210
  OUT_35
BitsTypeResetNameDescription
6:0rw0x2OUT_35

For OUT35


PINMUX.MIO_OUTSEL_36 @ 0x310

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_36
31302928272625242322212019181716
 
1514131211109876543210
  OUT_36
BitsTypeResetNameDescription
6:0rw0x2OUT_36

For OUT36


PINMUX.MIO_OUTSEL_37 @ 0x314

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_37
31302928272625242322212019181716
 
1514131211109876543210
  OUT_37
BitsTypeResetNameDescription
6:0rw0x2OUT_37

For OUT37


PINMUX.MIO_OUTSEL_38 @ 0x318

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_38
31302928272625242322212019181716
 
1514131211109876543210
  OUT_38
BitsTypeResetNameDescription
6:0rw0x2OUT_38

For OUT38


PINMUX.MIO_OUTSEL_39 @ 0x31c

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_39
31302928272625242322212019181716
 
1514131211109876543210
  OUT_39
BitsTypeResetNameDescription
6:0rw0x2OUT_39

For OUT39


PINMUX.MIO_OUTSEL_40 @ 0x320

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_40
31302928272625242322212019181716
 
1514131211109876543210
  OUT_40
BitsTypeResetNameDescription
6:0rw0x2OUT_40

For OUT40


PINMUX.MIO_OUTSEL_41 @ 0x324

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_41
31302928272625242322212019181716
 
1514131211109876543210
  OUT_41
BitsTypeResetNameDescription
6:0rw0x2OUT_41

For OUT41


PINMUX.MIO_OUTSEL_42 @ 0x328

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_42
31302928272625242322212019181716
 
1514131211109876543210
  OUT_42
BitsTypeResetNameDescription
6:0rw0x2OUT_42

For OUT42


PINMUX.MIO_OUTSEL_43 @ 0x32c

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_43
31302928272625242322212019181716
 
1514131211109876543210
  OUT_43
BitsTypeResetNameDescription
6:0rw0x2OUT_43

For OUT43


PINMUX.MIO_OUTSEL_44 @ 0x330

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_44
31302928272625242322212019181716
 
1514131211109876543210
  OUT_44
BitsTypeResetNameDescription
6:0rw0x2OUT_44

For OUT44


PINMUX.MIO_OUTSEL_45 @ 0x334

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_45
31302928272625242322212019181716
 
1514131211109876543210
  OUT_45
BitsTypeResetNameDescription
6:0rw0x2OUT_45

For OUT45


PINMUX.MIO_OUTSEL_46 @ 0x338

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f
Register enable = MIO_OUTSEL_REGWEN_46
31302928272625242322212019181716
 
1514131211109876543210
  OUT_46
BitsTypeResetNameDescription
6:0rw0x2OUT_46

For OUT46


PINMUX.MIO_PAD_ATTR_REGWEN_0 @ 0x33c

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_0
BitsTypeResetNameDescription
0rw0c0x1EN_0

Register write enable bit. If this is cleared to 0, the corresponding !!MIO_PAD_ATTR is not writable anymore.


PINMUX.MIO_PAD_ATTR_REGWEN_1 @ 0x340

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_1
BitsTypeResetNameDescription
0rw0c0x1EN_1

For MIO_PAD1


PINMUX.MIO_PAD_ATTR_REGWEN_2 @ 0x344

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_2
BitsTypeResetNameDescription
0rw0c0x1EN_2

For MIO_PAD2


PINMUX.MIO_PAD_ATTR_REGWEN_3 @ 0x348

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_3
BitsTypeResetNameDescription
0rw0c0x1EN_3

For MIO_PAD3


PINMUX.MIO_PAD_ATTR_REGWEN_4 @ 0x34c

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_4
BitsTypeResetNameDescription
0rw0c0x1EN_4

For MIO_PAD4


PINMUX.MIO_PAD_ATTR_REGWEN_5 @ 0x350

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_5
BitsTypeResetNameDescription
0rw0c0x1EN_5

For MIO_PAD5


PINMUX.MIO_PAD_ATTR_REGWEN_6 @ 0x354

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_6
BitsTypeResetNameDescription
0rw0c0x1EN_6

For MIO_PAD6


PINMUX.MIO_PAD_ATTR_REGWEN_7 @ 0x358

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_7
BitsTypeResetNameDescription
0rw0c0x1EN_7

For MIO_PAD7


PINMUX.MIO_PAD_ATTR_REGWEN_8 @ 0x35c

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_8
BitsTypeResetNameDescription
0rw0c0x1EN_8

For MIO_PAD8


PINMUX.MIO_PAD_ATTR_REGWEN_9 @ 0x360

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_9
BitsTypeResetNameDescription
0rw0c0x1EN_9

For MIO_PAD9


PINMUX.MIO_PAD_ATTR_REGWEN_10 @ 0x364

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_10
BitsTypeResetNameDescription
0rw0c0x1EN_10

For MIO_PAD10


PINMUX.MIO_PAD_ATTR_REGWEN_11 @ 0x368

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_11
BitsTypeResetNameDescription
0rw0c0x1EN_11

For MIO_PAD11


PINMUX.MIO_PAD_ATTR_REGWEN_12 @ 0x36c

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_12
BitsTypeResetNameDescription
0rw0c0x1EN_12

For MIO_PAD12


PINMUX.MIO_PAD_ATTR_REGWEN_13 @ 0x370

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_13
BitsTypeResetNameDescription
0rw0c0x1EN_13

For MIO_PAD13


PINMUX.MIO_PAD_ATTR_REGWEN_14 @ 0x374

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_14
BitsTypeResetNameDescription
0rw0c0x1EN_14

For MIO_PAD14


PINMUX.MIO_PAD_ATTR_REGWEN_15 @ 0x378

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_15
BitsTypeResetNameDescription
0rw0c0x1EN_15

For MIO_PAD15


PINMUX.MIO_PAD_ATTR_REGWEN_16 @ 0x37c

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_16
BitsTypeResetNameDescription
0rw0c0x1EN_16

For MIO_PAD16


PINMUX.MIO_PAD_ATTR_REGWEN_17 @ 0x380

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_17
BitsTypeResetNameDescription
0rw0c0x1EN_17

For MIO_PAD17


PINMUX.MIO_PAD_ATTR_REGWEN_18 @ 0x384

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_18
BitsTypeResetNameDescription
0rw0c0x1EN_18

For MIO_PAD18


PINMUX.MIO_PAD_ATTR_REGWEN_19 @ 0x388

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_19
BitsTypeResetNameDescription
0rw0c0x1EN_19

For MIO_PAD19


PINMUX.MIO_PAD_ATTR_REGWEN_20 @ 0x38c

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_20
BitsTypeResetNameDescription
0rw0c0x1EN_20

For MIO_PAD20


PINMUX.MIO_PAD_ATTR_REGWEN_21 @ 0x390

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_21
BitsTypeResetNameDescription
0rw0c0x1EN_21

For MIO_PAD21


PINMUX.MIO_PAD_ATTR_REGWEN_22 @ 0x394

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_22
BitsTypeResetNameDescription
0rw0c0x1EN_22

For MIO_PAD22


PINMUX.MIO_PAD_ATTR_REGWEN_23 @ 0x398

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_23
BitsTypeResetNameDescription
0rw0c0x1EN_23

For MIO_PAD23


PINMUX.MIO_PAD_ATTR_REGWEN_24 @ 0x39c

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_24
BitsTypeResetNameDescription
0rw0c0x1EN_24

For MIO_PAD24


PINMUX.MIO_PAD_ATTR_REGWEN_25 @ 0x3a0

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_25
BitsTypeResetNameDescription
0rw0c0x1EN_25

For MIO_PAD25


PINMUX.MIO_PAD_ATTR_REGWEN_26 @ 0x3a4

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_26
BitsTypeResetNameDescription
0rw0c0x1EN_26

For MIO_PAD26


PINMUX.MIO_PAD_ATTR_REGWEN_27 @ 0x3a8

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_27
BitsTypeResetNameDescription
0rw0c0x1EN_27

For MIO_PAD27


PINMUX.MIO_PAD_ATTR_REGWEN_28 @ 0x3ac

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_28
BitsTypeResetNameDescription
0rw0c0x1EN_28

For MIO_PAD28


PINMUX.MIO_PAD_ATTR_REGWEN_29 @ 0x3b0

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_29
BitsTypeResetNameDescription
0rw0c0x1EN_29

For MIO_PAD29


PINMUX.MIO_PAD_ATTR_REGWEN_30 @ 0x3b4

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_30
BitsTypeResetNameDescription
0rw0c0x1EN_30

For MIO_PAD30


PINMUX.MIO_PAD_ATTR_REGWEN_31 @ 0x3b8

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_31
BitsTypeResetNameDescription
0rw0c0x1EN_31

For MIO_PAD31


PINMUX.MIO_PAD_ATTR_REGWEN_32 @ 0x3bc

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_32
BitsTypeResetNameDescription
0rw0c0x1EN_32

For MIO_PAD32


PINMUX.MIO_PAD_ATTR_REGWEN_33 @ 0x3c0

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_33
BitsTypeResetNameDescription
0rw0c0x1EN_33

For MIO_PAD33


PINMUX.MIO_PAD_ATTR_REGWEN_34 @ 0x3c4

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_34
BitsTypeResetNameDescription
0rw0c0x1EN_34

For MIO_PAD34


PINMUX.MIO_PAD_ATTR_REGWEN_35 @ 0x3c8

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_35
BitsTypeResetNameDescription
0rw0c0x1EN_35

For MIO_PAD35


PINMUX.MIO_PAD_ATTR_REGWEN_36 @ 0x3cc

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_36
BitsTypeResetNameDescription
0rw0c0x1EN_36

For MIO_PAD36


PINMUX.MIO_PAD_ATTR_REGWEN_37 @ 0x3d0

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_37
BitsTypeResetNameDescription
0rw0c0x1EN_37

For MIO_PAD37


PINMUX.MIO_PAD_ATTR_REGWEN_38 @ 0x3d4

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_38
BitsTypeResetNameDescription
0rw0c0x1EN_38

For MIO_PAD38


PINMUX.MIO_PAD_ATTR_REGWEN_39 @ 0x3d8

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_39
BitsTypeResetNameDescription
0rw0c0x1EN_39

For MIO_PAD39


PINMUX.MIO_PAD_ATTR_REGWEN_40 @ 0x3dc

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_40
BitsTypeResetNameDescription
0rw0c0x1EN_40

For MIO_PAD40


PINMUX.MIO_PAD_ATTR_REGWEN_41 @ 0x3e0

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_41
BitsTypeResetNameDescription
0rw0c0x1EN_41

For MIO_PAD41


PINMUX.MIO_PAD_ATTR_REGWEN_42 @ 0x3e4

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_42
BitsTypeResetNameDescription
0rw0c0x1EN_42

For MIO_PAD42


PINMUX.MIO_PAD_ATTR_REGWEN_43 @ 0x3e8

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_43
BitsTypeResetNameDescription
0rw0c0x1EN_43

For MIO_PAD43


PINMUX.MIO_PAD_ATTR_REGWEN_44 @ 0x3ec

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_44
BitsTypeResetNameDescription
0rw0c0x1EN_44

For MIO_PAD44


PINMUX.MIO_PAD_ATTR_REGWEN_45 @ 0x3f0

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_45
BitsTypeResetNameDescription
0rw0c0x1EN_45

For MIO_PAD45


PINMUX.MIO_PAD_ATTR_REGWEN_46 @ 0x3f4

Register write enable for MIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_46
BitsTypeResetNameDescription
0rw0c0x1EN_46

For MIO_PAD46


PINMUX.MIO_PAD_ATTR_0 @ 0x3f8

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_0
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_0
BitsTypeResetNameDescription
12:0rw0x0ATTR_0

Bit 0: input/output inversion, Bit 1: Virtual open drain enable. Bit 2: Pull enable. Bit 3: Pull select (0: pull down, 1: pull up). Bit 4: Keeper enable. Bit 5: Schmitt trigger enable. Bit 6: Open drain enable Bit 7/8: Slew rate (0x0: slowest, 0x3: fastest). Bit 9/12: Drive strength (0x0: weakest, 0xf: strongest).


PINMUX.MIO_PAD_ATTR_1 @ 0x3fc

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_1
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_1
BitsTypeResetNameDescription
12:0rw0x0ATTR_1

For MIO_PAD1


PINMUX.MIO_PAD_ATTR_2 @ 0x400

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_2
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_2
BitsTypeResetNameDescription
12:0rw0x0ATTR_2

For MIO_PAD2


PINMUX.MIO_PAD_ATTR_3 @ 0x404

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_3
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_3
BitsTypeResetNameDescription
12:0rw0x0ATTR_3

For MIO_PAD3


PINMUX.MIO_PAD_ATTR_4 @ 0x408

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_4
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_4
BitsTypeResetNameDescription
12:0rw0x0ATTR_4

For MIO_PAD4


PINMUX.MIO_PAD_ATTR_5 @ 0x40c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_5
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_5
BitsTypeResetNameDescription
12:0rw0x0ATTR_5

For MIO_PAD5


PINMUX.MIO_PAD_ATTR_6 @ 0x410

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_6
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_6
BitsTypeResetNameDescription
12:0rw0x0ATTR_6

For MIO_PAD6


PINMUX.MIO_PAD_ATTR_7 @ 0x414

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_7
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_7
BitsTypeResetNameDescription
12:0rw0x0ATTR_7

For MIO_PAD7


PINMUX.MIO_PAD_ATTR_8 @ 0x418

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_8
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_8
BitsTypeResetNameDescription
12:0rw0x0ATTR_8

For MIO_PAD8


PINMUX.MIO_PAD_ATTR_9 @ 0x41c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_9
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_9
BitsTypeResetNameDescription
12:0rw0x0ATTR_9

For MIO_PAD9


PINMUX.MIO_PAD_ATTR_10 @ 0x420

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_10
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_10
BitsTypeResetNameDescription
12:0rw0x0ATTR_10

For MIO_PAD10


PINMUX.MIO_PAD_ATTR_11 @ 0x424

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_11
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_11
BitsTypeResetNameDescription
12:0rw0x0ATTR_11

For MIO_PAD11


PINMUX.MIO_PAD_ATTR_12 @ 0x428

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_12
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_12
BitsTypeResetNameDescription
12:0rw0x0ATTR_12

For MIO_PAD12


PINMUX.MIO_PAD_ATTR_13 @ 0x42c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_13
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_13
BitsTypeResetNameDescription
12:0rw0x0ATTR_13

For MIO_PAD13


PINMUX.MIO_PAD_ATTR_14 @ 0x430

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_14
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_14
BitsTypeResetNameDescription
12:0rw0x0ATTR_14

For MIO_PAD14


PINMUX.MIO_PAD_ATTR_15 @ 0x434

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_15
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_15
BitsTypeResetNameDescription
12:0rw0x0ATTR_15

For MIO_PAD15


PINMUX.MIO_PAD_ATTR_16 @ 0x438

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_16
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_16
BitsTypeResetNameDescription
12:0rw0x0ATTR_16

For MIO_PAD16


PINMUX.MIO_PAD_ATTR_17 @ 0x43c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_17
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_17
BitsTypeResetNameDescription
12:0rw0x0ATTR_17

For MIO_PAD17


PINMUX.MIO_PAD_ATTR_18 @ 0x440

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_18
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_18
BitsTypeResetNameDescription
12:0rw0x0ATTR_18

For MIO_PAD18


PINMUX.MIO_PAD_ATTR_19 @ 0x444

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_19
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_19
BitsTypeResetNameDescription
12:0rw0x0ATTR_19

For MIO_PAD19


PINMUX.MIO_PAD_ATTR_20 @ 0x448

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_20
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_20
BitsTypeResetNameDescription
12:0rw0x0ATTR_20

For MIO_PAD20


PINMUX.MIO_PAD_ATTR_21 @ 0x44c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_21
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_21
BitsTypeResetNameDescription
12:0rw0x0ATTR_21

For MIO_PAD21


PINMUX.MIO_PAD_ATTR_22 @ 0x450

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_22
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_22
BitsTypeResetNameDescription
12:0rw0x0ATTR_22

For MIO_PAD22


PINMUX.MIO_PAD_ATTR_23 @ 0x454

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_23
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_23
BitsTypeResetNameDescription
12:0rw0x0ATTR_23

For MIO_PAD23


PINMUX.MIO_PAD_ATTR_24 @ 0x458

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_24
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_24
BitsTypeResetNameDescription
12:0rw0x0ATTR_24

For MIO_PAD24


PINMUX.MIO_PAD_ATTR_25 @ 0x45c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_25
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_25
BitsTypeResetNameDescription
12:0rw0x0ATTR_25

For MIO_PAD25


PINMUX.MIO_PAD_ATTR_26 @ 0x460

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_26
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_26
BitsTypeResetNameDescription
12:0rw0x0ATTR_26

For MIO_PAD26


PINMUX.MIO_PAD_ATTR_27 @ 0x464

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_27
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_27
BitsTypeResetNameDescription
12:0rw0x0ATTR_27

For MIO_PAD27


PINMUX.MIO_PAD_ATTR_28 @ 0x468

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_28
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_28
BitsTypeResetNameDescription
12:0rw0x0ATTR_28

For MIO_PAD28


PINMUX.MIO_PAD_ATTR_29 @ 0x46c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_29
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_29
BitsTypeResetNameDescription
12:0rw0x0ATTR_29

For MIO_PAD29


PINMUX.MIO_PAD_ATTR_30 @ 0x470

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_30
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_30
BitsTypeResetNameDescription
12:0rw0x0ATTR_30

For MIO_PAD30


PINMUX.MIO_PAD_ATTR_31 @ 0x474

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_31
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_31
BitsTypeResetNameDescription
12:0rw0x0ATTR_31

For MIO_PAD31


PINMUX.MIO_PAD_ATTR_32 @ 0x478

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_32
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_32
BitsTypeResetNameDescription
12:0rw0x0ATTR_32

For MIO_PAD32


PINMUX.MIO_PAD_ATTR_33 @ 0x47c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_33
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_33
BitsTypeResetNameDescription
12:0rw0x0ATTR_33

For MIO_PAD33


PINMUX.MIO_PAD_ATTR_34 @ 0x480

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_34
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_34
BitsTypeResetNameDescription
12:0rw0x0ATTR_34

For MIO_PAD34


PINMUX.MIO_PAD_ATTR_35 @ 0x484

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_35
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_35
BitsTypeResetNameDescription
12:0rw0x0ATTR_35

For MIO_PAD35


PINMUX.MIO_PAD_ATTR_36 @ 0x488

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_36
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_36
BitsTypeResetNameDescription
12:0rw0x0ATTR_36

For MIO_PAD36


PINMUX.MIO_PAD_ATTR_37 @ 0x48c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_37
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_37
BitsTypeResetNameDescription
12:0rw0x0ATTR_37

For MIO_PAD37


PINMUX.MIO_PAD_ATTR_38 @ 0x490

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_38
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_38
BitsTypeResetNameDescription
12:0rw0x0ATTR_38

For MIO_PAD38


PINMUX.MIO_PAD_ATTR_39 @ 0x494

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_39
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_39
BitsTypeResetNameDescription
12:0rw0x0ATTR_39

For MIO_PAD39


PINMUX.MIO_PAD_ATTR_40 @ 0x498

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_40
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_40
BitsTypeResetNameDescription
12:0rw0x0ATTR_40

For MIO_PAD40


PINMUX.MIO_PAD_ATTR_41 @ 0x49c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_41
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_41
BitsTypeResetNameDescription
12:0rw0x0ATTR_41

For MIO_PAD41


PINMUX.MIO_PAD_ATTR_42 @ 0x4a0

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_42
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_42
BitsTypeResetNameDescription
12:0rw0x0ATTR_42

For MIO_PAD42


PINMUX.MIO_PAD_ATTR_43 @ 0x4a4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_43
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_43
BitsTypeResetNameDescription
12:0rw0x0ATTR_43

For MIO_PAD43


PINMUX.MIO_PAD_ATTR_44 @ 0x4a8

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_44
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_44
BitsTypeResetNameDescription
12:0rw0x0ATTR_44

For MIO_PAD44


PINMUX.MIO_PAD_ATTR_45 @ 0x4ac

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_45
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_45
BitsTypeResetNameDescription
12:0rw0x0ATTR_45

For MIO_PAD45


PINMUX.MIO_PAD_ATTR_46 @ 0x4b0

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = MIO_PAD_ATTR_REGWEN_46
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_46
BitsTypeResetNameDescription
12:0rw0x0ATTR_46

For MIO_PAD46


PINMUX.DIO_PAD_ATTR_REGWEN_0 @ 0x4b4

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_0
BitsTypeResetNameDescription
0rw0c0x1EN_0

Register write enable bit. If this is cleared to 0, the corresponding !!DIO_PAD_ATTR is not writable anymore.


PINMUX.DIO_PAD_ATTR_REGWEN_1 @ 0x4b8

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_1
BitsTypeResetNameDescription
0rw0c0x1EN_1

For DIO_PAD1


PINMUX.DIO_PAD_ATTR_REGWEN_2 @ 0x4bc

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_2
BitsTypeResetNameDescription
0rw0c0x1EN_2

For DIO_PAD2


PINMUX.DIO_PAD_ATTR_REGWEN_3 @ 0x4c0

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_3
BitsTypeResetNameDescription
0rw0c0x1EN_3

For DIO_PAD3


PINMUX.DIO_PAD_ATTR_REGWEN_4 @ 0x4c4

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_4
BitsTypeResetNameDescription
0rw0c0x1EN_4

For DIO_PAD4


PINMUX.DIO_PAD_ATTR_REGWEN_5 @ 0x4c8

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_5
BitsTypeResetNameDescription
0rw0c0x1EN_5

For DIO_PAD5


PINMUX.DIO_PAD_ATTR_REGWEN_6 @ 0x4cc

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_6
BitsTypeResetNameDescription
0rw0c0x1EN_6

For DIO_PAD6


PINMUX.DIO_PAD_ATTR_REGWEN_7 @ 0x4d0

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_7
BitsTypeResetNameDescription
0rw0c0x1EN_7

For DIO_PAD7


PINMUX.DIO_PAD_ATTR_REGWEN_8 @ 0x4d4

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_8
BitsTypeResetNameDescription
0rw0c0x1EN_8

For DIO_PAD8


PINMUX.DIO_PAD_ATTR_REGWEN_9 @ 0x4d8

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_9
BitsTypeResetNameDescription
0rw0c0x1EN_9

For DIO_PAD9


PINMUX.DIO_PAD_ATTR_REGWEN_10 @ 0x4dc

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_10
BitsTypeResetNameDescription
0rw0c0x1EN_10

For DIO_PAD10


PINMUX.DIO_PAD_ATTR_REGWEN_11 @ 0x4e0

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_11
BitsTypeResetNameDescription
0rw0c0x1EN_11

For DIO_PAD11


PINMUX.DIO_PAD_ATTR_REGWEN_12 @ 0x4e4

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_12
BitsTypeResetNameDescription
0rw0c0x1EN_12

For DIO_PAD12


PINMUX.DIO_PAD_ATTR_REGWEN_13 @ 0x4e8

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_13
BitsTypeResetNameDescription
0rw0c0x1EN_13

For DIO_PAD13


PINMUX.DIO_PAD_ATTR_REGWEN_14 @ 0x4ec

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_14
BitsTypeResetNameDescription
0rw0c0x1EN_14

For DIO_PAD14


PINMUX.DIO_PAD_ATTR_REGWEN_15 @ 0x4f0

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_15
BitsTypeResetNameDescription
0rw0c0x1EN_15

For DIO_PAD15


PINMUX.DIO_PAD_ATTR_REGWEN_16 @ 0x4f4

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_16
BitsTypeResetNameDescription
0rw0c0x1EN_16

For DIO_PAD16


PINMUX.DIO_PAD_ATTR_REGWEN_17 @ 0x4f8

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_17
BitsTypeResetNameDescription
0rw0c0x1EN_17

For DIO_PAD17


PINMUX.DIO_PAD_ATTR_REGWEN_18 @ 0x4fc

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_18
BitsTypeResetNameDescription
0rw0c0x1EN_18

For DIO_PAD18


PINMUX.DIO_PAD_ATTR_REGWEN_19 @ 0x500

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_19
BitsTypeResetNameDescription
0rw0c0x1EN_19

For DIO_PAD19


PINMUX.DIO_PAD_ATTR_REGWEN_20 @ 0x504

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_20
BitsTypeResetNameDescription
0rw0c0x1EN_20

For DIO_PAD20


PINMUX.DIO_PAD_ATTR_REGWEN_21 @ 0x508

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_21
BitsTypeResetNameDescription
0rw0c0x1EN_21

For DIO_PAD21


PINMUX.DIO_PAD_ATTR_REGWEN_22 @ 0x50c

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_22
BitsTypeResetNameDescription
0rw0c0x1EN_22

For DIO_PAD22


PINMUX.DIO_PAD_ATTR_REGWEN_23 @ 0x510

Register write enable for DIO PAD attributes.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_23
BitsTypeResetNameDescription
0rw0c0x1EN_23

For DIO_PAD23


PINMUX.DIO_PAD_ATTR_0 @ 0x514

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = DIO_PAD_ATTR_REGWEN_0
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_0
BitsTypeResetNameDescription
12:0rw0x0ATTR_0

Bit 0: input/output inversion, Bit 1: Virtual open drain enable. Bit 2: Pull enable. Bit 3: Pull select (0: pull down, 1: pull up). Bit 4: Keeper enable. Bit 5: Schmitt trigger enable. Bit 6: Open drain enable Bit 7/8: Slew rate (0x0: slowest, 0x3: fastest). Bit 9/12: Drive strength (0x0: weakest, 0xf: strongest).


PINMUX.DIO_PAD_ATTR_1 @ 0x518

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = DIO_PAD_ATTR_REGWEN_1
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_1
BitsTypeResetNameDescription
12:0rw0x0ATTR_1

For DIO_PAD1


PINMUX.DIO_PAD_ATTR_2 @ 0x51c

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = DIO_PAD_ATTR_REGWEN_2
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_2
BitsTypeResetNameDescription
12:0rw0x0ATTR_2

For DIO_PAD2


PINMUX.DIO_PAD_ATTR_3 @ 0x520

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = DIO_PAD_ATTR_REGWEN_3
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_3
BitsTypeResetNameDescription
12:0rw0x0ATTR_3

For DIO_PAD3


PINMUX.DIO_PAD_ATTR_4 @ 0x524

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = DIO_PAD_ATTR_REGWEN_4
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_4
BitsTypeResetNameDescription
12:0rw0x0ATTR_4

For DIO_PAD4


PINMUX.DIO_PAD_ATTR_5 @ 0x528

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = DIO_PAD_ATTR_REGWEN_5
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_5
BitsTypeResetNameDescription
12:0rw0x0ATTR_5

For DIO_PAD5


PINMUX.DIO_PAD_ATTR_6 @ 0x52c

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = DIO_PAD_ATTR_REGWEN_6
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_6
BitsTypeResetNameDescription
12:0rw0x0ATTR_6

For DIO_PAD6


PINMUX.DIO_PAD_ATTR_7 @ 0x530

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = DIO_PAD_ATTR_REGWEN_7
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_7
BitsTypeResetNameDescription
12:0rw0x0ATTR_7

For DIO_PAD7


PINMUX.DIO_PAD_ATTR_8 @ 0x534

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = DIO_PAD_ATTR_REGWEN_8
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_8
BitsTypeResetNameDescription
12:0rw0x0ATTR_8

For DIO_PAD8


PINMUX.DIO_PAD_ATTR_9 @ 0x538

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = DIO_PAD_ATTR_REGWEN_9
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_9
BitsTypeResetNameDescription
12:0rw0x0ATTR_9

For DIO_PAD9


PINMUX.DIO_PAD_ATTR_10 @ 0x53c

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = DIO_PAD_ATTR_REGWEN_10
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_10
BitsTypeResetNameDescription
12:0rw0x0ATTR_10

For DIO_PAD10


PINMUX.DIO_PAD_ATTR_11 @ 0x540

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = DIO_PAD_ATTR_REGWEN_11
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_11
BitsTypeResetNameDescription
12:0rw0x0ATTR_11

For DIO_PAD11


PINMUX.DIO_PAD_ATTR_12 @ 0x544

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = DIO_PAD_ATTR_REGWEN_12
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_12
BitsTypeResetNameDescription
12:0rw0x0ATTR_12

For DIO_PAD12


PINMUX.DIO_PAD_ATTR_13 @ 0x548

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = DIO_PAD_ATTR_REGWEN_13
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_13
BitsTypeResetNameDescription
12:0rw0x0ATTR_13

For DIO_PAD13


PINMUX.DIO_PAD_ATTR_14 @ 0x54c

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = DIO_PAD_ATTR_REGWEN_14
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_14
BitsTypeResetNameDescription
12:0rw0x0ATTR_14

For DIO_PAD14


PINMUX.DIO_PAD_ATTR_15 @ 0x550

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = DIO_PAD_ATTR_REGWEN_15
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_15
BitsTypeResetNameDescription
12:0rw0x0ATTR_15

For DIO_PAD15


PINMUX.DIO_PAD_ATTR_16 @ 0x554

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = DIO_PAD_ATTR_REGWEN_16
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_16
BitsTypeResetNameDescription
12:0rw0x0ATTR_16

For DIO_PAD16


PINMUX.DIO_PAD_ATTR_17 @ 0x558

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = DIO_PAD_ATTR_REGWEN_17
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_17
BitsTypeResetNameDescription
12:0rw0x0ATTR_17

For DIO_PAD17


PINMUX.DIO_PAD_ATTR_18 @ 0x55c

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = DIO_PAD_ATTR_REGWEN_18
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_18
BitsTypeResetNameDescription
12:0rw0x0ATTR_18

For DIO_PAD18


PINMUX.DIO_PAD_ATTR_19 @ 0x560

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = DIO_PAD_ATTR_REGWEN_19
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_19
BitsTypeResetNameDescription
12:0rw0x0ATTR_19

For DIO_PAD19


PINMUX.DIO_PAD_ATTR_20 @ 0x564

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = DIO_PAD_ATTR_REGWEN_20
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_20
BitsTypeResetNameDescription
12:0rw0x0ATTR_20

For DIO_PAD20


PINMUX.DIO_PAD_ATTR_21 @ 0x568

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = DIO_PAD_ATTR_REGWEN_21
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_21
BitsTypeResetNameDescription
12:0rw0x0ATTR_21

For DIO_PAD21


PINMUX.DIO_PAD_ATTR_22 @ 0x56c

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = DIO_PAD_ATTR_REGWEN_22
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_22
BitsTypeResetNameDescription
12:0rw0x0ATTR_22

For DIO_PAD22


PINMUX.DIO_PAD_ATTR_23 @ 0x570

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0x1fff
Register enable = DIO_PAD_ATTR_REGWEN_23
31302928272625242322212019181716
 
1514131211109876543210
  ATTR_23
BitsTypeResetNameDescription
12:0rw0x0ATTR_23

For DIO_PAD23


PINMUX.MIO_PAD_SLEEP_STATUS_0 @ 0x574

Register indicating whether the corresponding pad is in sleep mode.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
EN_31 EN_30 EN_29 EN_28 EN_27 EN_26 EN_25 EN_24 EN_23 EN_22 EN_21 EN_20 EN_19 EN_18 EN_17 EN_16
1514131211109876543210
EN_15 EN_14 EN_13 EN_12 EN_11 EN_10 EN_9 EN_8 EN_7 EN_6 EN_5 EN_4 EN_3 EN_2 EN_1 EN_0
BitsTypeResetNameDescription
0rw0c0x0EN_0

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

1rw0c0x0EN_1

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

2rw0c0x0EN_2

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

3rw0c0x0EN_3

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

4rw0c0x0EN_4

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

5rw0c0x0EN_5

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

6rw0c0x0EN_6

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

7rw0c0x0EN_7

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

8rw0c0x0EN_8

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

9rw0c0x0EN_9

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

10rw0c0x0EN_10

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

11rw0c0x0EN_11

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

12rw0c0x0EN_12

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

13rw0c0x0EN_13

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

14rw0c0x0EN_14

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

15rw0c0x0EN_15

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

16rw0c0x0EN_16

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

17rw0c0x0EN_17

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

18rw0c0x0EN_18

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

19rw0c0x0EN_19

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

20rw0c0x0EN_20

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

21rw0c0x0EN_21

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

22rw0c0x0EN_22

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

23rw0c0x0EN_23

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

24rw0c0x0EN_24

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

25rw0c0x0EN_25

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

26rw0c0x0EN_26

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

27rw0c0x0EN_27

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

28rw0c0x0EN_28

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

29rw0c0x0EN_29

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

30rw0c0x0EN_30

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

31rw0c0x0EN_31

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.


PINMUX.MIO_PAD_SLEEP_STATUS_1 @ 0x578

Register indicating whether the corresponding pad is in sleep mode.

Reset default = 0x0, mask 0x7fff
31302928272625242322212019181716
 
1514131211109876543210
  EN_46 EN_45 EN_44 EN_43 EN_42 EN_41 EN_40 EN_39 EN_38 EN_37 EN_36 EN_35 EN_34 EN_33 EN_32
BitsTypeResetNameDescription
0rw0c0x0EN_32

For MIO_PAD1

1rw0c0x0EN_33

For MIO_PAD1

2rw0c0x0EN_34

For MIO_PAD1

3rw0c0x0EN_35

For MIO_PAD1

4rw0c0x0EN_36

For MIO_PAD1

5rw0c0x0EN_37

For MIO_PAD1

6rw0c0x0EN_38

For MIO_PAD1

7rw0c0x0EN_39

For MIO_PAD1

8rw0c0x0EN_40

For MIO_PAD1

9rw0c0x0EN_41

For MIO_PAD1

10rw0c0x0EN_42

For MIO_PAD1

11rw0c0x0EN_43

For MIO_PAD1

12rw0c0x0EN_44

For MIO_PAD1

13rw0c0x0EN_45

For MIO_PAD1

14rw0c0x0EN_46

For MIO_PAD1


PINMUX.MIO_PAD_SLEEP_REGWEN_0 @ 0x57c

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_0
BitsTypeResetNameDescription
0rw0c0x1EN_0

Register write enable bit. If this is cleared to 0, the corresponding !!MIO_OUT_SLEEP_MODE is not writable anymore.


PINMUX.MIO_PAD_SLEEP_REGWEN_1 @ 0x580

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_1
BitsTypeResetNameDescription
0rw0c0x1EN_1

For MIO_PAD1


PINMUX.MIO_PAD_SLEEP_REGWEN_2 @ 0x584

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_2
BitsTypeResetNameDescription
0rw0c0x1EN_2

For MIO_PAD2


PINMUX.MIO_PAD_SLEEP_REGWEN_3 @ 0x588

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_3
BitsTypeResetNameDescription
0rw0c0x1EN_3

For MIO_PAD3


PINMUX.MIO_PAD_SLEEP_REGWEN_4 @ 0x58c

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_4
BitsTypeResetNameDescription
0rw0c0x1EN_4

For MIO_PAD4


PINMUX.MIO_PAD_SLEEP_REGWEN_5 @ 0x590

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_5
BitsTypeResetNameDescription
0rw0c0x1EN_5

For MIO_PAD5


PINMUX.MIO_PAD_SLEEP_REGWEN_6 @ 0x594

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_6
BitsTypeResetNameDescription
0rw0c0x1EN_6

For MIO_PAD6


PINMUX.MIO_PAD_SLEEP_REGWEN_7 @ 0x598

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_7
BitsTypeResetNameDescription
0rw0c0x1EN_7

For MIO_PAD7


PINMUX.MIO_PAD_SLEEP_REGWEN_8 @ 0x59c

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_8
BitsTypeResetNameDescription
0rw0c0x1EN_8

For MIO_PAD8


PINMUX.MIO_PAD_SLEEP_REGWEN_9 @ 0x5a0

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_9
BitsTypeResetNameDescription
0rw0c0x1EN_9

For MIO_PAD9


PINMUX.MIO_PAD_SLEEP_REGWEN_10 @ 0x5a4

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_10
BitsTypeResetNameDescription
0rw0c0x1EN_10

For MIO_PAD10


PINMUX.MIO_PAD_SLEEP_REGWEN_11 @ 0x5a8

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_11
BitsTypeResetNameDescription
0rw0c0x1EN_11

For MIO_PAD11


PINMUX.MIO_PAD_SLEEP_REGWEN_12 @ 0x5ac

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_12
BitsTypeResetNameDescription
0rw0c0x1EN_12

For MIO_PAD12


PINMUX.MIO_PAD_SLEEP_REGWEN_13 @ 0x5b0

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_13
BitsTypeResetNameDescription
0rw0c0x1EN_13

For MIO_PAD13


PINMUX.MIO_PAD_SLEEP_REGWEN_14 @ 0x5b4

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_14
BitsTypeResetNameDescription
0rw0c0x1EN_14

For MIO_PAD14


PINMUX.MIO_PAD_SLEEP_REGWEN_15 @ 0x5b8

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_15
BitsTypeResetNameDescription
0rw0c0x1EN_15

For MIO_PAD15


PINMUX.MIO_PAD_SLEEP_REGWEN_16 @ 0x5bc

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_16
BitsTypeResetNameDescription
0rw0c0x1EN_16

For MIO_PAD16


PINMUX.MIO_PAD_SLEEP_REGWEN_17 @ 0x5c0

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_17
BitsTypeResetNameDescription
0rw0c0x1EN_17

For MIO_PAD17


PINMUX.MIO_PAD_SLEEP_REGWEN_18 @ 0x5c4

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_18
BitsTypeResetNameDescription
0rw0c0x1EN_18

For MIO_PAD18


PINMUX.MIO_PAD_SLEEP_REGWEN_19 @ 0x5c8

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_19
BitsTypeResetNameDescription
0rw0c0x1EN_19

For MIO_PAD19


PINMUX.MIO_PAD_SLEEP_REGWEN_20 @ 0x5cc

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_20
BitsTypeResetNameDescription
0rw0c0x1EN_20

For MIO_PAD20


PINMUX.MIO_PAD_SLEEP_REGWEN_21 @ 0x5d0

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_21
BitsTypeResetNameDescription
0rw0c0x1EN_21

For MIO_PAD21


PINMUX.MIO_PAD_SLEEP_REGWEN_22 @ 0x5d4

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_22
BitsTypeResetNameDescription
0rw0c0x1EN_22

For MIO_PAD22


PINMUX.MIO_PAD_SLEEP_REGWEN_23 @ 0x5d8

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_23
BitsTypeResetNameDescription
0rw0c0x1EN_23

For MIO_PAD23


PINMUX.MIO_PAD_SLEEP_REGWEN_24 @ 0x5dc

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_24
BitsTypeResetNameDescription
0rw0c0x1EN_24

For MIO_PAD24


PINMUX.MIO_PAD_SLEEP_REGWEN_25 @ 0x5e0

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_25
BitsTypeResetNameDescription
0rw0c0x1EN_25

For MIO_PAD25


PINMUX.MIO_PAD_SLEEP_REGWEN_26 @ 0x5e4

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_26
BitsTypeResetNameDescription
0rw0c0x1EN_26

For MIO_PAD26


PINMUX.MIO_PAD_SLEEP_REGWEN_27 @ 0x5e8

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_27
BitsTypeResetNameDescription
0rw0c0x1EN_27

For MIO_PAD27


PINMUX.MIO_PAD_SLEEP_REGWEN_28 @ 0x5ec

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_28
BitsTypeResetNameDescription
0rw0c0x1EN_28

For MIO_PAD28


PINMUX.MIO_PAD_SLEEP_REGWEN_29 @ 0x5f0

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_29
BitsTypeResetNameDescription
0rw0c0x1EN_29

For MIO_PAD29


PINMUX.MIO_PAD_SLEEP_REGWEN_30 @ 0x5f4

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_30
BitsTypeResetNameDescription
0rw0c0x1EN_30

For MIO_PAD30


PINMUX.MIO_PAD_SLEEP_REGWEN_31 @ 0x5f8

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_31
BitsTypeResetNameDescription
0rw0c0x1EN_31

For MIO_PAD31


PINMUX.MIO_PAD_SLEEP_REGWEN_32 @ 0x5fc

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_32
BitsTypeResetNameDescription
0rw0c0x1EN_32

For MIO_PAD32


PINMUX.MIO_PAD_SLEEP_REGWEN_33 @ 0x600

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_33
BitsTypeResetNameDescription
0rw0c0x1EN_33

For MIO_PAD33


PINMUX.MIO_PAD_SLEEP_REGWEN_34 @ 0x604

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_34
BitsTypeResetNameDescription
0rw0c0x1EN_34

For MIO_PAD34


PINMUX.MIO_PAD_SLEEP_REGWEN_35 @ 0x608

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_35
BitsTypeResetNameDescription
0rw0c0x1EN_35

For MIO_PAD35


PINMUX.MIO_PAD_SLEEP_REGWEN_36 @ 0x60c

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_36
BitsTypeResetNameDescription
0rw0c0x1EN_36

For MIO_PAD36


PINMUX.MIO_PAD_SLEEP_REGWEN_37 @ 0x610

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_37
BitsTypeResetNameDescription
0rw0c0x1EN_37

For MIO_PAD37


PINMUX.MIO_PAD_SLEEP_REGWEN_38 @ 0x614

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_38
BitsTypeResetNameDescription
0rw0c0x1EN_38

For MIO_PAD38


PINMUX.MIO_PAD_SLEEP_REGWEN_39 @ 0x618

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_39
BitsTypeResetNameDescription
0rw0c0x1EN_39

For MIO_PAD39


PINMUX.MIO_PAD_SLEEP_REGWEN_40 @ 0x61c

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_40
BitsTypeResetNameDescription
0rw0c0x1EN_40

For MIO_PAD40


PINMUX.MIO_PAD_SLEEP_REGWEN_41 @ 0x620

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_41
BitsTypeResetNameDescription
0rw0c0x1EN_41

For MIO_PAD41


PINMUX.MIO_PAD_SLEEP_REGWEN_42 @ 0x624

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_42
BitsTypeResetNameDescription
0rw0c0x1EN_42

For MIO_PAD42


PINMUX.MIO_PAD_SLEEP_REGWEN_43 @ 0x628

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  EN_43
BitsTypeResetNameDescription
0rw0c0x1EN_43

For MIO_PAD43


PINMUX.MIO_PAD_SLEEP_REGWEN_44 @ 0x62c

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_44
BitsTypeResetNameDescription
0rw0c0x1EN_44

For MIO_PAD44


PINMUX.MIO_PAD_SLEEP_REGWEN_45 @ 0x630

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_45
BitsTypeResetNameDescription
0rw0c0x1EN_45

For MIO_PAD45


PINMUX.MIO_PAD_SLEEP_REGWEN_46 @ 0x634

Register write enable for MIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_46
BitsTypeResetNameDescription
0rw0c0x1EN_46

For MIO_PAD46


PINMUX.MIO_PAD_SLEEP_EN_0 @ 0x638

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_0
31302928272625242322212019181716
 
1514131211109876543210
  EN_0
BitsTypeResetNameDescription
0rw0x0EN_0

Deep sleep mode enable. If this bit is set to 1 the corresponding pad will enable the sleep behavior specified in !!MIO_PAD_SLEEP_MODE upon deep sleep entry, and the corresponding bit in !!MIO_PAD_SLEEP_STATUS will be set to 1. The pad remains in deep sleep mode until the corresponding bit in !!MIO_PAD_SLEEP_STATUS is cleared by SW. Note that if an always on peripheral is connected to a specific MIO pad, the corresponding !!MIO_PAD_SLEEP_EN bit should be set to 0.


PINMUX.MIO_PAD_SLEEP_EN_1 @ 0x63c

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_1
31302928272625242322212019181716
 
1514131211109876543210
  EN_1
BitsTypeResetNameDescription
0rw0x0EN_1

For OUT1


PINMUX.MIO_PAD_SLEEP_EN_2 @ 0x640

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_2
31302928272625242322212019181716
 
1514131211109876543210
  EN_2
BitsTypeResetNameDescription
0rw0x0EN_2

For OUT2


PINMUX.MIO_PAD_SLEEP_EN_3 @ 0x644

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_3
31302928272625242322212019181716
 
1514131211109876543210
  EN_3
BitsTypeResetNameDescription
0rw0x0EN_3

For OUT3


PINMUX.MIO_PAD_SLEEP_EN_4 @ 0x648

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_4
31302928272625242322212019181716
 
1514131211109876543210
  EN_4
BitsTypeResetNameDescription
0rw0x0EN_4

For OUT4


PINMUX.MIO_PAD_SLEEP_EN_5 @ 0x64c

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_5
31302928272625242322212019181716
 
1514131211109876543210
  EN_5
BitsTypeResetNameDescription
0rw0x0EN_5

For OUT5


PINMUX.MIO_PAD_SLEEP_EN_6 @ 0x650

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_6
31302928272625242322212019181716
 
1514131211109876543210
  EN_6
BitsTypeResetNameDescription
0rw0x0EN_6

For OUT6


PINMUX.MIO_PAD_SLEEP_EN_7 @ 0x654

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_7
31302928272625242322212019181716
 
1514131211109876543210
  EN_7
BitsTypeResetNameDescription
0rw0x0EN_7

For OUT7


PINMUX.MIO_PAD_SLEEP_EN_8 @ 0x658

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_8
31302928272625242322212019181716
 
1514131211109876543210
  EN_8
BitsTypeResetNameDescription
0rw0x0EN_8

For OUT8


PINMUX.MIO_PAD_SLEEP_EN_9 @ 0x65c

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_9
31302928272625242322212019181716
 
1514131211109876543210
  EN_9
BitsTypeResetNameDescription
0rw0x0EN_9

For OUT9


PINMUX.MIO_PAD_SLEEP_EN_10 @ 0x660

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_10
31302928272625242322212019181716
 
1514131211109876543210
  EN_10
BitsTypeResetNameDescription
0rw0x0EN_10

For OUT10


PINMUX.MIO_PAD_SLEEP_EN_11 @ 0x664

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_11
31302928272625242322212019181716
 
1514131211109876543210
  EN_11
BitsTypeResetNameDescription
0rw0x0EN_11

For OUT11


PINMUX.MIO_PAD_SLEEP_EN_12 @ 0x668

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_12
31302928272625242322212019181716
 
1514131211109876543210
  EN_12
BitsTypeResetNameDescription
0rw0x0EN_12

For OUT12


PINMUX.MIO_PAD_SLEEP_EN_13 @ 0x66c

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_13
31302928272625242322212019181716
 
1514131211109876543210
  EN_13
BitsTypeResetNameDescription
0rw0x0EN_13

For OUT13


PINMUX.MIO_PAD_SLEEP_EN_14 @ 0x670

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_14
31302928272625242322212019181716
 
1514131211109876543210
  EN_14
BitsTypeResetNameDescription
0rw0x0EN_14

For OUT14


PINMUX.MIO_PAD_SLEEP_EN_15 @ 0x674

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_15
31302928272625242322212019181716
 
1514131211109876543210
  EN_15
BitsTypeResetNameDescription
0rw0x0EN_15

For OUT15


PINMUX.MIO_PAD_SLEEP_EN_16 @ 0x678

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_16
31302928272625242322212019181716
 
1514131211109876543210
  EN_16
BitsTypeResetNameDescription
0rw0x0EN_16

For OUT16


PINMUX.MIO_PAD_SLEEP_EN_17 @ 0x67c

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_17
31302928272625242322212019181716
 
1514131211109876543210
  EN_17
BitsTypeResetNameDescription
0rw0x0EN_17

For OUT17


PINMUX.MIO_PAD_SLEEP_EN_18 @ 0x680

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_18
31302928272625242322212019181716
 
1514131211109876543210
  EN_18
BitsTypeResetNameDescription
0rw0x0EN_18

For OUT18


PINMUX.MIO_PAD_SLEEP_EN_19 @ 0x684

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_19
31302928272625242322212019181716
 
1514131211109876543210
  EN_19
BitsTypeResetNameDescription
0rw0x0EN_19

For OUT19


PINMUX.MIO_PAD_SLEEP_EN_20 @ 0x688

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_20
31302928272625242322212019181716
 
1514131211109876543210
  EN_20
BitsTypeResetNameDescription
0rw0x0EN_20

For OUT20


PINMUX.MIO_PAD_SLEEP_EN_21 @ 0x68c

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_21
31302928272625242322212019181716
 
1514131211109876543210
  EN_21
BitsTypeResetNameDescription
0rw0x0EN_21

For OUT21


PINMUX.MIO_PAD_SLEEP_EN_22 @ 0x690

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_22
31302928272625242322212019181716
 
1514131211109876543210
  EN_22
BitsTypeResetNameDescription
0rw0x0EN_22

For OUT22


PINMUX.MIO_PAD_SLEEP_EN_23 @ 0x694

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_23
31302928272625242322212019181716
 
1514131211109876543210
  EN_23
BitsTypeResetNameDescription
0rw0x0EN_23

For OUT23


PINMUX.MIO_PAD_SLEEP_EN_24 @ 0x698

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_24
31302928272625242322212019181716
 
1514131211109876543210
  EN_24
BitsTypeResetNameDescription
0rw0x0EN_24

For OUT24


PINMUX.MIO_PAD_SLEEP_EN_25 @ 0x69c

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_25
31302928272625242322212019181716
 
1514131211109876543210
  EN_25
BitsTypeResetNameDescription
0rw0x0EN_25

For OUT25


PINMUX.MIO_PAD_SLEEP_EN_26 @ 0x6a0

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_26
31302928272625242322212019181716
 
1514131211109876543210
  EN_26
BitsTypeResetNameDescription
0rw0x0EN_26

For OUT26


PINMUX.MIO_PAD_SLEEP_EN_27 @ 0x6a4

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_27
31302928272625242322212019181716
 
1514131211109876543210
  EN_27
BitsTypeResetNameDescription
0rw0x0EN_27

For OUT27


PINMUX.MIO_PAD_SLEEP_EN_28 @ 0x6a8

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_28
31302928272625242322212019181716
 
1514131211109876543210
  EN_28
BitsTypeResetNameDescription
0rw0x0EN_28

For OUT28


PINMUX.MIO_PAD_SLEEP_EN_29 @ 0x6ac

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_29
31302928272625242322212019181716
 
1514131211109876543210
  EN_29
BitsTypeResetNameDescription
0rw0x0EN_29

For OUT29


PINMUX.MIO_PAD_SLEEP_EN_30 @ 0x6b0

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_30
31302928272625242322212019181716
 
1514131211109876543210
  EN_30
BitsTypeResetNameDescription
0rw0x0EN_30

For OUT30


PINMUX.MIO_PAD_SLEEP_EN_31 @ 0x6b4

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_31
31302928272625242322212019181716
 
1514131211109876543210
  EN_31
BitsTypeResetNameDescription
0rw0x0EN_31

For OUT31


PINMUX.MIO_PAD_SLEEP_EN_32 @ 0x6b8

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_32
31302928272625242322212019181716
 
1514131211109876543210
  EN_32
BitsTypeResetNameDescription
0rw0x0EN_32

For OUT32


PINMUX.MIO_PAD_SLEEP_EN_33 @ 0x6bc

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_33
31302928272625242322212019181716
 
1514131211109876543210
  EN_33
BitsTypeResetNameDescription
0rw0x0EN_33

For OUT33


PINMUX.MIO_PAD_SLEEP_EN_34 @ 0x6c0

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_34
31302928272625242322212019181716
 
1514131211109876543210
  EN_34
BitsTypeResetNameDescription
0rw0x0EN_34

For OUT34


PINMUX.MIO_PAD_SLEEP_EN_35 @ 0x6c4

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_35
31302928272625242322212019181716
 
1514131211109876543210
  EN_35
BitsTypeResetNameDescription
0rw0x0EN_35

For OUT35


PINMUX.MIO_PAD_SLEEP_EN_36 @ 0x6c8

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_36
31302928272625242322212019181716
 
1514131211109876543210
  EN_36
BitsTypeResetNameDescription
0rw0x0EN_36

For OUT36


PINMUX.MIO_PAD_SLEEP_EN_37 @ 0x6cc

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_37
31302928272625242322212019181716
 
1514131211109876543210
  EN_37
BitsTypeResetNameDescription
0rw0x0EN_37

For OUT37


PINMUX.MIO_PAD_SLEEP_EN_38 @ 0x6d0

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_38
31302928272625242322212019181716
 
1514131211109876543210
  EN_38
BitsTypeResetNameDescription
0rw0x0EN_38

For OUT38


PINMUX.MIO_PAD_SLEEP_EN_39 @ 0x6d4

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_39
31302928272625242322212019181716
 
1514131211109876543210
  EN_39
BitsTypeResetNameDescription
0rw0x0EN_39

For OUT39


PINMUX.MIO_PAD_SLEEP_EN_40 @ 0x6d8

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_40
31302928272625242322212019181716
 
1514131211109876543210
  EN_40
BitsTypeResetNameDescription
0rw0x0EN_40

For OUT40


PINMUX.MIO_PAD_SLEEP_EN_41 @ 0x6dc

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_41
31302928272625242322212019181716
 
1514131211109876543210
  EN_41
BitsTypeResetNameDescription
0rw0x0EN_41

For OUT41


PINMUX.MIO_PAD_SLEEP_EN_42 @ 0x6e0

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_42
31302928272625242322212019181716
 
1514131211109876543210
  EN_42
BitsTypeResetNameDescription
0rw0x0EN_42

For OUT42


PINMUX.MIO_PAD_SLEEP_EN_43 @ 0x6e4

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_43
31302928272625242322212019181716
 
1514131211109876543210
  EN_43
BitsTypeResetNameDescription
0rw0x0EN_43

For OUT43


PINMUX.MIO_PAD_SLEEP_EN_44 @ 0x6e8

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_44
31302928272625242322212019181716
 
1514131211109876543210
  EN_44
BitsTypeResetNameDescription
0rw0x0EN_44

For OUT44


PINMUX.MIO_PAD_SLEEP_EN_45 @ 0x6ec

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_45
31302928272625242322212019181716
 
1514131211109876543210
  EN_45
BitsTypeResetNameDescription
0rw0x0EN_45

For OUT45


PINMUX.MIO_PAD_SLEEP_EN_46 @ 0x6f0

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1
Register enable = MIO_PAD_SLEEP_REGWEN_46
31302928272625242322212019181716
 
1514131211109876543210
  EN_46
BitsTypeResetNameDescription
0rw0x0EN_46

For OUT46


PINMUX.MIO_PAD_SLEEP_MODE_0 @ 0x6f4

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_0
31302928272625242322212019181716
 
1514131211109876543210
  OUT_0
BitsTypeResetNameDescription
1:0rw0x2OUT_0

Value to drive in deep sleep.

0Tie-Low

The pad is driven actively to zero in deep sleep mode.

1Tie-High

The pad is driven actively to one in deep sleep mode.

2High-Z

The pad is left undriven in deep sleep mode. Note that the actual driving behavior during deep sleep will then depend on the pull-up/-down configuration of in !!MIO_PAD_ATTR.

3Keep

Keep last driven value (including high-Z).


PINMUX.MIO_PAD_SLEEP_MODE_1 @ 0x6f8

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_1
31302928272625242322212019181716
 
1514131211109876543210
  OUT_1
BitsTypeResetNameDescription
1:0rw0x2OUT_1

For OUT1


PINMUX.MIO_PAD_SLEEP_MODE_2 @ 0x6fc

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_2
31302928272625242322212019181716
 
1514131211109876543210
  OUT_2
BitsTypeResetNameDescription
1:0rw0x2OUT_2

For OUT2


PINMUX.MIO_PAD_SLEEP_MODE_3 @ 0x700

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_3
31302928272625242322212019181716
 
1514131211109876543210
  OUT_3
BitsTypeResetNameDescription
1:0rw0x2OUT_3

For OUT3


PINMUX.MIO_PAD_SLEEP_MODE_4 @ 0x704

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_4
31302928272625242322212019181716
 
1514131211109876543210
  OUT_4
BitsTypeResetNameDescription
1:0rw0x2OUT_4

For OUT4


PINMUX.MIO_PAD_SLEEP_MODE_5 @ 0x708

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_5
31302928272625242322212019181716
 
1514131211109876543210
  OUT_5
BitsTypeResetNameDescription
1:0rw0x2OUT_5

For OUT5


PINMUX.MIO_PAD_SLEEP_MODE_6 @ 0x70c

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_6
31302928272625242322212019181716
 
1514131211109876543210
  OUT_6
BitsTypeResetNameDescription
1:0rw0x2OUT_6

For OUT6


PINMUX.MIO_PAD_SLEEP_MODE_7 @ 0x710

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_7
31302928272625242322212019181716
 
1514131211109876543210
  OUT_7
BitsTypeResetNameDescription
1:0rw0x2OUT_7

For OUT7


PINMUX.MIO_PAD_SLEEP_MODE_8 @ 0x714

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_8
31302928272625242322212019181716
 
1514131211109876543210
  OUT_8
BitsTypeResetNameDescription
1:0rw0x2OUT_8

For OUT8


PINMUX.MIO_PAD_SLEEP_MODE_9 @ 0x718

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_9
31302928272625242322212019181716
 
1514131211109876543210
  OUT_9
BitsTypeResetNameDescription
1:0rw0x2OUT_9

For OUT9


PINMUX.MIO_PAD_SLEEP_MODE_10 @ 0x71c

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_10
31302928272625242322212019181716
 
1514131211109876543210
  OUT_10
BitsTypeResetNameDescription
1:0rw0x2OUT_10

For OUT10


PINMUX.MIO_PAD_SLEEP_MODE_11 @ 0x720

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_11
31302928272625242322212019181716
 
1514131211109876543210
  OUT_11
BitsTypeResetNameDescription
1:0rw0x2OUT_11

For OUT11


PINMUX.MIO_PAD_SLEEP_MODE_12 @ 0x724

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_12
31302928272625242322212019181716
 
1514131211109876543210
  OUT_12
BitsTypeResetNameDescription
1:0rw0x2OUT_12

For OUT12


PINMUX.MIO_PAD_SLEEP_MODE_13 @ 0x728

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_13
31302928272625242322212019181716
 
1514131211109876543210
  OUT_13
BitsTypeResetNameDescription
1:0rw0x2OUT_13

For OUT13


PINMUX.MIO_PAD_SLEEP_MODE_14 @ 0x72c

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_14
31302928272625242322212019181716
 
1514131211109876543210
  OUT_14
BitsTypeResetNameDescription
1:0rw0x2OUT_14

For OUT14


PINMUX.MIO_PAD_SLEEP_MODE_15 @ 0x730

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_15
31302928272625242322212019181716
 
1514131211109876543210
  OUT_15
BitsTypeResetNameDescription
1:0rw0x2OUT_15

For OUT15


PINMUX.MIO_PAD_SLEEP_MODE_16 @ 0x734

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_16
31302928272625242322212019181716
 
1514131211109876543210
  OUT_16
BitsTypeResetNameDescription
1:0rw0x2OUT_16

For OUT16


PINMUX.MIO_PAD_SLEEP_MODE_17 @ 0x738

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_17
31302928272625242322212019181716
 
1514131211109876543210
  OUT_17
BitsTypeResetNameDescription
1:0rw0x2OUT_17

For OUT17


PINMUX.MIO_PAD_SLEEP_MODE_18 @ 0x73c

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_18
31302928272625242322212019181716
 
1514131211109876543210
  OUT_18
BitsTypeResetNameDescription
1:0rw0x2OUT_18

For OUT18


PINMUX.MIO_PAD_SLEEP_MODE_19 @ 0x740

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_19
31302928272625242322212019181716
 
1514131211109876543210
  OUT_19
BitsTypeResetNameDescription
1:0rw0x2OUT_19

For OUT19


PINMUX.MIO_PAD_SLEEP_MODE_20 @ 0x744

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_20
31302928272625242322212019181716
 
1514131211109876543210
  OUT_20
BitsTypeResetNameDescription
1:0rw0x2OUT_20

For OUT20


PINMUX.MIO_PAD_SLEEP_MODE_21 @ 0x748

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_21
31302928272625242322212019181716
 
1514131211109876543210
  OUT_21
BitsTypeResetNameDescription
1:0rw0x2OUT_21

For OUT21


PINMUX.MIO_PAD_SLEEP_MODE_22 @ 0x74c

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_22
31302928272625242322212019181716
 
1514131211109876543210
  OUT_22
BitsTypeResetNameDescription
1:0rw0x2OUT_22

For OUT22


PINMUX.MIO_PAD_SLEEP_MODE_23 @ 0x750

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_23
31302928272625242322212019181716
 
1514131211109876543210
  OUT_23
BitsTypeResetNameDescription
1:0rw0x2OUT_23

For OUT23


PINMUX.MIO_PAD_SLEEP_MODE_24 @ 0x754

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_24
31302928272625242322212019181716
 
1514131211109876543210
  OUT_24
BitsTypeResetNameDescription
1:0rw0x2OUT_24

For OUT24


PINMUX.MIO_PAD_SLEEP_MODE_25 @ 0x758

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_25
31302928272625242322212019181716
 
1514131211109876543210
  OUT_25
BitsTypeResetNameDescription
1:0rw0x2OUT_25

For OUT25


PINMUX.MIO_PAD_SLEEP_MODE_26 @ 0x75c

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_26
31302928272625242322212019181716
 
1514131211109876543210
  OUT_26
BitsTypeResetNameDescription
1:0rw0x2OUT_26

For OUT26


PINMUX.MIO_PAD_SLEEP_MODE_27 @ 0x760

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_27
31302928272625242322212019181716
 
1514131211109876543210
  OUT_27
BitsTypeResetNameDescription
1:0rw0x2OUT_27

For OUT27


PINMUX.MIO_PAD_SLEEP_MODE_28 @ 0x764

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_28
31302928272625242322212019181716
 
1514131211109876543210
  OUT_28
BitsTypeResetNameDescription
1:0rw0x2OUT_28

For OUT28


PINMUX.MIO_PAD_SLEEP_MODE_29 @ 0x768

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_29
31302928272625242322212019181716
 
1514131211109876543210
  OUT_29
BitsTypeResetNameDescription
1:0rw0x2OUT_29

For OUT29


PINMUX.MIO_PAD_SLEEP_MODE_30 @ 0x76c

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_30
31302928272625242322212019181716
 
1514131211109876543210
  OUT_30
BitsTypeResetNameDescription
1:0rw0x2OUT_30

For OUT30


PINMUX.MIO_PAD_SLEEP_MODE_31 @ 0x770

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_31
31302928272625242322212019181716
 
1514131211109876543210
  OUT_31
BitsTypeResetNameDescription
1:0rw0x2OUT_31

For OUT31


PINMUX.MIO_PAD_SLEEP_MODE_32 @ 0x774

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_32
31302928272625242322212019181716
 
1514131211109876543210
  OUT_32
BitsTypeResetNameDescription
1:0rw0x2OUT_32

For OUT32


PINMUX.MIO_PAD_SLEEP_MODE_33 @ 0x778

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_33
31302928272625242322212019181716
 
1514131211109876543210
  OUT_33
BitsTypeResetNameDescription
1:0rw0x2OUT_33

For OUT33


PINMUX.MIO_PAD_SLEEP_MODE_34 @ 0x77c

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_34
31302928272625242322212019181716
 
1514131211109876543210
  OUT_34
BitsTypeResetNameDescription
1:0rw0x2OUT_34

For OUT34


PINMUX.MIO_PAD_SLEEP_MODE_35 @ 0x780

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_35
31302928272625242322212019181716
 
1514131211109876543210
  OUT_35
BitsTypeResetNameDescription
1:0rw0x2OUT_35

For OUT35


PINMUX.MIO_PAD_SLEEP_MODE_36 @ 0x784

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_36
31302928272625242322212019181716
 
1514131211109876543210
  OUT_36
BitsTypeResetNameDescription
1:0rw0x2OUT_36

For OUT36


PINMUX.MIO_PAD_SLEEP_MODE_37 @ 0x788

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_37
31302928272625242322212019181716
 
1514131211109876543210
  OUT_37
BitsTypeResetNameDescription
1:0rw0x2OUT_37

For OUT37


PINMUX.MIO_PAD_SLEEP_MODE_38 @ 0x78c

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_38
31302928272625242322212019181716
 
1514131211109876543210
  OUT_38
BitsTypeResetNameDescription
1:0rw0x2OUT_38

For OUT38


PINMUX.MIO_PAD_SLEEP_MODE_39 @ 0x790

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_39
31302928272625242322212019181716
 
1514131211109876543210
  OUT_39
BitsTypeResetNameDescription
1:0rw0x2OUT_39

For OUT39


PINMUX.MIO_PAD_SLEEP_MODE_40 @ 0x794

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_40
31302928272625242322212019181716
 
1514131211109876543210
  OUT_40
BitsTypeResetNameDescription
1:0rw0x2OUT_40

For OUT40


PINMUX.MIO_PAD_SLEEP_MODE_41 @ 0x798

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_41
31302928272625242322212019181716
 
1514131211109876543210
  OUT_41
BitsTypeResetNameDescription
1:0rw0x2OUT_41

For OUT41


PINMUX.MIO_PAD_SLEEP_MODE_42 @ 0x79c

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_42
31302928272625242322212019181716
 
1514131211109876543210
  OUT_42
BitsTypeResetNameDescription
1:0rw0x2OUT_42

For OUT42


PINMUX.MIO_PAD_SLEEP_MODE_43 @ 0x7a0

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_43
31302928272625242322212019181716
 
1514131211109876543210
  OUT_43
BitsTypeResetNameDescription
1:0rw0x2OUT_43

For OUT43


PINMUX.MIO_PAD_SLEEP_MODE_44 @ 0x7a4

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_44
31302928272625242322212019181716
 
1514131211109876543210
  OUT_44
BitsTypeResetNameDescription
1:0rw0x2OUT_44

For OUT44


PINMUX.MIO_PAD_SLEEP_MODE_45 @ 0x7a8

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_45
31302928272625242322212019181716
 
1514131211109876543210
  OUT_45
BitsTypeResetNameDescription
1:0rw0x2OUT_45

For OUT45


PINMUX.MIO_PAD_SLEEP_MODE_46 @ 0x7ac

Defines sleep behavior of the corresponding muxed pad.

Reset default = 0x2, mask 0x3
Register enable = MIO_PAD_SLEEP_REGWEN_46
31302928272625242322212019181716
 
1514131211109876543210
  OUT_46
BitsTypeResetNameDescription
1:0rw0x2OUT_46

For OUT46


PINMUX.DIO_PAD_SLEEP_STATUS @ 0x7b0

Register indicating whether the corresponding pad is in sleep mode.

Reset default = 0x0, mask 0xffffff
31302928272625242322212019181716
  EN_23 EN_22 EN_21 EN_20 EN_19 EN_18 EN_17 EN_16
1514131211109876543210
EN_15 EN_14 EN_13 EN_12 EN_11 EN_10 EN_9 EN_8 EN_7 EN_6 EN_5 EN_4 EN_3 EN_2 EN_1 EN_0
BitsTypeResetNameDescription
0rw0c0x0EN_0

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

1rw0c0x0EN_1

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

2rw0c0x0EN_2

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

3rw0c0x0EN_3

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

4rw0c0x0EN_4

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

5rw0c0x0EN_5

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

6rw0c0x0EN_6

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

7rw0c0x0EN_7

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

8rw0c0x0EN_8

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

9rw0c0x0EN_9

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

10rw0c0x0EN_10

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

11rw0c0x0EN_11

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

12rw0c0x0EN_12

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

13rw0c0x0EN_13

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

14rw0c0x0EN_14

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

15rw0c0x0EN_15

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

16rw0c0x0EN_16

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

17rw0c0x0EN_17

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

18rw0c0x0EN_18

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

19rw0c0x0EN_19

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

20rw0c0x0EN_20

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

21rw0c0x0EN_21

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

22rw0c0x0EN_22

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

23rw0c0x0EN_23

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.


PINMUX.DIO_PAD_SLEEP_REGWEN_0 @ 0x7b4

Register write enable for DIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_0
BitsTypeResetNameDescription
0rw0c0x1EN_0

Register write enable bit. If this is cleared to 0, the corresponding !!DIO_PAD_SLEEP_MODE is not writable anymore.


PINMUX.DIO_PAD_SLEEP_REGWEN_1 @ 0x7b8

Register write enable for DIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_1
BitsTypeResetNameDescription
0rw0c0x1EN_1

For DIO_PAD1


PINMUX.DIO_PAD_SLEEP_REGWEN_2 @ 0x7bc

Register write enable for DIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_2
BitsTypeResetNameDescription
0rw0c0x1EN_2

For DIO_PAD2


PINMUX.DIO_PAD_SLEEP_REGWEN_3 @ 0x7c0

Register write enable for DIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_3
BitsTypeResetNameDescription
0rw0c0x1EN_3

For DIO_PAD3


PINMUX.DIO_PAD_SLEEP_REGWEN_4 @ 0x7c4

Register write enable for DIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_4
BitsTypeResetNameDescription
0rw0c0x1EN_4

For DIO_PAD4


PINMUX.DIO_PAD_SLEEP_REGWEN_5 @ 0x7c8

Register write enable for DIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_5
BitsTypeResetNameDescription
0rw0c0x1EN_5

For DIO_PAD5


PINMUX.DIO_PAD_SLEEP_REGWEN_6 @ 0x7cc

Register write enable for DIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_6
BitsTypeResetNameDescription
0rw0c0x1EN_6

For DIO_PAD6


PINMUX.DIO_PAD_SLEEP_REGWEN_7 @ 0x7d0

Register write enable for DIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_7
BitsTypeResetNameDescription
0rw0c0x1EN_7

For DIO_PAD7


PINMUX.DIO_PAD_SLEEP_REGWEN_8 @ 0x7d4

Register write enable for DIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_8
BitsTypeResetNameDescription
0rw0c0x1EN_8

For DIO_PAD8


PINMUX.DIO_PAD_SLEEP_REGWEN_9 @ 0x7d8

Register write enable for DIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_9
BitsTypeResetNameDescription
0rw0c0x1EN_9

For DIO_PAD9


PINMUX.DIO_PAD_SLEEP_REGWEN_10 @ 0x7dc

Register write enable for DIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_10
BitsTypeResetNameDescription
0rw0c0x1EN_10

For DIO_PAD10


PINMUX.DIO_PAD_SLEEP_REGWEN_11 @ 0x7e0

Register write enable for DIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_11
BitsTypeResetNameDescription
0rw0c0x1EN_11

For DIO_PAD11


PINMUX.DIO_PAD_SLEEP_REGWEN_12 @ 0x7e4

Register write enable for DIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_12
BitsTypeResetNameDescription
0rw0c0x1EN_12

For DIO_PAD12


PINMUX.DIO_PAD_SLEEP_REGWEN_13 @ 0x7e8

Register write enable for DIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_13
BitsTypeResetNameDescription
0rw0c0x1EN_13

For DIO_PAD13


PINMUX.DIO_PAD_SLEEP_REGWEN_14 @ 0x7ec

Register write enable for DIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_14
BitsTypeResetNameDescription
0rw0c0x1EN_14

For DIO_PAD14


PINMUX.DIO_PAD_SLEEP_REGWEN_15 @ 0x7f0

Register write enable for DIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_15
BitsTypeResetNameDescription
0rw0c0x1EN_15

For DIO_PAD15


PINMUX.DIO_PAD_SLEEP_REGWEN_16 @ 0x7f4

Register write enable for DIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_16
BitsTypeResetNameDescription
0rw0c0x1EN_16

For DIO_PAD16


PINMUX.DIO_PAD_SLEEP_REGWEN_17 @ 0x7f8

Register write enable for DIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_17
BitsTypeResetNameDescription
0rw0c0x1EN_17

For DIO_PAD17


PINMUX.DIO_PAD_SLEEP_REGWEN_18 @ 0x7fc

Register write enable for DIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_18
BitsTypeResetNameDescription
0rw0c0x1EN_18

For DIO_PAD18


PINMUX.DIO_PAD_SLEEP_REGWEN_19 @ 0x800

Register write enable for DIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_19
BitsTypeResetNameDescription
0rw0c0x1EN_19

For DIO_PAD19


PINMUX.DIO_PAD_SLEEP_REGWEN_20 @ 0x804

Register write enable for DIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_20
BitsTypeResetNameDescription
0rw0c0x1EN_20

For DIO_PAD20


PINMUX.DIO_PAD_SLEEP_REGWEN_21 @ 0x808

Register write enable for DIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_21
BitsTypeResetNameDescription
0rw0c0x1EN_21

For DIO_PAD21


PINMUX.DIO_PAD_SLEEP_REGWEN_22 @ 0x80c

Register write enable for DIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_22
BitsTypeResetNameDescription
0rw0c0x1EN_22

For DIO_PAD22


PINMUX.DIO_PAD_SLEEP_REGWEN_23 @ 0x810

Register write enable for DIO sleep value configuration.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_23
BitsTypeResetNameDescription
0rw0c0x1EN_23

For DIO_PAD23


PINMUX.DIO_PAD_SLEEP_EN_0 @ 0x814

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1
Register enable = DIO_PAD_SLEEP_REGWEN_0
31302928272625242322212019181716
 
1514131211109876543210
  EN_0
BitsTypeResetNameDescription
0rw0x0EN_0

Deep sleep mode enable. If this bit is set to 1 the corresponding pad will enable the sleep behavior specified in !!DIO_PAD_SLEEP_MODE upon deep sleep entry, and the corresponding bit in DIO_PAD_SLEEP_STATUS will be set to 1. The pad remains in deep sleep mode until the corresponding bit in DIO_PAD_SLEEP_STATUS is cleared by SW. Note that if an always on peripheral is connected to a specific DIO pad, the corresponding !!DIO_PAD_SLEEP_EN bit should be set to 0.


PINMUX.DIO_PAD_SLEEP_EN_1 @ 0x818

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1
Register enable = DIO_PAD_SLEEP_REGWEN_1
31302928272625242322212019181716
 
1514131211109876543210
  EN_1
BitsTypeResetNameDescription
0rw0x0EN_1

For OUT1


PINMUX.DIO_PAD_SLEEP_EN_2 @ 0x81c

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1
Register enable = DIO_PAD_SLEEP_REGWEN_2
31302928272625242322212019181716
 
1514131211109876543210
  EN_2
BitsTypeResetNameDescription
0rw0x0EN_2

For OUT2


PINMUX.DIO_PAD_SLEEP_EN_3 @ 0x820

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1
Register enable = DIO_PAD_SLEEP_REGWEN_3
31302928272625242322212019181716
 
1514131211109876543210
  EN_3
BitsTypeResetNameDescription
0rw0x0EN_3

For OUT3


PINMUX.DIO_PAD_SLEEP_EN_4 @ 0x824

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1
Register enable = DIO_PAD_SLEEP_REGWEN_4
31302928272625242322212019181716
 
1514131211109876543210
  EN_4
BitsTypeResetNameDescription
0rw0x0EN_4

For OUT4


PINMUX.DIO_PAD_SLEEP_EN_5 @ 0x828

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1
Register enable = DIO_PAD_SLEEP_REGWEN_5
31302928272625242322212019181716
 
1514131211109876543210
  EN_5
BitsTypeResetNameDescription
0rw0x0EN_5

For OUT5


PINMUX.DIO_PAD_SLEEP_EN_6 @ 0x82c

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1
Register enable = DIO_PAD_SLEEP_REGWEN_6
31302928272625242322212019181716
 
1514131211109876543210
  EN_6
BitsTypeResetNameDescription
0rw0x0EN_6

For OUT6


PINMUX.DIO_PAD_SLEEP_EN_7 @ 0x830

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1
Register enable = DIO_PAD_SLEEP_REGWEN_7
31302928272625242322212019181716
 
1514131211109876543210
  EN_7
BitsTypeResetNameDescription
0rw0x0EN_7

For OUT7


PINMUX.DIO_PAD_SLEEP_EN_8 @ 0x834

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1
Register enable = DIO_PAD_SLEEP_REGWEN_8
31302928272625242322212019181716
 
1514131211109876543210
  EN_8
BitsTypeResetNameDescription
0rw0x0EN_8

For OUT8


PINMUX.DIO_PAD_SLEEP_EN_9 @ 0x838

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1
Register enable = DIO_PAD_SLEEP_REGWEN_9
31302928272625242322212019181716
 
1514131211109876543210
  EN_9
BitsTypeResetNameDescription
0rw0x0EN_9

For OUT9


PINMUX.DIO_PAD_SLEEP_EN_10 @ 0x83c

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1
Register enable = DIO_PAD_SLEEP_REGWEN_10
31302928272625242322212019181716
 
1514131211109876543210
  EN_10
BitsTypeResetNameDescription
0rw0x0EN_10

For OUT10


PINMUX.DIO_PAD_SLEEP_EN_11 @ 0x840

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1
Register enable = DIO_PAD_SLEEP_REGWEN_11
31302928272625242322212019181716
 
1514131211109876543210
  EN_11
BitsTypeResetNameDescription
0rw0x0EN_11

For OUT11


PINMUX.DIO_PAD_SLEEP_EN_12 @ 0x844

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1
Register enable = DIO_PAD_SLEEP_REGWEN_12
31302928272625242322212019181716
 
1514131211109876543210
  EN_12
BitsTypeResetNameDescription
0rw0x0EN_12

For OUT12


PINMUX.DIO_PAD_SLEEP_EN_13 @ 0x848

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1
Register enable = DIO_PAD_SLEEP_REGWEN_13
31302928272625242322212019181716
 
1514131211109876543210
  EN_13
BitsTypeResetNameDescription
0rw0x0EN_13

For OUT13


PINMUX.DIO_PAD_SLEEP_EN_14 @ 0x84c

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1
Register enable = DIO_PAD_SLEEP_REGWEN_14
31302928272625242322212019181716
 
1514131211109876543210
  EN_14
BitsTypeResetNameDescription
0rw0x0EN_14

For OUT14


PINMUX.DIO_PAD_SLEEP_EN_15 @ 0x850

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1
Register enable = DIO_PAD_SLEEP_REGWEN_15
31302928272625242322212019181716
 
1514131211109876543210
  EN_15
BitsTypeResetNameDescription
0rw0x0EN_15

For OUT15


PINMUX.DIO_PAD_SLEEP_EN_16 @ 0x854

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1
Register enable = DIO_PAD_SLEEP_REGWEN_16
31302928272625242322212019181716
 
1514131211109876543210
  EN_16
BitsTypeResetNameDescription
0rw0x0EN_16

For OUT16


PINMUX.DIO_PAD_SLEEP_EN_17 @ 0x858

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1
Register enable = DIO_PAD_SLEEP_REGWEN_17
31302928272625242322212019181716
 
1514131211109876543210
  EN_17
BitsTypeResetNameDescription
0rw0x0EN_17

For OUT17


PINMUX.DIO_PAD_SLEEP_EN_18 @ 0x85c

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1
Register enable = DIO_PAD_SLEEP_REGWEN_18
31302928272625242322212019181716
 
1514131211109876543210
  EN_18
BitsTypeResetNameDescription
0rw0x0EN_18

For OUT18


PINMUX.DIO_PAD_SLEEP_EN_19 @ 0x860

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1
Register enable = DIO_PAD_SLEEP_REGWEN_19
31302928272625242322212019181716
 
1514131211109876543210
  EN_19
BitsTypeResetNameDescription
0rw0x0EN_19

For OUT19


PINMUX.DIO_PAD_SLEEP_EN_20 @ 0x864

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1
Register enable = DIO_PAD_SLEEP_REGWEN_20
31302928272625242322212019181716
 
1514131211109876543210
  EN_20
BitsTypeResetNameDescription
0rw0x0EN_20

For OUT20


PINMUX.DIO_PAD_SLEEP_EN_21 @ 0x868

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1
Register enable = DIO_PAD_SLEEP_REGWEN_21
31302928272625242322212019181716
 
1514131211109876543210
  EN_21
BitsTypeResetNameDescription
0rw0x0EN_21

For OUT21


PINMUX.DIO_PAD_SLEEP_EN_22 @ 0x86c

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1
Register enable = DIO_PAD_SLEEP_REGWEN_22
31302928272625242322212019181716
 
1514131211109876543210
  EN_22
BitsTypeResetNameDescription
0rw0x0EN_22

For OUT22


PINMUX.DIO_PAD_SLEEP_EN_23 @ 0x870

Enables the sleep mode of the corresponding dedicated pad.

Reset default = 0x0, mask 0x1
Register enable = DIO_PAD_SLEEP_REGWEN_23
31302928272625242322212019181716
 
1514131211109876543210
  EN_23
BitsTypeResetNameDescription
0rw0x0EN_23

For OUT23


PINMUX.DIO_PAD_SLEEP_MODE_0 @ 0x874

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3
Register enable = DIO_PAD_SLEEP_REGWEN_0
31302928272625242322212019181716
 
1514131211109876543210
  OUT_0
BitsTypeResetNameDescription
1:0rw0x2OUT_0

Value to drive in deep sleep.

0Tie-Low

The pad is driven actively to zero in deep sleep mode.

1Tie-High

The pad is driven actively to one in deep sleep mode.

2High-Z

The pad is left undriven in deep sleep mode. Note that the actual driving behavior during deep sleep will then depend on the pull-up/-down configuration of in !!DIO_PAD_ATTR.

3Keep

Keep last driven value (including high-Z).


PINMUX.DIO_PAD_SLEEP_MODE_1 @ 0x878

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3
Register enable = DIO_PAD_SLEEP_REGWEN_1
31302928272625242322212019181716
 
1514131211109876543210
  OUT_1
BitsTypeResetNameDescription
1:0rw0x2OUT_1

For OUT1


PINMUX.DIO_PAD_SLEEP_MODE_2 @ 0x87c

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3
Register enable = DIO_PAD_SLEEP_REGWEN_2
31302928272625242322212019181716
 
1514131211109876543210
  OUT_2
BitsTypeResetNameDescription
1:0rw0x2OUT_2

For OUT2


PINMUX.DIO_PAD_SLEEP_MODE_3 @ 0x880

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3
Register enable = DIO_PAD_SLEEP_REGWEN_3
31302928272625242322212019181716
 
1514131211109876543210
  OUT_3
BitsTypeResetNameDescription
1:0rw0x2OUT_3

For OUT3


PINMUX.DIO_PAD_SLEEP_MODE_4 @ 0x884

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3
Register enable = DIO_PAD_SLEEP_REGWEN_4
31302928272625242322212019181716
 
1514131211109876543210
  OUT_4
BitsTypeResetNameDescription
1:0rw0x2OUT_4

For OUT4


PINMUX.DIO_PAD_SLEEP_MODE_5 @ 0x888

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3
Register enable = DIO_PAD_SLEEP_REGWEN_5
31302928272625242322212019181716
 
1514131211109876543210
  OUT_5
BitsTypeResetNameDescription
1:0rw0x2OUT_5

For OUT5


PINMUX.DIO_PAD_SLEEP_MODE_6 @ 0x88c

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3
Register enable = DIO_PAD_SLEEP_REGWEN_6
31302928272625242322212019181716
 
1514131211109876543210
  OUT_6
BitsTypeResetNameDescription
1:0rw0x2OUT_6

For OUT6


PINMUX.DIO_PAD_SLEEP_MODE_7 @ 0x890

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3
Register enable = DIO_PAD_SLEEP_REGWEN_7
31302928272625242322212019181716
 
1514131211109876543210
  OUT_7
BitsTypeResetNameDescription
1:0rw0x2OUT_7

For OUT7


PINMUX.DIO_PAD_SLEEP_MODE_8 @ 0x894

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3
Register enable = DIO_PAD_SLEEP_REGWEN_8
31302928272625242322212019181716
 
1514131211109876543210
  OUT_8
BitsTypeResetNameDescription
1:0rw0x2OUT_8

For OUT8


PINMUX.DIO_PAD_SLEEP_MODE_9 @ 0x898

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3
Register enable = DIO_PAD_SLEEP_REGWEN_9
31302928272625242322212019181716
 
1514131211109876543210
  OUT_9
BitsTypeResetNameDescription
1:0rw0x2OUT_9

For OUT9


PINMUX.DIO_PAD_SLEEP_MODE_10 @ 0x89c

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3
Register enable = DIO_PAD_SLEEP_REGWEN_10
31302928272625242322212019181716
 
1514131211109876543210
  OUT_10
BitsTypeResetNameDescription
1:0rw0x2OUT_10

For OUT10


PINMUX.DIO_PAD_SLEEP_MODE_11 @ 0x8a0

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3
Register enable = DIO_PAD_SLEEP_REGWEN_11
31302928272625242322212019181716
 
1514131211109876543210
  OUT_11
BitsTypeResetNameDescription
1:0rw0x2OUT_11

For OUT11


PINMUX.DIO_PAD_SLEEP_MODE_12 @ 0x8a4

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3
Register enable = DIO_PAD_SLEEP_REGWEN_12
31302928272625242322212019181716
 
1514131211109876543210
  OUT_12
BitsTypeResetNameDescription
1:0rw0x2OUT_12

For OUT12


PINMUX.DIO_PAD_SLEEP_MODE_13 @ 0x8a8

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3
Register enable = DIO_PAD_SLEEP_REGWEN_13
31302928272625242322212019181716
 
1514131211109876543210
  OUT_13
BitsTypeResetNameDescription
1:0rw0x2OUT_13

For OUT13


PINMUX.DIO_PAD_SLEEP_MODE_14 @ 0x8ac

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3
Register enable = DIO_PAD_SLEEP_REGWEN_14
31302928272625242322212019181716
 
1514131211109876543210
  OUT_14
BitsTypeResetNameDescription
1:0rw0x2OUT_14

For OUT14


PINMUX.DIO_PAD_SLEEP_MODE_15 @ 0x8b0

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3
Register enable = DIO_PAD_SLEEP_REGWEN_15
31302928272625242322212019181716
 
1514131211109876543210
  OUT_15
BitsTypeResetNameDescription
1:0rw0x2OUT_15

For OUT15


PINMUX.DIO_PAD_SLEEP_MODE_16 @ 0x8b4

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3
Register enable = DIO_PAD_SLEEP_REGWEN_16
31302928272625242322212019181716
 
1514131211109876543210
  OUT_16
BitsTypeResetNameDescription
1:0rw0x2OUT_16

For OUT16


PINMUX.DIO_PAD_SLEEP_MODE_17 @ 0x8b8

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3
Register enable = DIO_PAD_SLEEP_REGWEN_17
31302928272625242322212019181716
 
1514131211109876543210
  OUT_17
BitsTypeResetNameDescription
1:0rw0x2OUT_17

For OUT17


PINMUX.DIO_PAD_SLEEP_MODE_18 @ 0x8bc

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3
Register enable = DIO_PAD_SLEEP_REGWEN_18
31302928272625242322212019181716
 
1514131211109876543210
  OUT_18
BitsTypeResetNameDescription
1:0rw0x2OUT_18

For OUT18


PINMUX.DIO_PAD_SLEEP_MODE_19 @ 0x8c0

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3
Register enable = DIO_PAD_SLEEP_REGWEN_19
31302928272625242322212019181716
 
1514131211109876543210
  OUT_19
BitsTypeResetNameDescription
1:0rw0x2OUT_19

For OUT19


PINMUX.DIO_PAD_SLEEP_MODE_20 @ 0x8c4

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3
Register enable = DIO_PAD_SLEEP_REGWEN_20
31302928272625242322212019181716
 
1514131211109876543210
  OUT_20
BitsTypeResetNameDescription
1:0rw0x2OUT_20

For OUT20


PINMUX.DIO_PAD_SLEEP_MODE_21 @ 0x8c8

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3
Register enable = DIO_PAD_SLEEP_REGWEN_21
31302928272625242322212019181716
 
1514131211109876543210
  OUT_21
BitsTypeResetNameDescription
1:0rw0x2OUT_21

For OUT21


PINMUX.DIO_PAD_SLEEP_MODE_22 @ 0x8cc

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3
Register enable = DIO_PAD_SLEEP_REGWEN_22
31302928272625242322212019181716
 
1514131211109876543210
  OUT_22
BitsTypeResetNameDescription
1:0rw0x2OUT_22

For OUT22


PINMUX.DIO_PAD_SLEEP_MODE_23 @ 0x8d0

Defines sleep behavior of the corresponding dedicated pad.

Reset default = 0x2, mask 0x3
Register enable = DIO_PAD_SLEEP_REGWEN_23
31302928272625242322212019181716
 
1514131211109876543210
  OUT_23
BitsTypeResetNameDescription
1:0rw0x2OUT_23

For OUT23


PINMUX.WKUP_DETECTOR_REGWEN_0 @ 0x8d4

Register write enable for wakeup detectors.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_0
BitsTypeResetNameDescription
0rw0c0x1EN_0

Register write enable bit. If this is cleared to 0, the corresponding WKUP_DETECTOR configuration is not writable anymore.


PINMUX.WKUP_DETECTOR_REGWEN_1 @ 0x8d8

Register write enable for wakeup detectors.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_1
BitsTypeResetNameDescription
0rw0c0x1EN_1

For WKUP_DETECTOR1


PINMUX.WKUP_DETECTOR_REGWEN_2 @ 0x8dc

Register write enable for wakeup detectors.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_2
BitsTypeResetNameDescription
0rw0c0x1EN_2

For WKUP_DETECTOR2


PINMUX.WKUP_DETECTOR_REGWEN_3 @ 0x8e0

Register write enable for wakeup detectors.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_3
BitsTypeResetNameDescription
0rw0c0x1EN_3

For WKUP_DETECTOR3


PINMUX.WKUP_DETECTOR_REGWEN_4 @ 0x8e4

Register write enable for wakeup detectors.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_4
BitsTypeResetNameDescription
0rw0c0x1EN_4

For WKUP_DETECTOR4


PINMUX.WKUP_DETECTOR_REGWEN_5 @ 0x8e8

Register write enable for wakeup detectors.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_5
BitsTypeResetNameDescription
0rw0c0x1EN_5

For WKUP_DETECTOR5


PINMUX.WKUP_DETECTOR_REGWEN_6 @ 0x8ec

Register write enable for wakeup detectors.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_6
BitsTypeResetNameDescription
0rw0c0x1EN_6

For WKUP_DETECTOR6


PINMUX.WKUP_DETECTOR_REGWEN_7 @ 0x8f0

Register write enable for wakeup detectors.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_7
BitsTypeResetNameDescription
0rw0c0x1EN_7

For WKUP_DETECTOR7


PINMUX.WKUP_DETECTOR_EN_0 @ 0x8f4

Enables for the wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

Reset default = 0x0, mask 0x1
Register enable = WKUP_DETECTOR_REGWEN_0
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  EN_0
BitsTypeResetNameDescription
0rw0x0EN_0

Setting this bit activates the corresponding wakeup detector. The behavior is as specified in !!WKUP_DETECTOR, !!WKUP_DETECTOR_CNT_TH and !!WKUP_DETECTOR_PADSEL.


PINMUX.WKUP_DETECTOR_EN_1 @ 0x8f8

Enables for the wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

Reset default = 0x0, mask 0x1
Register enable = WKUP_DETECTOR_REGWEN_1
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  EN_1
BitsTypeResetNameDescription
0rw0x0EN_1

For DETECTOR1


PINMUX.WKUP_DETECTOR_EN_2 @ 0x8fc

Enables for the wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

Reset default = 0x0, mask 0x1
Register enable = WKUP_DETECTOR_REGWEN_2
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  EN_2
BitsTypeResetNameDescription
0rw0x0EN_2

For DETECTOR2


PINMUX.WKUP_DETECTOR_EN_3 @ 0x900

Enables for the wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

Reset default = 0x0, mask 0x1
Register enable = WKUP_DETECTOR_REGWEN_3
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  EN_3
BitsTypeResetNameDescription
0rw0x0EN_3

For DETECTOR3


PINMUX.WKUP_DETECTOR_EN_4 @ 0x904

Enables for the wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

Reset default = 0x0, mask 0x1
Register enable = WKUP_DETECTOR_REGWEN_4
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  EN_4
BitsTypeResetNameDescription
0rw0x0EN_4

For DETECTOR4


PINMUX.WKUP_DETECTOR_EN_5 @ 0x908

Enables for the wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

Reset default = 0x0, mask 0x1
Register enable = WKUP_DETECTOR_REGWEN_5
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  EN_5
BitsTypeResetNameDescription
0rw0x0EN_5

For DETECTOR5


PINMUX.WKUP_DETECTOR_EN_6 @ 0x90c

Enables for the wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

Reset default = 0x0, mask 0x1
Register enable = WKUP_DETECTOR_REGWEN_6
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  EN_6
BitsTypeResetNameDescription
0rw0x0EN_6

For DETECTOR6


PINMUX.WKUP_DETECTOR_EN_7 @ 0x910

Enables for the wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

Reset default = 0x0, mask 0x1
Register enable = WKUP_DETECTOR_REGWEN_7
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  EN_7
BitsTypeResetNameDescription
0rw0x0EN_7

For DETECTOR7


PINMUX.WKUP_DETECTOR_0 @ 0x914

Configuration of wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

Reset default = 0x0, mask 0x1f
Register enable = WKUP_DETECTOR_REGWEN_0
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  MIODIO_0 FILTER_0 MODE_0
BitsTypeResetNameDescription
2:0rw0x0MODE_0

Wakeup detection mode.

0Posedge

Trigger a wakeup request when observing a positive edge.

1Negedge

Trigger a wakeup request when observing a negative edge.

2Edge

Trigger a wakeup request when observing an edge in any direction.

3TimedHigh

Trigger a wakeup request when pin is driven HIGH for a certain amount of always-on clock cycles as configured in !!WKUP_DETECTOR_CNT_TH.

4TimedLow

Trigger a wakeup request when pin is driven LOW for a certain amount of always-on clock cycles as configured in !!WKUP_DETECTOR_CNT_TH.

Other values are reserved.

3rw0x0FILTER_0

0: signal filter disabled, 1: signal filter enabled. the signal must be stable for 4 always-on clock cycles before the value is being forwarded. can be used for debouncing.

4rw0x0MIODIO_0

0: select index !!WKUP_DETECTOR_PADSEL from MIO pads, 1: select index !!WKUP_DETECTOR_PADSEL from DIO pads.


PINMUX.WKUP_DETECTOR_1 @ 0x918

Configuration of wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

Reset default = 0x0, mask 0x1f
Register enable = WKUP_DETECTOR_REGWEN_1