PWM DV document


  • DV
    • Verify all PWM IP features by running dynamic simulations with a SV/UVM based testbench
    • Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
  • FPV
    • Verify TileLink device protocol compliance with an SVA based testbench

Current status

Design features

For detailed information on PWM design features, please see the PWM HWIP technical specification.

Testbench architecture

PWM testbench has been constructed based on the CIP testbench architecture.

Block diagram

Block diagram

Top level testbench

Top level testbench is located at hw/ip/pwm/dv/tb/ It instantiates the PWM DUT module hw/ip/pwm/rtl/ In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db:

Common DV utility components

The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

Global types & methods

All common types and methods defined at the package level can be found in pwm_env_pkg. Some of them in use are:

parameter uint NUM_PWM_CHANNELS = 6;

 // datatype
  typedef enum bit [1:0] {
    Standard  = 2'b00,
    Blinking  = 2'b01,
    Heartbeat = 2'b11,
    Allmodes  = 2'b10
  } pwm_mode_e;

  typedef enum bit {
    Enable  = 1'b1,
    Disable = 1'b0
  } pwm_status_e;

  typedef struct packed {
    bit [26:0]   ClkDiv;
    bit [3:0]    DcResn;
    bit          CntrEn;
  } cfg_reg_t;

  typedef struct packed {
    bit          BlinkEn;
    bit          HtbtEn;
    bit [13:0]   RsvParam;
    bit [15:0]   PhaseDelay;
  } param_reg_t;

  typedef struct packed {
    bit [15:0]   B;
    bit [15:0]   A;
  } dc_blink_t;

  // function
  function automatic pwm_mode_e get_pwm_mode(bit [1:0] mode);
    return (mode == 2'b10) ? Blinking  :
           (mode == 2'b11) ? Heartbeat :
           (mode == 2'b00) ? Standard  :
  endfunction : get_pwm_mode


PWM instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into PWM device.

PWM monitor

Because the DUT does require any response a full agent is not needed. Instead a PWM monitor has been developed. It will capture all traffic on the PWM channel and each pulse in a pwm sequence item for later analysis in the scoreboard. For each pulse a number of features are captured such as:

  • pulse length in number of clk’s
  • number of active cycles
  • number of inactive cycles
  • relative delay to be used for phase calculation


The PWM RAL model is created with the ralgen FuseSoC generator script automatically when the simulation is at the build stage.

It can be created manually by invoking regtool

Stimulus strategy

Test sequences

All test sequences reside in hw/ip/pwm/dv/env/seq_lib. The pwm_base_vseq virtual sequence is extended from cip_base_vseq and serves as a starting point. All test sequences are extended from pwm_base_vseq. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.

Some of the most commonly used tasks / functions are as follows:

  • set_reg_en(pwm_status_e state): enable registers for writing
  • set_cfg_reg(cfg_reg_t cfg_reg): program global configuration (ClkDiv/DcResn/CntrEn))
  • set_ch_enables(bit [PWM_NUM_CHANNELS-1:0] enables): used to enable and disable the different channels
  • set_duty_cycle(bit [$bits(PWM_NUM_CHANNELS)-1:0] channel, dc_blink_t value ,bit [3:0] resn) set the A and B values for channel
  • set_blink(bit [$bits(PWM_NUM_CHANNELS)-1:0] channel, dc_blink_t value): set X and Y value for pulse and heart bit
  • set_param(bit [$bits(PWM_NUM_CHANNELS)-1:0] channel, param_reg_t value): set channel configuration (blink/heatbeat/phase)
  • shutdown_dut(): this will disable all channels as an indication for the scoreboard to verify all remaining items.

Functional coverage

To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The functional coverage plan can be found here: coverageplan

Self-checking strategy


The pwm_scoreboard is primarily used for end to end checking. It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:

  • item_fifo[NUM_PWM_CHANNELS]: the FIFO w.r.t channels receives the dut items sent by the pwm_monitor
  • exp_item_q[PWM_NUM_CHANNELS]: the queues w.r.t channels are used to store the expected/referenced items which are constructed from tl address and data channels

when a channel is configured to start sending pulses the first expected item is generated and put in the exp_item_q. Because of the way the PWM IP is design the first and the last pulse might not match the configuration settings. Therefore the scoreboard will wait until a channel is disabled before checking the output. Once a channel is disabled it will first discard the first two items received from the monitor. The is send because the channel was enabled and has no valid information. The second is the one that cannot be expected to match configuration. For pulse mode it will get the expected pulse item and match all incoming item to this one. For blink and heart beat mode after an item is compared successfully the scoreboard will generate the next expected item based on the previous item and the settings of the blink parameters. If an error is found the scoreboard will throw a fatal error.


  • TLUL assertions: The tb/ binds the tlul_assert assertions to the IP to ensure TileLink interface protocol compliance.
  • Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.

Building and running tests

We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:

$ $REPO_TOP/util/dvsim/ $REPO_TOP/hw/ip/pwm/dv/pwm_sim_cfg.hjson -i pwm_smoke



Milestone Name Tests Description
V1 smoke pwm_smoke

pwm_smoke tests pulse and blink mode for a single channel


  • configure the envionment for one PWM channel
  • program the duty cycle a and b values
  • configure the ClkDiv and Resn


  • ensure pulses are generated correctly in pulse or blink mode
V1 csr_hw_reset pwm_csr_hw_reset

Verify the reset values as indicated in the RAL specification.

  • Write all CSRs with a random value.
  • Apply reset to the DUT as well as the RAL model.
  • Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_rw pwm_csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

  • Loop through each CSR to write it with a random value.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_bit_bash pwm_csr_bit_bash

Verify no aliasing within individual bits of a CSR.

  • Walk a 1 through each CSR by flipping 1 bit at a time.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • This verify that writing a specific bit within the CSR did not affect any of the other bits.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_aliasing pwm_csr_aliasing

Verify no aliasing within the CSR address space.

  • Loop through each CSR to write it with a random value
  • Shuffle and read ALL CSRs back.
  • All CSRs except for the one that was written in this iteration should read back the previous value.
  • The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_mem_rw_with_rand_resetpwm_csr_mem_rw_with_rand_reset

Verify random reset during CSR/memory access.

  • Run csr_rw sequence to randomly access CSRs
  • If memory exists, run mem_partial_access in parallel with csr_rw
  • Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
V2 dutycycle pwm_smoke

Verify different duty cycle settings in Pulse, Blink and Heart Beat mode.

V2 pulse pwm_smoke

Verify the pulse mode of the PWM by de-asserting blink_en field in the PWM_PARAM register

V2 Blink pwm_moke

Verify the blink mode of the PWM by asserting the blink_en field in the PWM_PARAM register

V2 heartbeat

Verify the Heart Beat mode of the PWM by asserting the blink_en and HTBT field in the PWM_PARAM register

V2 resolution pwm_smoke

Verify the PWM generates correct duty cycle for different resolution settings

V2 multi_channel

Verifies that PWM correctly generates pulses on multiple channels concurrently

V2 polarity

Verify that the polarity of the pulse can be inverted by setting the invert channel bit in the invert register

V2 phase

Check that the relative phase between pulses matches the setting in the phase_delay field in the PWM_PARAM register.

V2 lowpower

Verify the PWM can continue when the chip is in low power mode. Stimulus: - start PWM on one or more channels - stop the TL UL clock

Checks: - Ensure pulses are still generated when in LP mode

V2 perf

Checking ip operation at min/max bandwidth

Stimulus: - Program timing registers (CLK_DIV, DC_RESN) to high/low values (slow/fast data rate) - Program other required registers for pwm operation - Start pwm channels

Checks: - Ensure the output pulses are correctly modulated for all channels

V2 clock_domain

TBD -Verify the function of clock-crossing domain for pwm


  • TBD


  • TBD
V2 stress_all

Combine above sequences in one test then randomly select for running


  • Start sequences and randomly add reset between each sequence


  • All sequences should be finished and checked by the scoreboard
V2 intr_test pwm_intr_test

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

  • Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
  • Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s).
  • Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
  • Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
  • Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
  • Repeat the above steps a bunch of times.
V2 enable_reg pwm_csr_rw

The CSR test sequences will read and write accessible CSRs including the enable registers and their locked registers. The RAL model supports predicting the correct value of the locked registers based on their enable registers.

V2 tl_d_oob_addr_access pwm_tl_errors

Access out of bounds address and verify correctness of response / behavior

V2 tl_d_illegal_access pwm_tl_errors

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the [TLUL spec]({{< relref "hw/ip/tlul/doc/" >}})

  • TL-UL protocol error cases
    • invalid opcode
    • some mask bits not set when opcode is PutFullData
    • mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
    • mask and address misaligned, e.g. a_address = 0x01, a_mask = 'b0001
    • address and size aren't aligned, e.g. a_address = 0x01, a_size != 0
    • size is greater than 2
  • OpenTitan defined error cases
    • access unmapped address, expect d_error = 1 when devmode_i == 1
    • write a CSR with unaligned address, e.g. a_address[1:0] != 0
    • write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
    • write a memory with a_mask != '1 when it doesn't support partial accesses
    • read a WO (write-only) memory
    • write a RO (read-only) memory
V2 tl_d_outstanding_access pwm_csr_hw_reset

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

V2 tl_d_partial_access pwm_csr_hw_reset

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

V2S tl_intg_err pwm_tl_intg_err

Verify that the data integrity check violation generates an alert.

Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.

V3 stress_all_with_rand_resetpwm_stress_all_with_rand_reset

This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.


Name Description

Covers that a good range of combinations of values for X and Y have been seend. Also cover that multiple channels can run concurrently with different settings for X and Y.


Covers that valid settings for the PWM.CFG register has been tested. This includes values for: - clk_div - dc_resn - cntr_en


Cover that a range of frequencies have been tested for the PWM clock including a clock that matches the TL clk.


Covers that a good range of combinations of values for A and B have been send. Also cover that multiple channels can run concurrently with different settings for A and B.


Covers that channels have been tested with different polarity Also cover that a mix channels with invert enabled and disabled concurrently have been tested.


Covers that the DUT will continue to produce pulses with TL clock disabled (low power mode)


Cover that a the PWM configuration cannot be altered while a channel is active


Covers that both runs with a single PWM channel and multiple channels has been tested. Verifies both when the channels are enabled for parallel behavior (activated at the same time) and activated individually


Covers that both pulse, blink and heart beat mode have been tested. Also covers that.

  • various phase delays have been tested
  • different delays on different concurrent channels

Covers that an attempt to write wen REG enable was made and was unsuccessful


Cover the following error cases on TL-UL bus:

  • TL-UL protocol error cases.
  • OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.