PWM DV document

Goals

  • DV
    • Verify all PWM IP features by running dynamic simulations with a SV/UVM based testbench
    • Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
  • FPV
    • Verify TileLink device protocol compliance with an SVA based testbench

Current status

Design features

For detailed information on PWM design features, please see the PWM HWIP technical specification.

Testbench architecture

PWM testbench has been constructed based on the CIP testbench architecture.

Block diagram

Block diagram

Top level testbench

Top level testbench is located at hw/ip/pwm/dv/tb/tb.sv. It instantiates the PWM DUT module hw/ip/pwm/rtl/pwm.sv. In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db:

Common DV utility components

The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

Global types & methods

All common types and methods defined at the package level can be found in pwm_env_pkg. Some of them in use are:

parameter uint NUM_PWM_CHANNELS = 6;

TL_agent

PWM instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into PWM device.

PWM agent

PWM agent is configured to work device mode. The agent monitor captures pulses generated in channels then sends to the scoreboard for verification
Since the DUT does not require any response thus agent driver is fairly simple.

UVM RAL Model

The PWM RAL model is created with the ralgen FuseSoC generator script automatically when the simulation is at the build stage.

It can be created manually by invoking regtool:

Stimulus strategy

Test sequences

All test sequences reside in hw/ip/pwm/dv/env/seq_lib. The pwm_base_vseq virtual sequence is extended from cip_base_vseq and serves as a starting point. All test sequences are extended from pwm_base_vseq. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.

Some of the most commonly used tasks / functions are as follows:

  • initialize_pwm: wait for out of reset then program REGEN register
  • program_pwm_cfg_regs: program the CFG.CLK_DIV and CFG.DC_RESN for all channels
  • program_pwm_mode_regs: program the operation modes (Standard/Blinking/Heartbeat) for all channels
  • start_pwm_channels: program CFG.CNTR_EN, PWM_EN, INVERT registers for all channels
  • run_pwm_channels: wait for a certain number of pulses generated in activate channels then stop all channels

Functional coverage

To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:

  • TODO:

Self-checking strategy

Scoreboard

The pwm_scoreboard is primarily used for end to end checking. It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:

  • item_fifo[NUM_PWM_CHANNELS]: the FIFO w.r.t channels receives the dut items sent by the pwm_monitor
  • exp_item_q[PWM_NUM_CHANNELS]: the queues w.r.t channels are used to store the expected/referenced items which are constructed from tl address and data channels

Once the expected items and dut items are found in the exp_item_q and item_fifo respectively, they are pop out for comparison

Assertions

  • TLUL assertions: The tb/pwm_bind.sv binds the tlul_assert assertions to the IP to ensure TileLink interface protocol compliance.
  • Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
  • TODO:

Building and running tests

We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:

$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/pwm/dv/pwm_sim_cfg.hjson -i pwm_smoke

Testplan

Testpoints

Milestone Name Tests Description
V1 smoke pwm_smoke

Smoke test accessing a major datapath within the pwm

Stimulus:

  • Program pwm enable register (PWM_EN)
  • Program configuration registers (CFG, INVERT)
  • Disable blink and heartbeat enable registers (these mode are verified with other tests)
  • Program REGEN to lock (enable) register settings and start pwm function

Checks:

  • Ensure the output pulses are correctly modulated for all channels
V1 csr_hw_reset pwm_csr_hw_reset

Verify the reset values as indicated in the RAL specification.

  • Write all CSRs with a random value.
  • Apply reset to the DUT as well as the RAL model.
  • Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_rw pwm_csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

  • Loop through each CSR to write it with a random value.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_bit_bash pwm_csr_bit_bash

Verify no aliasing within individual bits of a CSR.

  • Walk a 1 through each CSR by flipping 1 bit at a time.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • This verify that writing a specific bit within the CSR did not affect any of the other bits.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_aliasing pwm_csr_aliasing

Verify no aliasing within the CSR address space.

  • Loop through each CSR to write it with a random value
  • Shuffle and read ALL CSRs back.
  • All CSRs except for the one that was written in this iteration should read back the previous value.
  • The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_mem_rw_with_rand_resetpwm_csr_mem_rw_with_rand_reset

Verify random reset during CSR/memory access.

  • Run csr_rw sequence to randomly access CSRs
  • If memory exists, run mem_partial_access in parallel with csr_rw
  • Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
V2 perf pwm_perf

Checking ip operation at min/max bandwidth

Stimulus:

  • Program timing registers (CLK_DIV, DC_RESN) to high/low values (slow/fast data rate)
  • Program other required registers for pwm operation
  • Start pwm channels

Checks:

  • Ensure the output pulses are correctly modulated for all channels
V2 blink pwm_blink

Test the blinking mode of pwm

Stimulus:

  • Program pwm enable register (PWM_EN)
  • Program configuration registers (CFG, INVERT)
  • Enable blink mode (BLINK_EN) and program DUTY_CYCLE register
  • Program REGEN to lock (enable) register settings and start pwm function

Checks:

  • Ensure the output pulses are correctly modulated for all channels
  • Ensure blinking channel toggles by two duty cycle values programmed to DUTY_CYCLE register
V2 heartbeat pwm_heartbeat

Test the heartbeat mode of pwm

Stimulus:

  • Program pwm enable register (PWM_EN)
  • Program configuration registers (CFG, INVERT)
  • Enable heartbeat mode (HTBT_EN) and programm BLINK_PARAM register
  • Program REGEN to lock (enable) register settings and start pwm function

Checks:

  • Ensure the output pulses are correctly modulated for all channels
  • Ensure output duty cycle linearly increments and decrements between two blink-rate values programmed to BLINK_PARAM register
V2 clock_domain pwm_clock_domain

TBD -Verify the function of clock-crossing domain for pwm

Stimulus:

  • TBD

Checking:

  • TBD
V2 stress_all pwm_stress_all

Combine above sequences in one test then randomly select for running

Stimulus:

  • Start sequences and randomly add reset between each sequence

Checking:

  • All sequences should be finished and checked by the scoreboard
V2 intr_test pwm_intr_test

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

  • Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
  • Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s).
  • Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
  • Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
  • Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
  • Repeat the above steps a bunch of times.
V2 enable_reg pwm_csr_rw
pwm_csr_bit_bash
pwm_csr_aliasing

The CSR test sequences will read and write accessible CSRs including the enable registers and their locked registers. The RAL model supports predicting the correct value of the locked registers based on their enable registers.

V2 tl_d_oob_addr_access pwm_tl_errors

Access out of bounds address and verify correctness of response / behavior

V2 tl_d_illegal_access pwm_tl_errors

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the [TLUL spec]({{< relref "hw/ip/tlul/doc/_index.md#explicit-error-cases" >}})

  • TL-UL protocol error cases
    • invalid opcode
    • some mask bits not set when opcode is PutFullData
    • mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
    • mask and address misaligned, e.g. a_address = 0x01, a_mask = 'b0001
    • address and size aren't aligned, e.g. a_address = 0x01, a_size != 0
    • size is greater than 2
  • OpenTitan defined error cases
    • access unmapped address, expect d_error = 1 when devmode_i == 1
    • write a CSR with unaligned address, e.g. a_address[1:0] != 0
    • write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
    • write a memory with a_mask != '1 when it doesn't support partial accesses
    • read a WO (write-only) memory
    • write a RO (read-only) memory
V2 tl_d_outstanding_access pwm_csr_hw_reset
pwm_csr_rw
pwm_csr_aliasing
pwm_same_csr_outstanding

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

V2 tl_d_partial_access pwm_csr_hw_reset
pwm_csr_rw
pwm_csr_aliasing
pwm_same_csr_outstanding

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

V3 tl_intg_err pwm_tl_intg_err

Verify that the data integrity check violation generates an alert.

Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.

Covergroups

Name Description
tl_errors_cg

Cover the following error cases on TL-UL bus:

  • TL-UL protocol error cases.
  • OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.
tl_intg_err_cg

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

tl_intg_err_mem_subword_cg

Cover the kinds of integrity errors with byte enabled write on memory.

Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.