ROM Controller DV document


  • DV
    • Verify all rom_ctrl IP features by running dynamic simulations with a SV/UVM based testbench
    • Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
  • FPV
    • Verify TileLink device protocol compliance with an SVA based testbench

Current status

Design features

For detailed information on rom_ctrl design features, please see the ROM Controller HWIP technical specification.

Testbench architecture

The rom_ctrl testbench has been constructed based on the CIP testbench architecture.

Block diagram

Block diagram

Top level testbench

The top level testbench is located at hw/ip/rom_ctrl/dv/tb/ It instantiates the rom_ctrl DUT module hw/ip/rom_ctrl/rtl/ In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db:

Common DV utility components

The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

Compile-time configurations

There is only one compile-time configuration, where arbitrary values are chosen for compile-time constants.


The rom_ctrl testbench instantiates (already handled in CIP base env) tl_agent. This provides the ability to drive and independently monitor random traffic via both TL host interfaces into the DUT.


The rom_ctrl RAL model is created with the ralgen FuseSoC generator script automatically when the simulation is at the build stage.

Stimulus strategy

Test sequences

The test sequences reside in hw/ip/rom_ctrl/dv/env/seq_lib. All test sequences are extended from rom_ctrl_base_vseq, which is extended from cip_base_vseq and serves as a starting point. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. Some of the most commonly used tasks / functions are as follows:

  • rom_ctrl_mem_init: initialize the rom to random values
  • do_rand_ops: drive random traffic into the rom TLUL interface

Functional coverage

To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:

  • TODO

Self-checking strategy


The rom_ctrl_scoreboard is primarily used for end to end checking. It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:

  • kmac_req_fifo
  • kmac_resp_fifo

The scoreboard monitors traffic sent to and from the KMAC interface. Data sent to KMAC during rom checking are compared against expected values from the memory model. The data received from the KMAC interface are used to update expected digest values and expected check pass/fail values.

Traffic from the ROM TLUL interface is monitored and compared against memory model to check for correctness.


  • TLUL assertions: The tb/ file binds the tlul_assert assertions to the IP to ensure TileLink interface protocol compliance.
  • Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.

Building and running tests

We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:

$ $REPO_TOP/util/dvsim/ $REPO_TOP/hw/ip/rom_ctrl/dv/rom_ctrl_sim_cfg.hjson -i rom_ctrl_smoke



Milestone Name Tests Description
V1 smoke rom_ctrl_smoke

Smoke test exercising the main features of rom_ctrl.


  • Create a random valid ROM where expected digest doesn't match with the KMAC digest image and load into memory model
  • Allow the rom check to complete
  • Perform some random memory accesses
  • Create a random valid ROM where expected digest matches with the KMAC digest
  • Repeat steps 2 and 3.


  • Check that all data supplied to kmac is correct
  • Check that the rom checking sequence gives the expected result
  • Check that the memory accesses return expected data
  • Check that pwrmgr_data_o.good is not asserted in first iteration.
  • Check that pwrmgr_data_o.good is asserted in second iteration.
  • Check that tile link accesses are blocked till pwrmgr_data_o.done is asserted.
V1 csr_hw_reset rom_ctrl_csr_hw_reset

Verify the reset values as indicated in the RAL specification.

  • Write all CSRs with a random value.
  • Apply reset to the DUT as well as the RAL model.
  • Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_rw rom_ctrl_csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

  • Loop through each CSR to write it with a random value.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_bit_bash rom_ctrl_csr_bit_bash

Verify no aliasing within individual bits of a CSR.

  • Walk a 1 through each CSR by flipping 1 bit at a time.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • This verify that writing a specific bit within the CSR did not affect any of the other bits.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_aliasing rom_ctrl_csr_aliasing

Verify no aliasing within the CSR address space.

  • Loop through each CSR to write it with a random value
  • Shuffle and read ALL CSRs back.
  • All CSRs except for the one that was written in this iteration should read back the previous value.
  • The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_mem_rw_with_rand_resetrom_ctrl_csr_mem_rw_with_rand_reset

Verify random reset during CSR/memory access.

  • Run csr_rw sequence to randomly access CSRs
  • If memory exists, run mem_partial_access in parallel with csr_rw
  • Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
V1 mem_walk rom_ctrl_mem_walk

Verify accessibility of all memories in the design.

  • Run the standard UVM mem walk sequence on all memories in the RAL model.
  • It is mandatory to run this test from all available interfaces the memories are accessible from.
V1 mem_partial_access rom_ctrl_mem_partial_access

Verify partial-accessibility of all memories in the design.

  • Do partial reads and writes into the memories and verify the outcome for correctness.
  • Also test outstanding access on memories
V2 stress_all rom_ctrl_stress_all
  • Combine above sequences in one test to run sequentially.
  • Randomly add reset between each sequence
V2 alert_test rom_ctrl_alert_test

Verify common alert_test CSR that allows SW to mock-inject alert requests.

  • Enable a random set of alert requests by writing random value to alert_test CSR.
  • Check each alert_tx.alert_p pin to verify that only the requested alerts are triggered.
  • During alert_handshakes, write alert_test CSR again to verify that: If alert_test writes to current ongoing alert handshake, the alert_test request will be ignored. If alert_test writes to current idle alert handshake, a new alert_handshake should be triggered.
  • Wait for the alert handshakes to finish and verify alert_tx.alert_p pins all sets back to 0.
  • Repeat the above steps a bunch of times.
V2 tl_d_oob_addr_access rom_ctrl_tl_errors

Access out of bounds address and verify correctness of response / behavior

V2 tl_d_illegal_access rom_ctrl_tl_errors

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the [TLUL spec]({{< relref "hw/ip/tlul/doc/" >}})

  • TL-UL protocol error cases
    • invalid opcode
    • some mask bits not set when opcode is PutFullData
    • mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
    • mask and address misaligned, e.g. a_address = 0x01, a_mask = 'b0001
    • address and size aren't aligned, e.g. a_address = 0x01, a_size != 0
    • size is greater than 2
  • OpenTitan defined error cases
    • access unmapped address, expect d_error = 1 when devmode_i == 1
    • write a CSR with unaligned address, e.g. a_address[1:0] != 0
    • write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
    • write a memory with a_mask != '1 when it doesn't support partial accesses
    • read a WO (write-only) memory
    • write a RO (read-only) memory
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

V2 tl_d_partial_access rom_ctrl_csr_hw_reset

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

V2S corrupt_sig_fatal_chk

Corrupt integrity of signals like the select signal to addr mux.


  • Check that fatal error is flagged.
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err

Verify data integrity is stored in the passthru memory rather than generated after a read.

  • Randomly read a memory location and check the data integrity is correct.
  • Backdoor inject fault into this location.
  • Check the data integrity is incorrect but there is no d_error as the memory block should just pass the stored data and integrity to the processor where the integrity is compared.
  • Above sequences will be run with csr_rw_vseq to ensure it won't affect CSR accesses.
V2S tl_intg_err rom_ctrl_tl_intg_err

Verify that the data integrity check violation generates an alert.

Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.


Name Description

Collect coverage on the outputs sent to the power manager to confirm that we see pass and fail results.


Collect coverage on the rom_ctrl / kmac interface, specifically around stalling and back-pressure behavior.

The agent needs to cover the case where the kmac returns a digest before the rom_ctrl finishes reading the expected digest from memory, and also after.


-Collect coverage on the two TLUL interfaces, specifically checking that we see requests around the same time as the rom check completes.

  • Collect coverage to ensure that a_valid goes high when rom check is in progress. This ensures that the scenario where TL accesses are blocked until the ROM check is done is covered.

Cover the following error cases on TL-UL bus:

  • TL-UL protocol error cases.
  • OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.