Reset Manager HWIP Technical Specification

Overview

This document describes the functionality of the reset controller and its interaction with the rest of the OpenTitan system.

Features

  • Stretch incoming POR.
  • Cascaded system resets.
  • Peripheral system reset requests.
  • RISC-V non-debug-module reset support.
  • Limited and selective software controlled module reset.
  • Always-on reset information register.
  • Always-on alert crash dump register.
  • Always-on CPU crash dump register.
  • Reset consistency checks.

Theory of Operation

The OpenTitan reset topology and reset controller block diagram are shown in the diagram below. The reset controller is closely related to the power controller, please refer to that spec for details on how reset controller inputs are controlled.

Reset Topology

Reset Topology

The topology can be summarized as follows:

  • There are two reset domains
    • Test Domain - Driven by TRSTn
    • Core Domain - Driven by internal POR circuitry.
  • Test domain is comprised of the following components
    • SOC TAP and related DFT circuits
    • RISC-V TAP (part of the rv_dm module)

The test domain does not have sub reset trees. TRSTn is used directly by all components in the domain.

The Core domain consists of all remaining logic and contains 4 sub reset trees, see table below.

Reset Tree Description
rst_por_n POR reset tree.

This reset is driven by ast, stretched inside the reset manager and resets all core domain logic in the design.

rst_lc_n Life Cycle reset tree.

This reset is derived from rst_por_n and resets all logic in the design except:

  • rv_dm
  • A small portion of pinmux
rst_sys_n Debug reset tree.

This reset is derived from rst_por_n and resets debug domain logic excluded in the life cycle reset tree

rst_{module}_n Module specific reset.

This reset is derived from rst_lc_n and sets only the targeted module and nothing else.

For OpenTitan, the only current targets are spi_device, all instances of spi_host, all instances of i2c and usbdev

The reset trees are cascaded upon one another in this order:

  • rst_por_n -> rst_lc_n -> rst_module_n
  • rst_por_n -> rst_sys_n -> rst_module_n This means when a particular reset asserts, all downstream resets also assert.

The primary difference between rst_lc_n and rst_sys_n is that the former controls the reset state of most logic in the system, while the latter controls the reset state only of the debug domain. This separation is required because the debug domain may request the system to reset while retaining debug info and control. This is particularly useful if one wanted to debug something early during the boot flow, and thus needed to set a break point after requesting a debug reset.

The reset topology also contains additional properties:

  • Selective processor HART resets, such as hartreset in dmcontrol, are not implemented, as it causes a security policy inconsistency with the remaining system.
    • Specifically, these selective resets can cause the cascaded property shown above to not be obeyed.
  • Modules do not implement local resets that wipe configuration registers, especially if there are configuration locks.
    • Modules are allowed to implement local soft resets that clear datapaths; but these are examined on a case by case basis for possible security side channels.
  • In a production system, the Test Reset Input (TRSTn) should be explicitly asserted through system integration.
    • In a production system, TRSTn only needs to be released for RMA transitions and nothing else. .

Reset Manager

The reset manager handles the reset of the core domain, and also holds relevant reset information in CSR registers, such as:

  • RESET_INFO indicates why the system was reset.
  • ALERT_INFO contains the recorded alert status prior to system reset.
    • This is useful in case the reset was triggered by an alert escalation.
  • CPU_INFO contains recorded CPU state prior to system reset.
    • This is useful in case the reset was triggered by a watchdog where the host hung on a particular bus transaction.

Additionally, the reset manager, along with the power manager, accepts requests from the system and asserts resets for the appropriate clock trees. These requests primarily come from the following sources:

  • Peripherals capable of reset requests: such as sysrst_ctrl and always on timers .
  • Debug modules such as rv_dm.
  • Power manager request for low power entry and exit.
  • Escalation reset requests such as those from alert_handler or pwrmgr itself.
  • Direct software request for reset.

Shadow Resets

OpenTitan supports the shadow configuration registers. These are registers stored in two constantly checking copies to ensure the values are not maliciously or accidentally disturbed. For these components, the reset manager outputs a shadow reset dedicated to resetting only the shadow storage. This reset separation ensures that a targetted attack on the reset line cannot easily defeat shadow registers.

Reset Consistency Checks

The reset manager implements reset consistency checks to ensure that triggered resets are supposed to happen and not due to some fault in the system. Every leaf reset in the system has an associated consistency checker.

The consistency check ensures that when a leaf reset asserts, either its parent reset must have asserted, or the software request, if available, has asserted. While this sounds simple in principle, the check itself crosses up to 3 clock domains and must be carefully managed.

First, the parent and leaf resets are used to asynchronously assert a flag indication. This flag indication is then synchronized into the reset manager’s local clock domain.

The reset manager then checks as follows:

  • If a leaf reset has asserted, check to see either its parent or software request (synchronous to the local domain) has asserted.

  • If the condition is not true, it is possible the parent reset indication is still being synchronized, thus we wait for the parent indication.

  • It is also possible the parent indication was seen first, but the leaf condition was not, in this case, we wait for the leaf indication.

  • A timeout period corresponding to the maximum synchronization delay is used to cover both waits.

    • If the appropriate pairing is not seen in the given amount of time, signal an error, as the leaf reset asserted without cause.
  • If all reset conditions are satisfied, wait for the reset release to gracefully complete the cycle.

Hardware Interfaces

Parameters

The following table lists the instantiation parameters of rstmgr.

Parameter Default Description
SecCheck 1 Enables reset consistency checks on the leaf reset. Each check contains a small FSM.
SecMaxSyncDelay 2 The default synchronization delay assumptions used in reset consistency checks. If a design uses a sync cell with more stages of delay, that value should be supplied.

Signals

Referring to the Comportable guideline for peripheral device functionality, the module RSTMGR has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: clk_aon_i, clk_io_div4_i, clk_main_i, clk_io_i, clk_io_div2_i, clk_usb_i, clk_por_i

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO: none

Inter-Module Signals: Reference

Inter-Module Signals
Port Name Package::Struct Type Act Width Description
por_n logic uni rcv 2 Root power on reset signals from ast. There is one root reset signal for each core power domain.
pwr pwr_rst req_rsp rsp 1 Reset request signals from power manager. Power manager can request for specific domains of the lc/sys reset tree to assert.
resets rstmgr_pkg::rstmgr_out uni req 1 Leaf resets fed to the system.
rst_en rstmgr_pkg::rstmgr_rst_en uni req 1 Low-power-group outputs used by alert handler.
alert_dump alert_pkg::alert_crashdump uni rcv 1 Alert handler crash dump information.
cpu_dump rv_core_ibex_pkg::cpu_crash_dump uni rcv 1 Main processing element crash dump information.
sw_rst_req prim_mubi_pkg::mubi4 uni req 1 Software requested system reset to pwrmgr.
tl tlul_pkg::tl req_rsp rsp 1

Interrupts: none

Security Alerts:

Alert NameDescription
fatal_fault

This fatal alert is triggered when a fatal structural fault is detected. Structural faults include errors such as sparse fsm errors and tlul integrity errors.

fatal_cnsty_fault

This fatal alert is triggered when a reset consistency fault is detected. It is separated from the category above for clearer error collection and debug.

Security Countermeasures:

Countermeasure IDDescription
RSTMGR.BUS.INTEGRITY

End-to-end bus integrity scheme.

RSTMGR.SCAN.INTERSIG.MUBI

scan control signals are multibit

RSTMGR.LEAF.RST.BKGN_CHK

Background consistency checks for each leaf reset.

RSTMGR.LEAF.RST.SHADOW

Leaf resets to blocks containing shadow registers are shadowed

RSTMGR.LEAF.FSM.SPARSE

Sparsely encoded fsm for each leaf rst check. The Hamming delta is only 3 as there are a significant number of leaf resets

RSTMGR.SW_RST.CONFIG.REGWEN

Software reset controls are protected by regwen

RSTMGR.DUMP_CTRL.CONFIG.REGWEN

Crash dump controls are protected by regwen

Design Details

The reset manager generates the resets required by the system by synchronizing reset tree components to appropriate output clocks. As a result, a particular reset tree (for example rst_lc_n) may have multiple outputs depending on the clock domains of its consumers.

Each reset tree is discussed in detail below.

POR Reset Tree

The POR reset tree, rst_por_n, is the root reset of the entire device. If this reset ever asserts, everything in the design is reset.

The ast input aon_pok is used as the root reset indication. It is filtered and stretched to cover any slow voltage ramp scenarios. The stretch parameters are design time configurations.

  • The filter acts as a synchronizer and is by default 3 stages.
  • The count by default is 32.
    • The counter increments only when all stages of the filter are 1.
    • If any stage at any point becomes ‘0’, the reset counter returns to 0 and downstream logic is driven to reset again.
  • Both functions are expected to operate on slow, always available KHz clocks.

Life Cycle Reset Tree

Life cycle reset, rst_lc_n asserts under the following conditions:

  • Whenever rst_por_n asserts.
  • Whenever a peripheral reset request (always on timer watchdog, rbox reset request, alert handler escalation, direct software request) is received.

The rst_lc_n tree contains both always-on and non-always-on versions. How many non-always-on versions is dependent on how many power domains are supported by the system.

System Reset Tree

System reset, rst_sys_n , assertion depends on life cycle state.

When in PROD and PROD_END states, rst_sys_n is identical to rst_lc_n.

When in TEST, RMA and DEV states, rst_sys_n is identical to rst_lc_n unless the reset request is ndmreset_req. ndmreset_req is issued by the debug module of the system, it requests for all logic, except those needed to maintain debug state to reset.

Since ndmreset_req is valid only during TEST, RMA and DEV states, it is the only place where the reset is differentiated. During these states, when ndmreset_req is issued, all logic except the debug module and associated glue logic are reset.

The rst_sys_n tree contains both always-on and non-always-on versions. How many non-always-on versions is dependent on how many power domains are supported by the system.

Output Leaf Resets

The reset trees discussed above are not directly output to the system for consumption. Instead, the output leaf resets are synchronized versions of the various root resets. How many leaf resets there are and to which clock is decided by the system and templated through the reset manager module.

Assuming a leaf output has N power domains and M clock domains, it potentially means one reset tree may output NxM outputs to satisfy all the reset scenario combinations.

Power Domains and Reset Trees

It is alluded above that reset trees may contain both always-on and non-always-on versions. This distinction is required to support power manager’s various low power states. When a power domain goes offline, all of its components must reset, regardless of the reset tree to which it belongs.

For example, assume a system with two power domains - Domain A is always-on, and Domain B is non-always-on. When Domain B is powered off, all of Domain B’s resets, from rst_lc_n, rst_sys_n to rst_module_n are asserted. However, the corresponding resets for Domain A are left untouched because it has not been powered off.

Software Controlled Resets

Certain leaf resets can be directly controlled by software. Due to security considerations, most leaf resets cannot be controlled, only a few blocks are given exceptions. The only blocks currently allowed to software reset are spi_device, usbdev, spi_host and i2c.

The criteria for selecting which block is software reset controllable is meant to be overly restrictive. Unless there is a clear need, the default option is to not provide reset control.

In general, the following rules apply:

  • If a module has configuration register lockdown, it cannot be software resettable.
  • If a module operates on secret data (keys), it cannot be software resettable.
    • Or a software reset should render the secret data unusable until some initialization routine is run to reduce the Hamming leakage of secret data.
  • If a module can alter the software’s perception of time or general control flow (timer or interrupt aggregator), it cannot be software resettable.
  • If a module contains sensor functions for security, it cannot be software resettable.
  • If a module controls life cycle or related function, it cannot be software resettable.

Summary

The following table summarizes the different reset requests and which part of each reset tree, along with what power domain is affected.

Reset Request Type Example POR Reset Tree LC Reset Tree SYS Reset Tree Module Specific Reset
POR VCC toggle, POR_N pad toggle all domains all domains all domains all domains
HW reset Request aon_timer reset request, alert_handler escalation request all domains all domains all domains
Directed SW system reset request rstmgr SW_RESET all domains all domains all domains
Ndm reset request (PROD/PROD_END) rv_dm non-debug-module reset request in PROD all domains all domains all domains
Ndm reset request (Other states) rv_dm non-debug-module reset request in DEV all domains all domains
SW low power entry wait-for-interrupt deep sleep entry non-aon domains non-aon domains non-aon domains
SW controlled reset request rstmgr SW_RST_CTRL_N all domains

Reset Information

The reset information register is a reflection of the reset state from the perspective of the system. In OpenTitan, since there is only 1 host, it is thus from the perspective of the processor. This also suggests that if the design had multiple processors, there would need to be multiple such registers.

If a reset does not cause the processor to reset, there is no reason for the reset information to change (this is also why there is a strong security link between the reset of the processor and the rest of the system). The following are the currently defined reset reasons and their meaning:

Reset Cause Description
POR Cold boot, the system was reset through POR circuitry.
LOW_POWER_EXIT Warm boot, the system was reset through low power exit.
NDM RESET Warm boot, the system was reset through rv_dm non-debug-module request.
SW_REQ Warm boot, the system was reset through RESET_REQ.
HW_REQ Warm boot, the system was reset through peripheral requests. There may be multiple such requests.

The reset info register is write 1 clear. It is software responsibility to clear old reset reasons; the reset manager simply records based on the rules below.

Excluding power on reset, which is always recorded when the device POR circuitry is triggered, the other resets are recorded when authorized by the reset manager. Reset manager authorization is based on reset categories as indicated by the power manager. The power manager has three reset categories that are mutually exclusive:

  • No reset has been triggered by pwrmgr.
  • Low power entry reset has been triggered by pwrmgr.
  • Software or peripheral reset request has been triggered by pwrmgr.

The reset categories are sent to the reset manager so that it can decide which reason to record when the processor reset is observed. Non-debug-module resets are allowed only when no resets have been triggered by pwrmgr.

Since a reset could be motivated by multiple reasons (a security escalation during low power transition for example), the reset information registers constantly record all reset causes in which it is allowed. The only case where this is not done is POR, where active recording is silenced until the first processor reset release.

Even though four reset causes are labeled as warm boot, their effects on the system are not identical.

  • When the reset cause is LOW_POWER_EXIT, it means only the non-always-on domains have been reset.
    • Always-on domains retain their pre-low power values.
  • When the reset cause is NDM_RESET, it means only the rst_sys_n tree has asserted for all power domains.
  • When the reset cause is HW_REQ or SW_REQ, it means everything other than power / clock / reset managers have reset.

This behavioral difference may be important to software, as it implies the configuration of the system may need to be different.

Crash Dump Information

The reset manager manages crash dump information for software debugging across unexpected resets and watchdogs. When enabled, the latest alert information and latest CPU information are captured in always-on registers.

When the software resumes after the reset, it is then able to examine the last CPU state or the last set of alert information to understand why the system has reset.

The enable for such debug capture can be locked such that it never captures.

Alert Information

The alert information register contains the value of the alert crash dump prior to a triggered reset. Since this information differs in length between system implementation, the alert information register only displays 32-bits at a time. The ALERT_INFO_ATTR register indicates how many 32-bit data segments must be read.

To enable alert crash dump capture, set ALERT_INFO_CTRL.EN to 1. Once the system has reset, check ALERT_INFO_ATTR.CNT_AVAIL for how many reads need to be done. Set ALERT_INFO_CTRL.INDEX to the desired segment, and then read the output from ALERT_INFO.

CPU Information

The CPU information register contains the value of the CPU state prior to a triggered reset. Since this information differs in length between system implementation, the information register only displays 32-bits at a time.

For more details on the CPU dump details, please see crash dump.

The CPU_INFO_ATTR register indicates how many 32-bit data segments must be read. Software then simply needs to write in CPU_INFO_CTRL.INDEX which segment it wishes and then read out the CPU_INFO register.

Programmers Guide

Device Interface Functions (DIFs)

To use this DIF, include the following C header:

#include "sw/device/lib/dif/dif_rstmgr.h"

This header provides the following device interface functions:

Register Table

Summary
Name Offset Length Description
RSTMGR.ALERT_TEST 0x0 4

Alert Test Register

RSTMGR.RESET_REQ 0x4 4

Software requested system reset.

RSTMGR.RESET_INFO 0x8 4

Device reset reason.

RSTMGR.ALERT_REGWEN 0xc 4

Alert write enable

RSTMGR.ALERT_INFO_CTRL 0x10 4

Alert info dump controls.

RSTMGR.ALERT_INFO_ATTR 0x14 4

Alert info dump attributes.

RSTMGR.ALERT_INFO 0x18 4

Alert dump information prior to last reset. Which value read is controlled by the ALERT_INFO_CTRL register.

RSTMGR.CPU_REGWEN 0x1c 4

Cpu write enable

RSTMGR.CPU_INFO_CTRL 0x20 4

Cpu info dump controls.

RSTMGR.CPU_INFO_ATTR 0x24 4

Cpu info dump attributes.

RSTMGR.CPU_INFO 0x28 4

Cpu dump information prior to last reset. Which value read is controlled by the CPU_INFO_CTRL register.

RSTMGR.SW_RST_REGWEN_0 0x2c 4

Register write enable for software controllable resets. When a particular bit value is 0, the corresponding value in !!SW_RST_CTRL_N can no longer be changed. When a particular bit value is 1, the corresponding value in !!SW_RST_CTRL_N can be changed.

RSTMGR.SW_RST_REGWEN_1 0x30 4

Register write enable for software controllable resets. When a particular bit value is 0, the corresponding value in !!SW_RST_CTRL_N can no longer be changed. When a particular bit value is 1, the corresponding value in !!SW_RST_CTRL_N can be changed.

RSTMGR.SW_RST_REGWEN_2 0x34 4

Register write enable for software controllable resets. When a particular bit value is 0, the corresponding value in !!SW_RST_CTRL_N can no longer be changed. When a particular bit value is 1, the corresponding value in !!SW_RST_CTRL_N can be changed.

RSTMGR.SW_RST_REGWEN_3 0x38 4

Register write enable for software controllable resets. When a particular bit value is 0, the corresponding value in !!SW_RST_CTRL_N can no longer be changed. When a particular bit value is 1, the corresponding value in !!SW_RST_CTRL_N can be changed.

RSTMGR.SW_RST_REGWEN_4 0x3c 4

Register write enable for software controllable resets. When a particular bit value is 0, the corresponding value in !!SW_RST_CTRL_N can no longer be changed. When a particular bit value is 1, the corresponding value in !!SW_RST_CTRL_N can be changed.

RSTMGR.SW_RST_REGWEN_5 0x40 4

Register write enable for software controllable resets. When a particular bit value is 0, the corresponding value in !!SW_RST_CTRL_N can no longer be changed. When a particular bit value is 1, the corresponding value in !!SW_RST_CTRL_N can be changed.

RSTMGR.SW_RST_REGWEN_6 0x44 4

Register write enable for software controllable resets. When a particular bit value is 0, the corresponding value in !!SW_RST_CTRL_N can no longer be changed. When a particular bit value is 1, the corresponding value in !!SW_RST_CTRL_N can be changed.

RSTMGR.SW_RST_REGWEN_7 0x48 4

Register write enable for software controllable resets. When a particular bit value is 0, the corresponding value in !!SW_RST_CTRL_N can no longer be changed. When a particular bit value is 1, the corresponding value in !!SW_RST_CTRL_N can be changed.

RSTMGR.SW_RST_CTRL_N_0 0x4c 4

Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset.

RSTMGR.SW_RST_CTRL_N_1 0x50 4

Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset.

RSTMGR.SW_RST_CTRL_N_2 0x54 4

Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset.

RSTMGR.SW_RST_CTRL_N_3 0x58 4

Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset.

RSTMGR.SW_RST_CTRL_N_4 0x5c 4

Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset.

RSTMGR.SW_RST_CTRL_N_5 0x60 4

Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset.

RSTMGR.SW_RST_CTRL_N_6 0x64 4

Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset.

RSTMGR.SW_RST_CTRL_N_7 0x68 4

Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset.

RSTMGR.ERR_CODE 0x6c 4

A bit vector of all the errors that have occurred in reset manager

RSTMGR.ALERT_TEST @ 0x0

Alert Test Register

Reset default = 0x0, mask 0x3
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  fatal_cnsty_fault fatal_fault
BitsTypeResetNameDescription
0wo0x0fatal_fault

Write 1 to trigger one alert event of this kind.

1wo0x0fatal_cnsty_fault

Write 1 to trigger one alert event of this kind.


RSTMGR.RESET_REQ @ 0x4

Software requested system reset.

Reset default = 0x9, mask 0xf
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  VAL
BitsTypeResetNameDescription
3:0rw0x9VAL

When set to kMultiBitBool4True, a reset to power manager is requested. Upon completion of reset, this bit is automatically cleared by hardware.


RSTMGR.RESET_INFO @ 0x8

Device reset reason.

Reset default = 0x1, mask 0xff
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  HW_REQ SW_RESET LOW_POWER_EXIT POR
BitsTypeResetNameDescription
0rw1c0x1POR

Indicates when a device has reset due to power up.

1rw1c0x0LOW_POWER_EXIT

Indicates when a device has reset due low power exit.

2rw1c0x0SW_RESET

Indicates when a device has reset due to RESET_REQ.

7:3rw1c0x0HW_REQ

Indicates when a device has reset due to a hardware requested reset. The bit mapping is as follows: b3: sysrst_ctrl_aon: OpenTitan reset request to rstmgr (running on AON clock). b4: aon_timer_aon: watchdog reset requestt b5: pwrmgr_aon: main power glitch reset request b6: alert_handler: escalation reset request b7: rv_dm: non-debug-module reset request


RSTMGR.ALERT_REGWEN @ 0xc

Alert write enable

Reset default = 0x1, mask 0x1
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  EN
BitsTypeResetNameDescription
0rw0c0x1EN

When 1, ALERT_INFO_CTRL can be modified.


RSTMGR.ALERT_INFO_CTRL @ 0x10

Alert info dump controls.

Reset default = 0x0, mask 0xf1
Register enable = ALERT_REGWEN
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  INDEX   EN
BitsTypeResetNameDescription
0rw0x0EN

Enable alert dump to capture new information. This field is automatically set to 0 upon system reset (even if rstmgr is not reset).

3:1Reserved
7:4rw0x0INDEX

Controls which 32-bit value to read.


RSTMGR.ALERT_INFO_ATTR @ 0x14

Alert info dump attributes.

Reset default = 0x0, mask 0xf
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  CNT_AVAIL
BitsTypeResetNameDescription
3:0ro0x0CNT_AVAIL

The number of 32-bit values contained in the alert info dump.


RSTMGR.ALERT_INFO @ 0x18

Alert dump information prior to last reset. Which value read is controlled by the ALERT_INFO_CTRL register.

Reset default = 0x0, mask 0xffffffff
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VALUE...
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...VALUE
BitsTypeResetNameDescription
31:0ro0x0VALUE

The current 32-bit value of crash dump.


RSTMGR.CPU_REGWEN @ 0x1c

Cpu write enable

Reset default = 0x1, mask 0x1
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  EN
BitsTypeResetNameDescription
0rw0c0x1EN

When 1, CPU_INFO_CTRL can be modified.


RSTMGR.CPU_INFO_CTRL @ 0x20

Cpu info dump controls.

Reset default = 0x0, mask 0xf1
Register enable = CPU_REGWEN
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  INDEX   EN
BitsTypeResetNameDescription
0rw0x0EN

Enable cpu dump to capture new information. This field is automatically set to 0 upon system reset (even if rstmgr is not reset).

3:1Reserved
7:4rw0x0INDEX

Controls which 32-bit value to read.


RSTMGR.CPU_INFO_ATTR @ 0x24

Cpu info dump attributes.

Reset default = 0x0, mask 0xf
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  CNT_AVAIL
BitsTypeResetNameDescription
3:0ro0x0CNT_AVAIL

The number of 32-bit values contained in the cpu info dump.


RSTMGR.CPU_INFO @ 0x28

Cpu dump information prior to last reset. Which value read is controlled by the CPU_INFO_CTRL register.

Reset default = 0x0, mask 0xffffffff
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VALUE...
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...VALUE
BitsTypeResetNameDescription
31:0ro0x0VALUE

The current 32-bit value of crash dump.


RSTMGR.SW_RST_REGWEN_0 @ 0x2c

Register write enable for software controllable resets. When a particular bit value is 0, the corresponding value in !!SW_RST_CTRL_N can no longer be changed. When a particular bit value is 1, the corresponding value in !!SW_RST_CTRL_N can be changed.

Reset default = 0x1, mask 0x1
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  EN_0
BitsTypeResetNameDescription
0rw0c0x1EN_0

Register write enable for software controllable resets


RSTMGR.SW_RST_REGWEN_1 @ 0x30

Register write enable for software controllable resets. When a particular bit value is 0, the corresponding value in !!SW_RST_CTRL_N can no longer be changed. When a particular bit value is 1, the corresponding value in !!SW_RST_CTRL_N can be changed.

Reset default = 0x1, mask 0x1
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  EN_1
BitsTypeResetNameDescription
0rw0c0x1EN_1

For RSTMGR_SW_RST1


RSTMGR.SW_RST_REGWEN_2 @ 0x34

Register write enable for software controllable resets. When a particular bit value is 0, the corresponding value in !!SW_RST_CTRL_N can no longer be changed. When a particular bit value is 1, the corresponding value in !!SW_RST_CTRL_N can be changed.

Reset default = 0x1, mask 0x1
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  EN_2
BitsTypeResetNameDescription
0rw0c0x1EN_2

For RSTMGR_SW_RST2


RSTMGR.SW_RST_REGWEN_3 @ 0x38

Register write enable for software controllable resets. When a particular bit value is 0, the corresponding value in !!SW_RST_CTRL_N can no longer be changed. When a particular bit value is 1, the corresponding value in !!SW_RST_CTRL_N can be changed.

Reset default = 0x1, mask 0x1
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  EN_3
BitsTypeResetNameDescription
0rw0c0x1EN_3

For RSTMGR_SW_RST3


RSTMGR.SW_RST_REGWEN_4 @ 0x3c

Register write enable for software controllable resets. When a particular bit value is 0, the corresponding value in !!SW_RST_CTRL_N can no longer be changed. When a particular bit value is 1, the corresponding value in !!SW_RST_CTRL_N can be changed.

Reset default = 0x1, mask 0x1
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  EN_4
BitsTypeResetNameDescription
0rw0c0x1EN_4

For RSTMGR_SW_RST4


RSTMGR.SW_RST_REGWEN_5 @ 0x40

Register write enable for software controllable resets. When a particular bit value is 0, the corresponding value in !!SW_RST_CTRL_N can no longer be changed. When a particular bit value is 1, the corresponding value in !!SW_RST_CTRL_N can be changed.

Reset default = 0x1, mask 0x1
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  EN_5
BitsTypeResetNameDescription
0rw0c0x1EN_5

For RSTMGR_SW_RST5


RSTMGR.SW_RST_REGWEN_6 @ 0x44

Register write enable for software controllable resets. When a particular bit value is 0, the corresponding value in !!SW_RST_CTRL_N can no longer be changed. When a particular bit value is 1, the corresponding value in !!SW_RST_CTRL_N can be changed.

Reset default = 0x1, mask 0x1
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  EN_6
BitsTypeResetNameDescription
0rw0c0x1EN_6

For RSTMGR_SW_RST6


RSTMGR.SW_RST_REGWEN_7 @ 0x48

Register write enable for software controllable resets. When a particular bit value is 0, the corresponding value in !!SW_RST_CTRL_N can no longer be changed. When a particular bit value is 1, the corresponding value in !!SW_RST_CTRL_N can be changed.

Reset default = 0x1, mask 0x1
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  EN_7
BitsTypeResetNameDescription
0rw0c0x1EN_7

For RSTMGR_SW_RST7


RSTMGR.SW_RST_CTRL_N_0 @ 0x4c

Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset.

Reset default = 0x1, mask 0x1
Register enable = SW_RST_REGWEN_0
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  VAL_0
BitsTypeResetNameDescription
0rw0x1VAL_0

Software reset value


RSTMGR.SW_RST_CTRL_N_1 @ 0x50

Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset.

Reset default = 0x1, mask 0x1
Register enable = SW_RST_REGWEN_1
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  VAL_1
BitsTypeResetNameDescription
0rw0x1VAL_1

For RSTMGR_SW_RST1


RSTMGR.SW_RST_CTRL_N_2 @ 0x54

Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset.

Reset default = 0x1, mask 0x1
Register enable = SW_RST_REGWEN_2
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  VAL_2
BitsTypeResetNameDescription
0rw0x1VAL_2

For RSTMGR_SW_RST2


RSTMGR.SW_RST_CTRL_N_3 @ 0x58

Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset.

Reset default = 0x1, mask 0x1
Register enable = SW_RST_REGWEN_3
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  VAL_3
BitsTypeResetNameDescription
0rw0x1VAL_3

For RSTMGR_SW_RST3


RSTMGR.SW_RST_CTRL_N_4 @ 0x5c

Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset.

Reset default = 0x1, mask 0x1
Register enable = SW_RST_REGWEN_4
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  VAL_4
BitsTypeResetNameDescription
0rw0x1VAL_4

For RSTMGR_SW_RST4


RSTMGR.SW_RST_CTRL_N_5 @ 0x60

Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset.

Reset default = 0x1, mask 0x1
Register enable = SW_RST_REGWEN_5
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  VAL_5
BitsTypeResetNameDescription
0rw0x1VAL_5

For RSTMGR_SW_RST5


RSTMGR.SW_RST_CTRL_N_6 @ 0x64

Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset.

Reset default = 0x1, mask 0x1
Register enable = SW_RST_REGWEN_6
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  VAL_6
BitsTypeResetNameDescription
0rw0x1VAL_6

For RSTMGR_SW_RST6


RSTMGR.SW_RST_CTRL_N_7 @ 0x68

Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset.

Reset default = 0x1, mask 0x1
Register enable = SW_RST_REGWEN_7
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  VAL_7
BitsTypeResetNameDescription
0rw0x1VAL_7

For RSTMGR_SW_RST7


RSTMGR.ERR_CODE @ 0x6c

A bit vector of all the errors that have occurred in reset manager

Reset default = 0x0, mask 0x7
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  FSM_ERR RESET_CONSISTENCY_ERR REG_INTG_ERR
BitsTypeResetNameDescription
0ro0x0REG_INTG_ERR

The register file has experienced an integrity error.

1ro0x0RESET_CONSISTENCY_ERR

A inconsistent parent / child reset was observed.

2ro0x0FSM_ERR

Sparsely encoded fsm error.