# RSTMGR DV document

## Goals

• DV
• Verify all RSTMGR IP features by running dynamic simulations with a SV/UVM based testbench
• Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
• FPV
• Verify TileLink device protocol compliance with an SVA based testbench

## Design features

For detailed information on RSTMGR design features, please see the RSTMGR HWIP technical specification.

## Testbench architecture

RSTMGR testbench has been constructed based on the CIP testbench architecture.

### Top level testbench

The top level testbench is located at hw/ip/rstmgr/dv/tb.sv. It instantiates the RSTMGR DUT module hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv. In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db:

### Common DV utility components

The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

### Compile-time configurations

[list compile time configurations, if any and what are they used for]

### Global types & methods

All common types and methods defined at the package level can be found in rstmgr_env_pkg. Some of them in use are:

[list a few parameters, types & methods; no need to mention all]


### TL_agent

The RSTMGR testbench instantiates (already handled in CIP base env) tl_agent. This provides the ability to drive and independently monitor random traffic via the TL host interface into the RSTMGR device.

### UVM RAL Model

The RSTMGR RAL model is created with the ralgen FuseSoC generator script automatically when the simulation is at the build stage.

It can be created manually by invoking regtool:

### Reference models

[Describe reference models in use if applicable, example: SHA256/HMAC]

### Stimulus strategy

The following test sequences and covergroupsare described in more detail in the testplan at hw/ip/pwrmgr/data/rstmgr_testplan.hjson, and also included below.

#### Test sequences

The test sequences reside in hw/ip/rstmgr/dv/env/seq_lib. All test sequences are extended from rstmgr_base_vseq, which is extended from cip_base_vseq and serves as a starting point. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. Some of the most commonly used tasks / functions are as follows:

• task wait_for_cpu_out_of_reset: Waits for the resets_o.rst_sys_n[1] to go high, indicating the CPU is out of reset and CSRs can be accessed.

The rstmgr_smoke_vseq tests the rstmgr through software initiated low power, peripheral reset, ndm reset, and software initiated resets.

#### Functional coverage

To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:

• cg1:
• cg2:

### Self-checking strategy

#### Scoreboard

The rstmgr_scoreboard is primarily used for end to end checking. It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:

• analysis port1:
• analysis port2:

#### Assertions

• TLUL assertions: The tb/rstmgr_bind.sv file binds the tlul_assert assertions to the IP to ensure TileLink interface protocol compliance.
• Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
• assert prop 1:
• assert prop 2:

## Building and running tests

We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:

REPO_TOP/util/dvsim/dvsim.py \$REPO_TOP/hw/ip/rstmgr/dv/rstmgr_sim_cfg.hjson -i rstmgr_smoke


## Testplan

{{< incGenFromIpDesc “hw/ip/rstmgr/data/rstmgr_testplan.hjson” “testplan” >}}