RSTMGR DV document
Goals
- DV
- Verify all RSTMGR IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
- FPV
- Verify TileLink device protocol compliance with an SVA based testbench
Current status
Design features
For detailed information on RSTMGR design features, please see the RSTMGR HWIP technical specification.
Testbench architecture
RSTMGR testbench has been constructed based on the CIP testbench architecture.
Block diagram
Top level testbench
The top level testbench is located at hw/ip/rstmgr/dv/tb.sv
.
It instantiates the RSTMGR DUT module hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
.
In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db
:
- Clock and reset interface
- TileLink host interface
- RSTMGR interface
hw/ip/rstmgr/dv/env/rstmgr_if.sv
- Alerts (
alert_esc_if
) - Devmode (
pins_if
)
Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
Global types & methods
All common types and methods defined at the package level can be found in
rstmgr_env_pkg
. Some of them in use are:
typedef logic [NumSwResets-1:0] sw_rst_t;
typedef logic [$bits(alert_pkg::alert_crashdump_t)-1:0] linearized_alert_dump_t;
typedef virtual pwrmgr_rstmgr_sva_if #(.CHECK_RSTREQS(0)) parameterized_pwrmgr_rstmgr_sva_vif;
TL_agent
The RSTMGR testbench instantiates (already handled in CIP base env) tl_agent. This provides the ability to drive and independently monitor random traffic via the TL host interface into the RSTMGR device.
Alert_agents
RSTMGR testbench instantiates (already handled in CIP base env) alert_agents: [list alert names]. The alert_agents provide the ability to drive and independently monitor alert handshakes via alert interfaces in RSTMGR device.
UVM RAL Model
The RSTMGR RAL model is created with the ralgen
FuseSoC generator script automatically when the simulation is at the build stage.
It can be created manually by invoking regtool
.
Stimulus strategy
The following test sequences and covergroups are described in more detail in the testplan at hw/ip/pwrmgr/data/rstmgr_testplan.hjson
, and also included below.
This IP is only reset via the por_n_i
input, and by scan_rst_ni
qualified by scanmode_i
being active.
The regular rst_ni
input is connected to its own resets_o.rst_por_io_div4_n[0]
output, so the reset output from clk_rst_if
is not connected.
Similarly, all reset outputs from other clk_rst_if
instances are ignored, and only their clock output is used.
This is consistent with this IP being in charge of all derived resets in the chip.
Besides the POR resets above, the test sequences mostly assert various reset requests from pwrmgr and trigger resets vir RESET_REQ CSR. Alert and CPU dump info is randomized and checked on resets.
Test sequences
The test sequences reside in hw/ip/rstmgr/dv/env/seq_lib
.
All test sequences are extended from rstmgr_base_vseq
, which is extended from cip_base_vseq
and serves as a starting point.
It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:
- task
wait_for_cpu_out_of_reset
: Waits for theresets_o.rst_sys_n[1]
output to go high, indicating the CPU is out of reset and CSRs can be accessed. - task
check_cpu_dump_info
: Reads and compares each field in thecpu_info
CSR against the given cpu dump. - task
check_software_reset_csr_and_pins
: Reads and compares thesw_rst_ctrl_n
CSR and the output reset ports against the given value.
Other sequences follow:
rstmgr_smoke_vseq
tests the rstmgr through software initiated low power, peripheral reset, ndm reset, and software initiated resets.rstmgr_reset_stretcher_vseq
tests theresets_o.rst_por_aon_n[0]
output is asserted after 32 stable cycles ofast_i.aon_pok
.rstmgr_sw_rst_vseq
tests the functionality provided by thesw_rst_regwen
andsw_rst_ctrl_n
.rstmgr_reset_info_vseq
tests thereset_info
CSR contents correspond to the different resets.rstmgr_cpu_info_vseq
tests thecpu_info
CSR contents capture to thecpu_dump_i
present at the time of a reset.rstmgr_alert_info_vseq
tests thealert_info
CSR contents capture to thealert_dump_i
present at the time of a reset.
Functional coverage
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:
reset_stretcher_cg
alert_info_cg
cpu_info_cg
alert_info_capture_cg
cpu_info_capture_cg
sw_rst_cg
Self-checking strategy
Most self checking is done using SVA, and via explicit CSR reads. The latter are described in the testplan.
Assertions
- TLUL assertions: The
tb/rstmgr_bind.sv
file binds thetlul_assert
assertions to the IP to ensure TileLink interface protocol compliance. - Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
- Response to pwrmgr’s
rst_lc_req
andrst_sys_req
inputs: these trigger transitions inrst_lc_src_n
andrst_sys_rst_n
outputs. Checked via SVAs inhw/ip/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.sv
. - Response to
cpu_i.ndmreset_req
input: after it is asserted, rstmgr’srst_sys_src_n
should go active. Checked via SVA inhw/ip/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.sv
. - Resets cascade hierarchically per Reset Topology.
Checked via SVA in
hw/ip/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv
. - POR must be active for at least 32 consecutive cycles before going inactive before output resets go inactive.
Checked via SVA in
hw/ip/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv
. - The scan reset
scan_rst_ni
qualified byscanmode_i
triggers all cascaded resets thatpor_n_i
does. Checked via SVA inhw/ip/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv
. - Software resets to peripherals also cascade hierarchically.
Checked via SVA in
hw/ip/rstmgr/dv/sva/rstmgr_sw_rst_sva_if.sv
. - The output
rst_en_o
for alert_handler tracks their corresponding resets. Checked via SVA in bothhw/ip/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv
andhw/ip/rstmgr/dv/sva/rstmgr_sw_rst_sva_if.sv
. - The
alert
andcpu_info_attr
indicate the number of 32-bit words needed to capture their inputs. Checked via SVA inhw/ip/rstmgr/dv/sva/rstmgr_attrs_sva_if.sv
.
Testing V2S components
The rstmgr_cnsty_chk module is a D2S component.
It depends on very specific timing, and requires tampering stimulus to verify its functionality.
It has its own separate dv environment and tests at hw/ip/rstmgr/dv/rstmgr_cnsty_chk
.
It is excluded from coverage for the rstmgr dv tests.
Building and running tests
We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:
$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/rstmgr/dv/rstmgr_sim_cfg.hjson -i rstmgr_smoke
Testplan
Testpoints
Milestone | Name | Tests | Description |
---|---|---|---|
V1 | smoke | rstmgr_smoke | Smoke test accessing a major datapath within the rstmgr. Checks the behavior of rstmgr when receiving various reset requests. Stimulus:
Checks:
|
V1 | csr_hw_reset | rstmgr_csr_hw_reset | Verify the reset values as indicated in the RAL specification.
|
V1 | csr_rw | rstmgr_csr_rw | Verify accessibility of CSRs as indicated in the RAL specification.
|
V1 | csr_bit_bash | rstmgr_csr_bit_bash | Verify no aliasing within individual bits of a CSR.
|
V1 | csr_aliasing | rstmgr_csr_aliasing | Verify no aliasing within the CSR address space.
|
V1 | csr_mem_rw_with_rand_reset | rstmgr_csr_mem_rw_with_rand_reset | Verify random reset during CSR/memory access.
|
V1 | regwen_csr_and_corresponding_lockable_csr | rstmgr_csr_rw rstmgr_csr_aliasing | Verify regwen CSR and its corresponding lockable CSRs.
Note:
This is only applicable if the block contains regwen and locakable CSRs. |
V2 | reset_stretcher | rstmgr_por_stretcher | Test the POR reset signal must be stable for multiple cycles. The POR reset signal must remain active for at least 32 consecutive cycles before going inactive for the rest of the reset tree to go inactive. Stimulus:
Checks:
|
V2 | sw_rst | rstmgr_sw_rst | Test the sw_rst functionality. The
Stimulus:
Checks:
|
V2 | sw_rst_reset_race | rstmgr_sw_rst_reset_race | Test sw_rst and reset close in time. Sends sw_rst and regular resets in close temporal proximity. Stimulus:
Checks:
|
V2 | reset_info | rstmgr_reset | Test the reporting of reset reason. Stimulus:
Checks:
|
V2 | cpu_info | rstmgr_reset | Test the cpu_info recording. The Stimulus:
Checks:
|
V2 | alert_info | rstmgr_reset | Test the alert_info recording. The Stimulus:
Checks:
|
V2 | reset_info_capture | rstmgr_reset | Test the capture blocking effect of rst_cpu_n input. After an AON reset reset capture is blocked until the input rst_cpu_n goes inactive. Stimulus:
Checks:
|
V2 | stress_all | rstmgr_stress_all | This runs random tests sequentially. Stress with the following sequences:
|
V2 | alert_test | rstmgr_alert_test | Verify common
|
V2 | tl_d_oob_addr_access | rstmgr_tl_errors | Access out of bounds address and verify correctness of response / behavior |
V2 | tl_d_illegal_access | rstmgr_tl_errors | Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the [TLUL spec]({{< relref "hw/ip/tlul/doc/_index.md#explicit-error-cases" >}})
|
V2 | tl_d_outstanding_access | rstmgr_csr_hw_reset rstmgr_csr_rw rstmgr_csr_aliasing rstmgr_same_csr_outstanding | Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address. |
V2 | tl_d_partial_access | rstmgr_csr_hw_reset rstmgr_csr_rw rstmgr_csr_aliasing rstmgr_same_csr_outstanding | Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields. |
V2S | tl_intg_err | rstmgr_tl_intg_err rstmgr_sec_cm | Verify that the data integrity check violation generates an alert.
|
V2S | prim_count_check | rstmgr_sec_cm | Verify that violating prim_count counter properties generate a fatal alert. Stimulus:
Checks:
|
V2S | prim_fsm_check | rstmgr_sec_cm | Verify that entering to an undefined state generates a fatal alert. Stimulus:
Checks:
|
V2S | sec_cm_bus_integrity | rstmgr_tl_intg_err | Verify the countermeasure(s) BUS.INTEGRITY. This entry is covered by tl_access_test. |
V2S | sec_cm_scan_intersig_mubi | rstmgr_sec_cm_scan_intersig_mubi | Verify the countermeasure(s) SCAN.INTERSIG.MUBI. Stimulus: Same as smoke test but drive scanmode_i with a constant invalid value during the test. Check: If dut accepts any of invalid values, test will fail by turning dut to scanmode. |
V2S | sec_cm_leaf_rst_bkgn_chk | rstmgr_leaf_rst_cnsty | Verify the countermeasure(s) LEAF.RST.BKGN_CHK. ** Stimulus**: Execute a series of reset event - lowpower, hwreq, ndm, and sw reset -. And at the beginning of these events, create reset consistency error to one of 25 leaf modules. (exclude u_daon_por_io_div4 and u_daon_por_io_div4_shadowed, see #11858, #12729 for details) Do the same test for all 25 modules. Check: Upon asserting each reset consistency error, check alert_fatal_cnsty_fault is asserted. |
V2S | sec_cm_leaf_rst_shadow | rstmgr_leaf_rst_shadow_attack | Verify the countermeasure(s) LEAF.RST.SHADOW. After power up, create glitch to a shadow leaf reset module. Check if normal leaf reset module is not triggerred. Do over all {shadow, normal} leaf reset module pairs |
V2S | sec_cm_leaf_fsm_sparse | rstmgr_sec_cm | Verify the countermeasure(s) LEAF.FSM.SPARSE. Force leaf rst check state to illegal value. This is triggered by common cm primitives |
V2S | sec_cm_sw_rst_config_regwen | rstmgr_csr_rw | Verify the countermeasure(s) SW_RST.CONFIG.REGWEN. RSTMGR.SW_RST_CTRL_N. This is covered by auto csr test. |
V2S | sec_cm_dump_ctrl_config_regwen | rstmgr_csr_rw | Verify the countermeasure(s) DUMP_CTRL.CONFIG.REGWEN. RSTMGR.ALERT_INFO_CTRL and RSTMGR.CPU_INFO_CTRL This is covered by auto csr test. |
V3 | stress_all_with_rand_reset | rstmgr_stress_all_with_rand_reset | This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers. |
Covergroups
Name | Description |
---|---|
alert_info_access_cg | Collects coverage on the reads of alert_info. This captures |
alert_info_capture_cg | Collects coverage on reset type and enable when reset occurs. Uses |
cpu_info_access_cg | Collects coverage on the reads of cpu_info. This captures |
cpu_info_capture_cg | Collects coverage on the reset and enable when reset occurs. Uses |
regwen_val_when_new_value_written_cg | Cover each lockable reg field with these 2 cases:
This is only applicable if the block contains regwen and locakable CSRs. |
reset_stretcher_cg | Collects coverage on the reset_stretcher functionality. The stretcher counter is reset when por_n_i is not stable. Collect both the count at the point of instability, and the number of times the counter was reset. |
sw_rst_cg | Collects coverage on the software reset functionality. Each bit of the pair |
tl_errors_cg | Cover the following error cases on TL-UL bus:
|
tl_intg_err_cg | Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check. Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied. |