# RSTMGR DV document

## Goals

• DV
• Verify all RSTMGR IP features by running dynamic simulations with a SV/UVM based testbench
• Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
• FPV
• Verify TileLink device protocol compliance with an SVA based testbench

## Design features

For detailed information on RSTMGR design features, please see the RSTMGR HWIP technical specification.

## Testbench architecture

RSTMGR testbench has been constructed based on the CIP testbench architecture.

### Top level testbench

The top level testbench is located at hw/ip/rstmgr/dv/tb.sv. It instantiates the RSTMGR DUT module hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv. In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db:

### Common DV utility components

The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

### Global types & methods

All common types and methods defined at the package level can be found in rstmgr_env_pkg. Some of them in use are:

virtual rstmgr_if rstmgr_vif;
virtual pwrmgr_rstmgr_sva_if pwrmgr_rstmgr_sva_vif;


### TL_agent

The RSTMGR testbench instantiates (already handled in CIP base env) tl_agent. This provides the ability to drive and independently monitor random traffic via the TL host interface into the RSTMGR device.

RSTMGR testbench instantiates (already handled in CIP base env) alert_agents: [list alert names]. The alert_agents provide the ability to drive and independently monitor alert handshakes via alert interfaces in RSTMGR device.

### UVM RAL Model

The RSTMGR RAL model is created with the ralgen FuseSoC generator script automatically when the simulation is at the build stage.

It can be created manually by invoking regtool.

### Stimulus strategy

The following test sequences and covergroups are described in more detail in the testplan at hw/ip/pwrmgr/data/rstmgr_testplan.hjson, and also included below.

This IP is only reset via the por_n_i input, and by scan_rst_ni qualified by scanmode_i being active. The regular rst_ni input is connected to its own resets_o.rst_por_io_div4_n[0] output, so the reset output from clk_rst_if is not connected. Similarly, all reset outputs from other clk_rst_if instances are ignored, and only their clock output is used. This is consistent with this IP being in charge of all derived resets in the chip.

#### Test sequences

The test sequences reside in hw/ip/rstmgr/dv/env/seq_lib. All test sequences are extended from rstmgr_base_vseq, which is extended from cip_base_vseq and serves as a starting point. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. Some of the most commonly used tasks / functions are as follows:

• task wait_for_cpu_out_of_reset: Waits for the resets_o.rst_sys_n[1] output to go high, indicating the CPU is out of reset and CSRs can be accessed.
• task check_cpu_dump_info: Reads and compares each field in the cpu_info CSR against the given cpu dump.
• task check_software_reset_csr_and_pins: Reads and compares the sw_rst_ctrl_n CSR and the output reset ports against the given value.

Other sequences follow:

• rstmgr_smoke_vseq tests the rstmgr through software initiated low power, peripheral reset, ndm reset, and software initiated resets.
• rstmgr_reset_stretcher_vseq tests the resets_o.rst_por_aon_n[0] output is asserted after 32 stable cycles of ast_i.aon_pok.
• rstmgr_sw_rst_vseq tests the functionality provided by the sw_rst_regwen and sw_rst_ctrl_n.
• rstmgr_reset_info_vseq tests the reset_info CSR contents correspond to the different resets.
• rstmgr_cpu_info_vseq tests the cpu_info CSR contents capture to the cpu_dump_i present at the time of a reset.
• rstmgr_alert_info_vseq tests the alert_info CSR contents capture to the alert_dump_i present at the time of a reset.

#### Functional coverage

To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:

• reset_stretcher_cg
• alert_info_cg
• cpu_info_cg
• alert_info_capture_cg
• cpu_info_capture_cg

### Self-checking strategy

The partition between checks done in the scoreboard is not fixed.

#### Scoreboard

The rstmgr_scoreboard is primarily used for end to end checking. The following checks are performed:

• The software controlled peripheral resets are asserted based on both sw_rst_regwen and sw_rst_ctrl_n CSRs when not set by rst_lc_reg, rst_sys_req, or por.
• The cpu_info CSRs record the expected values based on the inputs on a system reset.
• The alert_info CSRs record the expected values based on the inputs on a system reset.
• The reset_info CSR records the expected reset cause.

#### Assertions

• TLUL assertions: The tb/rstmgr_bind.sv file binds the tlul_assert assertions to the IP to ensure TileLink interface protocol compliance.
• Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
• Response to pwrmgr’s rst_lc_req and rst_sys_req inputs: these trigger transitions in rst_lc_src_n and rst_sys_rst_n outputs. Checked via SVAs in hw/ip/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.sv.
• Response to cpu_i.ndmreset_req input: after it is asserted, rstmgr’s rst_sys_src_n should go active. Checked via SVA in hw/ip/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.sv.
• Resets cascade hierarchically per Reset Topology. Checked via SVA in hw/ip/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv.
• POR must be active for at least 32 consecutive cycles before going inactive before output resets go inactive. Checked via SVA in hw/ip/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv.
• The scan reset scan_rst_ni qualified by scanmode_i triggers all cascaded resets that por_n_i does. Checked via SVA in hw/ip/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv.
• The alert and cpu_info_attr indicate the number of 32-bit words needed to capture their inputs. Checked via SVA in hw/ip/rstmgr/dv/sva/rstmgr_attrs_sva_if.sv.

## Building and running tests

We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:

REPO_TOP/util/dvsim/dvsim.py \$REPO_TOP/hw/ip/rstmgr/dv/rstmgr_sim_cfg.hjson -i rstmgr_smoke


## Testplan

### Testpoints

Milestone Name Tests Description
V1 smoke rstmgr_smoke

Smoke test accessing a major datapath within the rstmgr.

Checks the behavior of rstmgr when receiving various reset requests.

Stimulus:

• Send a low power entry reset.
• Send a peripheral reset request.
• Send a debug reset.
• Configure a software request for peripheral reset.
• Set alert and cpu dump inputs to random values.

Checks:

• Checks the reset_info matches expected values.
• Checks the alert_info CSR correctly captures the input info.
• Checks the cpu_info CSR correctly captures the input info.
• Checks the output reset pins corresponding to sw resettable units match sw_rst_ctrl_n CSR.
V1 csr_hw_reset rstmgr_csr_hw_reset

Verify the reset values as indicated in the RAL specification.

• Write all CSRs with a random value.
• Apply reset to the DUT as well as the RAL model.
• Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_rw rstmgr_csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

• Loop through each CSR to write it with a random value.
• Read the CSR back and check for correctness while adhering to its access policies.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_bit_bash rstmgr_csr_bit_bash

Verify no aliasing within individual bits of a CSR.

• Walk a 1 through each CSR by flipping 1 bit at a time.
• Read the CSR back and check for correctness while adhering to its access policies.
• This verify that writing a specific bit within the CSR did not affect any of the other bits.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_aliasing rstmgr_csr_aliasing

Verify no aliasing within the CSR address space.

• Loop through each CSR to write it with a random value
• Shuffle and read ALL CSRs back.
• All CSRs except for the one that was written in this iteration should read back the previous value.
• The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_mem_rw_with_rand_resetrstmgr_csr_mem_rw_with_rand_reset

Verify random reset during CSR/memory access.

• Run csr_rw sequence to randomly access CSRs
• If memory exists, run mem_partial_access in parallel with csr_rw
• Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
V2 reset_stretcher rstmgr_por_stretcher

Test the POR reset signal must be stable for multiple cycles.

The POR reset signal must remain active for at least 32 consecutive cycles before going inactive for the rest of the reset tree to go inactive.

Stimulus:

• Activate POR, and de-activate it at a random width less than 32 cycles between de-activations for N de-activations.

Checks:

• With SVA check the output reset is only set if the input reset has had at least 32 cycles of steady input reset active.
V2 sw_rst

Test the sw_rst functionality.

The sw_rst_regwen and sw_rst_ctrl_n CSRs control the specific reset outputs to peripherals in the following sequence:

• Test all sw_rst_ctrl_n bits when sw_rst_regwen is all 1's.
• Clear each sw_rst_regwen bit to verify the corresponding resets are masked.

Stimulus:

• Write sw_rst_ctrl_n CSR with random values when regwen is all 1's.
• Clear each sw_rst_regwen bit and write sw_rst_ctrl_n CSR with all 0's.
• After each regwen bit check set sw_rst_ctrl_n to all 1's.

Checks:

• Check that the zero bits in sw_rst_ctrl_n enabled by sw_rst_regwen cause the respective resets to become active.
• Check that the zero bits in sw_rst_ctrl_n disabled by sw_rst_regwen have no effect on resets.
• Check the reset_info, cpu_info, and alert_info CSRs are not modified.
V2 reset_info

Test the reporting of reset reason.

Stimulus:

• Generate the different resets recorded in reset_info CSR.
• Randomly clear reset_info (it is rw1c).

Checks:

• The resulting setting of reset_info is as expected.
• Each bit was set at least once.
• Each bit was cleared at least once.
V2 cpu_info

Test the cpu_info recording.

The cpu_info CSR register(s) can capture the contents of the cpu_dump_i input when resets happen and it is enabled.

Stimulus:

• Regularly modify the cpu_dump_i input.
• With cpu_regwen on, randomly set cpu_info_ctrl.en to control whether the dump should be captured.
• Generate reset(s) as in smoke testpoint.

Checks:

• Check that cpu_regwen doesn't transition to 1 after reset.

• Verify the cpu_info is only captured when enabled.

• Verify the cpu_info contents at each cpu_info_ctrl.index matches the expected value.

• Checking that cpu_regwen controls when cpu_info_ctrl can be modified should be done in common csr tests.

Test the alert_info recording.

The alert_info CSR register(s) can capture the contents of the alert_dump_i input when resets happen and it is enabled.

Stimulus:

• Regularly modify the alert_dump_i input.
• With alert_regwen on, randomly set alert_info_ctrl.en to control whether the dump should be captured.
• Generate reset(s) as in smoke testpoint.

Checks:

• Check that alert_regwen doesn't transition to 1 after reset.

• Verify the alert_info is only captured when enabled.

• Verify the alert_info contents at each alert_info_ctrl.index matches the expected value.

• Checking that alert_regwen controls when alert_info_ctrl can be modified should be done in common csr tests.

Verify common alert_test CSR that allows SW to mock-inject alert requests.

• Enable a random set of alert requests by writing random value to alert_test CSR.
• Check each alert_tx.alert_p pin to verify that only the requested alerts are triggered.
• During alert_handshakes, write alert_test CSR again to verify that: If alert_test writes to current ongoing alert handshake, the alert_test request will be ignored. If alert_test writes to current idle alert handshake, a new alert_handshake should be triggered.
• Wait for the alert handshakes to finish and verify alert_tx.alert_p pins all sets back to 0.
• Repeat the above steps a bunch of times.

Access out of bounds address and verify correctness of response / behavior

V2 tl_d_illegal_access rstmgr_tl_errors

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the [TLUL spec]({{&lt; relref &quot;hw/ip/tlul/doc/_index.md#explicit-error-cases&quot; &gt;}})

• TL-UL protocol error cases
• invalid opcode
• some mask bits not set when opcode is PutFullData
• mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = &#x27;b0010
• mask and address misaligned, e.g. a_address = 0x01, a_mask = &#x27;b0001
• address and size aren't aligned, e.g. a_address = 0x01, a_size != 0
• size is greater than 2
• OpenTitan defined error cases
• access unmapped address, expect d_error = 1 when devmode_i == 1
• write a CSR with unaligned address, e.g. a_address[1:0] != 0
• write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
• write a memory with a_mask != &#x27;1 when it doesn't support partial accesses
• read a WO (write-only) memory
• write a RO (read-only) memory
V2 tl_d_outstanding_access rstmgr_csr_hw_reset
rstmgr_csr_rw
rstmgr_csr_aliasing
rstmgr_same_csr_outstanding

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

V2 tl_d_partial_access rstmgr_csr_hw_reset
rstmgr_csr_rw
rstmgr_csr_aliasing
rstmgr_same_csr_outstanding

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

V3 stress

The standard stress test.

V3 tl_intg_err rstmgr_tl_intg_err

Verify that the data integrity check violation generates an alert.

Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.

V3 stress_all_with_rand_resetrstmgr_stress_all_with_rand_reset

This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.

### Covergroups

Name Description

Collects coverage on the reset and enable when reset occurs.

Uses reset_cp that records the reset when it occurs, encoded as in reset_info CSR, and ctrl_en_cp as described in alert_info_cg, and creates their cross.

Collects coverage on the controls of alert_info.

The alert_info capture uses coverpoints regwen_cp capturing alert_regwen CSR, ctrl_en_cp capturing alert_info_ctrl.en CSR, and ctrl_index capturing alert_info_ctrl.index CSR.

cpu_info_capture_cg

Collects coverage on the reset and enable when reset occurs.

Uses reset_cp that records the reset when it occurs, encoded as in reset_info CSR, and ctrl_en_cp as described in cpu_info_cg, and creates their cross.

cpu_info_cg

Collects coverage on the controls of cpu_info.

The cpu_info capture uses coverpoints regwen_cp capturing cpu_regwen CSR, ctrl_en_cp capturing cpu_info_ctrl.en CSR, and ctrl_index capturing cpu_info_ctrl.index CSR.

reset_stretcher_cg

Collects coverage on the reset_stretcher functionality.

The stretcher counter is reset when por_n_i is not stable. Collect both the count at the point of instability, and the number of times the counter was reset.

sw_rst_cg

Collects coverage on the software reset functionality.

Each bit of the pair sw_rst_regwen and sw_rst_ctrl_n CSRs independently control if the corresponding output reset is asserted (active low). This collects one coverpoint for each, and their cross.

tl_errors_cg

Cover the following error cases on TL-UL bus:

• TL-UL protocol error cases.
• OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.
tl_intg_err_cg

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

tl_intg_err_mem_subword_cg

Cover the kinds of integrity errors with byte enabled write on memory.

Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.