Ibex RISC-V Core Wrapper Technical Specification

Overview

This document specifies Ibex CPU core wrapper functionality.

Features

  • Instantiation of a Ibex RV32 CPU Core.
  • TileLink Uncached Light (TL-UL) host interfaces for the instruction and data ports.
  • Simple address translation.
  • NMI support for security alert events for watchdog bark.
  • General error status collection and alert generation.
  • Crash dump collection for software debug.

Description

The Ibex RISC-V Core Wrapper instantiates an Ibex RV32 CPU Core, and wraps its data and instruction memory interfaces to TileLink Uncached Light (TL-UL). All configuration parameters of Ibex are passed through. The pipelining of the bus adapters is configurable.

Compatibility

Ibex is a compliant RV32 RISC-V CPU core, as documented in the Ibex documentation.

The TL-UL bus interfaces exposed by this wrapper block are compliant to the TileLink Uncached Lite Specification version 1.7.1.

Theory of Operations

Simple Address Translation

The wrapper supports a simple address translation scheme. The goal of the scheme is to provide hardware support for A/B software copies.

Each copy of the software is stored at a different location. Depending upon which execution slot is active, a different copy is used. This creates an issue because each copy of software has different addresses and thus must be linked differently. Ideally, software should be able to assume one address all the time, and the hardware should remap to the appropriate physical location.

The translation scheme is based on NAPOT (natural alignment to power of two). Software picks a matching region and also a remap address. When an incoming transaction matches the selected power-of-2 region, it is redirected to the new address. If a transaction does not match, then it is directly passed through.

This allows software to place the executable code at a virtual address in the system and re-map that to the appropriate physical block.

There are separate translations controls for instruction and data. Each control contains two programmable regions (2 for instruction and 2 for data). If a transaction matches multiple regions, the lowest indexed region has priority.

For details on how to program the related registers, please see IBUS_ADDR_MATCHING_0 and IBUS_REMAP_ADDR_0.

Translation and Instruction Caching

The simple address translation scheme used in this design is not aware of the processor context, specifically, any instruction caching done in the core. This means if the address translation scheme were to change, instructions that are already cached may not reflect the updated address setting.

In order to correctly utilize simple address translation along with instruction caching, it is recommended that after the address is updated a FENCE.I instruction is issued. The FENCE.I instruction forces the instruction cache to flush, and this aligns the core to the new address setting.

Random Number Generation

The wrapper has a connection to the Entropy Distribution Network (EDN) with a register based interface. The RND_DATA register provides 32-bits directly from the EDN. RND_STATUS.RND_DATA_VALID indicates if the data in RND_DATA is valid or not. A polling style interface is used to get new random data. Any read to RND_DATA when it is valid invalidates the data and triggers an EDN request for new data. Software should poll RND_STATUS.RND_DATA_VALID until it is valid and then read from RND_DATA to get the new random data. Either the data is valid or a request for new data is pending. It is not possible to have a state where there is no valid data without new data being requested.

Upon reset RND_DATA is invalid. A request is made to the EDN immediately out of reset, this will not be answered until the EDN is enabled. Software should take care not to enable the EDN until the entropy complex configuration is as desired. When the entropy complex configuration is changed reading RND_DATA when it is valid will suffice to flush any old random data to trigger a new request under the new configuration. If a EDN request is pending when the entropy complex configuration is changed ( RND_STATUS.RND_DATA_VALID is clear), it is advisable to wait until it is complete and then flush out the data to ensure the fresh value was produced under the new configuration.

Crash Dump Collection

In general, when the CPU encounters an error, it is software’s responsibility to collect error status and supply it for debug.

However, there are situations where it may not be possible for software to collect any error logging. These situations include but are not limited to:

  • A hung transaction that causes watchdog to expire.
  • A double fault that causes the processor to stop execution.
  • An alert escalation that directly resets the system without any software intervention.

Under these situations, the software has no hints as to where the error occurred. To mitigate this issue, Ibex provides crash dump information that can be directly captured in the rstmgr for last resort debug after the reset event.

The Ibex crash dump state contains 5 words of debug data:

  • word 0: The last exception address (mtval)
  • word 1: The last exception PC (mepc)
  • word 2: The last data access address
  • word 3: The next PC
  • word 4: The current PC

The crash dump information transmitted to the rstmgr contains 7 words of debug data and a 1-bit valid indication:

  • words 0-4: The current crash dump state
  • word 5: The previous exception address (mtval)
  • word 6: The previous exception PC (mepc)
  • MSB: Previous state valid indication.

Under normal circumstances, only the current crash dump state is valid. When the CPU encounters a double fault, the current crash dump is moved to previous, and the new crash dump is shown in current.

This allows the software to see both fault locations and debug accordingly.

In terms of how the crash state information can be used, the following are a few examples.

Hung Transaction

Assuming the system has a watchdog counter setup, when a CPU transaction hangs the bus (accessing a device whose clock is not turned on or is under reset), the PC and bus access freeze in place until the watchdog resets the system. Upon reset release, software can check the last PC and data access address to get an idea of what transaction might have caused the bus to hang.

Double Exception

If the software has some kind of error and encounters two exceptions in a row, the previous exception PC and address show the location of the first exception, while the current exception address and PC show the location of the most recent exception.

Fetch Enable

Ibex has a top-level fetch enable input (fetch_enable_i), which uses the same multi-bit encoding used by the lifecycle controller. When Ibex fetch is disabled it will cease to execute, but will complete instructions currently in the pipeline. Ibex fetch is enabled when all of the following conditions are met:

  • The lifecycle controller has enabled it
  • The power manager has enabled it
  • A fatal_hw_err alert hasn’t been raised

Local Escalation Path

When the fatal_hw_err alert is raised Ibex fetch is disabled and will remain disabled until rv_core_ibex is reset.

Hardware Interfaces

Signals

Referring to the Comportable guideline for peripheral device functionality, the module RV_CORE_IBEX has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: clk_edn_i, clk_esc_i, clk_otp_i

Bus Device Interfaces (TL-UL): cfg_tl_d

Bus Host Interfaces (TL-UL): corei_tl_h, cored_tl_h

Peripheral Pins for Chip IO: none

Inter-Module Signals: Reference

Inter-Module Signals
Port Name Package::Struct Type Act Width Description
rst_cpu_n logic uni req 1
ram_cfg prim_ram_1p_pkg::ram_1p_cfg uni rcv 1
hart_id logic uni rcv 32
boot_addr logic uni rcv 32
irq_software logic uni rcv 1
irq_timer logic uni rcv 1
irq_external logic uni rcv 1
esc_tx prim_esc_pkg::esc_tx uni rcv 1
esc_rx prim_esc_pkg::esc_rx uni req 1
debug_req logic uni rcv 1
crash_dump rv_core_ibex_pkg::cpu_crash_dump uni req 1
lc_cpu_en lc_ctrl_pkg::lc_tx uni rcv 1
pwrmgr_cpu_en lc_ctrl_pkg::lc_tx uni rcv 1
pwrmgr pwrmgr_pkg::pwr_cpu uni req 1
nmi_wdog logic uni rcv 1
edn edn_pkg::edn req_rsp req 1
icache_otp_key otp_ctrl_pkg::sram_otp_key req_rsp req 1
fpga_info logic uni rcv 32
corei_tl_h tlul_pkg::tl req_rsp req 1
cored_tl_h tlul_pkg::tl req_rsp req 1
cfg_tl_d tlul_pkg::tl req_rsp rsp 1

Interrupts: none

Security Alerts:

Alert NameDescription
fatal_sw_err

Software triggered alert for fatal faults

recov_sw_err

Software triggered Alert for recoverable faults

fatal_hw_err

Triggered when - Ibex raises alert_major_internal_o - Ibex raises alert_major_bus_o - A double fault is seen (Ibex raises double_fault_seen_o) - A bus integrity error is seen

recov_hw_err

Triggered when Ibex raises alert_minor_o

Security Countermeasures:

Countermeasure IDDescription
RV_CORE_IBEX.BUS.INTEGRITY

End-to-end bus integrity scheme.

RV_CORE_IBEX.SCRAMBLE.KEY.SIDELOAD

The scrambling key for the icache is sideloaded from OTP and thus unreadable by SW.

RV_CORE_IBEX.CORE.DATA_REG_SW.SCA

Data independent timing.

RV_CORE_IBEX.PC.CTRL_FLOW.CONSISTENCY

Correct PC increment check.

RV_CORE_IBEX.CTRL_FLOW.UNPREDICTABLE

Randomized dummy instruction insertion.

RV_CORE_IBEX.DATA_REG_SW.INTEGRITY

Register file integrity checking. Note that whilst the core itself is duplicated (see LOGIC.SHADOW) the register file is not. Protection is provided by an ECC.

RV_CORE_IBEX.DATA_REG_SW.GLITCH_DETECT

This countermeasure augments DATA_REG_SW.INTEGRITY and checks for spurious write-enable signals on the register file by monitoring the one-hot0 property of the individual write-enable strobes.

RV_CORE_IBEX.LOGIC.SHADOW

Shadow core run in lockstep to crosscheck CPU behaviour. This provides broad protection for all assets with the the Ibex core.

RV_CORE_IBEX.FETCH.CTRL.LC_GATED

Fetch enable so core execution can be halted.

RV_CORE_IBEX.EXCEPTION.CTRL_FLOW.LOCAL_ESC

A mechanism to detect and act on double faults. Local escalation shuts down the core when a double fault is seen.

RV_CORE_IBEX.EXCEPTION.CTRL_FLOW.GLOBAL_ESC

A mechanism to detect and act on double faults. Global escalation sends a fatal alert when a double fault is seen.

RV_CORE_IBEX.ICACHE.MEM.SCRAMBLE

ICache memory scrambling.

RV_CORE_IBEX.ICACHE.MEM.INTEGRITY

ICache memory integrity checking.

All ports and parameters of Ibex are exposed through this wrapper module, except for the instruction and data memory interfaces (signals starting with instr_ and data_). Refer to the Ibex documentation for a detailed description of these signals and parameters.

The instruction and data memory ports are exposed as TL-UL ports. The table below lists other signals and the TL-UL ports.

Signal Direction Type Description
rst_cpu_n_o output logic Outgoing indication to reset manager that the process has reset.
ram_cfg_i input prim_ram_1p_pkg::ram_1p_cfg_t Incoming memory configuration that is technology dependent.
hart_id_i input logic [31:0] Static Hard ID input signal.
boot_addr_i input logic [31:0] Static boot address input signal.
fpga_info_i input logic [31:0] Fpga info input signal, coming from a Xilinx USR_ACCESSE2 primitive for example.
irq_software_i input logic Software interrupt input.
irq_timer_i input logic Timer interrupt input.
irq_external_i input logic External interrupt input.
debug_req_i input logic Debug request from the debug module.
corei_tl_h_o output tlul_pkg::tl_h2d_t Outgoing instruction tlul request.
corei_tl_h_i input tlul_pkg::tl_d2h_t Incoming instruction tlul response.
cored_tl_h_o output tlul_pkg::tl_h2d_t Outgoing data tlul request.
cored_tl_h_i input tlul_pkg::tl_d2h_t Incoming data tlul response.
cfg_tl_d_i output tlul_pkg::tl_h2d_t Outgoing data tlul request for peripheral registers.
cfg_tl_d_o input tlul_pkg::tl_d2h_t Incoming data tlul response for peripheral registers.
alert_rx_i input prim_alert_pkg::alert_rx_t Incoming alert response / ping.
alert_tx_o output prim_alert_pkg::alert_tx_t Outgoing alert request.
esc_tx_i input prim_esc_pkg::esc_tx_t Incoming escalation request / ping.
esc_rx_o output prim_esc_pkg::esc_rx_t Outgoing escalation response.
nmi_wdog_i input logic Incoming watchdog NMI bark.
crash_dump_o output ibex_pkg::crash_dump_t Outgoing crash dump information to rstmgr.
cfg_tl_d_i input tlul_pkg::tl_h2d_t Incoming configuration bus request.
cfg_tl_d_o output tlul_pkg::tl_d2h_t Outgoing configuration bus response.
lc_cpu_en_i input lc_ctrl_pkg::lc_tx_t CPU enable signal from life cycle controller.
pwrmgr_cpu_en_i input lc_ctrl_pkg::lc_tx_t CPU enable signal from power manager.
pwrmgr_o output pwrmgr_pkg::pwr_cpu_t Low-power CPU status to power manager.
edn_i input edn_pkg::edn_rsp_t Incoming entropy response from entropy distribution network.
edn_o output edn_pkg::edn_req_t Outgoing entropy request to entropy distribution network.
icache_otp_key_i input otp_ctrl_pkg::sram_otp_key_rsp_t Incoming scrambling key response from OTP to icache.
icache_otp_key_o output otp_ctrl_pkg::sram_otp_key_req_t Outgoing scrambling key request from icache to OTP.

The PipeLine parameter can be used to configure the bus adapter pipelining.

  • Setting PipeLine to 0 disables pipelining, which gives minimal latency between the bus and the core, at the cost of a combinatorial path into the core.
  • Setting PipeLine to 1 introduces a pipelining FIFO between the core instruction/data interfaces and the bus. This setting increases the memory access latency, but improves timing.

Device Interface Functions (DIFs)

To use this DIF, include the following C header:

#include "sw/device/lib/dif/dif_rv_core_ibex.h"

This header provides the following device interface functions:

Register Table

A number of memory-mapped registers are available to control Ibex-related functionality that’s specific to OpenTitan.

Summary
Name Offset Length Description
RV_CORE_IBEX.ALERT_TEST 0x0 4

Alert Test Register

RV_CORE_IBEX.SW_RECOV_ERR 0x4 4

Software recoverable error

RV_CORE_IBEX.SW_FATAL_ERR 0x8 4

Software fatal error

RV_CORE_IBEX.IBUS_REGWEN_0 0xc 4

Ibus address control regwen.

RV_CORE_IBEX.IBUS_REGWEN_1 0x10 4

Ibus address control regwen.

RV_CORE_IBEX.IBUS_ADDR_EN_0 0x14 4

Enable Ibus address matching

RV_CORE_IBEX.IBUS_ADDR_EN_1 0x18 4

Enable Ibus address matching

RV_CORE_IBEX.IBUS_ADDR_MATCHING_0 0x1c 4

Matching region programming for ibus.

RV_CORE_IBEX.IBUS_ADDR_MATCHING_1 0x20 4

Matching region programming for ibus.

RV_CORE_IBEX.IBUS_REMAP_ADDR_0 0x24 4

The remap address after a match has been made. The remap bits apply only to top portion of address bits not covered by the matching region.

RV_CORE_IBEX.IBUS_REMAP_ADDR_1 0x28 4

The remap address after a match has been made. The remap bits apply only to top portion of address bits not covered by the matching region.

RV_CORE_IBEX.DBUS_REGWEN_0 0x2c 4

Dbus address control regwen.

RV_CORE_IBEX.DBUS_REGWEN_1 0x30 4

Dbus address control regwen.

RV_CORE_IBEX.DBUS_ADDR_EN_0 0x34 4

Enable dbus address matching

RV_CORE_IBEX.DBUS_ADDR_EN_1 0x38 4

Enable dbus address matching

RV_CORE_IBEX.DBUS_ADDR_MATCHING_0 0x3c 4

See IBUS_ADDR_MATCHING_0 for detailed description.

RV_CORE_IBEX.DBUS_ADDR_MATCHING_1 0x40 4

See IBUS_ADDR_MATCHING_0 for detailed description.

RV_CORE_IBEX.DBUS_REMAP_ADDR_0 0x44 4

See IBUS_REMAP_ADDR_0 for a detailed description.

RV_CORE_IBEX.DBUS_REMAP_ADDR_1 0x48 4

See IBUS_REMAP_ADDR_0 for a detailed description.

RV_CORE_IBEX.NMI_ENABLE 0x4c 4

Enable mask for NMI. Once an enable mask is set, it cannot be disabled.

RV_CORE_IBEX.NMI_STATE 0x50 4

Current NMI state

RV_CORE_IBEX.ERR_STATUS 0x54 4

error status

RV_CORE_IBEX.RND_DATA 0x58 4

Random data from EDN

RV_CORE_IBEX.RND_STATUS 0x5c 4

Status of random data in RND_DATA

RV_CORE_IBEX.FPGA_INFO 0x60 4

FPGA build timestamp info. This register only contains valid data for fpga, for all other variants it is simply 0.

RV_CORE_IBEX.DV_SIM_WINDOW 0x80 32

Exposed tlul window for DV only purposes.

RV_CORE_IBEX.ALERT_TEST @ 0x0

Alert Test Register

Reset default = 0x0, mask 0xf
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  recov_hw_err fatal_hw_err recov_sw_err fatal_sw_err
BitsTypeResetNameDescription
0wo0x0fatal_sw_err

Write 1 to trigger one alert event of this kind.

1wo0x0recov_sw_err

Write 1 to trigger one alert event of this kind.

2wo0x0fatal_hw_err

Write 1 to trigger one alert event of this kind.

3wo0x0recov_hw_err

Write 1 to trigger one alert event of this kind.


RV_CORE_IBEX.SW_RECOV_ERR @ 0x4

Software recoverable error

Reset default = 0x9, mask 0xf
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  VAL
BitsTypeResetNameDescription
3:0rw0x9VAL

Software recoverable alert. When set to any value other than kMultiBitBool4False, a recoverable alert is sent. Once the alert is sent, the field is then reset to kMultiBitBool4False.


RV_CORE_IBEX.SW_FATAL_ERR @ 0x8

Software fatal error

Reset default = 0x9, mask 0xf
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  VAL
BitsTypeResetNameDescription
3:0rw0c0x9VAL

Software fatal alert. When set to any value other than kMultiBitBool4False, a fatal alert is sent. Note, this field once cleared cannot be set and will continuously cause alert events.


RV_CORE_IBEX.IBUS_REGWEN_0 @ 0xc

Ibus address control regwen.

Reset default = 0x1, mask 0x1
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  EN_0
BitsTypeResetNameDescription
0rw0c0x1EN_0

Ibus address controls write enable. Once set to 0, it can longer be configured to 1

0x0locked

Address controls can no longer be configured until next reset.

0x1enabled

Address controls can still be configured.


RV_CORE_IBEX.IBUS_REGWEN_1 @ 0x10

Ibus address control regwen.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  EN_1
BitsTypeResetNameDescription
0rw0c0x1EN_1

For IBUS_REGWEN1


RV_CORE_IBEX.IBUS_ADDR_EN_0 @ 0x14

Enable Ibus address matching

Reset default = 0x0, mask 0x1
Register enable = IBUS_REGWEN_0
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  EN_0
BitsTypeResetNameDescription
0rw0x0EN_0

Enable ibus address matching.


RV_CORE_IBEX.IBUS_ADDR_EN_1 @ 0x18

Enable Ibus address matching

Reset default = 0x0, mask 0x1
Register enable = IBUS_REGWEN_1
31302928272625242322212019181716
 
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  EN_1
BitsTypeResetNameDescription
0rw0x0EN_1

For IBUS_ADDR_CFG1


RV_CORE_IBEX.IBUS_ADDR_MATCHING_0 @ 0x1c

Matching region programming for ibus.

Reset default = 0x0, mask 0xffffffff
Register enable = IBUS_REGWEN_0

The value programmed is done at power-of-2 alignment. For example, if the intended matching region is 0x8000_0000 to 0x8000_FFFF, the value programmed is 0x8000_7FFF.

The value programmed can be determined from the translation granule. Assume the user wishes to translate a specific 64KB block to a different address: 64KB has a hex value of 0x10000. Subtract 1 from this value and then right shift by one to obtain 0x7FFF. This value is then logically OR'd with the upper address bits that would select which 64KB to translate.

In this example, the user wishes to translate the 0x8000-th 64KB block. The value programmed is then 0x8000_7FFF.

If the user were to translate the 0x8001-th 64KB block, the value programmed would be 0x8001_7FFF.

31302928272625242322212019181716
VAL_0...
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...VAL_0
BitsTypeResetNameDescription
31:0rw0x0VAL_0

Matching region value


RV_CORE_IBEX.IBUS_ADDR_MATCHING_1 @ 0x20

Matching region programming for ibus.

Reset default = 0x0, mask 0xffffffff
Register enable = IBUS_REGWEN_1

The value programmed is done at power-of-2 alignment. For example, if the intended matching region is 0x8000_0000 to 0x8000_FFFF, the value programmed is 0x8000_7FFF.

The value programmed can be determined from the translation granule. Assume the user wishes to translate a specific 64KB block to a different address: 64KB has a hex value of 0x10000. Subtract 1 from this value and then right shift by one to obtain 0x7FFF. This value is then logically OR'd with the upper address bits that would select which 64KB to translate.

In this example, the user wishes to translate the 0x8000-th 64KB block. The value programmed is then 0x8000_7FFF.

If the user were to translate the 0x8001-th 64KB block, the value programmed would be 0x8001_7FFF.

31302928272625242322212019181716
VAL_1...
1514131211109876543210
...VAL_1
BitsTypeResetNameDescription
31:0rw0x0VAL_1

For IBUS_ADDR_MATCHING1


RV_CORE_IBEX.IBUS_REMAP_ADDR_0 @ 0x24

The remap address after a match has been made. The remap bits apply only to top portion of address bits not covered by the matching region.

Reset default = 0x0, mask 0xffffffff
Register enable = IBUS_REGWEN_0

For example, if the translation region is 64KB, the remapped address applies only to the upper address bits that select which 64KB to be translated.

31302928272625242322212019181716
VAL_0...
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...VAL_0
BitsTypeResetNameDescription
31:0rw0x0VAL_0

Remap addr value


RV_CORE_IBEX.IBUS_REMAP_ADDR_1 @ 0x28

The remap address after a match has been made. The remap bits apply only to top portion of address bits not covered by the matching region.

Reset default = 0x0, mask 0xffffffff
Register enable = IBUS_REGWEN_1

For example, if the translation region is 64KB, the remapped address applies only to the upper address bits that select which 64KB to be translated.

31302928272625242322212019181716
VAL_1...
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...VAL_1
BitsTypeResetNameDescription
31:0rw0x0VAL_1

For IBUS_REMAP_ADDR1


RV_CORE_IBEX.DBUS_REGWEN_0 @ 0x2c

Dbus address control regwen.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  EN_0
BitsTypeResetNameDescription
0rw0c0x1EN_0

Ibus address controls write enable. Once set to 0, it can longer be configured to 1

0x0locked

Address controls can no longer be configured until next reset.

0x1enabled

Address controls can still be configured.


RV_CORE_IBEX.DBUS_REGWEN_1 @ 0x30

Dbus address control regwen.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  EN_1
BitsTypeResetNameDescription
0rw0c0x1EN_1

For DBUS_REGWEN1


RV_CORE_IBEX.DBUS_ADDR_EN_0 @ 0x34

Enable dbus address matching

Reset default = 0x0, mask 0x1
Register enable = DBUS_REGWEN_0
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  EN_0
BitsTypeResetNameDescription
0rw0x0EN_0

Enable dbus address matching.


RV_CORE_IBEX.DBUS_ADDR_EN_1 @ 0x38

Enable dbus address matching

Reset default = 0x0, mask 0x1
Register enable = DBUS_REGWEN_1
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  EN_1
BitsTypeResetNameDescription
0rw0x0EN_1

For DBUS_ADDR_CFG1


RV_CORE_IBEX.DBUS_ADDR_MATCHING_0 @ 0x3c

See IBUS_ADDR_MATCHING_0 for detailed description.

Reset default = 0x0, mask 0xffffffff
Register enable = DBUS_REGWEN_0
31302928272625242322212019181716
VAL_0...
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...VAL_0
BitsTypeResetNameDescription
31:0rw0x0VAL_0

Matching region value


RV_CORE_IBEX.DBUS_ADDR_MATCHING_1 @ 0x40

See IBUS_ADDR_MATCHING_0 for detailed description.

Reset default = 0x0, mask 0xffffffff
Register enable = DBUS_REGWEN_1
31302928272625242322212019181716
VAL_1...
1514131211109876543210
...VAL_1
BitsTypeResetNameDescription
31:0rw0x0VAL_1

For DBUS_ADDR_MATCHING1


RV_CORE_IBEX.DBUS_REMAP_ADDR_0 @ 0x44

See IBUS_REMAP_ADDR_0 for a detailed description.

Reset default = 0x0, mask 0xffffffff
Register enable = DBUS_REGWEN_0
31302928272625242322212019181716
VAL_0...
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...VAL_0
BitsTypeResetNameDescription
31:0rw0x0VAL_0

Remap addr value


RV_CORE_IBEX.DBUS_REMAP_ADDR_1 @ 0x48

See IBUS_REMAP_ADDR_0 for a detailed description.

Reset default = 0x0, mask 0xffffffff
Register enable = DBUS_REGWEN_1
31302928272625242322212019181716
VAL_1...
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...VAL_1
BitsTypeResetNameDescription
31:0rw0x0VAL_1

For DBUS_REMAP_ADDR1


RV_CORE_IBEX.NMI_ENABLE @ 0x4c

Enable mask for NMI. Once an enable mask is set, it cannot be disabled.

Reset default = 0x0, mask 0x3
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  WDOG_EN ALERT_EN
BitsTypeResetNameDescription
0rw1s0x0ALERT_EN

Enable mask for alert NMI

1rw1s0x0WDOG_EN

Enable mask for watchdog NMI


RV_CORE_IBEX.NMI_STATE @ 0x50

Current NMI state

Reset default = 0x0, mask 0x3
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  WDOG ALERT
BitsTypeResetNameDescription
0rw1c0x0ALERT

Current state for alert NMI

1rw1c0x0WDOG

Current state for watchdog NMI


RV_CORE_IBEX.ERR_STATUS @ 0x54

error status

Reset default = 0x0, mask 0x701
31302928272625242322212019181716
 
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  RECOV_CORE_ERR FATAL_CORE_ERR FATAL_INTG_ERR   REG_INTG_ERR
BitsTypeResetNameDescription
0rw1c0x0REG_INTG_ERR

rv_core_ibex_peri detected a register transmission integrity error

7:1Reserved
8rw1c0x0FATAL_INTG_ERR

rv_core_ibex detected a response integrity error

9rw1c0x0FATAL_CORE_ERR

rv_core_ibex detected a fatal internal error (alert_major_internal_o from Ibex seen)

10rw1c0x0RECOV_CORE_ERR

rv_core_ibex detected a recoverable internal error (alert_minor from Ibex seen)


RV_CORE_IBEX.RND_DATA @ 0x58

Random data from EDN

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
DATA...
1514131211109876543210
...DATA
BitsTypeResetNameDescription
31:0ro0x0DATA

Random bits taken from the EDN. RND_STATUS.RND_DATA_VALID indicates if this data is valid. When valid, reading from this register invalidates the data and requests new data from the EDN. The register becomes valid again when the EDN provides new data. When invalid the register value will read as 0x0 with an EDN request for new data pending. Upon reset the data will be invalid with a new EDN request pending.


RV_CORE_IBEX.RND_STATUS @ 0x5c

Status of random data in RND_DATA

Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  RND_DATA_FIPS RND_DATA_VALID
BitsTypeResetNameDescription
0ro0x0RND_DATA_VALID

When set, the data in RND_DATA is valid. When clear an EDN request for new data for RND_DATA is pending.

1ro0x0RND_DATA_FIPS

When RND_STATUS.RND_DATA_VALID is 1, this bit indicates whether RND_DATA is fips quality.

When RND_STATUS.RND_DATA_VALID is 0, this bit has no meaning.


RV_CORE_IBEX.FPGA_INFO @ 0x60

FPGA build timestamp info. This register only contains valid data for fpga, for all other variants it is simply 0.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
VAL...
1514131211109876543210
...VAL
BitsTypeResetNameDescription
31:0ro0x0VAL

FPGA build timestamp information.


RV_CORE_IBEX.DV_SIM_WINDOW @ + 0x80
8 item rw window
Byte writes are supported
310
+0x80 
+0x84 
 ...
+0x98 
+0x9c 

Exposed tlul window for DV only purposes.