Ibex Processor Core Checklist

This checklist is for Hardware Stage transitions for the Ibex Processor Core. All checklist items refer to the content in the Checklist.

Design Checklist

D1

Type Item Resolution Note/Collaterals
Documentation SPEC_COMPLETE Done
Documentation CSR_DEFINED Done lowRISC/ibex#307
RTL CLKRST_CONNECTED Done
RTL IP_TOP Done
RTL IP_INSTANTIABLE Done
RTL MEM_INSTANCED_80 N/A
RTL FUNC_IMPLEMENTED Done
RTL ASSERT_KNOWN_ADDED Done
Code Quality LINT_SETUP Done

D1 Exceptions

MEM_INSTANCED_80 is waived as Ibex doesn't have memories inside.

D2

Type Item Resolution Note/Collaterals
Documentation NEW_FEATURES N/A
Documentation BLOCK_DIAGRAM Done
Documentation DOC_INTERFACE Done
Documentation MISSING_FUNC N/A
Documentation FEATURE_FROZEN Done
RTL FEATURE_COMPLETE Done
RTL AREA_SANITY_CHECK Done Area Sanity Check Done (on FPGA)
RTL PORT_FROZEN Done
RTL ARCHITECTURE_FROZEN Done
RTL REVIEW_TODO Done Minor TODOs remain, waived
RTL STYLE_X Done will be reworked (#366)
Code Quality LINT_PASS Done Lint waivers created, not finalized
Code Quality CDC_SETUP N/A No CDC path
Code Quality FPGA_TIMING Done FPGA timing acceptable
Code Quality CDC_SYNCMACRO N/A
Security SEC_CM_IMPLEMENTED Not Started
Security SEC_NON_RESET_FLOPS Not Started
Security SEC_SHADOW_REGS Not Started

D3

Type Item Resolution Note/Collaterals
Documentation NEW_FEATURES_D3 Not Started
RTL TODO_COMPLETE Not Started
Code Quality LINT_COMPLETE Not Started
Code Quality CDC_COMPLETE Not Started
Review REVIEW_RTL Not Started
Review REVIEW_DELETED_FF Not Started
Review REVIEW_SW_CSR Not Started
Review REVIEW_SW_FATAL_ERR Not Started
Review REVIEW_SW_CHANGE Not Started
Review REVIEW_SW_ERRATA Not Started

Verification Checklist

V1

Type Item Resolution Note/Collaterals
Documentation DV_PLAN_DRAFT_COMPLETED Waived Plan created, but does not conform to other templates
Documentation TESTPLAN_COMPLETED Done
Testbench TB_TOP_CREATED Done
Testbench PRELIMINARY_ASSERTION_CHECKS_ADDED N/A
Testbench TB_ENV_CREATED Done
Testbench RAL_MODEL_GEN_AUTOMATED N/A
Testbench TB_GEN_AUTOMATED N/A
Tests SANITY_TEST_PASSING Done
Tests CSR_MEM_TEST_SUITE_PASSING Done
Tool Setup ALT_TOOL_SETUP Waived waived for now, doesn't follow standard tool flow
Regression SANITY_REGRESSION_SETUP Done
Regression NIGHTLY_REGRESSION_SETUP Done
Coverage COVERAGE_MODEL_ADDED Done
Integration PRE_VERIFIED_SUB_MODULES_V1 N/A
Review DESIGN_SPEC_REVIEWED Done
Review DV_PLAN_TESTPLAN_REVIEWED Waived Not done, will be reviewed in V2
Review STD_TEST_CATEGORIES_PLANNED Done different format than comportable modules
Review V2_CHECKLIST_SCOPED Done

V2

Type Item Resolution Note/Collaterals
Documentation DESIGN_DELTAS_CAPTURED_V2 Not Started
Documentation DV_PLAN_COMPLETED Not Started
Testbench ALL_INTERFACES_EXERCISED Not Started
Testbench ALL_ASSERTION_CHECKS_ADDED Not Started
Testbench TB_ENV_COMPLETED Not Started
Tests ALL_TESTS_PASSING Not Started
Tests FW_SIMULATED Not Started
Regression NIGHTLY_REGRESSION_V2 Not Started
Coverage CODE_COVERAGE_V2 Not Started
Coverage FUNCTIONAL_COVERAGE_V2 Not Started
Issues NO_HIGH_PRIORITY_ISSUES_PENDING Not Started
Issues ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED Not Started
Integration PRE_VERIFIED_SUB_MODULES_V2 N/A
Review V3_CHECKLIST_SCOPED Not Started

V3

Type Item Resolution Note/Collaterals
Documentation DESIGN_DELTAS_CAPTURED_V3 Not Started
Testbench ALL_TODOS_RESOLVED Not Started
Tests X_PROP_ANALYSIS_COMPLETED Not Started
Regression NIGHTLY_REGRESSION_AT_100 Not Started
Coverage CODE_COVERAGE_AT_100 Not Started
Coverage FUNCTIONAL_COVERAGE_AT_100 Not Started
Issues NO_ISSUES_PENDING Not Started
Code Quality NO_TOOL_WARNINGS_THROWN Not Started
Integration PRE_VERIFIED_SUB_MODULES_V3 Not Started