Ibex RISC-V Core Wrapper Technical Specification

Overview

This document specifies Ibex CPU core wrapper functionality.

Features

  • Instantiation of a Ibex RV32 CPU Core.
  • TileLink Uncached Light (TL-UL) host interfaces for the instruction and data ports.
  • Simple address translation.
  • NMI support for security alert events for watchdog bark.
  • General error status collection and alert generation.

Description

The Ibex RISC-V Core Wrapper instantiates an Ibex RV32 CPU Core, and wraps its data and instruction memory interfaces to TileLink Uncached Light (TL-UL). All configuration parameters of Ibex are passed through. The pipelining of the bus adapters is configurable.

Compatibility

Ibex is a compliant RV32 RISC-V CPU core, as documented in the Ibex documentation.

The TL-UL bus interfaces exposed by this wrapper block are compliant to the TileLink Uncached Lite Specification version 1.7.1.

Theory of Operations

Simple Address Translation

The wrapper supports a simple address translation scheme. The goal of the scheme is to provide hardware support for A/B software copies.

Each copy of the software is stored at a different location. Depending upon which execution slot is active, a different copy is used. This creates an issue because each copy of software has different addresses and thus must be linked differently. Ideally, software should be able to assume one address all the time, and the hardware should remap to the appropriate physical location.

The translation scheme is based on NAPOT (natural alignment to power of two). Software picks a matching region and also a remap address. When an incoming transaction matches the selected power-of-2 region, it is redirected to the new address. If a transaction does not match, then it is directly passed through.

This allows software to place the executable code at a virtual address in the system and re-map that to the appropriate physical block.

There are separate translations controls for instruction and data. Each control contains two programmable regions (2 for instruction and 2 for data). If a transaction matches multiple regions, the lowest indexed region has priority.

For details on how to program the related registers, please see IBUS_ADDR_MATCHING_0 and IBUS_REMAP_ADDR_0.

Random Number Generation

The wrapper has a connection to the Entropy Distribution Network (EDN) with a register based interface. The RND_DATA register provides 32-bits directly from the EDN. RND_STATUS.RND_DATA_VALID indicates if the data in RND_DATA is valid or not. A polling style interface is used to get new random data. Any read to RND_DATA when it is valid invalidates the data and triggers an EDN request for new data. Software should poll RND_STATUS.RND_DATA_VALID until it is valid and then read from RND_DATA to get the new random data. Either the data is valid or a request for new data is pending. It is not possible to have a state where there is no valid data without new data being requested.

Upon reset RND_DATA is invalid. A request is made to the EDN immediately out of reset, this will not be answered until the EDN is enabled. Software should take care not to enable the EDN until the entropy complex configuration is as desired. When the entropy complex configuration is changed reading RND_DATA when it is valid will suffice to flush any old random data to trigger a new request under the new configuration. If a EDN request is pending when the entropy complex configuration is changed (RND_STATUS.RND_DATA_VALID is clear), it is advisable to wait until it is complete and then flush out the data to ensure the fresh value was produced under the new configuration.

Register Table

A number of memory-mapped registers are available to control Ibex-related functionality that’s specific to OpenTitan.

RV_CORE_IBEX.ALERT_TEST @ 0x0

Alert Test Register

Reset default = 0x0, mask 0xf
31302928272625242322212019181716
 
1514131211109876543210
  recov_hw_err fatal_hw_err recov_sw_err fatal_sw_err
BitsTypeResetNameDescription
0wo0x0fatal_sw_err

Write 1 to trigger one alert event of this kind.

1wo0x0recov_sw_err

Write 1 to trigger one alert event of this kind.

2wo0x0fatal_hw_err

Write 1 to trigger one alert event of this kind.

3wo0x0recov_hw_err

Write 1 to trigger one alert event of this kind.


RV_CORE_IBEX.SW_ALERT_REGWEN_0 @ 0x4

Software alert regwen.

Reset default = 0x1, mask 0x1
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  EN_0
BitsTypeResetNameDescription
0rw0c0x1EN_0

Software alert write-enable. Once set to 0, it can longer be configured to 1

0Software alert locked

Software alert can no longer be configured until next reset.

1Software alert enabled

Software alert can still be configured.


RV_CORE_IBEX.SW_ALERT_REGWEN_1 @ 0x8

Software alert regwen.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
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  EN_1
BitsTypeResetNameDescription
0rw0c0x1EN_1

For SW_ALERTS_REGWEN1


RV_CORE_IBEX.SW_ALERT_0 @ 0xc

Software trigger alerts. When set to 1, triggers an alert to the alert handler

Reset default = 0x1, mask 0x3
Register enable = SW_ALERT_REGWEN_0
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  VAL_0
BitsTypeResetNameDescription
1:0rw0x1VAL_0

Software alert trigger value. Any value NOT 1 will trigger an alert.


RV_CORE_IBEX.SW_ALERT_1 @ 0x10

Software trigger alerts. When set to 1, triggers an alert to the alert handler

Reset default = 0x1, mask 0x3
Register enable = SW_ALERT_REGWEN_1
31302928272625242322212019181716
 
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  VAL_1
BitsTypeResetNameDescription
1:0rw0x1VAL_1

For SW_ALERTS1


RV_CORE_IBEX.IBUS_REGWEN_0 @ 0x14

Ibus address control regwen.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_0
BitsTypeResetNameDescription
0rw0c0x1EN_0

Ibus address controls write enable. Once set to 0, it can longer be configured to 1

0locked

Address controls can no longer be configured until next reset.

1enabled

Address controls can still be configured.


RV_CORE_IBEX.IBUS_REGWEN_1 @ 0x18

Ibus address control regwen.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_1
BitsTypeResetNameDescription
0rw0c0x1EN_1

For IBUS_REGWEN1


RV_CORE_IBEX.IBUS_ADDR_EN_0 @ 0x1c

Enable Ibus address matching

Reset default = 0x0, mask 0x1
Register enable = IBUS_REGWEN_0
31302928272625242322212019181716
 
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  EN_0
BitsTypeResetNameDescription
0rw0x0EN_0

Enable ibus address matching.


RV_CORE_IBEX.IBUS_ADDR_EN_1 @ 0x20

Enable Ibus address matching

Reset default = 0x0, mask 0x1
Register enable = IBUS_REGWEN_1
31302928272625242322212019181716
 
1514131211109876543210
  EN_1
BitsTypeResetNameDescription
0rw0x0EN_1

For IBUS_ADDR_CFG1


RV_CORE_IBEX.IBUS_ADDR_MATCHING_0 @ 0x24

Matching region programming for ibus.

Reset default = 0x0, mask 0xffffffff
Register enable = IBUS_REGWEN_0

The value programmed is done at power-of-2 alignment. For example, if the intended matching region is 0x8000_0000 to 0x8000_FFFF, the value programmed is 0x8000_7FFF.

The value programmed can be determined from the translation granule. Assume the user wishes to translate a specific 64KB block to a different address: 64KB has a hex value of 0x10000. Subtract 1 from this value and then right shift by one to obtain 0x7FFF. This value is then logically OR'd with the upper address bits that would select which 64KB to translate.

In this exampole, the user wishes to translate the 0x8000-th 64KB block. The value programmed is then 0x8000_7FFF.

If the user were to translate the 0x8001-th 64KB block, the value programmed would be 0x8001_7FFF.

31302928272625242322212019181716
VAL_0...
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...VAL_0
BitsTypeResetNameDescription
31:0rw0x0VAL_0

Matching region value


RV_CORE_IBEX.IBUS_ADDR_MATCHING_1 @ 0x28

Matching region programming for ibus.

Reset default = 0x0, mask 0xffffffff
Register enable = IBUS_REGWEN_1

The value programmed is done at power-of-2 alignment. For example, if the intended matching region is 0x8000_0000 to 0x8000_FFFF, the value programmed is 0x8000_7FFF.

The value programmed can be determined from the translation granule. Assume the user wishes to translate a specific 64KB block to a different address: 64KB has a hex value of 0x10000. Subtract 1 from this value and then right shift by one to obtain 0x7FFF. This value is then logically OR'd with the upper address bits that would select which 64KB to translate.

In this exampole, the user wishes to translate the 0x8000-th 64KB block. The value programmed is then 0x8000_7FFF.

If the user were to translate the 0x8001-th 64KB block, the value programmed would be 0x8001_7FFF.

31302928272625242322212019181716
VAL_1...
1514131211109876543210
...VAL_1
BitsTypeResetNameDescription
31:0rw0x0VAL_1

For IBUS_ADDR_MATCHING1


RV_CORE_IBEX.IBUS_REMAP_ADDR_0 @ 0x2c

The remap address after a match has been made. The remap bits apply only to top portion of address bits not covered by the matching region.

Reset default = 0x0, mask 0xffffffff
Register enable = IBUS_REGWEN_0

For example, if the translation region is 64KB, the remapped address applies only to the upper address bits that select which 64KB to be translated.

31302928272625242322212019181716
VAL_0...
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...VAL_0
BitsTypeResetNameDescription
31:0rw0x0VAL_0

Remap addr value


RV_CORE_IBEX.IBUS_REMAP_ADDR_1 @ 0x30

The remap address after a match has been made. The remap bits apply only to top portion of address bits not covered by the matching region.

Reset default = 0x0, mask 0xffffffff
Register enable = IBUS_REGWEN_1

For example, if the translation region is 64KB, the remapped address applies only to the upper address bits that select which 64KB to be translated.

31302928272625242322212019181716
VAL_1...
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...VAL_1
BitsTypeResetNameDescription
31:0rw0x0VAL_1

For IBUS_REMAP_ADDR1


RV_CORE_IBEX.DBUS_REGWEN_0 @ 0x34

Dbus address control regwen.

Reset default = 0x1, mask 0x1
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  EN_0
BitsTypeResetNameDescription
0rw0c0x1EN_0

Ibus address controls write enable. Once set to 0, it can longer be configured to 1

0locked

Address controls can no longer be configured until next reset.

1enabled

Address controls can still be configured.


RV_CORE_IBEX.DBUS_REGWEN_1 @ 0x38

Dbus address control regwen.

Reset default = 0x1, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  EN_1
BitsTypeResetNameDescription
0rw0c0x1EN_1

For DBUS_REGWEN1


RV_CORE_IBEX.DBUS_ADDR_EN_0 @ 0x3c

Enable dbus address matching

Reset default = 0x0, mask 0x1
Register enable = DBUS_REGWEN_0
31302928272625242322212019181716
 
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  EN_0
BitsTypeResetNameDescription
0rw0x0EN_0

Enable dbus address matching.


RV_CORE_IBEX.DBUS_ADDR_EN_1 @ 0x40

Enable dbus address matching

Reset default = 0x0, mask 0x1
Register enable = DBUS_REGWEN_1
31302928272625242322212019181716
 
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  EN_1
BitsTypeResetNameDescription
0rw0x0EN_1

For DBUS_ADDR_CFG1


RV_CORE_IBEX.DBUS_ADDR_MATCHING_0 @ 0x44

See IBUS_ADDR_MATCHING_0 for detailed description.

Reset default = 0x0, mask 0xffffffff
Register enable = DBUS_REGWEN_0
31302928272625242322212019181716
VAL_0...
1514131211109876543210
...VAL_0
BitsTypeResetNameDescription
31:0rw0x0VAL_0

Matching region value


RV_CORE_IBEX.DBUS_ADDR_MATCHING_1 @ 0x48

See IBUS_ADDR_MATCHING_0 for detailed description.

Reset default = 0x0, mask 0xffffffff
Register enable = DBUS_REGWEN_1
31302928272625242322212019181716
VAL_1...
1514131211109876543210
...VAL_1
BitsTypeResetNameDescription
31:0rw0x0VAL_1

For DBUS_ADDR_MATCHING1


RV_CORE_IBEX.DBUS_REMAP_ADDR_0 @ 0x4c

See IBUS_REMAP_ADDR_0 for a detailed description.

Reset default = 0x0, mask 0xffffffff
Register enable = DBUS_REGWEN_0
31302928272625242322212019181716
VAL_0...
1514131211109876543210
...VAL_0
BitsTypeResetNameDescription
31:0rw0x0VAL_0

Remap addr value


RV_CORE_IBEX.DBUS_REMAP_ADDR_1 @ 0x50

See IBUS_REMAP_ADDR_0 for a detailed description.

Reset default = 0x0, mask 0xffffffff
Register enable = DBUS_REGWEN_1
31302928272625242322212019181716
VAL_1...
1514131211109876543210
...VAL_1
BitsTypeResetNameDescription
31:0rw0x0VAL_1

For DBUS_REMAP_ADDR1


RV_CORE_IBEX.NMI_ENABLE @ 0x54

Enable mask for NMI. Once an enable mask is set, it cannot be disabled.

Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
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  WDOG_EN ALERT_EN
BitsTypeResetNameDescription
0rw1s0x0ALERT_EN

Enable mask for alert NMI

1rw1s0x0WDOG_EN

Enable mask for watchdog NMI


RV_CORE_IBEX.NMI_STATE @ 0x58

Current NMI state

Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  WDOG ALERT
BitsTypeResetNameDescription
0rw1c0x0ALERT

Current state for alert NMI

1rw1c0x0WDOG

Current state for watchdog NMI


RV_CORE_IBEX.ERR_STATUS @ 0x5c

error status

Reset default = 0x0, mask 0x701
31302928272625242322212019181716
 
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  RECOV_CORE_ERR FATAL_CORE_ERR FATAL_INTG_ERR   REG_INTG_ERR
BitsTypeResetNameDescription
0rw1c0x0REG_INTG_ERR

rv_core_ibex_peri detected a register transmission integrity error

7:1Reserved
8rw1c0x0FATAL_INTG_ERR

rv_core_ibex detected a response integrity error

9rw1c0x0FATAL_CORE_ERR

rv_core_ibex detected a fatal internal error

10rw1c0x0RECOV_CORE_ERR

rv_core_ibex detected a recoverable internal error


RV_CORE_IBEX.RND_DATA @ 0x60

Random data from EDN

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
DATA...
1514131211109876543210
...DATA
BitsTypeResetNameDescription
31:0ro0x0DATA

Random bits taken from the EDN. RND_STATUS.RND_DATA_VALID indicates if this data is valid. When valid, reading from this register invalidates the data and requests new data from the EDN. The register becomes valid again when the EDN provides new data. When invalid the register value will read as 0x0 with an EDN request for new data pending. Upon reset the data will be invalid with a new EDN request pending.


RV_CORE_IBEX.RND_STATUS @ 0x64

Status of random data in RND_DATA

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
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  RND_DATA_VALID
BitsTypeResetNameDescription
0ro0x0RND_DATA_VALID

When set, the data in RND_DATA is valid. When clear an EDN request for new data for RND_DATA is pending.


Hardware Interfaces

Signals

Referring to the Comportable guideline for peripheral device functionality, the module RV_CORE_IBEX has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: clk_esc_i

Bus Device Interfaces (TL-UL): cfg_tl_d

Bus Host Interfaces (TL-UL): corei_tl_h, cored_tl_h

Peripheral Pins for Chip IO: none

Interrupts: none

Security Alerts:

Alert NameDescription
fatal_sw_err

Software triggered alert for fatal faults

recov_sw_err

Software triggered Alert for recoverable faults

fatal_hw_err

Ibex core triggered alert for fatal faults, including integrity faults

recov_hw_err

Ibex core triggered alert for recoverable faults

All ports and parameters of Ibex are exposed through this wrapper module, except for the instruction and data memory interfaces (signals starting with instr_ and data_). Refer to the Ibex documentation for a detailed description of these signals and parameters.

The instruction and data memory ports are exposed as TL-UL ports. The table below lists other signals and the TL-UL ports.

Signal Direction Type Description
rst_cpu_n_o output logic Outgoing indication to reset manager that the process has reset.
ram_cfg_i input prim_ram_1p_pkg::ram_1p_cfg_t Incoming memory configuration that is technology dependent.
corei_tl_h_o output tlul_pkg::tl_h2d_t Outgoing instruction tlul request
corei_tl_h_i input tlul_pkg::tl_d2h_t Incoming instruction tlul response.
cored_tl_h_o output tlul_pkg::tl_h2d_t Outgoing data tlul request
cored_tl_h_i input tlul_pkg::tl_d2h_t Incoming data tlul response.
esc_tx_i input prim_esc_pkg::esc_tx_t Incoming escalation request / ping.
esc_rx_o output prim_esc_pkg::esc_rx_t Outgoing escalation response.
nmi_wdog_i input logic Incoming watchdog NMI bark.
crash_dump_o output ibex_pkg::crash_dump_t Outgoing crash dump information to rstmgr.
cfg_tl_d_i input tlul_pkg::tl_h2d_t Incoming configuration bus request.
cfg_tl_d_o output tlul_pkg::tl_d2h_t Outgoing configuration bus response.

The PipeLine parameter can be used to configure the bus adapter pipelining.

  • Setting PipeLine to 0 disables pipelining, which gives minimal latency between the bus and the core, at the cost of a combinatorial path into the core.
  • Setting PipeLine to 1 introduces a pipelining FIFO between the core instruction/data interfaces and the bus. This setting increases the memory access latency, but improves timing.