Interrupt Controller Technical Specification

Overview

This document specifies the Interrupt Controller (RV_PLIC) functionality. This module conforms to the Comportable guideline for peripheral functionality. See that document for integration overview within the broader top level system.

Features

  • RISC-V Platform-Level Interrupt Controller (PLIC) compliant interrupt controller
  • Support arbitrary number of interrupt vectors (up to 255) and targets
  • Support interrupt enable, interrupt status registers
  • Memory-mapped MSIP register per HART for software interrupt control.

Description

The RV_PLIC module is designed to manage various interrupt sources from the peripherals. It receives interrupt events as either edge or level of the incoming interrupt signals (intr_src_i) and can notify multiple targets.

Compatibility

The RV_PLIC is compatible with any RISC-V core implementing the RISC-V privilege specification.

Theory of Operations

Block Diagram

RV_PLIC Block Diagram

Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module RV_PLIC has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: none

Bus Device Interface: tlul

Bus Host Interface: none

Peripheral Pins for Chip IO: none

Interrupts: none

Security Alerts: none

Design Details

Identifier

Each interrupt source has a unique ID assigned based upon its bit position within the input intr_src_i. ID ranges from 0 to N, the number of interrupt sources. ID 0 is reserved and represents no interrupt. The bit 0 of intr_src_i shall be tied to 0 from the outside of RV_PLIC. The intr_src_i[i] bit has an ID of i. This ID is used when targets “claim” the interrupt and to “complete” the interrupt event.

Priority and Threshold

Interrupt sources have configurable priority values. The maximum value of the priority is configurable through the localparam MAX_PRIO in the rv_plic top-level module. For each target there is a threshold value (THRESHOLD0 for target 0). RV_PLIC notifies a target of an interrupt only if it's priority is strictly greater than the target's threshold. Note this means an interrupt with a priority is 0 is effectively prevented from causing an interrupt at any target and a target can suppress all interrupts by setting it's threshold to the max priority value.

MAX_PRIO parameter is most area contributing option in RV_PLIC. If MAX_PRIO is big, then finding the highest priority in Process module may consume a lot of logic gates.

Interrupt Gateways

The Gateway observes incoming interrupt sources and converts them to a common interrupt format used internally by RV_PLIC. It can be configured to detect interrupts events on an edge (when the signal changes from 0 to 1) or level basis (where the signal remains at 1).

When the gateway detects an interrupt event it raises the interrupt pending bit (IP) for that interrupt source. When an interrupt is claimed by a target the relevant bit of IP is cleared. A bit in IP will not be reasserted until the target signals completion of the interrupt. Any new interrupt event between a bit in IP asserting and completing that interrupt is ignored. In particular this means that for edge triggered interrupts if a new edge is seen after the source's IP bit is asserted but before completion, that edge will be ignored (counting missed edges as discussed in the RISC-V PLIC specification is not supported).

Note that there is no ability for a level triggered interrupt to be cancelled. If the interrupt drops after the gateway has set a bit in IP, the bit will remain set until the interrupt is completed. The SW handler should be conscious of this and check the interrupt still requires handling in the handler if this behaviour is possible.

Interrupt Enables

Each target has a set of Interrupt Enable (IE0 for target 0) registers. Each bit in the IE0 registers controls the corresponding interrupt source. If an interrupt source is disabled for a target, then interrupt events from that source won't trigger an interrupt at the target. RV_PLIC doesn't have a global interrupt disable feature.

Interrupt Claims

“Claiming” an interrupt is done by a target reading the associated Claim/Completion register for the target (CC0 for target 0). The return value of the CC0 read represents the ID of the pending interrupt that has the highest priority. If two or more pending interrupts have the same priority, RV_PLIC chooses the one with lowest ID. Only interrupts that that are enabled for the target can be claimed. The target priority threshold doesn't matter (this only factors into whether an interrupt is signalled to the target) so lower priority interrupt IDs can be returned on a read from CC0. If no interrupt is pending (or all pending interrupts are disabled for the target) a read of CC0 returns an ID of 0.

Interrupt Completion

After an interrupt is claimed, the relevant bit of interrupt pending (IP) is cleared, regardless of the status of the intr_src_i input value. Until a target “completes” the interrupt, it won't be re-asserted if a new event for the interrupt occurs. A target completes the interrupt by writing the ID of the interrupt to the Claim/Complete register (CC0 for target 0). The write event is forwarded to the Gateway logic, which resets the interrupt status to accept a new interrupt event. The assumption is that the processor has cleaned up the originating interrupt event during the time between claim and complete such that intr_src_i[ID] will have de-asserted (unless a new interrupt has occurred).

{ signal: [
  { name: 'clk',           wave: 'p...........' },
  { name: 'intr_src_i[i]', wave: '01....0.1...', node:'.a....e.f...'},
  { name: 'irq_o',         wave: '0.1.0......1', node:'..b.d......h'},
  { name: 'irq_id_o',      wave: '=.=.=......=',
                           data: ["0","i","0","i"] },
  { name: 'claim',         wave: '0..10.......', node:'...c........'},
  { name: 'complete',      wave: '0.........10', node:'..........g.'},
  ],
  head:{
    text: 'Interrupt Flow',
    tick: 0,
  },
}

In the example above an interrupt for source ID i is configured as a level interrupt and is raised at a, this results in the target being notified of the interrupt at b. The target claims the interrupt at c (reading i from it's Claim/Complete register) so irq_o deasserts though intr_src_i[i] remains raised. The SW handles the interrupt and it drops at e. However a new interrupt quickly occurs at f. As complete hasn't been signaled yet irq_o isn't asserted. At g the interrupt is completed (by writing i to it's Claim/Complete register) so at h irq_o is asserted due to the new interrupt.

Programmers Guide

Initialization

After reset, RV_PLIC doesn't generate any interrupts to any targets even if interrupt sources are set, as all priorities and thresholds are 0 by default and all IE values are 0. Software should configure the above three registers and the interrupt source type LE .

LE and PRIO0 .. PRIO31 registers are unique. So, only one of the targets shall configure them.

// Pseudo-code below
void plic_init() {
  // Set to level-triggered for interrupt sources
  for (int i = 0; i < ceil(N_SOURCE / 32); ++i) {
    *(LE + i) = 0;
  }

  // Configure priority
  // Note that PRIO0 register doesn't affect as intr_src_i[0] is tied to 0.
  for (int i = 0; i < N_SOURCE; ++i) {
    *(PRIO + i) = value(i);
  }
}

void plic_threshold(tid, threshold) {
  *(THRESHOLD + tid) = threshold;
}

void plic_enable(tid, iid) {
  // iid: 0-based ID
  int offset = ceil(N_SOURCE / 32) * tid + (iid >> 5);

  *(IE + offset) = *(IE + offset) | (1 << (iid % 32));
}

Handling Interrupt Request Events

If software receives an interrupt request, it is recommended to follow the steps shown below (assuming target 0 which uses CC0 for claim/complete).

  1. Claim the interrupts right after entering to the interrupt service routine by reading the CC0 register.
  2. Determine which interrupt should be serviced based on the values read from the CC0 register.
  3. Execute ISR, clearing the originating peripheral interrupt.
  4. Write Interrupt ID to CC0
  5. Repeat as necessary for other pending interrupts.

It is possible to have multiple interrupt events claimed. If software claims one interrupt request, then the process module advertises any pending interrupts with lower priority unless new higher priority interrupt events occur. If a higher interrupt event occurs after previous interrupt is claimed, the RV_PLIC IP advertises the higher priority interrupt. Software may utilize an event manager inside a loop so that interrupt claiming and completion can be separated.

void interrupt_service() {
  uint32_t tid = /* ... */;
  uint32_t iid = *(CC + tid);
  if (iid == 0) {
    // Interrupt is claimed by one of other targets.
    return;
  }

  do {
    // Process interrupts...
    // ...

    // Finish.
    *(CC + tid) = iid;
    iid = *(CC + tid);
  } while (iid != 0);
}

Device Interface Functions (DIFs)

To use this DIF, include the following C header:

#include "sw/device/lib/dif/dif_plic.h"

This header provides the following device interface functions:

Registers

The register description below matches the instance in the Earl Grey top level design.

A similar register description can be generated with reg_rv_plic.py script. The reason another script for register generation is that RV_PLIC is configurable to the number of input sources and output targets. To implement it, some of the registers (see below IE) should be double nested in register description file. As of Jan. 2019, regtool.py supports only one nested multiple register format multireg.

The RV_PLIC in the top level is generated by topgen tool so that the number of interrupt sources may be different.

  • LE: CEILING(N_SOURCE / DW) Value 1 indicates the interrupt source's behavior is edge-triggered It is used in the gateways module.
  • IE: CEILING(N_SOURCE / DW) X N_TARGET Each bit enables corresponding interrupt source. Each target has IE set.
  • PRIO: N_SOURCE Universal set across all targets. Lower n bits are valid. n is determined by MAX_PRIO parameter
  • THRESHOLD: N_TARGET Priority threshold per target. Only priority of the interrupt greater than threshold can raise interrupt notification to the target.
  • IP: CEILING(N_SOURCE / DW) Pending bits right after the gateways. Read-only
  • CC: N_TARGET Claim by read, complete by write
RV_PLIC.IP0 @ + 0x0
Interrupt Pending
Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16
1514131211109876543210
P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
BitsTypeResetNameDescription
0ro0x0P0Interrupt Pending of Source for RV_PLIC0
31:1for RV_PLIC1..RV_PLIC31


RV_PLIC.IP1 @ + 0x4
Interrupt Pending
Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
P63 P62 P61 P60 P59 P58 P57 P56 P55 P54 P53 P52 P51 P50 P49 P48
1514131211109876543210
P47 P46 P45 P44 P43 P42 P41 P40 P39 P38 P37 P36 P35 P34 P33 P32
BitsTypeResetNameDescription
0ro0x0P32Interrupt Pending of Source for RV_PLIC32
31:1for RV_PLIC33..RV_PLIC63


RV_PLIC.IP2 @ + 0x8
Interrupt Pending
Reset default = 0x0, mask 0x7ffff
31302928272625242322212019181716
  P82 P81 P80
1514131211109876543210
P79 P78 P77 P76 P75 P74 P73 P72 P71 P70 P69 P68 P67 P66 P65 P64
BitsTypeResetNameDescription
0ro0x0P64Interrupt Pending of Source for RV_PLIC64
18:1for RV_PLIC65..RV_PLIC82


RV_PLIC.LE0 @ + 0xc
Interrupt Source mode. 0: Level, 1: Edge-triggered
Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
LE31 LE30 LE29 LE28 LE27 LE26 LE25 LE24 LE23 LE22 LE21 LE20 LE19 LE18 LE17 LE16
1514131211109876543210
LE15 LE14 LE13 LE12 LE11 LE10 LE9 LE8 LE7 LE6 LE5 LE4 LE3 LE2 LE1 LE0
BitsTypeResetNameDescription
0rw0x0LE0L0E1 for RV_PLIC0
31:1for RV_PLIC1..RV_PLIC31


RV_PLIC.LE1 @ + 0x10
Interrupt Source mode. 0: Level, 1: Edge-triggered
Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
LE63 LE62 LE61 LE60 LE59 LE58 LE57 LE56 LE55 LE54 LE53 LE52 LE51 LE50 LE49 LE48
1514131211109876543210
LE47 LE46 LE45 LE44 LE43 LE42 LE41 LE40 LE39 LE38 LE37 LE36 LE35 LE34 LE33 LE32
BitsTypeResetNameDescription
0rw0x0LE32L0E1 for RV_PLIC32
31:1for RV_PLIC33..RV_PLIC63


RV_PLIC.LE2 @ + 0x14
Interrupt Source mode. 0: Level, 1: Edge-triggered
Reset default = 0x0, mask 0x7ffff
31302928272625242322212019181716
  LE82 LE81 LE80
1514131211109876543210
LE79 LE78 LE77 LE76 LE75 LE74 LE73 LE72 LE71 LE70 LE69 LE68 LE67 LE66 LE65 LE64
BitsTypeResetNameDescription
0rw0x0LE64L0E1 for RV_PLIC64
18:1for RV_PLIC65..RV_PLIC82


RV_PLIC.PRIO0 @ + 0x18
Interrupt Source 0 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO0
BitsTypeResetNameDescription
1:0rw0x0PRIO0


RV_PLIC.PRIO1 @ + 0x1c
Interrupt Source 1 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO1
BitsTypeResetNameDescription
1:0rw0x0PRIO1


RV_PLIC.PRIO2 @ + 0x20
Interrupt Source 2 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO2
BitsTypeResetNameDescription
1:0rw0x0PRIO2


RV_PLIC.PRIO3 @ + 0x24
Interrupt Source 3 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO3
BitsTypeResetNameDescription
1:0rw0x0PRIO3


RV_PLIC.PRIO4 @ + 0x28
Interrupt Source 4 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO4
BitsTypeResetNameDescription
1:0rw0x0PRIO4


RV_PLIC.PRIO5 @ + 0x2c
Interrupt Source 5 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO5
BitsTypeResetNameDescription
1:0rw0x0PRIO5


RV_PLIC.PRIO6 @ + 0x30
Interrupt Source 6 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO6
BitsTypeResetNameDescription
1:0rw0x0PRIO6


RV_PLIC.PRIO7 @ + 0x34
Interrupt Source 7 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO7
BitsTypeResetNameDescription
1:0rw0x0PRIO7


RV_PLIC.PRIO8 @ + 0x38
Interrupt Source 8 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO8
BitsTypeResetNameDescription
1:0rw0x0PRIO8


RV_PLIC.PRIO9 @ + 0x3c
Interrupt Source 9 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO9
BitsTypeResetNameDescription
1:0rw0x0PRIO9


RV_PLIC.PRIO10 @ + 0x40
Interrupt Source 10 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO10
BitsTypeResetNameDescription
1:0rw0x0PRIO10


RV_PLIC.PRIO11 @ + 0x44
Interrupt Source 11 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO11
BitsTypeResetNameDescription
1:0rw0x0PRIO11


RV_PLIC.PRIO12 @ + 0x48
Interrupt Source 12 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO12
BitsTypeResetNameDescription
1:0rw0x0PRIO12


RV_PLIC.PRIO13 @ + 0x4c
Interrupt Source 13 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO13
BitsTypeResetNameDescription
1:0rw0x0PRIO13


RV_PLIC.PRIO14 @ + 0x50
Interrupt Source 14 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO14
BitsTypeResetNameDescription
1:0rw0x0PRIO14


RV_PLIC.PRIO15 @ + 0x54
Interrupt Source 15 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO15
BitsTypeResetNameDescription
1:0rw0x0PRIO15


RV_PLIC.PRIO16 @ + 0x58
Interrupt Source 16 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO16
BitsTypeResetNameDescription
1:0rw0x0PRIO16


RV_PLIC.PRIO17 @ + 0x5c
Interrupt Source 17 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO17
BitsTypeResetNameDescription
1:0rw0x0PRIO17


RV_PLIC.PRIO18 @ + 0x60
Interrupt Source 18 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO18
BitsTypeResetNameDescription
1:0rw0x0PRIO18


RV_PLIC.PRIO19 @ + 0x64
Interrupt Source 19 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO19
BitsTypeResetNameDescription
1:0rw0x0PRIO19


RV_PLIC.PRIO20 @ + 0x68
Interrupt Source 20 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO20
BitsTypeResetNameDescription
1:0rw0x0PRIO20


RV_PLIC.PRIO21 @ + 0x6c
Interrupt Source 21 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO21
BitsTypeResetNameDescription
1:0rw0x0PRIO21


RV_PLIC.PRIO22 @ + 0x70
Interrupt Source 22 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO22
BitsTypeResetNameDescription
1:0rw0x0PRIO22


RV_PLIC.PRIO23 @ + 0x74
Interrupt Source 23 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO23
BitsTypeResetNameDescription
1:0rw0x0PRIO23


RV_PLIC.PRIO24 @ + 0x78
Interrupt Source 24 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO24
BitsTypeResetNameDescription
1:0rw0x0PRIO24


RV_PLIC.PRIO25 @ + 0x7c
Interrupt Source 25 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO25
BitsTypeResetNameDescription
1:0rw0x0PRIO25


RV_PLIC.PRIO26 @ + 0x80
Interrupt Source 26 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO26
BitsTypeResetNameDescription
1:0rw0x0PRIO26


RV_PLIC.PRIO27 @ + 0x84
Interrupt Source 27 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO27
BitsTypeResetNameDescription
1:0rw0x0PRIO27


RV_PLIC.PRIO28 @ + 0x88
Interrupt Source 28 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO28
BitsTypeResetNameDescription
1:0rw0x0PRIO28


RV_PLIC.PRIO29 @ + 0x8c
Interrupt Source 29 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO29
BitsTypeResetNameDescription
1:0rw0x0PRIO29


RV_PLIC.PRIO30 @ + 0x90
Interrupt Source 30 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO30
BitsTypeResetNameDescription
1:0rw0x0PRIO30


RV_PLIC.PRIO31 @ + 0x94
Interrupt Source 31 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO31
BitsTypeResetNameDescription
1:0rw0x0PRIO31


RV_PLIC.PRIO32 @ + 0x98
Interrupt Source 32 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO32
BitsTypeResetNameDescription
1:0rw0x0PRIO32


RV_PLIC.PRIO33 @ + 0x9c
Interrupt Source 33 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO33
BitsTypeResetNameDescription
1:0rw0x0PRIO33


RV_PLIC.PRIO34 @ + 0xa0
Interrupt Source 34 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO34
BitsTypeResetNameDescription
1:0rw0x0PRIO34


RV_PLIC.PRIO35 @ + 0xa4
Interrupt Source 35 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO35
BitsTypeResetNameDescription
1:0rw0x0PRIO35


RV_PLIC.PRIO36 @ + 0xa8
Interrupt Source 36 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO36
BitsTypeResetNameDescription
1:0rw0x0PRIO36


RV_PLIC.PRIO37 @ + 0xac
Interrupt Source 37 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO37
BitsTypeResetNameDescription
1:0rw0x0PRIO37


RV_PLIC.PRIO38 @ + 0xb0
Interrupt Source 38 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO38
BitsTypeResetNameDescription
1:0rw0x0PRIO38


RV_PLIC.PRIO39 @ + 0xb4
Interrupt Source 39 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO39
BitsTypeResetNameDescription
1:0rw0x0PRIO39


RV_PLIC.PRIO40 @ + 0xb8
Interrupt Source 40 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO40
BitsTypeResetNameDescription
1:0rw0x0PRIO40


RV_PLIC.PRIO41 @ + 0xbc
Interrupt Source 41 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO41
BitsTypeResetNameDescription
1:0rw0x0PRIO41


RV_PLIC.PRIO42 @ + 0xc0
Interrupt Source 42 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO42
BitsTypeResetNameDescription
1:0rw0x0PRIO42


RV_PLIC.PRIO43 @ + 0xc4
Interrupt Source 43 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO43
BitsTypeResetNameDescription
1:0rw0x0PRIO43


RV_PLIC.PRIO44 @ + 0xc8
Interrupt Source 44 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO44
BitsTypeResetNameDescription
1:0rw0x0PRIO44


RV_PLIC.PRIO45 @ + 0xcc
Interrupt Source 45 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO45
BitsTypeResetNameDescription
1:0rw0x0PRIO45


RV_PLIC.PRIO46 @ + 0xd0
Interrupt Source 46 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO46
BitsTypeResetNameDescription
1:0rw0x0PRIO46


RV_PLIC.PRIO47 @ + 0xd4
Interrupt Source 47 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO47
BitsTypeResetNameDescription
1:0rw0x0PRIO47


RV_PLIC.PRIO48 @ + 0xd8
Interrupt Source 48 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO48
BitsTypeResetNameDescription
1:0rw0x0PRIO48


RV_PLIC.PRIO49 @ + 0xdc
Interrupt Source 49 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO49
BitsTypeResetNameDescription
1:0rw0x0PRIO49


RV_PLIC.PRIO50 @ + 0xe0
Interrupt Source 50 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO50
BitsTypeResetNameDescription
1:0rw0x0PRIO50


RV_PLIC.PRIO51 @ + 0xe4
Interrupt Source 51 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO51
BitsTypeResetNameDescription
1:0rw0x0PRIO51


RV_PLIC.PRIO52 @ + 0xe8
Interrupt Source 52 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO52
BitsTypeResetNameDescription
1:0rw0x0PRIO52


RV_PLIC.PRIO53 @ + 0xec
Interrupt Source 53 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO53
BitsTypeResetNameDescription
1:0rw0x0PRIO53


RV_PLIC.PRIO54 @ + 0xf0
Interrupt Source 54 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO54
BitsTypeResetNameDescription
1:0rw0x0PRIO54


RV_PLIC.PRIO55 @ + 0xf4
Interrupt Source 55 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO55
BitsTypeResetNameDescription
1:0rw0x0PRIO55


RV_PLIC.PRIO56 @ + 0xf8
Interrupt Source 56 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO56
BitsTypeResetNameDescription
1:0rw0x0PRIO56


RV_PLIC.PRIO57 @ + 0xfc
Interrupt Source 57 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO57
BitsTypeResetNameDescription
1:0rw0x0PRIO57


RV_PLIC.PRIO58 @ + 0x100
Interrupt Source 58 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO58
BitsTypeResetNameDescription
1:0rw0x0PRIO58


RV_PLIC.PRIO59 @ + 0x104
Interrupt Source 59 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO59
BitsTypeResetNameDescription
1:0rw0x0PRIO59


RV_PLIC.PRIO60 @ + 0x108
Interrupt Source 60 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO60
BitsTypeResetNameDescription
1:0rw0x0PRIO60


RV_PLIC.PRIO61 @ + 0x10c
Interrupt Source 61 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO61
BitsTypeResetNameDescription
1:0rw0x0PRIO61


RV_PLIC.PRIO62 @ + 0x110
Interrupt Source 62 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO62
BitsTypeResetNameDescription
1:0rw0x0PRIO62


RV_PLIC.PRIO63 @ + 0x114
Interrupt Source 63 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO63
BitsTypeResetNameDescription
1:0rw0x0PRIO63


RV_PLIC.PRIO64 @ + 0x118
Interrupt Source 64 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO64
BitsTypeResetNameDescription
1:0rw0x0PRIO64


RV_PLIC.PRIO65 @ + 0x11c
Interrupt Source 65 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO65
BitsTypeResetNameDescription
1:0rw0x0PRIO65


RV_PLIC.PRIO66 @ + 0x120
Interrupt Source 66 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO66
BitsTypeResetNameDescription
1:0rw0x0PRIO66


RV_PLIC.PRIO67 @ + 0x124
Interrupt Source 67 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO67
BitsTypeResetNameDescription
1:0rw0x0PRIO67


RV_PLIC.PRIO68 @ + 0x128
Interrupt Source 68 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO68
BitsTypeResetNameDescription
1:0rw0x0PRIO68


RV_PLIC.PRIO69 @ + 0x12c
Interrupt Source 69 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO69
BitsTypeResetNameDescription
1:0rw0x0PRIO69


RV_PLIC.PRIO70 @ + 0x130
Interrupt Source 70 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO70
BitsTypeResetNameDescription
1:0rw0x0PRIO70


RV_PLIC.PRIO71 @ + 0x134
Interrupt Source 71 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO71
BitsTypeResetNameDescription
1:0rw0x0PRIO71


RV_PLIC.PRIO72 @ + 0x138
Interrupt Source 72 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO72
BitsTypeResetNameDescription
1:0rw0x0PRIO72


RV_PLIC.PRIO73 @ + 0x13c
Interrupt Source 73 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO73
BitsTypeResetNameDescription
1:0rw0x0PRIO73


RV_PLIC.PRIO74 @ + 0x140
Interrupt Source 74 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO74
BitsTypeResetNameDescription
1:0rw0x0PRIO74


RV_PLIC.PRIO75 @ + 0x144
Interrupt Source 75 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO75
BitsTypeResetNameDescription
1:0rw0x0PRIO75


RV_PLIC.PRIO76 @ + 0x148
Interrupt Source 76 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO76
BitsTypeResetNameDescription
1:0rw0x0PRIO76


RV_PLIC.PRIO77 @ + 0x14c
Interrupt Source 77 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO77
BitsTypeResetNameDescription
1:0rw0x0PRIO77


RV_PLIC.PRIO78 @ + 0x150
Interrupt Source 78 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO78
BitsTypeResetNameDescription
1:0rw0x0PRIO78


RV_PLIC.PRIO79 @ + 0x154
Interrupt Source 79 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO79
BitsTypeResetNameDescription
1:0rw0x0PRIO79


RV_PLIC.PRIO80 @ + 0x158
Interrupt Source 80 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO80
BitsTypeResetNameDescription
1:0rw0x0PRIO80


RV_PLIC.PRIO81 @ + 0x15c
Interrupt Source 81 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO81
BitsTypeResetNameDescription
1:0rw0x0PRIO81


RV_PLIC.PRIO82 @ + 0x160
Interrupt Source 82 Priority
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  PRIO82
BitsTypeResetNameDescription
1:0rw0x0PRIO82


RV_PLIC.IE00 @ + 0x200
Interrupt Enable for Target 0
Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16
1514131211109876543210
E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
BitsTypeResetNameDescription
0rw0x0E0Interrupt Enable of Source for RV_PLIC0
31:1for RV_PLIC1..RV_PLIC31


RV_PLIC.IE01 @ + 0x204
Interrupt Enable for Target 0
Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
E63 E62 E61 E60 E59 E58 E57 E56 E55 E54 E53 E52 E51 E50 E49 E48
1514131211109876543210
E47 E46 E45 E44 E43 E42 E41 E40 E39 E38 E37 E36 E35 E34 E33 E32
BitsTypeResetNameDescription
0rw0x0E32Interrupt Enable of Source for RV_PLIC32
31:1for RV_PLIC33..RV_PLIC63


RV_PLIC.IE02 @ + 0x208
Interrupt Enable for Target 0
Reset default = 0x0, mask 0x7ffff
31302928272625242322212019181716
  E82 E81 E80
1514131211109876543210
E79 E78 E77 E76 E75 E74 E73 E72 E71 E70 E69 E68 E67 E66 E65 E64
BitsTypeResetNameDescription
0rw0x0E64Interrupt Enable of Source for RV_PLIC64
18:1for RV_PLIC65..RV_PLIC82


RV_PLIC.THRESHOLD0 @ + 0x20c
Threshold of priority for Target 0
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  THRESHOLD0
BitsTypeResetNameDescription
1:0rw0x0THRESHOLD0


RV_PLIC.CC0 @ + 0x210
Claim interrupt by read, complete interrupt by write for Target 0. Value read/written is interrupt ID. Reading a value of 0 means no pending interrupts.
Reset default = 0x0, mask 0x7f
31302928272625242322212019181716
 
1514131211109876543210
  CC0
BitsTypeResetNameDescription
6:0rw0x0CC0


RV_PLIC.MSIP0 @ + 0x214
msip for Hart 0. Write 1 to here asserts software interrupt for Hart msip_o[0], write 0 to clear.
Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  MSIP0
BitsTypeResetNameDescription
0rw0x0MSIP0Software Interrupt Pending register