RV_TIMER DV Plan

Goals

  • DV
    • Verify all RV_TIMER IP features by running dynamic simulations with a SV/UVM based testbench
    • Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
  • FPV
    • Verify TileLink device protocol compliance with an SVA based testbench

Current status

Design features

For detailed information on RV_TIMER design features, please see the RV_TIMER design specification.

Testbench architecture

RV_TIMER testbench has been constructed based on the CIP testbench architecture.

Block diagram

Block diagram

Top level testbench

Top level testbench is located at hw/ip/rv_timer/dv/tb/tb.sv. It instantiates the RV_TIMER DUT module hw/ip/rv_timer/rtl/rv_timer.sv. In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db:

Common DV utility components

The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

Global types & methods

All common types and methods defined at the package level can be found in env/rv_timer_env_pkg. Some of them in use are:

parameter uint NUM_HARTS = 1;
parameter uint NUM_TIMERS = 1;

TL_agent

RV_TIMER testbench instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into RV_TIMER device.

UVM RAL Model

The RV_TIMER RAL model is created with the ralgen FuseSoC generator script automatically when the simulation is at the build stage.

It can be created manually (separately) by running make in the the hw/ area.

Stimulus strategy

Test sequences

All test sequences reside in hw/ip/rv_timer/dv/env/seq_lib. The rv_timer_base_vseq virtual sequence is extended from cip_base_vseq and serves as a starting point. All test sequences are extended from rv_timer_base_vseq. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. Some of the most commonly used tasks / functions are as follows:

  • cfg_timer : set a particular timer active or inactive
  • cfg_hart : set timer step and prescale values
  • intr_state_spinwait : poll a intr_status randomly until it reads the expected value
  • status_read_for_clks : read intr_status register randomly for num clks

Functional coverage

To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:

  • timer_cfg_cg : cover group define bins for timer config parameters
  • timer_active_cg : cover group define bin all timers active at same time

Self-checking strategy

Scoreboard

The rv_timer_scoreboard is primarily used for end to end checking. It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:

  • tl_a_chan_fifo: tl address channel
  • tl_d_chan_fifo: tl data channel

rv_timer scoreboard monitors all CSR registers and interrupt pins.

For a write transaction, during the address channel, CSR values are updated in RAL and config values (timer enable, step, prescale, timer value, compare value) are updated in internal arrays. When particular timer is enabled, rv_timer scoreboard calculate timeout clocks and start a thread to wait for timeout, then if any of timer configuration updated on active timer, rv_timer scoreboard recalculate and update the timeout clocks in ther running timeout thread. If multiple timers are enabled, multipe threads will be initiated. On timeout scoreboard calculate the expected interrupt status and update RAL registers.

For a read transaction, during the address channel for interrupt status CSR rv_timer will predict its value according to the timer timeout threads. During the data channel, rv_timer scoreboard will compare the read data with expected data in RAL.

Interrupt pins are checked against expected at every read/write data channel.

Assertions

  • TLUL assertions: The tb/rv_timer_bind.sv binds the tlul_assert assertions to the IP to ensure TileLink interface protocol compliance
  • Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset

Building and running tests

We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here's how to run a basic sanity test:

$ cd hw/ip/rv_timer/dv
$ make TEST_NAME=rv_timer_sanity

Testplan

Milestone Name Description Tests
V1 sanity <p>Basic rv_timer sanity test perform following steps for number of iterations</p> <ul> <li>Program zero to CTRL.active* Register(deactivate timer)</li> <li>Program random legal values in CFG*, TIMER_V_<em>, COMPARE_</em>, INTR_ENABLE*</li> <li>Program one to CTRL.active* (activate timer)</li> <li>Wait for number of cycles to have mTime&gt;= mTimeCmp</li> <li>Check Interrupt state register and Interrupt signal (scoreboard logic)</li> </ul> rv_timer_sanity<br>
V1 csr_hw_reset <p>Verify the reset values as indicated in the RAL specification.</p> <ul> <li>Write all CSRs with a random value.</li> <li>Apply reset to the DUT as well as the RAL model.</li> <li>Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.</li> <li>It is mandatory to run this test for all available interfaces the CSRs are accessible from.</li> <li>Shuffle the list of CSRs first to remove the effect of ordering.</li> </ul> rv_timer_csr_hw_reset<br>
V1 csr_rw <p>Verify accessibility of CSRs as indicated in the RAL specification.</p> <ul> <li>Loop through each CSR to write it with a random value.</li> <li>Read the CSR back and check for correctness while adhering to its access policies.</li> <li>It is mandatory to run this test for all available interfaces the CSRs are accessible from.</li> <li>Shuffle the list of CSRs first to remove the effect of ordering.</li> </ul> rv_timer_csr_rw<br>
V1 csr_bit_bash <p>Verify no aliasing within individual bits of a CSR.</p> <ul> <li>Walk a 1 through each CSR by flipping 1 bit at a time.</li> <li>Read the CSR back and check for correctness while adhering to its access policies.</li> <li>This verify that writing a specific bit within the CSR did not affect any of the other bits.</li> <li>It is mandatory to run this test for all available interfaces the CSRs are accessible from.</li> <li>Shuffle the list of CSRs first to remove the effect of ordering.</li> </ul> rv_timer_csr_bit_bash<br>
V1 csr_aliasing <p>Verify no aliasing within the CSR address space.</p> <ul> <li>Loop through each CSR to write it with a random value</li> <li>Shuffle and read ALL CSRs back.</li> <li>All CSRs except for the one that was written in this iteration should read back the previous value.</li> <li>The CSR that was written in this iteration is checked for correctness while adhering to its access policies.</li> <li>It is mandatory to run this test for all available interfaces the CSRs are accessible from.</li> <li>Shuffle the list of CSRs first to remove the effect of ordering.</li> </ul> rv_timer_csr_aliasing<br>
V1 csr_mem_rw_with_rand_reset<p>Verify random reset during CSR/memory access.</p> <ul> <li>Run csr_rw sequence to randomly access CSRs</li> <li>If memory exists, run mem_partial_access in parallel with csr_rw</li> <li>Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value</li> <li>It is mandatory to run this test for all available interfaces the CSRs are accessible from.</li> </ul> rv_timer_csr_mem_rw_with_rand_reset<br>
V2 random_reset <p>This test is to exercise on the fly reset(timer is active)</p> <ul> <li>Assert reset randomly in the middle of sanity test steps</li> <li>Scoreboard check for all register go back to reset value</li> </ul> rv_timer_random_reset<br>
V2 disabled <p>This test to verify no activity in mTime, Interrupt Status, Interrupt signal, When all timers are deactive (ctrl.active = 0).</p> <ul> <li>Program 1 in interrupt enable and 0 in control register and random value for rest of the registers</li> <li>Scoreboard check for no activity and no interrupt whatever is setting</li> </ul> rv_timer_disabled<br>
V2 cfg_update_on_fly <p>This test will verify update timer configuration on running timer.</p> <ul> <li>Program timer.Active to zero</li> <li>Program random values in interrrupt enable, prescaler, step, mtime and mtime cmp</li> <li>After some clocks update timer config values</li> <li>Check for interrupt as per new config set</li> </ul> rv_timer_cfg_update_on_fly<br>
V2 no_interrupt_test <p>This test will update timer value and compare value just before timer is going to expire (multiple times) and verify no interrupt is asserted</p> <ul> <li>Program timer.Active to zero</li> <li>Program random values in interrrupt enable, prescaler, step, mtime and mtime cmp</li> <li>Update timer config values just before timer is about to expire</li> <li>Check for no interrupt set</li> </ul> rv_timer_cfg_update_on_fly<br>
V2 stress <p>Do combinations of multiple of above scenarios to get multiple interrupts asserted at the same time. Scoreboard should be robust enough to deal with all scenarios.</p> rv_timer_stress_all<br>
V2 intr_test <p>Verify common intr_test CSRs that allows SW to mock-inject interrupts.</p> <ul> <li>Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).</li> <li>Randomly &quot;turn on&quot; interrupts by writing random value(s) to intr_test CSR(s).</li> <li>Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.</li> <li>Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.</li> <li>Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).</li> <li>Repeat the above steps a bunch of times.</li> </ul> rv_timer_intr_test<br>
V2 stress_all_with_rand_reset<p>This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.</p> rv_timer_stress_all_with_rand_reset<br>
V2 oob_addr_access <p>Access out of bounds address and verify correctness of response / behavior</p>rv_timer_tl_errors<br>
V2 illegal_access <p>Drive unsupported requests via TL interface and verify correctness of response / behavior</p> rv_timer_tl_errors<br>
V2 outstanding_access <p>Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.</p> rv_timer_csr_hw_reset<br> rv_timer_csr_rw<br> rv_timer_csr_aliasing<br> rv_timer_same_csr_outstanding<br>
V2 partial_access <p>Do partial accesses.</p> rv_timer_csr_hw_reset<br> rv_timer_csr_rw<br> rv_timer_csr_aliasing<br>