SPI Device HWIP Technical Specification

Overview

Features

  • Single-bit wide SPI device interface implementing a raw data transfer protocol termed “Firmware Operation Mode”
    • No address bits, data is sent and received from peripheral pins to/from an internal buffer
    • Intended to be used to bulk-load data into and out of the chip
    • Not intended to support EEPROM or other addressing modes (functionality to come in later versions)
  • Supports clock polarity and reverse bit order configurations
  • Flexible RX/TX Buffer size within an SRAM range
  • Interrupts for RX/TX SRAM FIFO conditions (empty, full, designated level for RX, TX)

Description

The SPI device module is a serial-to-parallel receive (RX) and parallel-to-serial transmit (TX) full duplex design (single line mode) used to communicate with an outside host. This first version of the module supports operations controlled by firmware to dump incoming single-line RX data (SDI) to an internal RX buffer, and send data from a transmit buffer to single-line TX output (SDO). The clock for the peripheral data transfer uses the SPI peripheral pin SCK. In this design the SCK is directly used to drive the interface logic as its primary clock, which has performance benefits, but incurs design complications described later.

Compatibility

The SPI device doesn’t support emulating an EEPROM as of this initial version.

Theory of Operations

Block Diagram

Block Diagram

The block diagram above shows how the SPI Device IP converts incoming bit-serialized SDI data into a valid byte, where the data bit is valid when the chip select signal (CSB) is 0 (active low) and SCK is at positive or negative edge (configurable, henceforth called the “active edge”). The bit order within the byte is determined by CFG.rx_order configuration register field. After a byte is gathered, the interface module writes the byte data into a small FIFO (“RXFIFO”) using SCK. It is read out of the FIFO and written into to the buffer SRAM (“DP_SRAM”) using the system bus clock. If RXFIFO is full, this is an error condition and the interface module discards the byte.

The interface module also serializes data from the small transmit FIFO (“TXFIFO”) and shifts it out on the SDO pin when CSB is 0 and SCK is at the active edge. The bit order within the byte can be configured with configuration register field CFG.tx_order. It is expected that software has prepared TX data based on the description in the “Defining Firmware Operation Mode” section below. Since SCK is not under the control of software or the device (it is driven by the external SPI host), it is possible that there is no data ready in the TXFIFO when chip select becomes active and the interface needs to send data on the SDO pin. Either software has not prepared TX data or software does not care about the contents of the TX data - then the hardware will send whatever lingering data is in the empty TXFIFO. If this is a functional issue, then software should at least soft-reset the contents of the TXFIFO using the CONTROL.rst_txfifo register. The soft-reset signal is not synchronized to the SCK clock, so software should drive the reset signal when the SPI interface is idle.

Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module SPI_DEVICE has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: scan_clk_i

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO:

Pin namedirectionDescription
sckinput

SPI Clock

csbinput

Chip Enable#

sd[3:0]inout

SPI IO, IO2/IO3 has multi-purpose (/WP, /HOLD)

Interrupts:

Interrupt NameDescription
rxf

RX SRAM FIFO Full

rxlvl

RX SRAM FIFO is above the level

txlvl

TX SRAM FIFO is under the level

rxerr

SDI in FwMode has error

rxoverflow

RX Async FIFO overflow

txunderflow

TX Async FIFO underflow

Security Alerts: none

General Data Transfer on Pins

Data transfers with the SPI device module involve four peripheral SPI pins: SCK, CSB, SDI, SDO. SCK is the SPI clock driven by an external SPI host. CSB (chip select bar) is an active low enable signal that frames a transfer, driven by the external host. Transfers with active SCK edges but inactive (high) CSB are ignored. Data is driven into the SPI device on the SDI pin (“Serial Data In”, though we’re otherwise using host/device terminology) and driven out on SDO. Any transfer length is legal, though higher level protocols typically assume word width boundaries. See details on protocols and transfers that follow. The diagram below shows a typical transfer, here for 8 bytes (64 cycles, showing the beginning and end of the transfer). Configurability for active edges, polarities, and bit orders are described later.

Defining “Firmware Operation Mode”

Firmware operation mode, as implemented by this SPI device, is used to bulk copy data in and out of the chip using the pins as shown above. In general, it is used to load firmware into the chip, but can be used for any data transfer into or out of the chip. The transfers are “generic” in the sense that there is no addressing or overarching protocol involved. Data transferred into the chip goes into a SPI Device circular buffer implemented in an SRAM, and firmware decides what to do with the data. Data transferred out of the chip comes out of a circular buffer in an SRAM. Software can build any number of higher level protocols on top of this basic mechanism. All transfers are by definition full duplex: whenever an active SCK edge is received, a bit of RX data is latched into the peripheral, and a bit of TX data is sent out of the peripheral. If transfers only require unidirectional movement of data, the other direction can be ignored but will still be active. For instance, if only receive data is needed in the transfer, the device will still be transmitting data out on the TX (“SDO”) pin.

SPI Generic Protocol

The primary protocol considered is one used by an external SPI host to send chunks of firmware data into the device in the receive direction, confirming the contents with an echo back of a hash of the received data in the transmit direction. This is generally termed the ‘SPI Generic’ protocol, since SPI is used to send firmware into device memory, brokered by software confirming integrity of the received firmware data. This special case will be described first, and then a generic understanding of how firmware mode operates will follow.

The following diagram shows the expected data transfer in SPI Generic mode.

data transfer in SPI Device

In this diagram, bursts of data transfer are shown as “pages” of firmware content being driven into the device. The size of the page is not relevant, though it must be less than the size of the internal SPI Device SRAM. Typically the SRAM is divided in half for RX and TX buffers, but the boundary is configurable. The total size of RX and TX buffer must fit in the SPI device SRAM. Since the external SPI Host is in charge of the clock (SCK), it controls all aspects of the transfer, including the size of the page. But it is done in coordination with software running on the device that manages the higher level protocol.

The protocol assumes that for each page written into the device, a response will be prepared for the next page. But since the SPI Device is always transmitting during every received page, the first transmitted page can be ignored. After the first page is received, software will get alerted as to its completion (via an RX interrupt), and will execute whatever integrity check is required on that data. It can then prepare its response to page zero by writing into the SPI Device TX buffer. What it writes into the TX buffer the concern of the higher level protocol. It could be a “good” indication, a full echo of the RX data, or a hash of the received contents. The decision is not in scope for this specification.

Clearly there is a potential race condition here as a new page could begin to be received before software has prepared the transmit response to page zero (including the time to read data out of the SRAM), but that is a condition that the higher level protocol must prepare for. That protocol is not in scope for this document, but some hints to its implementation are given in the programmers guide section below.

The transfer continues until all received data is taken in, and responded back. In this protocol the last “received” page of data is a “don’t care” as long as the response is transmitted successfully.

Firmware Operation Mode

Taking this example as a guide, we can see the general method of the SPI Firmware Operation Mode. On every active SCK clock edge, data is received from the SDI pin into the SPI device, and data is transmitted on the SDO pin. Received data is gathered into bytes and written into the RX circular buffer in the SPI Device SRAM as it is accumulated. Whatever data exists in the TX circular buffer is serialized and transmitted. Transfers are framed using the active low chip select pin SCB. What happens when data arrives and the RX circular buffer is full, or when the transmitter encounters an empty TX circular buffer are error conditions discussed in the Design Details section that follows.

RXFIFO, TXFIFO, and DP_SRAM

The relationship between the Dual Port SRAM (DP_SRAM) and the RX and TXFIFOs should be explained. The SRAM is divided into a section for the transmit direction, named TXF, and a section for the receive direction, named RXF. Each section has its own read and write pointer. The SRAM may be read and written by software at any time, but for correct normal operation it will only write the empty area of the TXF (between the write pointer and read pointer) and only read the full area of the RXF (between the read pointer and write pointer) with the other areas used by the hardware. It is first worth noting that the hardware implications of the asynchronous nature of SCK and the fact it may not be free running, complicate some of the logic. The full feature set of that interface logic (clocked by SCK) includes the serial to parallel converter for RX data, the parallel-to-serial converter for TX data, and the interfaces to RXFIFO and TXFIFO. Before the first bit transfer and after the last SCK is stopped, there is no clock for any of this logic. So for instance there is no guarantee of the two-clock-edges normally required for asynchronous handshaking protocols. The RXFIFO and TXFIFO exist to facilitate this situation.

In the receive direction, data gathered from the SDI pin is written into the RXFIFO (see details below) at appropriate size boundaries. This data is handshake-received on the core clock side, gathered into byte or word quantity, and written into the RX circular buffer of the dual-port SRAM. On each write, the RXF write pointer (RXF_PTR.wptr) is incremented by hardware, wrapping at the size of the circular buffer. Software can watch (via polling or interrupts) the incrementing of this write pointer to determine how much valid data has been received, and determine when and what data to act upon. Once it has acted upon data, the software should update the RXF read pointer to indicate that space in the SRAM is available for future writes by the hardware. If incrementing the write pointer would result in it becoming equal to the read pointer then the RXF is full and any subsequently received data will be discarded. Thus in normal operation, the RXF write pointer is updated automatically by hardware and the RXF read pointer is managed by software. As an optimization the hardware will normally only write to the 32-bit wide SRAM when an entire word can be written. Since the end of the received data may not be aligned, there is a timer that forces sub-word writes if data has been staged for too long. The timer value (CFG.timer_v) represents the number of core clock cycles. For instance, if timer value is configured in 0xFF, the RXF control logic will write gathered sub-word data in 255 cycles if no further bit stream from SPI is received.

In the transmit direction, things are a little more tricky. Since the pin interface logic begins transmitting data on its very first SCK edge, there are no previous clock edges in the interface side of the fifo to allow an empty flag to be updated. The interface must blindly take whatever data is at the read pointer of the TXFIFO (in a typical asynchronous FIFO with free-running clocks the pointers can always be sent across the asynchronous boundary to determine if the FIFO is truly empty or not). Hence the need to potentially send out garbage data if software has not prepared the TXFIFO in time.

The software writes data that it wants to transmit into the TXF circular buffer of the DP_SRAM buffer. It then passes the data to the hardware by moving the TXF write pointer to point to the next location after the data (this is the location it will use to start the data for the next transmission). Hardware that manages the TXFIFO detects the change in TXF write pointer and begins reading from the SRAM and prefilling the TXFIFO until it is full or until all valid TXF data has been read. This prepares the TXFIFO with the desired data for when the next SCK data arrives. As the SCK domain logic pulls data out of the TXFIFO to transmit on the SDO pin, that TXFIFO read is detected (after synchronization to the core clock domain) and potentially another word of data is read from the SRAM and written into the TXFIFO. Each time the SRAM is read the hardware increments the TXF read pointer making the space available to software. Like above, though conversely, in normal operation the TXF write pointer is managed completely by software and the TXF read pointer is incremented by hardware.

All reads and writes to/from the SRAM for RXF and TXF activity are managed by direct reads and writes through the TLUL bus interface, managed by the auto-generated register file control logic.

Design Details

Clock and Phase

The SPI device module has two programmable register bits to control the SPI clock, CFG.CPOL and CFG.CPHA. CPOL controls clock polarity and CPHA controls the clock phase. For further details, please refer to this diagram from Wikipedia: File:SPI_timing_diagram2.svg

SPI Device Firmware Operation Mode

As described in the Theory of Operations above, in this mode, the SPI device writes incoming data directly into the SRAM (through RXFIFO) and updates the SPI device SRAM write pointer (RXF_PTR.wptr). It does not parse a command byte nor address bytes, analyzing incoming data relies on firmware implementation of a higher level protocol. Data is sent from the TXF SRAM contents via TXFIFO.

It is important that the data path inside the block should meet the timing that is a half cycle of SCK. As SCK clock is shut off right after the last bit of the last byte is received, the hardware module cannot register the SDI signal. The module registers bits [7:1] and combines them with the SDI signal directly to form the input to RXFIFO. This is detailed in the waveform below.

As shown above, the RXFIFO write request signal (RX_WEN) is asserted when BitCount reaches 0h. Bitcount is reset by CSB asynchronously, returning to 7h for the next round. RXFIFO input data changes on the half clock cycle. RXFIFO latches WEN at the positive edge of SCK. When BitCount is 0h, bit 0 of FIFO data shows the bit 1 value for the first half clock cycle then shows correct value once the incoming SDI value is updated.

TXFIFO is similar. TX_REN is asserted when Tx BitCount reaches 1, and the current entry of TXFIFO is popped at the negative edge of SCK. It results in a change of SDO value at the negative edge of SCK. SDO_OE is controlled by the CSB signal. If CSB goes to high, SDO is returned to High-Z state.

Note that in the SPI mode 3 configuration (CFG.CPOL=1, CFG.CPHA=1), the logic isn’t able to pop the entry from the TX async FIFO after the last bit in the last byte of a transaction. In mode 3, no further SCK edge is given after sending the last bit before the CSB de-assertion. The design is chosen to pop the entry at the 7th bit position. This introduces unavoidable behavior of dropping the last byte if CSB is de-asserted before a byte transfer is completed. If CSB is de-asserted in bit 1 to 6 position, the FIFO entry isn’t popped. TX logic will re-send the byte in next transaction. If CSB is de-asserted in the 7th or 8th bit position, the data is dropped and will re-commence with the next byte in the next transaction.

RXFIFO control

RXF CTRL State Machine

The RXFIFO Control module controls data flow from RXFIFO to SRAM. It connects two FIFOs having different data widths. RXFIFO is byte width, SRAM storing incoming data to serve FW is TL-UL interface width.

To reduce traffic to SRAM, the control logic gathers FIFO entries up to full SRAM data width, then does a full-word SRAM write. A programmable timer exists in the case when partial bytes are received at the end of a transfer. If the timer expires while bytes are still in the RXFIFO, the logic writes partial words to SRAM. A read-modify-write operation is triggered to perform the partial update.

State Machine

TXFIFO control

The TXFIFO control module reads data from SRAM then pushes to TXFIFO whenever there is space in TXFIFO and when the TXF wptr and rptr indicate there is data to transmit. Data is written into the TXF SRAM by software which also controls the TXF write pointer.

TXF CTRL Data Path

The TXFIFO control module latches the write pointer then uses it internally. This prevents HW from using incorrect data from SRAM if the write pointer and read pointer are pointing at the same location. It is recommended for the software to update the write pointer at the SRAM data width granularity if it has more than 1 DWord data to send out. If software updates write pointer every byte, HW tries to fetch data from SRAM every time it hits the write pointer leading to inefficiency of SRAM access.

If TXFIFO is empty, HW module repeatedly sends current entry of TXFIFO output as explained in “Theory of Operations” section. It cannot use an empty signal from TXFIFO due to asynchronous timing constraints.

So, if software wants to send specific dummy data, it should prepare the amount of data with that value. As shown in the Theory Of Operations figure, for example, internal software could prepare FFh values for first page.

State Machine

Data Storage Sizes

SPI Device IP uses a 2kB internal Dual-Port SRAM. Firmware can resize RX / TX circular buffers within the SRAM size. For example, the firmware is able to set RX circular buffer to be 1.5kB and 512B for TX circular buffer.

To increase SRAM size, the SramAw local parameter in spi_device.sv should be changed. It cannot exceed 13 (32kB) due to the read and write pointers' widths.

Programmers Guide

Initialization

By default, RX SRAM FIFO base and limit address (via RXF_ADDR register) are set to 0x0 and 0x1FC, 512 bytes. And TX SRAM FIFO base and limit addresses (in the TXF_ADDR register) are 0x200 and 0x3FC. If FW wants bigger spaces, it can change the values of the above registers RXF_ADDR and TXF_ADDR.

Software can configure the timer value CFG.timer_v to change the delay between partial DATA received from SPI interface being written into the SRAM. The value of the field is the number of the core clock cycles that the logic waits for.

Pointers

RX / TX SRAM FIFO has read and write pointers, RXF_PTR and TXF_PTR . Those pointers are used to manage circular FIFOs inside the SRAM. The pointer width in the register description is 16 bit but the number of valid bits in the pointers depends on the size of the SRAM.

The current SRAM size is 2kB and the pointer width is 12 bits, 11bits representing a byte offset and 1 most-significant bit for indicating phase of the FIFO. Since they represent bytes, the low 2 bits indicate the offset within the 32-bit wide SRAM word. The pointers indicate the offset into the area described by the base and limit values, so the lower bits (11 bits in this case) of a pointer should not exceed the size in bytes (4 * (limit address - base address)) reserved for the region (RXF or TXF) that the pointer is in. For instance, if FW sets RXFIFO depth to 128 (default value), it should not update the read pointer outside the range 0x000 - 0x1FF (128*4 = 512Bytes ignoring the phase bit, bit 11).

Device Interface Functions (DIFs)

To use this DIF, include the following C header:

#include "sw/device/lib/dif/dif_spi_device.h"

This header provides the following device interface functions:

Register Table

SPI_DEVICE.INTR_STATE @ 0x0

Interrupt State Register

Reset default = 0x0, mask 0x3f
31302928272625242322212019181716
 
1514131211109876543210
  txunderflow rxoverflow rxerr txlvl rxlvl rxf
BitsTypeResetNameDescription
0rw1c0x0rxf

RX SRAM FIFO Full

1rw1c0x0rxlvl

RX SRAM FIFO is above the level

2rw1c0x0txlvl

TX SRAM FIFO is under the level

3rw1c0x0rxerr

SDI in FwMode has error

4rw1c0x0rxoverflow

RX Async FIFO overflow

5rw1c0x0txunderflow

TX Async FIFO underflow


SPI_DEVICE.INTR_ENABLE @ 0x4

Interrupt Enable Register

Reset default = 0x0, mask 0x3f
31302928272625242322212019181716
 
1514131211109876543210
  txunderflow rxoverflow rxerr txlvl rxlvl rxf
BitsTypeResetNameDescription
0rw0x0rxf

Enable interrupt when INTR_STATE.rxf is set.

1rw0x0rxlvl

Enable interrupt when INTR_STATE.rxlvl is set.

2rw0x0txlvl

Enable interrupt when INTR_STATE.txlvl is set.

3rw0x0rxerr

Enable interrupt when INTR_STATE.rxerr is set.

4rw0x0rxoverflow

Enable interrupt when INTR_STATE.rxoverflow is set.

5rw0x0txunderflow

Enable interrupt when INTR_STATE.txunderflow is set.


SPI_DEVICE.INTR_TEST @ 0x8

Interrupt Test Register

Reset default = 0x0, mask 0x3f
31302928272625242322212019181716
 
1514131211109876543210
  txunderflow rxoverflow rxerr txlvl rxlvl rxf
BitsTypeResetNameDescription
0wo0x0rxf

Write 1 to force INTR_STATE.rxf to 1.

1wo0x0rxlvl

Write 1 to force INTR_STATE.rxlvl to 1.

2wo0x0txlvl

Write 1 to force INTR_STATE.txlvl to 1.

3wo0x0rxerr

Write 1 to force INTR_STATE.rxerr to 1.

4wo0x0rxoverflow

Write 1 to force INTR_STATE.rxoverflow to 1.

5wo0x0txunderflow

Write 1 to force INTR_STATE.txunderflow to 1.


SPI_DEVICE.CONTROL @ 0xc

Control register

Reset default = 0x80000000, mask 0x80030031
31302928272625242322212019181716
sram_clk_en   rst_rxfifo rst_txfifo
1514131211109876543210
  MODE   ABORT
BitsTypeResetNameDescription
0rw0x0ABORT

Abort pending jobs. If TX_FIFO (async) is full, this command can let TXF Control logic back to Idle state

3:1Reserved
5:4rwxMODE

SPI Device operation mode. Currently only FwMode is supported.

0fwmode

FW operation mode.

HW just dumps incoming data to SRAM and reads from SRAM and sends to SDO. This mode doesn't support Dual or Quad mode

Other values are reserved.

15:6Reserved
16rw0x0rst_txfifo

Reset Async TX_FIFO.

This only resets asynchronous fifo. If firmware wants to reset SRAM FIFO, it should write 0 into read/write pointers.

_Note_: This value should be controlled only when SPI interface is in Idle state as this reset signal doesn't have reset synchronizer.

17rw0x0rst_rxfifo

Reset Async RX_FIFO.

This only resets asynchronous fifo. If firmware wants to reset SRAM FIFO, it should write 0 into read pointer and write pointer.

_Note_: This value should be controlled only when SPI interface is in Idle state as this reset signal doesn't have reset synchronizer.

30:18Reserved
31rw0x1sram_clk_en

SRAM Clock Enable.

This controls the clock gating cell lying on DP SRAM clock. As the nature of absent of SPI_CLK in idle state, the clock mux for SRAM B port cannot be glitch-free MUX. So, it is up to SW to change the clock safely.

Programming sequence:

1. Check if SPI line is idle 2. Clear sram_clk_en to 0. 3. Change mode to FwMode for peri clk, FlashMode or PassThrough for SPI_CLK. 4. Set sram_clk_en to 1.


SPI_DEVICE.CFG @ 0x10

Configuration Register

Reset default = 0x7f00, mask 0x1ff0f
31302928272625242322212019181716
  addr_4b_en
1514131211109876543210
timer_v   rx_order tx_order CPHA CPOL
BitsTypeResetNameDescription
0rw0x0CPOL

Clock polarity. 0 for normal SPI, 1 for negative edge latch

1rw0x0CPHA

Data phase. 0 for negative edge change, 1 for positive edge change

2rw0x0tx_order

TX bit order on SDO. 0 for MSB to LSB, 1 for LSB to MSB

3rw0x0rx_order

RX bit order on SDI. Module stores bitstream from MSB to LSB if value is 0.

7:4Reserved
15:8rw0x7ftimer_v

number of clocks for RXF to wait.

To reduce traffic to SRAM, RXF control module waits given clock cycle if it doesn't fill SRAM data width even if Async RX FIFO is empty.

16rwxaddr_4b_en

4B Address Mode enable.

This field configures the internal module to receive 32 bits of the SPI commands. The affected commands are the SPI read commands except QPI, and program commands.

Even though Read SFDP command has address fields, the SFDP command is not affected by this field. The command always parse 24 bits on the SPI line 0 following the SPI command as the address field.


SPI_DEVICE.FIFO_LEVEL @ 0x14

RX/ TX FIFO levels.

Reset default = 0x80, mask 0xffffffff
31302928272625242322212019181716
txlvl
1514131211109876543210
rxlvl
BitsTypeResetNameDescription
15:0rw0x80rxlvl

RX FIFO level.

If RX SRAM FIFO level exceeds this value, it triggers interrupt.

31:16rw0x0txlvl

TX FIFO level.

If TX SRAM FIFO level drops below this value, it triggers interrupt.


SPI_DEVICE.ASYNC_FIFO_LEVEL @ 0x18

RX/ TX Async FIFO levels between main clk and spi clock

Reset default = 0x0, mask 0xff00ff
31302928272625242322212019181716
  txlvl
1514131211109876543210
  rxlvl
BitsTypeResetNameDescription
7:0roxrxlvl

RX Async FIFO level.

This value shows the number of available entry in RX Async FIFO.

15:8Reserved
23:16roxtxlvl

TX Async FIFO level.

This value shows the number of available entry in TX Async FIFO. If the software writes message into SRAM FIFO and update FIFO write pointer but no clock from the host is given, the data stuck at this async fifo waiting host toggles SCK. This value represents the number of bytes.


SPI_DEVICE.STATUS @ 0x1c

SPI Device status register

Reset default = 0x3a, mask 0x3f
31302928272625242322212019181716
 
1514131211109876543210
  csb abort_done txf_empty txf_full rxf_empty rxf_full
BitsTypeResetNameDescription
0roxrxf_full

RX FIFO full

1ro0x1rxf_empty

RX FIFO empty

2roxtxf_full

TX FIFO full

3ro0x1txf_empty

TX FIFO empty

4ro0x1abort_done

Abort process is completed

5ro0x1csb

Direct input of CSb signal


SPI_DEVICE.RXF_PTR @ 0x20

Receiver FIFO (SRAM) pointers

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
WPTR
1514131211109876543210
RPTR
BitsTypeResetNameDescription
15:0rw0x0RPTR

Read pointer. bit x is for phase bit. check circular fifo description

31:16ro0x0WPTR

Write pointer. Bit x is phase bit.


SPI_DEVICE.TXF_PTR @ 0x24

Transmitter FIFO (SRAM) pointers

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
WPTR
1514131211109876543210
RPTR
BitsTypeResetNameDescription
15:0ro0x0RPTR

Read pointer. bit x is for phase bit. check circular fifo description

31:16rw0x0WPTR

Write pointer. Bit x is phase bit.


SPI_DEVICE.RXF_ADDR @ 0x28

Receiver FIFO (SRAM) Addresses

Reset default = 0x1fc0000, mask 0xffffffff
31302928272625242322212019181716
limit
1514131211109876543210
base
BitsTypeResetNameDescription
15:0rw0x0base

Base offset in bytes in the SRAM. Lower 2 bits are ignored.

31:16rw0x1fclimit

Limit offset in bytes in the SRAM. Lower 2 bits are ignored.


SPI_DEVICE.TXF_ADDR @ 0x2c

Transmitter FIFO (SRAM) Addresses

Reset default = 0x3fc0200, mask 0xffffffff
31302928272625242322212019181716
limit
1514131211109876543210
base
BitsTypeResetNameDescription
15:0rw0x200base

Base offset in bytes in the SRAM. Lower 2 bits are ignored.

31:16rw0x3fclimit

Limit offset in bytes in the SRAM. Lower 2 bits are ignored.


SPI_DEVICE.CMD_FILTER_0 @ 0x30

Command Filter

Reset default = 0x0, mask 0xffffffff

If a bit in this CSR is 1, then corresponding SPI command w.r.t the bit position among 256 bit is dropped in SPI Passthrough mode.

31302928272625242322212019181716
filter_31 filter_30 filter_29 filter_28 filter_27 filter_26 filter_25 filter_24 filter_23 filter_22 filter_21 filter_20 filter_19 filter_18 filter_17 filter_16
1514131211109876543210
filter_15 filter_14 filter_13 filter_12 filter_11 filter_10 filter_9 filter_8 filter_7 filter_6 filter_5 filter_4 filter_3 filter_2 filter_1 filter_0
BitsTypeResetNameDescription
0rw0x0filter_0

If 1, command will be filtered

1rw0x0filter_1

If 1, command will be filtered

2rw0x0filter_2

If 1, command will be filtered

3rw0x0filter_3

If 1, command will be filtered

4rw0x0filter_4

If 1, command will be filtered

5rw0x0filter_5

If 1, command will be filtered

6rw0x0filter_6

If 1, command will be filtered

7rw0x0filter_7

If 1, command will be filtered

8rw0x0filter_8

If 1, command will be filtered

9rw0x0filter_9

If 1, command will be filtered

10rw0x0filter_10

If 1, command will be filtered

11rw0x0filter_11

If 1, command will be filtered

12rw0x0filter_12

If 1, command will be filtered

13rw0x0filter_13

If 1, command will be filtered

14rw0x0filter_14

If 1, command will be filtered

15rw0x0filter_15

If 1, command will be filtered

16rw0x0filter_16

If 1, command will be filtered

17rw0x0filter_17

If 1, command will be filtered

18rw0x0filter_18

If 1, command will be filtered

19rw0x0filter_19

If 1, command will be filtered

20rw0x0filter_20

If 1, command will be filtered

21rw0x0filter_21

If 1, command will be filtered

22rw0x0filter_22

If 1, command will be filtered

23rw0x0filter_23

If 1, command will be filtered

24rw0x0filter_24

If 1, command will be filtered

25rw0x0filter_25

If 1, command will be filtered

26rw0x0filter_26

If 1, command will be filtered

27rw0x0filter_27

If 1, command will be filtered

28rw0x0filter_28

If 1, command will be filtered

29rw0x0filter_29

If 1, command will be filtered

30rw0x0filter_30

If 1, command will be filtered

31rw0x0filter_31

If 1, command will be filtered


SPI_DEVICE.CMD_FILTER_1 @ 0x34

Command Filter

Reset default = 0x0, mask 0xffffffff

If a bit in this CSR is 1, then corresponding SPI command w.r.t the bit position among 256 bit is dropped in SPI Passthrough mode.

31302928272625242322212019181716
filter_63 filter_62 filter_61 filter_60 filter_59 filter_58 filter_57 filter_56 filter_55 filter_54 filter_53 filter_52 filter_51 filter_50 filter_49 filter_48
1514131211109876543210
filter_47 filter_46 filter_45 filter_44 filter_43 filter_42 filter_41 filter_40 filter_39 filter_38 filter_37 filter_36 filter_35 filter_34 filter_33 filter_32
BitsTypeResetNameDescription
0rw0x0filter_32

For SPI_DEVICE1

1rw0x0filter_33

For SPI_DEVICE1

2rw0x0filter_34

For SPI_DEVICE1

3rw0x0filter_35

For SPI_DEVICE1

4rw0x0filter_36

For SPI_DEVICE1

5rw0x0filter_37

For SPI_DEVICE1

6rw0x0filter_38

For SPI_DEVICE1

7rw0x0filter_39

For SPI_DEVICE1

8rw0x0filter_40

For SPI_DEVICE1

9rw0x0filter_41

For SPI_DEVICE1

10rw0x0filter_42

For SPI_DEVICE1

11rw0x0filter_43

For SPI_DEVICE1

12rw0x0filter_44

For SPI_DEVICE1

13rw0x0filter_45

For SPI_DEVICE1

14rw0x0filter_46

For SPI_DEVICE1

15rw0x0filter_47

For SPI_DEVICE1

16rw0x0filter_48

For SPI_DEVICE1

17rw0x0filter_49

For SPI_DEVICE1

18rw0x0filter_50

For SPI_DEVICE1

19rw0x0filter_51

For SPI_DEVICE1

20rw0x0filter_52

For SPI_DEVICE1

21rw0x0filter_53

For SPI_DEVICE1

22rw0x0filter_54

For SPI_DEVICE1

23rw0x0filter_55

For SPI_DEVICE1

24rw0x0filter_56

For SPI_DEVICE1

25rw0x0filter_57

For SPI_DEVICE1

26rw0x0filter_58

For SPI_DEVICE1

27rw0x0filter_59

For SPI_DEVICE1

28rw0x0filter_60

For SPI_DEVICE1

29rw0x0filter_61

For SPI_DEVICE1

30rw0x0filter_62

For SPI_DEVICE1

31rw0x0filter_63

For SPI_DEVICE1


SPI_DEVICE.CMD_FILTER_2 @ 0x38

Command Filter

Reset default = 0x0, mask 0xffffffff

If a bit in this CSR is 1, then corresponding SPI command w.r.t the bit position among 256 bit is dropped in SPI Passthrough mode.

31302928272625242322212019181716
filter_95 filter_94 filter_93 filter_92 filter_91 filter_90 filter_89 filter_88 filter_87 filter_86 filter_85 filter_84 filter_83 filter_82 filter_81 filter_80
1514131211109876543210
filter_79 filter_78 filter_77 filter_76 filter_75 filter_74 filter_73 filter_72 filter_71 filter_70 filter_69 filter_68 filter_67 filter_66 filter_65 filter_64
BitsTypeResetNameDescription
0rw0x0filter_64

For SPI_DEVICE2

1rw0x0filter_65

For SPI_DEVICE2

2rw0x0filter_66

For SPI_DEVICE2

3rw0x0filter_67

For SPI_DEVICE2

4rw0x0filter_68

For SPI_DEVICE2

5rw0x0filter_69

For SPI_DEVICE2

6rw0x0filter_70

For SPI_DEVICE2

7rw0x0filter_71

For SPI_DEVICE2

8rw0x0filter_72

For SPI_DEVICE2

9rw0x0filter_73

For SPI_DEVICE2

10rw0x0filter_74

For SPI_DEVICE2

11rw0x0filter_75

For SPI_DEVICE2

12rw0x0filter_76

For SPI_DEVICE2

13rw0x0filter_77

For SPI_DEVICE2

14rw0x0filter_78

For SPI_DEVICE2

15rw0x0filter_79

For SPI_DEVICE2

16rw0x0filter_80

For SPI_DEVICE2

17rw0x0filter_81

For SPI_DEVICE2

18rw0x0filter_82

For SPI_DEVICE2

19rw0x0filter_83

For SPI_DEVICE2

20rw0x0filter_84

For SPI_DEVICE2

21rw0x0filter_85

For SPI_DEVICE2

22rw0x0filter_86

For SPI_DEVICE2

23rw0x0filter_87

For SPI_DEVICE2

24rw0x0filter_88

For SPI_DEVICE2

25rw0x0filter_89

For SPI_DEVICE2

26rw0x0filter_90

For SPI_DEVICE2

27rw0x0filter_91

For SPI_DEVICE2

28rw0x0filter_92

For SPI_DEVICE2

29rw0x0filter_93

For SPI_DEVICE2

30rw0x0filter_94

For SPI_DEVICE2

31rw0x0filter_95

For SPI_DEVICE2


SPI_DEVICE.CMD_FILTER_3 @ 0x3c

Command Filter

Reset default = 0x0, mask 0xffffffff

If a bit in this CSR is 1, then corresponding SPI command w.r.t the bit position among 256 bit is dropped in SPI Passthrough mode.

31302928272625242322212019181716
filter_127 filter_126 filter_125 filter_124 filter_123 filter_122 filter_121 filter_120 filter_119 filter_118 filter_117 filter_116 filter_115 filter_114 filter_113 filter_112
1514131211109876543210
filter_111 filter_110 filter_109 filter_108 filter_107 filter_106 filter_105 filter_104 filter_103 filter_102 filter_101 filter_100 filter_99 filter_98 filter_97 filter_96
BitsTypeResetNameDescription
0rw0x0filter_96

For SPI_DEVICE3

1rw0x0filter_97

For SPI_DEVICE3

2rw0x0filter_98

For SPI_DEVICE3

3rw0x0filter_99

For SPI_DEVICE3

4rw0x0filter_100

For SPI_DEVICE3

5rw0x0filter_101

For SPI_DEVICE3

6rw0x0filter_102

For SPI_DEVICE3

7rw0x0filter_103

For SPI_DEVICE3

8rw0x0filter_104

For SPI_DEVICE3

9rw0x0filter_105

For SPI_DEVICE3

10rw0x0filter_106

For SPI_DEVICE3

11rw0x0filter_107

For SPI_DEVICE3

12rw0x0filter_108

For SPI_DEVICE3

13rw0x0filter_109

For SPI_DEVICE3

14rw0x0filter_110

For SPI_DEVICE3

15rw0x0filter_111

For SPI_DEVICE3

16rw0x0filter_112

For SPI_DEVICE3

17rw0x0filter_113

For SPI_DEVICE3

18rw0x0filter_114

For SPI_DEVICE3

19rw0x0filter_115

For SPI_DEVICE3

20rw0x0filter_116

For SPI_DEVICE3

21rw0x0filter_117

For SPI_DEVICE3

22rw0x0filter_118

For SPI_DEVICE3

23rw0x0filter_119

For SPI_DEVICE3

24rw0x0filter_120

For SPI_DEVICE3

25rw0x0filter_121

For SPI_DEVICE3

26rw0x0filter_122

For SPI_DEVICE3

27rw0x0filter_123

For SPI_DEVICE3

28rw0x0filter_124

For SPI_DEVICE3

29rw0x0filter_125

For SPI_DEVICE3

30rw0x0filter_126

For SPI_DEVICE3

31rw0x0filter_127

For SPI_DEVICE3


SPI_DEVICE.CMD_FILTER_4 @ 0x40

Command Filter

Reset default = 0x0, mask 0xffffffff

If a bit in this CSR is 1, then corresponding SPI command w.r.t the bit position among 256 bit is dropped in SPI Passthrough mode.

31302928272625242322212019181716
filter_159 filter_158 filter_157 filter_156 filter_155 filter_154 filter_153 filter_152 filter_151 filter_150 filter_149 filter_148 filter_147 filter_146 filter_145 filter_144
1514131211109876543210
filter_143 filter_142 filter_141 filter_140 filter_139 filter_138 filter_137 filter_136 filter_135 filter_134 filter_133 filter_132 filter_131 filter_130 filter_129 filter_128
BitsTypeResetNameDescription
0rw0x0filter_128

For SPI_DEVICE4

1rw0x0filter_129

For SPI_DEVICE4

2rw0x0filter_130

For SPI_DEVICE4

3rw0x0filter_131

For SPI_DEVICE4

4rw0x0filter_132

For SPI_DEVICE4

5rw0x0filter_133

For SPI_DEVICE4

6rw0x0filter_134

For SPI_DEVICE4

7rw0x0filter_135

For SPI_DEVICE4

8rw0x0filter_136

For SPI_DEVICE4

9rw0x0filter_137

For SPI_DEVICE4

10rw0x0filter_138

For SPI_DEVICE4

11rw0x0filter_139

For SPI_DEVICE4

12rw0x0filter_140

For SPI_DEVICE4

13rw0x0filter_141

For SPI_DEVICE4

14rw0x0filter_142

For SPI_DEVICE4

15rw0x0filter_143

For SPI_DEVICE4

16rw0x0filter_144

For SPI_DEVICE4

17rw0x0filter_145

For SPI_DEVICE4

18rw0x0filter_146

For SPI_DEVICE4

19rw0x0filter_147

For SPI_DEVICE4

20rw0x0filter_148

For SPI_DEVICE4

21rw0x0filter_149

For SPI_DEVICE4

22rw0x0filter_150

For SPI_DEVICE4

23rw0x0filter_151

For SPI_DEVICE4

24rw0x0filter_152

For SPI_DEVICE4

25rw0x0filter_153

For SPI_DEVICE4

26rw0x0filter_154

For SPI_DEVICE4

27rw0x0filter_155

For SPI_DEVICE4

28rw0x0filter_156

For SPI_DEVICE4

29rw0x0filter_157

For SPI_DEVICE4

30rw0x0filter_158

For SPI_DEVICE4

31rw0x0filter_159

For SPI_DEVICE4


SPI_DEVICE.CMD_FILTER_5 @ 0x44

Command Filter

Reset default = 0x0, mask 0xffffffff

If a bit in this CSR is 1, then corresponding SPI command w.r.t the bit position among 256 bit is dropped in SPI Passthrough mode.

31302928272625242322212019181716
filter_191 filter_190 filter_189 filter_188 filter_187 filter_186 filter_185 filter_184 filter_183 filter_182 filter_181 filter_180 filter_179 filter_178 filter_177 filter_176
1514131211109876543210
filter_175 filter_174 filter_173 filter_172 filter_171 filter_170 filter_169 filter_168 filter_167 filter_166 filter_165 filter_164 filter_163 filter_162 filter_161 filter_160
BitsTypeResetNameDescription
0rw0x0filter_160

For SPI_DEVICE5

1rw0x0filter_161

For SPI_DEVICE5

2rw0x0filter_162

For SPI_DEVICE5

3rw0x0filter_163

For SPI_DEVICE5

4rw0x0filter_164

For SPI_DEVICE5

5rw0x0filter_165

For SPI_DEVICE5

6rw0x0filter_166

For SPI_DEVICE5

7rw0x0filter_167

For SPI_DEVICE5

8rw0x0filter_168

For SPI_DEVICE5

9rw0x0filter_169

For SPI_DEVICE5

10rw0x0filter_170

For SPI_DEVICE5

11rw0x0filter_171

For SPI_DEVICE5

12rw0x0filter_172

For SPI_DEVICE5

13rw0x0filter_173

For SPI_DEVICE5

14rw0x0filter_174

For SPI_DEVICE5

15rw0x0filter_175

For SPI_DEVICE5

16rw0x0filter_176

For SPI_DEVICE5

17rw0x0filter_177

For SPI_DEVICE5

18rw0x0filter_178

For SPI_DEVICE5

19rw0x0filter_179

For SPI_DEVICE5

20rw0x0filter_180

For SPI_DEVICE5

21rw0x0filter_181

For SPI_DEVICE5

22rw0x0filter_182

For SPI_DEVICE5

23rw0x0filter_183

For SPI_DEVICE5

24rw0x0filter_184

For SPI_DEVICE5

25rw0x0filter_185

For SPI_DEVICE5

26rw0x0filter_186

For SPI_DEVICE5

27rw0x0filter_187

For SPI_DEVICE5

28rw0x0filter_188

For SPI_DEVICE5

29rw0x0filter_189

For SPI_DEVICE5

30rw0x0filter_190

For SPI_DEVICE5

31rw0x0filter_191

For SPI_DEVICE5


SPI_DEVICE.CMD_FILTER_6 @ 0x48

Command Filter

Reset default = 0x0, mask 0xffffffff

If a bit in this CSR is 1, then corresponding SPI command w.r.t the bit position among 256 bit is dropped in SPI Passthrough mode.

31302928272625242322212019181716
filter_223 filter_222 filter_221 filter_220 filter_219 filter_218 filter_217 filter_216 filter_215 filter_214 filter_213 filter_212 filter_211 filter_210 filter_209 filter_208
1514131211109876543210
filter_207 filter_206 filter_205 filter_204 filter_203 filter_202 filter_201 filter_200 filter_199 filter_198 filter_197 filter_196 filter_195 filter_194 filter_193 filter_192
BitsTypeResetNameDescription
0rw0x0filter_192

For SPI_DEVICE6

1rw0x0filter_193

For SPI_DEVICE6

2rw0x0filter_194

For SPI_DEVICE6

3rw0x0filter_195

For SPI_DEVICE6

4rw0x0filter_196

For SPI_DEVICE6

5rw0x0filter_197

For SPI_DEVICE6

6rw0x0filter_198

For SPI_DEVICE6

7rw0x0filter_199

For SPI_DEVICE6

8rw0x0filter_200

For SPI_DEVICE6

9rw0x0filter_201

For SPI_DEVICE6

10rw0x0filter_202

For SPI_DEVICE6

11rw0x0filter_203

For SPI_DEVICE6

12rw0x0filter_204

For SPI_DEVICE6

13rw0x0filter_205

For SPI_DEVICE6

14rw0x0filter_206

For SPI_DEVICE6

15rw0x0filter_207

For SPI_DEVICE6

16rw0x0filter_208

For SPI_DEVICE6

17rw0x0filter_209

For SPI_DEVICE6

18rw0x0filter_210

For SPI_DEVICE6

19rw0x0filter_211

For SPI_DEVICE6

20rw0x0filter_212

For SPI_DEVICE6

21rw0x0filter_213

For SPI_DEVICE6

22rw0x0filter_214

For SPI_DEVICE6

23rw0x0filter_215

For SPI_DEVICE6

24rw0x0filter_216

For SPI_DEVICE6

25rw0x0filter_217

For SPI_DEVICE6

26rw0x0filter_218

For SPI_DEVICE6

27rw0x0filter_219

For SPI_DEVICE6

28rw0x0filter_220

For SPI_DEVICE6

29rw0x0filter_221

For SPI_DEVICE6

30rw0x0filter_222

For SPI_DEVICE6

31rw0x0filter_223

For SPI_DEVICE6


SPI_DEVICE.CMD_FILTER_7 @ 0x4c

Command Filter

Reset default = 0x0, mask 0xffffffff

If a bit in this CSR is 1, then corresponding SPI command w.r.t the bit position among 256 bit is dropped in SPI Passthrough mode.

31302928272625242322212019181716
filter_255 filter_254 filter_253 filter_252 filter_251 filter_250 filter_249 filter_248 filter_247 filter_246 filter_245 filter_244 filter_243 filter_242 filter_241 filter_240
1514131211109876543210
filter_239 filter_238 filter_237 filter_236 filter_235 filter_234 filter_233 filter_232 filter_231 filter_230 filter_229 filter_228 filter_227 filter_226 filter_225 filter_224
BitsTypeResetNameDescription
0rw0x0filter_224

For SPI_DEVICE7

1rw0x0filter_225

For SPI_DEVICE7

2rw0x0filter_226

For SPI_DEVICE7

3rw0x0filter_227

For SPI_DEVICE7

4rw0x0filter_228

For SPI_DEVICE7

5rw0x0filter_229

For SPI_DEVICE7

6rw0x0filter_230

For SPI_DEVICE7

7rw0x0filter_231

For SPI_DEVICE7

8rw0x0filter_232

For SPI_DEVICE7

9rw0x0filter_233

For SPI_DEVICE7

10rw0x0filter_234

For SPI_DEVICE7

11rw0x0filter_235

For SPI_DEVICE7

12rw0x0filter_236

For SPI_DEVICE7

13rw0x0filter_237

For SPI_DEVICE7

14rw0x0filter_238

For SPI_DEVICE7

15rw0x0filter_239

For SPI_DEVICE7

16rw0x0filter_240

For SPI_DEVICE7

17rw0x0filter_241

For SPI_DEVICE7

18rw0x0filter_242

For SPI_DEVICE7

19rw0x0filter_243

For SPI_DEVICE7

20rw0x0filter_244

For SPI_DEVICE7

21rw0x0filter_245

For SPI_DEVICE7

22rw0x0filter_246

For SPI_DEVICE7

23rw0x0filter_247

For SPI_DEVICE7

24rw0x0filter_248

For SPI_DEVICE7

25rw0x0filter_249

For SPI_DEVICE7

26rw0x0filter_250

For SPI_DEVICE7

27rw0x0filter_251

For SPI_DEVICE7

28rw0x0filter_252

For SPI_DEVICE7

29rw0x0filter_253

For SPI_DEVICE7

30rw0x0filter_254

For SPI_DEVICE7

31rw0x0filter_255

For SPI_DEVICE7


SPI_DEVICE.ADDR_SWAP_MASK @ 0x50

Address Swap Mask register.

Reset default = 0x0, mask 0xffffffff

This register is used in the SPI passthrough mode. If any of bits in this register is set, the corresponding address bit in the SPI Read commands is replaced with the data from ADDR_SWAP_DATA.

If 3B address mode is active, upper 8bit [31:24] is ignored.

31302928272625242322212019181716
mask...
1514131211109876543210
...mask
BitsTypeResetNameDescription
31:0rw0x0mask

When a bit is 1, the SPI read address to the downstream SPI Flash device is swapped to ADDR_SWAP_DATA.


SPI_DEVICE.ADDR_SWAP_DATA @ 0x54

The address value for the address swap feature.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
data...
1514131211109876543210
...data
BitsTypeResetNameDescription
31:0rw0x0data

Desired value to be swapped for the SPI read commands.


SPI_DEVICE.buffer @ + 0x1000
1024 item rw window
Byte writes are not supported
310
+0x1000 
+0x1004 
 ...
+0x1ff8 
+0x1ffc 

SPI internal buffer.

In Generic mode, this buffer is used for RX/TX buffer. In Flash & Passthrough mode, lower 2kB is for Read content emulating eFlash. next 1kB is for Mailbox read/write buffer. The rest is 64B of CmdFIFO, 64B of AddrFIFO, and 256B of payload FIFO.