SPI Device HWIP Technical Specification

Overview

Features

SPI Generic Mode

  • Single-bit wide SPI device interface implementing a raw data transfer protocol termed “Firmware Operation Mode”
    • No address bits, data is sent and received from peripheral pins to/from an internal buffer
    • Intended to be used to bulk-load data into and out of the chip
    • Not intended to support EEPROM or other addressing modes (functionality to come in later versions)
  • Supports clock polarity and reverse bit order configurations
  • Flexible RX/TX Buffer size within an SRAM range
  • Interrupts for RX/TX SRAM FIFO conditions (empty, full, designated level for RX, TX)

SPI Flash/ Passthrough Modes

  • Support Serial Flash emulation
    • HW processed Read Status, Read JEDEC ID, Read SFDP, EN4B/ EX4B, and multiple read commands
    • 16 depth Command/ Address FIFOs and 256B Payload buffer for command upload
    • 2x 1kB read buffer for read commands
    • 1kB mailbox buffer and configurable mailbox target address
  • Support SPI passthrough
    • Filtering of inadmissible commands (256-bit filter CSR)
    • Address translation for read commands
    • First 4B payload translation
    • HW control of SPI PADs' output enable based on command information list
    • SW configurable internal command process for Read Status, Read JEDEC ID, Read SFDP, and read access to the mailbox space
    • Targets 33MHz @ Quad read mode, fall backs to 25MHz
  • Automated tracking of 3B/ 4B address mode in the flash and passthrough modes
  • 24 entries of command information slots
    • Configurable address/ dummy/ payload size per opcode

TPM over SPI

  • In compliance with TPM PC Client Platform
  • up to 64B compile-time configurable read and write data buffer (default: 4B)
  • 1 TPM command (8b) and 1 address (24bit) buffer
  • HW controlled wait state
  • Shared SPI with other SPI Device functionalities. Unique CS# for the TPM
    • Flash or Passthrough mode can be active with TPM mode. Generic and TPM modes are mutually exclusive.
  • HW processed registers for the read requests
    • TPM_ACCESS_x, TPM_STS_x, TPM_INTF_CAPABILITY, TPM_INT_ENABLE, TPM_INT_STATUS, TPM_INT_VECTOR, TPM_DID_VID, TPM_RID
    • TPM_HASH_START returns FFh
  • 5 Locality (compile-time parameter)

Description

The SPI device module consists of four functions, the generic mode, SPI Flash mode, SPI passthrough mode, and TPM over SPI mode.

The SPI generic mode is a serial-to-parallel receive (RX) and parallel-to-serial transmit (TX) full duplex design (single line mode) used to communicate with an outside host. This first version of the module supports operations controlled by firmware to dump incoming single-line RX data (SDI) to an internal RX buffer, and send data from a transmit buffer to single-line TX output (SDO). The clock for the peripheral data transfer uses the SPI peripheral pin SCK. In this design the SCK is directly used to drive the interface logic as its primary clock, which has performance benefits, but incurs design complications described later.

The SW can receive TPM commands with payload (address and data) and respond to the read commands with the return data using the TPM submodule in the SPI_DEVICE HWIP. The submodule provides the command, address, write, and read FIFOs for the SW to communicate with the TPM host system. The submodule also supports the SW by managing a certain set of the FIFO registers and returning the read request by HW quickly.

In Flash mode, SPI Device HWIP behaves as a Serial Flash device by recognizing SPI Flash commands and processing those commands by HW. The commands processed by HW are Read Status (1, 2, 3), Read JEDEC ID, Read SFDP, EN4B/ EX4B, and read commands with aid of SW. The IP supports Normal Read, Fast Read, Fast Read Dual Output, Fast Read Quad Output. This version of IP does not support Dual IO, Quad IO, QPI commands.

In Passthrough mode, SPI Device receives SPI transactions from a host system and forwards the transactions to a downstream flash device. SW may filter prohibited commands by configuring 256-bit FILTER CSR. The IP cancels ongoing transaction if the received opcode matches to the filter CSR by de-asserting CSb and gating SCK to the downstream flash device.

SW may program CSRs to change the address and/or the first 4 bytes of payload on-the-fly in Passthrough mode. The address translation feature allows SW to maintain A/B binary images without aids of the host system. The payload translation may be used to change the payload of Write Status commands to not allow certain fields to be modified.

In Passthrough mode, parts of the Flash modules can be active. While in Passthrough mode, SW may configure the IP to process certain commands internally. SW is recommended to filter the commands being processed internally. Mailbox is an exception as it shares the Read command opcode.

SPI Device Modes and Active Submodules

SPI Device HWIP has three modes + TPM mode, which are “Generic” mode (also known as FwMode), “Flash” mode, and “Passthrough” mode. Generic mode is exclusive. Flash and Passthrough modes share many parts of the datapath. TPM mode only shares the SPI and has separate CSb port, which allows that the host sends TPM commands while other SPI mode is active (except Generic mode).

Mode FwMode Status JEDEC SFDP Mailbox Read Addr4B Upload Passthrough
Generic Y
Flash Y Y Y Y Y Y Y
Passthru Y/N Y/N Y/N Y/N N Y Y Y

Y/N: Based on INTERCEPT_EN

Compatibility

The SPI device supports emulating an EEPROM (SPI flash mode in this document). The TPM submodule conforms to the TPM over SPI 2.0 specification. The TPM operation follows TCG PC Client Platform TPM Profile Specification Section 7.

Theory of Operations

Block Diagram

Block Diagram

In Generic mode, the incoming data is stored byte-based into an asynchronous FIFO. The logic inside the generic mode then updates the DPSRAM RX space. The logic also reads data from the DPSRAM then pushes out to the SPI MISO line.

The Generic mode uses the entire DPSRAM space exclusively. The TX/RX size in the DPSRAM can be changed by compile-time parameters.

When Flash mode is selected, the command parser accepts the first byte of the SPI MOSI line then activates the flash submodules, such as Status, JEDEC, Read command, and Upload function. The Status logic processes the three Read Status commands. The SW may configure three bytes of the Flash Status CSR then the Status submodule returns the CSR data into the SPI MISO line. The SW may configure the Read Status commands' opcodes.

The JEDEC submodule returns the JEDEC Manufacturer ID followed by the additional information. The Manufacturer ID may vary depending on the company. For example, lowRISC JEDEC ID EFh follows twelve bytes of 7Fh Continuous Codes, requiring a total thirteen bytes for the manufacturer ID. The SW may configure how many Continuous Codes is needed and the actual manufacturer ID.

The Read submodule processes the Read SFDP (Serial Flash Discoverable Parameters) command, and up to six different types of the read commands. The read submodule receives address information from the SPI transaction, fetches the data from the read buffer in the DPSRAM, and returns the data on SPI lines (single, dual, quad lines). If the received address falls into the SW programmable mailbox address space, the logic fetches data not from the read buffer but from the mailbox buffer in the DPSRAM.

SW may configure command information slots to upload the command into the FIFOs and the payload buffer in the DPSRAM. SW may additionally let HW to set the BUSY bit in the Status register when the HW uploads the command.

In Passthrough mode, the logic filters the incoming transaction if the transaction is not permitted. The SW may configure the logic to change a portion of the address or first 4 bytes of the payload.

Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module SPI_DEVICE has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: scan_clk_i

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO:

Pin namedirectionDescription
sckinput

SPI Clock

csbinput

Chip Select#

tpm_csbinput

TPM Chip Select#

sd[3:0]inout

SPI IO, IO2/IO3 has multi-purpose (/WP, /HOLD)

Inter-Module Signals: Reference

Inter-Module Signals
Port Name Package::Struct Type Act Width Description
ram_cfg prim_ram_2p_pkg::ram_2p_cfg uni rcv 1
passthrough spi_device_pkg::passthrough req_rsp req 1
mbist_en logic uni rcv 1
sck_monitor logic uni req 1
tl tlul_pkg::tl req_rsp rsp 1

Interrupts:

Interrupt NameDescription
generic_rx_full

RX SRAM FIFO Full

generic_rx_watermark

RX SRAM FIFO is above the level

generic_tx_watermark

TX SRAM FIFO is under the level

generic_rx_error

SDI in FwMode has error

generic_rx_overflow

RX Async FIFO overflow

generic_tx_underflow

TX Async FIFO underflow

upload_cmdfifo_not_empty

Upload Command FIFO is not empty

upload_payload_not_empty

Upload payload is not empty.

The event occurs after SPI transaction completed

upload_payload_overflow

Upload payload overflow event.

When a SPI Host system issues a command with payload more than 256B, this event is reported. When it happens, SW should read the last written payload index CSR to figure out the starting address of the last 256B.

readbuf_watermark

Read Buffer Threshold event.

The host system accesses greater than or equal to the threshold of a buffer.

readbuf_flip

Read buffer flipped event.

The host system accesses other side of buffer.

tpm_header_not_empty

TPM Header(Command/Address) buffer available

Security Alerts:

Alert NameDescription
fatal_fault

This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures:

Countermeasure IDDescription
SPI_DEVICE.BUS.INTEGRITY

End-to-end bus integrity scheme.

The TPM submodule requires a separate input port for CS#. The TPM submodule and other SPI Device modes are able to be active together. The host system distinguishes between the TPM transactions and the other SPI transactions using separate CS# ports. Even though both submodules are able to be active, the host system cannot issue a TPM command and a SPI transaction at the same time due to the SPI IO lines being shared.

The TPM has no write FIFO interrupt. As TPM transactions are not bigger than 4B in current usage case, the waiting time of the core is not a concern. The core takes multiple cycles to pop a byte from the write FIFO due to the slower peripheral clock and multiple CDC paths. The gain of having write FIFO interrupt is not great.

SPI Device Generic mode

Generic Mode Block Diagram

The block diagram above shows how the SPI Device generic mode converts incoming bit-serialized SDI data into a valid byte, where the data bit is valid when the chip select signal (CSB) is 0 (active low) and SCK is at positive or negative edge (configurable, henceforth called the “active edge”). The bit order within the byte is determined by CFG.rx_order configuration register field. After a byte is gathered, the interface module writes the byte data into a small FIFO (“RXFIFO”) using SCK. It is read out of the FIFO and written into to the buffer SRAM (“DP_SRAM”) using the system bus clock. If RXFIFO is full, this is an error condition and the interface module discards the byte.

The interface module also serializes data from the small transmit FIFO (“TXFIFO”) and shifts it out on the SDO pin when CSB is 0 and SCK is at the active edge. The bit order within the byte can be configured with configuration register field CFG.tx_order. It is expected that software has prepared TX data based on the description in the “Defining Firmware Operation Mode” section below. Since SCK is not under the control of software or the device (it is driven by the external SPI host), it is possible that there is no data ready in the TXFIFO when chip select becomes active and the interface needs to send data on the SDO pin. Either software has not prepared TX data or software does not care about the contents of the TX data - then the hardware will send whatever lingering data is in the empty TXFIFO. If this is a functional issue, then software should at least soft-reset the contents of the TXFIFO using the CONTROL.rst_txfifo register. The soft-reset signal is not synchronized to the SCK clock, so software should drive the reset signal when the SPI interface is idle.

General Data Transfer on Pins

Data transfers with the SPI device module involve four peripheral SPI pins: SCK, CSB, SDI, SDO. SCK is the SPI clock driven by an external SPI host. CSB (chip select bar) is an active low enable signal that frames a transfer, driven by the external host. Transfers with active SCK edges but inactive (high) CSB are ignored. Data is driven into the SPI device on the SDI pin (“Serial Data In”, though we’re otherwise using host/device terminology) and driven out on SDO. Any transfer length is legal, though higher level protocols typically assume word width boundaries. See details on protocols and transfers that follow. The diagram below shows a typical transfer, here for 8 bytes (64 cycles, showing the beginning and end of the transfer). Configurability for active edges, polarities, and bit orders are described later.

Defining “Firmware Operation Mode”

Firmware operation mode, as implemented by this SPI device, is used to bulk copy data in and out of the chip using the pins as shown above. In general, it is used to load firmware into the chip, but can be used for any data transfer into or out of the chip. The transfers are “generic” in the sense that there is no addressing or overarching protocol involved. Data transferred into the chip goes into a SPI Device circular buffer implemented in an SRAM, and firmware decides what to do with the data. Data transferred out of the chip comes out of a circular buffer in an SRAM. Software can build any number of higher level protocols on top of this basic mechanism. All transfers are by definition full duplex: whenever an active SCK edge is received, a bit of RX data is latched into the peripheral, and a bit of TX data is sent out of the peripheral. If transfers only require unidirectional movement of data, the other direction can be ignored but will still be active. For instance, if only receive data is needed in the transfer, the device will still be transmitting data out on the TX (“SDO”) pin.

SPI Generic Protocol

The primary protocol considered is one used by an external SPI host to send chunks of firmware data into the device in the receive direction, confirming the contents with an echo back of a hash of the received data in the transmit direction. This is generally termed the ‘SPI Generic’ protocol, since SPI is used to send firmware into device memory, brokered by software confirming integrity of the received firmware data. This special case will be described first, and then a generic understanding of how firmware mode operates will follow.

The following diagram shows the expected data transfer in SPI Generic mode.

data transfer in SPI Device

In this diagram, bursts of data transfer are shown as “pages” of firmware content being driven into the device. The size of the page is not relevant, though it must be less than the size of the internal SPI Device SRAM. Typically the SRAM is divided in half for RX and TX buffers, but the boundary is configurable. The total size of RX and TX buffer must fit in the SPI device SRAM. Since the external SPI Host is in charge of the clock (SCK), it controls all aspects of the transfer, including the size of the page. But it is done in coordination with software running on the device that manages the higher level protocol.

The protocol assumes that for each page written into the device, a response will be prepared for the next page. But since the SPI Device is always transmitting during every received page, the first transmitted page can be ignored. After the first page is received, software will get alerted as to its completion (via an RX interrupt), and will execute whatever integrity check is required on that data. It can then prepare its response to page zero by writing into the SPI Device TX buffer. What it writes into the TX buffer the concern of the higher level protocol. It could be a “good” indication, a full echo of the RX data, or a hash of the received contents. The decision is not in scope for this specification.

Clearly there is a potential race condition here as a new page could begin to be received before software has prepared the transmit response to page zero (including the time to read data out of the SRAM), but that is a condition that the higher level protocol must prepare for. That protocol is not in scope for this document, but some hints to its implementation are given in the programmers guide section below.

The transfer continues until all received data is taken in, and responded back. In this protocol the last “received” page of data is a “don’t care” as long as the response is transmitted successfully.

Firmware Operation Mode

Taking this example as a guide, we can see the general method of the SPI Firmware Operation Mode. On every active SCK clock edge, data is received from the SDI pin into the SPI device, and data is transmitted on the SDO pin. Received data is gathered into bytes and written into the RX circular buffer in the SPI Device SRAM as it is accumulated. Whatever data exists in the TX circular buffer is serialized and transmitted. Transfers are framed using the active low chip select pin SCB. What happens when data arrives and the RX circular buffer is full, or when the transmitter encounters an empty TX circular buffer are error conditions discussed in the Design Details section that follows.

RXFIFO, TXFIFO, and DP_SRAM

The relationship between the Dual Port SRAM (DP_SRAM) and the RX and TXFIFOs should be explained. The SRAM is divided into a section for the transmit direction, named TXF, and a section for the receive direction, named RXF. Each section has its own read and write pointer. The SRAM may be read and written by software at any time, but for correct normal operation it will only write the empty area of the TXF (between the write pointer and read pointer) and only read the full area of the RXF (between the read pointer and write pointer) with the other areas used by the hardware. It is first worth noting that the hardware implications of the asynchronous nature of SCK and the fact it may not be free running, complicate some of the logic. The full feature set of that interface logic (clocked by SCK) includes the serial to parallel converter for RX data, the parallel-to-serial converter for TX data, and the interfaces to RXFIFO and TXFIFO. Before the first bit transfer and after the last SCK is stopped, there is no clock for any of this logic. So for instance there is no guarantee of the two-clock-edges normally required for asynchronous handshaking protocols. The RXFIFO and TXFIFO exist to facilitate this situation.

In the receive direction, data gathered from the SDI pin is written into the RXFIFO (see details below) at appropriate size boundaries. This data is handshake-received on the core clock side, gathered into byte or word quantity, and written into the RX circular buffer of the dual-port SRAM. On each write, the RXF write pointer ( RXF_PTR.wptr) is incremented by hardware, wrapping at the size of the circular buffer. Software can watch (via polling or interrupts) the incrementing of this write pointer to determine how much valid data has been received, and determine when and what data to act upon. Once it has acted upon data, the software should update the RXF read pointer to indicate that space in the SRAM is available for future writes by the hardware. If incrementing the write pointer would result in it becoming equal to the read pointer then the RXF is full and any subsequently received data will be discarded. Thus in normal operation, the RXF write pointer is updated automatically by hardware and the RXF read pointer is managed by software. As an optimization the hardware will normally only write to the 32-bit wide SRAM when an entire word can be written. Since the end of the received data may not be aligned, there is a timer that forces sub-word writes if data has been staged for too long. The timer value ( CFG.timer_v) represents the number of core clock cycles. For instance, if timer value is configured in 0xFF, the RXF control logic will write gathered sub-word data in 255 cycles if no further bit stream from SPI is received.

In the transmit direction, things are a little more tricky. Since the pin interface logic begins transmitting data on its very first SCK edge, there are no previous clock edges in the interface side of the fifo to allow an empty flag to be updated. The interface must blindly take whatever data is at the read pointer of the TXFIFO (in a typical asynchronous FIFO with free-running clocks the pointers can always be sent across the asynchronous boundary to determine if the FIFO is truly empty or not). Hence the need to potentially send out garbage data if software has not prepared the TXFIFO in time.

The software writes data that it wants to transmit into the TXF circular buffer of the DP_SRAM buffer. It then passes the data to the hardware by moving the TXF write pointer to point to the next location after the data (this is the location it will use to start the data for the next transmission). Hardware that manages the TXFIFO detects the change in TXF write pointer and begins reading from the SRAM and prefilling the TXFIFO until it is full or until all valid TXF data has been read. This prepares the TXFIFO with the desired data for when the next SCK data arrives. As the SCK domain logic pulls data out of the TXFIFO to transmit on the SDO pin, that TXFIFO read is detected (after synchronization to the core clock domain) and potentially another word of data is read from the SRAM and written into the TXFIFO. Each time the SRAM is read the hardware increments the TXF read pointer making the space available to software. Like above, though conversely, in normal operation the TXF write pointer is managed completely by software and the TXF read pointer is incremented by hardware.

All reads and writes to/from the SRAM for RXF and TXF activity are managed by direct reads and writes through the TLUL bus interface, managed by the auto-generated register file control logic.

SPI Flash and Passthrough Modes

Command Information List

The SW may configure the map from the received opcode to the command process module by programming cmd_info list. Current SPI_DEVICE provides 24 command information entries. Each entry represents a command. Details of the fields are explained in the CMD_INFO_0

First 11 commands are assigned to specific submodules.

Index Assigned Submodule
[2:0] Read Status
[3] Read JEDEC ID
[4] Read SFDP
[10:5] Read commands

If the IP is in flash mode or in passthrough mode with INTERCEPT_EN set, other than opcode and valid fields in the command information entries are ignored for Read Status and Read JEDEC ID commands. The submodules directly return data on the MISO line (SD[1]). In Passthrough mode, if Read Status and Read JEDEC ID commands are intercepted by the internal HW, the other fields in the command information entries are ignored also.

The main use of the fields other than opcode and valid is to control the output enable in the passthrough logic. See Output Enable Control section for more.

upload and busy fields are used in the SPI Flash/ Passthrough modes. See Command Upload section for details.

Command Parser

Command Parser block

Command parser (cmdparse) processes the first byte of the SPI and activates the processing submodules depending on the received opcode and the cmd_info list described in the previous section.

The cmdparse compares the received opcode with the cmd_info.opcode data structure. If any entry matches to the received opcode, the cmdparse hands over the matched command information entry with the index to the corresponding submodule. As explained in the previous section, the command parser checks the index to activate Read Status / Read JEDEC ID/ Read Command / Address 4B modules. Other than the first 11 slots and last two slots (the last two slots are not visible to SW), the cmdparse checks the upload field and activates the upload module if the field is set.

SW can configure whether a submodule should process the command while in the passthrough mode by setting the INTERCEPT_EN CSR.

Status Control

If the received command is one of the three read status commands, STATUS control module takes over the SPI interface after the opcode. The 3 bytes status register is not reset by CSb. Except BUSY bit and WEL bit, other bits are controlled by SW.

BUSY bit is set by HW when it receives any commands that are uploaded to the FIFOs and their busy fields are 1 in the command information entry. SW may clear BUSY bit when it completes the received commands (e.g Erase/ Program).

If BUSY is set, SPI_DEVICE IP blocks the passthrough interface in Passthrough mode. The blocking of the interface occurs in SPI transaction idle state (CSb == 1). When SW clears the BUSY bit, it is applied to the STATUS register in the SPI clock domain when SPI clock toggles. It means the update happens when the next SPI transaction is received. The BUSY bit in the CSR is the synchronized value of the STATUS BUSY bit in the SPI clock domain. Due to the CDC latency, SW may see the updated value (BUSY clear) with long delay.

WEL bit can be controlled by SW and also by HW. HW updates WEL bit when it receives WREN(06h) or WRDI(04h) commands. The opcode can be configured via CMD_INFO_WREN and CMD_INFO_WRDI.

The SW update of the STATUS register via FLASH_STATUS is not instantaneous. The IP stores the SW request into the asynchronous FIFO then the request is processed in the SPI clock domain. The request updates the temporal status register, which is called as staged registers in the design. The staged registers are latched into the committed registers when CSb is released. SW sees the committed registers when reading the FLASH_STATUS CSR.

The attached host system also reads back the committed registers via Read Status commands. This scheme is to guarantee the atomicity of the STATUS register.

If the host sends the Write Status commands, the commands are not processed in this module. SW must configure the remaining command information entries to upload the Write Status commands to the FIFOs.

JEDEC ID Control

JEDEC module returns JEDEC Device ID and Manufacturer ID following the Continuation Code (CC). SW may configure JEDEC_CC CSR for HW to return proper CC. The cc field in JEDEC_CC defines the return value, which is 0x7F by default. num_cc defines how many times the HW to send CC byte before sending the JEDEC ID.

The actual JEDEC ID consists of one byte manufacturer ID and two bytes device ID. The HW sends the manufacturer ID first, then [7:0] of the device ID then [15:8] byte.

Serial Flash Discoverable Parameters (SFDP) Control

HW parses SFDP command then fetch the data from SFDP space in the DPSRAM. HW provides 256B SFDP space. HW uses lower 8bit of the received 24 bit address to access the DPSRAM. Upper 16 bits are ignored (aliased). SW should prepare proper SFDP contents before the host system issues SFDP commands.

HW fetches from the DPSRAM in 4B and returns the data to the SPI line. HW repeats the operation until CSb is de-asserted.

Read Command Processor

The read command block has multiple sub-blocks to process normal Read, Fast Read, Fast Read Dual/ Quad from the internal DPSRAM. The DPSRAM has a 2kB region for the read command access. The read command region has two 1kB buffers. If HW receives the read access to the other half of the space first time, then the HW reports to the SW to refill the current 1kB region with new content.

The double buffering scheme aids the SW to prepare the next chunk of data. SW copies a portion of data (1kB) from the internal flash memory into SPI_DEVICE DPSRAM. From the host system, the emulated SPI Device is seen more than 2kB storage device with the double buffering scheme. The assumption is that the host system reads mostly sequentially.

Address Handling

For read commands such as Normal Read, Fast Read {Single/ Dual/ Quad} Output commands, the address comes through ID0 only. The state machine in this block shifts the address one-by-one and decrements the address counter register by 1.

When it reaches the 4B address (addr[2]), the module triggers the DPSRAM state machine to fetch data from the DPSRAM. When the module receives addr[0], at the positive edge of SCK, the module moves to appropriate command state based on the given CMD_INFO data.

If the received address falls into mailbox address range and mailbox feature is enabled, the module turns on the mailbox selection bit. Then all out-going requests to the DPSRAM are forwarded to the mailbox section, not the read buffer section.

Dummy Cycle

The SW may configure the dummy cycle field for each individual read commands. The default dummy cycle for those commands are 7 (0-based). The value is the number of cycles. For example, if SW programs the dummy cycle for Fast Read Quad to 3h, the module waits 4 cycles then returns data.

Buffer Management

Read Buffer Management

The SPI Device IP uses the first half of the DPSRAM as a read buffer when the SPI mode is flash or passthrough mode. The IP returns data from the read buffer based on the given address in the received read command. In the current version, the read buffer size is 2kB. The IP only uses lower 11 bits of the received read command address (addr[10:0]) to issue the read requests to the DPSRAM.

SW is responsible for updating the read buffer contents. The HW notifies the SW to update the buffer contents when needed. The HW provides a SW configurable read watermark CSR and read-only LAST_READ_ADDR CSR. The LAST_READ_ADDR shows the last read address of the recent read command. For instance, if the host system issues 0xABCD_E000 and reads 128 (or 0x80) bytes, the LAST_READ_ADDR after the transaction will show 0xABCD_E07F. It does not show the commands falling into the mailbox region or Read SFDP command’s address.

The read watermark address width is 1 bit smaller than the read buffer address. In the current version, the register has 10-bit width. The HW assumes the SW maintains the read buffer as a double buffer scheme. When the host system accesses one buffer (1kB), the SW prepares another 1kB by copying data from the internal non-volatile memory. If the received read address crosses the SW configured watermark address, the HW informs the SW. SW may configure the watermark CSR low enough so that the SW has enough time to copy over the data.

If a new read command crosses the current buffer boundary, the SW flips the internal buffer index bit and clears the cross event for the HW to detect the address cross event again.

4B Address Management (EN4B/ EX4B)

SW may configure the HW to receive EN4B and EX4B commands and change the read command address size between 3 bytes and 4 bytes. For the IP to recognize EN4B/ EX4B commands, SW should configure CMD_INFO_EN4B and CMD_INFO_EX4B.

The two CSRs omit unnecessary fields from the CMD_INFO data structure. The HW logic creates the default CMD_INFO structures for the two commands. The command parser module uses the generated structures to process and trigger the 4B management module.

When the HW receives one of the commands, the HW changes the broadcast signal cfg_addr_4b_en. Also the HW updates CFG.addr_4b_en after passing through CDC. It takes at most three SYS_CLK cycles to update the value in the CFG register after the completion of the SPI transaction (CSb de-assertion).

Note: The HW changes the broadcasting signal and the CSR even though the SPI host system sends more than 8 beats of the SPI S[0]. After the logic matches the received command byte with EN4B/ EX4B, the logic ignores the rest of the SPI data.

The broadcasted cfg_addr_4b_en signal affects the read commands which addr_mode is AddrCfg in their command information entries.

Command Upload

If the received command meets following conditions, the HW stores the command into the command/ address FIFOs and the payload buffer:

  • The command does not match to the first 11 command information entries nor EN4B/ EX4B.
  • The command matches to any of the rest command information entries.
  • The matched entry has the upload field set.

The upload module checks the command information entry to determine whether the address/ payload fields to be uploaded or not. The addr_mode is used to determine the address size in the command.

If busy field in the command information entry is set, the upload module also sets BUSY bit in the STATUS register. SW may clear the BUSY bit after processing the command.

The upload module provides UPLOAD_STATUS and UPLOAD_STATUS2 CSRs for SW to parse the command, address, and payload. If a received command has payload, SW may read the payload from the Payload buffer starting from payload_start_idx address. In normal case, payload_start_idx in UPLOAD_STATUS2 shows 0. In error case of the host sending more than the maximum allowed payload size (256B in the current version), the payload_start_idx may not be 0. It is expected that the payload_depth is maximum payload size, 256B if payload_start_idx is non-zero. In this scenario, SW should read from payload_start_idx to the end of the payload buffer then do a second read from the beginning of the buffer to the remained bytes.

If the error case above happens, the IP reports the event through the payload_overflow interrupt.

Passthrough

The passthrough module controls the data between a host system and the attached downstream SPI flash device. It snoops the SPI transactions and intervenes if the transaction is not permitted. The module also manipulates the data if needed.

Command Filtering

Filtering the incoming command is the key role of the Passthrough module.

Command Filtering logic in Passthrough mode

The passthrough logic filters the command based on the 256 bit of CMD_FILTER_0 CSR. Each bit corresponds to each opcode. For example, if bit 5 of CMD_FILTER_0 is set, the passthrough drops CSb when it receives 05h SPI command.

The SW does not know whether a SPI transaction is filtered or not. If the SW wants to check, it needs to set the upload field with the opcode in the command information list. Then, the HW uploads the command into the command/ address FIFOs and the payload buffer.

Address Manipulation

SW may configure the passthrough logic to swap certain address bits to desired values by configuring ADDR_SWAP_MASK and ADDR_SWAP_DATA CSRs. The address translation takes in effect only when the received command is in the command information list and addr_swap_en field in the entry is set.

For instance, the passthrough logic sets bit 20 of the address to 1 if ADDR_SWAP_MASK is 0x0010_0000 and ADDR_SWAP_DATA is 0x0010_0000.

Write Status Data Manipulation

The passthrough logic also provides a way to change the first 4 bytes of the payload to the downstream SPI flash device on-the-fly as same as the address. The main use of this feature is to protect the Status register.

SW may configure the PAYLOAD_SWAP_MASK and PAYLOAD_SWAP_DATA CSRs to change the specific bit of the first 4 byte of the write payload. For example, PAYLOAD_SWAP_MASK as 32'h 0000_0023 and PAYLOAD_SWAP_DATA as 32'h 0000_0022 change bit 0 to 0, bit 1 to 1, bit 5 to 1 in the first byte payload.

The CSRs are Little Endian (LE)s. The passthrough module consumes the lower byte first as SPI flash writes byte 0 first followed by byte 1. For example, bit [7:0] is processed then [15:8], [23:16], and [31:24] at last.

The CSRs affect the commands that have payload_swap_en as 1 in their command list entries. SW may use additional command information slots for the passthrough (index 11 to 23). SW must configure payload_dir to PayloadIn and payload_en to 4'b 0001 in order for the payload translation feature to work correctly.

Output Enable Control

Passthrough module controls the output enable signals on both host and downstream sides. Controlling the output enable ports is critical to not overdrive the PAD directions. The information of the pad enable and direction is given by SW. SW configures the address size, payload lanes, dummy size in CMD_INFO slots.

If passthrough logic does not find valid command information entry based on the received opcode, it assumes the command is PayloadIn Single IO command. SW is recommended to set the filter bit for Passthrough to not deliver the unmatched command to the downstream flash device.

Internally processed Commands

As described in SPI Device Modes, SPI_DEVICE may return the data from the IP even if the passthrough mode is set. The HW can process Read Status, Read JEDEC ID, Read SFDP, Read commands accessing the mailbox region, and EN4B/EX4B.

SW configures INTERCEPT_EN CSR to enable the feature. SW may selectively enable/disable commands. For example, HW returns only Read Status data internally if INTERCEPT_EN is {status: 1'b 1, default: 1'b 0}.

Other than Read command accessing mailbox space, it is recommended to filter the intercepted commands.

TPM over SPI

TPM over SPI block diagram

The TPM over SPI submodule processes the low level data only. The TPM submodule parses the incoming SPI MOSI line and stacks the stream up to the SW accessible registers, such as TPM_CMD_ADDR, and TPM_WRITE_FIFO. The SW must decode the command and the address. Then the SW reads the data from the write FIFO or pushes data into the read FIFO depending on the command.

The TPM submodule returns appropriate data for read commands depending on the current read FIFO status, the received address, and the Locality. The module sends bytes from the return-by-HW registers to the parallel-to-serial logic right after the address phase when the received address falls into the HW managed registers.

The TPM specification mandates the TPM module to return the data right after the address phase or send the WAIT at the last bit of the address phase. The address of the return-by-HW registers has a 4B boundary. The TPM submodule has enough time to determine if the incoming address falls into the return-by-HW registers or not. As the logic decides if the HW returns data or waits for the SW response at the address[2] bit phase, the logic always sends WAIT(0x00) at the last byte of the incoming address phase. The module sends START(0x01) at the next byte followed by the actual return-by-HW value if the received address falls into the list of the return-by-HW registers.

The module, by default, returns WAIT when the address does not fall into the return-by-HW register address. In the wait state, the TPM submodule watches the read FIFO status. The module stays in the wait state until the read FIFO has the data >= requested transfer size. The module sends START at the next byte when the read FIFO has enough data. Then the module pops data from the read FIFO and sends the data over SPI.

The TPM submodule accepts the payload for the TPM write command without the WAIT state if the write FIFO is empty. In other case, the TPM submodule sends WAIT until the write FIFO becomes available (empty).

Configuring Return-by-HW registers

The return-by-HW register values come from the SW read-writable CSRs. The module latches the CSRs from the SYS_CLK domain into the SPI SCK domain when CSb is asserted. The SW is allowed to modify the return-by-HW registers when CSb is not active.

The TCG PC Client Platform TPM Profile spec describes in the section 6 that the TPM device returns registers values based on the received locality (address[15:12]) and the TPM_ACCESS_x.activeLocality. The HW uses TPM_ACCESS_x.activeLocaltiy and the address bit 15:12 to determine what value the logic should return. If invalid_locality configuration is set, the logic returns INVALID value to the host system, when the host system sends a read request to the Locality greater than 4. If the request is in the supported locality (0-4), the logic checks TPM_ACCESS_x.activeLocality then returns data based on the table 39 in the spec for Return-by-HW registers. Other registers in the table should be processed by SW.

Design Details

Clock and Phase

The SPI device module has two programmable register bits to control the SPI clock, CFG.CPOL and CFG.CPHA. CPOL controls clock polarity and CPHA controls the clock phase. For further details, please refer to this diagram from Wikipedia: File:SPI_timing_diagram2.svg

SPI Device Firmware Operation Mode

As described in the Theory of Operations above, in this mode, the SPI device writes incoming data directly into the SRAM (through RXFIFO) and updates the SPI device SRAM write pointer ( RXF_PTR.wptr). It does not parse a command byte nor address bytes, analyzing incoming data relies on firmware implementation of a higher level protocol. Data is sent from the TXF SRAM contents via TXFIFO.

It is important that the data path inside the block should meet the timing that is a half cycle of SCK. As SCK clock is shut off right after the last bit of the last byte is received, the hardware module cannot register the SDI signal. The module registers bits [7:1] and combines them with the SDI signal directly to form the input to RXFIFO. This is detailed in the waveform below.

As shown above, the RXFIFO write request signal (RX_WEN) is asserted when BitCount reaches 0h. Bitcount is reset by CSB asynchronously, returning to 7h for the next round. RXFIFO input data changes on the half clock cycle. RXFIFO latches WEN at the positive edge of SCK. When BitCount is 0h, bit 0 of FIFO data shows the bit 1 value for the first half clock cycle then shows correct value once the incoming SDI value is updated.

TXFIFO is similar. TX_REN is asserted when Tx BitCount reaches 1, and the current entry of TXFIFO is popped at the negative edge of SCK. It results in a change of SDO value at the negative edge of SCK. SDO_OE is controlled by the CSB signal. If CSB goes to high, SDO is returned to High-Z state.

Note that in the SPI mode 3 configuration ( CFG.CPOL=1, CFG.CPHA=1), the logic isn’t able to pop the entry from the TX async FIFO after the last bit in the last byte of a transaction. In mode 3, no further SCK edge is given after sending the last bit before the CSB de-assertion. The design is chosen to pop the entry at the 7th bit position. This introduces unavoidable behavior of dropping the last byte if CSB is de-asserted before a byte transfer is completed. If CSB is de-asserted in bit 1 to 6 position, the FIFO entry isn’t popped. TX logic will re-send the byte in next transaction. If CSB is de-asserted in the 7th or 8th bit position, the data is dropped and will re-commence with the next byte in the next transaction.

RXFIFO control

RXF CTRL State Machine

The RXFIFO Control module controls data flow from RXFIFO to SRAM. It connects two FIFOs having different data widths. RXFIFO is byte width, SRAM storing incoming data to serve FW is TL-UL interface width.

To reduce traffic to SRAM, the control logic gathers FIFO entries up to full SRAM data width, then does a full-word SRAM write. A programmable timer exists in the case when partial bytes are received at the end of a transfer. If the timer expires while bytes are still in the RXFIFO, the logic writes partial words to SRAM. A read-modify-write operation is triggered to perform the partial update.

State Machine

TXFIFO control

The TXFIFO control module reads data from SRAM then pushes to TXFIFO whenever there is space in TXFIFO and when the TXF wptr and rptr indicate there is data to transmit. Data is written into the TXF SRAM by software which also controls the TXF write pointer.

TXF CTRL Data Path

The TXFIFO control module latches the write pointer then uses it internally. This prevents HW from using incorrect data from SRAM if the write pointer and read pointer are pointing at the same location. It is recommended for the software to update the write pointer at the SRAM data width granularity if it has more than 1 DWord data to send out. If software updates write pointer every byte, HW tries to fetch data from SRAM every time it hits the write pointer leading to inefficiency of SRAM access.

If TXFIFO is empty, HW module repeatedly sends current entry of TXFIFO output as explained in “Theory of Operations” section. It cannot use an empty signal from TXFIFO due to asynchronous timing constraints.

So, if software wants to send specific dummy data, it should prepare the amount of data with that value. As shown in the Theory Of Operations figure, for example, internal software could prepare FFh values for first page.

State Machine

Data Storage Sizes

SPI Device IP uses a 2kB internal Dual-Port SRAM. Firmware can resize RX / TX circular buffers within the SRAM size. For example, the firmware is able to set RX circular buffer to be 1.5kB and 512B for TX circular buffer.

To increase SRAM size, the SramAw local parameter in spi_device.sv should be changed. It cannot exceed 13 (32kB) due to the read and write pointers' widths.

Programmers Guide

Initialization

By default, RX SRAM FIFO base and limit address (via RXF_ADDR register) are set to 0x0 and 0x1FC, 512 bytes. And TX SRAM FIFO base and limit addresses (in the TXF_ADDR register) are 0x200 and 0x3FC. If FW wants bigger spaces, it can change the values of the above registers RXF_ADDR and TXF_ADDR.

Software can configure the timer value CFG.timer_v to change the delay between partial DATA received from SPI interface being written into the SRAM. The value of the field is the number of the core clock cycles that the logic waits for.

Pointers

RX / TX SRAM FIFO has read and write pointers, RXF_PTR and TXF_PTR . Those pointers are used to manage circular FIFOs inside the SRAM. The pointer width in the register description is 16 bit but the number of valid bits in the pointers depends on the size of the SRAM.

The current SRAM size is 2kB and the pointer width is 12 bits, 11bits representing a byte offset and 1 most-significant bit for indicating phase of the FIFO. Since they represent bytes, the low 2 bits indicate the offset within the 32-bit wide SRAM word. The pointers indicate the offset into the area described by the base and limit values, so the lower bits (11 bits in this case) of a pointer should not exceed the size in bytes (4 * (limit address - base address)) reserved for the region (RXF or TXF) that the pointer is in. For instance, if FW sets RXFIFO depth to 128 (default value), it should not update the read pointer outside the range 0x000 - 0x1FF (128*4 = 512Bytes ignoring the phase bit, bit 11).

Dual-port SRAM Layout

The figure below shows the SRAM layout in the Flash and Passthrough modes. In generic mode, the whole DPSRAM is used as RX/TX buffers as described in the generic mode section. The SRAM begins at 0x1000, which in the figure is 0x000.

SPI Device Dual-port SRAM Layout

The regions starting from 0xF00 to 0xFFF are assigned to TPM Read/Write FIFOs. They are not used in this version of IP.

TPM over SPI

Initialization

The SW should enable the TPM submodule by writing 1 to the TPM_CFG.en CSR field. Other SPI_DEVICE features (Generic, Flash, Passthrough) CSRs do not affect the TPM feature.

Update TPM_ACCESS_0, TPM_ACCESS_1 CSRs. The TPM submodule uses TPM_ACCESS_x.activeLocality to determine if the TPM_STS is returned to the host system. The SW may configure TPM_CFG.hw_reg_dis and/or TPM_CFG.invalid_locality to fully control the TPM transactions.

TPM mode: FIFO and CRB

The HW returns the return-by-HW registers for the read request in the TPM FIFO mode. In the TPM CRB mode (TPM_CFG.tpm_mode is 1), the logic always upload the command and address to the SW and waits for the read FIFO data even the received address falls into the managed address.

Return-by-HW register update

The SW manages the return-by-HW registers. The contents are placed inside the SPI_DEVICE CSRs. The SW must maintain the other TPM registers outside of the SPI_DEVICE HWIP and use write/read FIFOs to receive the content from/ send the register value to the host system.

When the SW updates the return-by-HW registers, the SW is recommended to read back the register to confirm the value is written. Due to the CDC issue, the SW is only permitted to update the registers when the TPM CS# is de-asserted.

TPM Read

  1. The host system sends the TPM read command with the address.
  2. The SW reads a word from TPM_CMD_ADDR CSR (optional cmdaddr_notempty interrupt).
  3. If the address falls into the return-by-HW registers and TPM_CFG.hw_reg_dis is not set, the HW does not push the command and address bytes into the TPM_CMD_ADDR CSR.
  4. The SW prepares the register value and writes the value into the read FIFO.
  5. The TPM submodule sends WAIT until the read FIFO is available. When available, the TPM submodule sends START followed by the register value.

TPM Write

  1. The host system sends the TPM write command with the address.
  2. The TPM submodule pushes the command and the address to the TPM_CMD_ADDR CSR.
  3. The TPM submodule checks the write FIFO status.
  4. If not empty, the TPM submodule sends WAIT to the host system.
  5. When the FIFO is empty, the TPM sends START to the host system, receives the payload, and stores the data into the write FIFO.
  6. The SW, in the meantime, reads TPM_CMD_ADDR then reads the write FIFO data when the FIFO is available.

TPM Interrupt

The TPM submodule does not process the TPM over SPI interrupt. The SW must check TPM_INT_ENABLE, TPM_INT_STATUS and control the GPIO pin that is designated to the TPM over SPI interrupt.

Device Interface Functions (DIFs)

To use this DIF, include the following C header:

#include "sw/device/lib/dif/dif_spi_device.h"

This header provides the following device interface functions:

Register Table

Summary
Name Offset Length Description
SPI_DEVICE.INTR_STATE 0x0 4

Interrupt State Register

SPI_DEVICE.INTR_ENABLE 0x4 4

Interrupt Enable Register

SPI_DEVICE.INTR_TEST 0x8 4

Interrupt Test Register

SPI_DEVICE.ALERT_TEST 0xc 4

Alert Test Register

SPI_DEVICE.CONTROL 0x10 4

Control register

SPI_DEVICE.CFG 0x14 4

Configuration Register

SPI_DEVICE.FIFO_LEVEL 0x18 4

RX/ TX FIFO levels.

SPI_DEVICE.ASYNC_FIFO_LEVEL 0x1c 4

RX/ TX Async FIFO levels between main clk and spi clock

SPI_DEVICE.STATUS 0x20 4

SPI Device status register

SPI_DEVICE.RXF_PTR 0x24 4

Receiver FIFO (SRAM) pointers

SPI_DEVICE.TXF_PTR 0x28 4

Transmitter FIFO (SRAM) pointers

SPI_DEVICE.RXF_ADDR 0x2c 4

Receiver FIFO (SRAM) Addresses

SPI_DEVICE.TXF_ADDR 0x30 4

Transmitter FIFO (SRAM) Addresses

SPI_DEVICE.INTERCEPT_EN 0x34 4

Intercept Passthrough datapath.

SPI_DEVICE.LAST_READ_ADDR 0x38 4

Last Read Address

SPI_DEVICE.FLASH_STATUS 0x3c 4

SPI Flash Status register.

SPI_DEVICE.JEDEC_CC 0x40 4

JEDEC Continuation Code configuration register.

SPI_DEVICE.JEDEC_ID 0x44 4

JEDEC ID register.

SPI_DEVICE.READ_THRESHOLD 0x48 4

Read Buffer threshold register.

SPI_DEVICE.MAILBOX_ADDR 0x4c 4

Mailbox Base address register.

SPI_DEVICE.UPLOAD_STATUS 0x50 4

Upload module status register.

SPI_DEVICE.UPLOAD_STATUS2 0x54 4

Upload module status 2 register.

SPI_DEVICE.UPLOAD_CMDFIFO 0x58 4

Command Fifo Read Port.

SPI_DEVICE.UPLOAD_ADDRFIFO 0x5c 4

Address Fifo Read Port.

SPI_DEVICE.CMD_FILTER_0 0x60 4

Command Filter

SPI_DEVICE.CMD_FILTER_1 0x64 4

Command Filter

SPI_DEVICE.CMD_FILTER_2 0x68 4

Command Filter

SPI_DEVICE.CMD_FILTER_3 0x6c 4

Command Filter

SPI_DEVICE.CMD_FILTER_4 0x70 4

Command Filter

SPI_DEVICE.CMD_FILTER_5 0x74 4

Command Filter

SPI_DEVICE.CMD_FILTER_6 0x78 4

Command Filter

SPI_DEVICE.CMD_FILTER_7 0x7c 4

Command Filter

SPI_DEVICE.ADDR_SWAP_MASK 0x80 4

Address Swap Mask register.

SPI_DEVICE.ADDR_SWAP_DATA 0x84 4

The address value for the address swap feature.

SPI_DEVICE.PAYLOAD_SWAP_MASK 0x88 4

Write Data Swap in the passthrough mode.

SPI_DEVICE.PAYLOAD_SWAP_DATA 0x8c 4

Write Data Swap in the passthrough mode.

SPI_DEVICE.CMD_INFO_0 0x90 4

Command Info register.

SPI_DEVICE.CMD_INFO_1 0x94 4

Command Info register.

SPI_DEVICE.CMD_INFO_2 0x98 4

Command Info register.

SPI_DEVICE.CMD_INFO_3 0x9c 4

Command Info register.

SPI_DEVICE.CMD_INFO_4 0xa0 4

Command Info register.

SPI_DEVICE.CMD_INFO_5 0xa4 4

Command Info register.

SPI_DEVICE.CMD_INFO_6 0xa8 4

Command Info register.

SPI_DEVICE.CMD_INFO_7 0xac 4

Command Info register.

SPI_DEVICE.CMD_INFO_8 0xb0 4

Command Info register.

SPI_DEVICE.CMD_INFO_9 0xb4 4

Command Info register.

SPI_DEVICE.CMD_INFO_10 0xb8 4

Command Info register.

SPI_DEVICE.CMD_INFO_11 0xbc 4

Command Info register.

SPI_DEVICE.CMD_INFO_12 0xc0 4

Command Info register.

SPI_DEVICE.CMD_INFO_13 0xc4 4

Command Info register.

SPI_DEVICE.CMD_INFO_14 0xc8 4

Command Info register.

SPI_DEVICE.CMD_INFO_15 0xcc 4

Command Info register.

SPI_DEVICE.CMD_INFO_16 0xd0 4

Command Info register.

SPI_DEVICE.CMD_INFO_17 0xd4 4

Command Info register.

SPI_DEVICE.CMD_INFO_18 0xd8 4

Command Info register.

SPI_DEVICE.CMD_INFO_19 0xdc 4

Command Info register.

SPI_DEVICE.CMD_INFO_20 0xe0 4

Command Info register.

SPI_DEVICE.CMD_INFO_21 0xe4 4

Command Info register.

SPI_DEVICE.CMD_INFO_22 0xe8 4

Command Info register.

SPI_DEVICE.CMD_INFO_23 0xec 4

Command Info register.

SPI_DEVICE.CMD_INFO_EN4B 0xf0 4

Opcode for EN4B.

SPI_DEVICE.CMD_INFO_EX4B 0xf4 4

Opcode for EX4B

SPI_DEVICE.CMD_INFO_WREN 0xf8 4

Opcode for Write Enable (WREN)

SPI_DEVICE.CMD_INFO_WRDI 0xfc 4

Opcode for Write Disable (WRDI)

SPI_DEVICE.TPM_CAP 0x800 4

TPM HWIP Capability register.

SPI_DEVICE.TPM_CFG 0x804 4

TPM Configuration register.

SPI_DEVICE.TPM_STATUS 0x808 4

TPM submodule state register.

SPI_DEVICE.TPM_ACCESS_0 0x80c 4

TPM_ACCESS_x register.

SPI_DEVICE.TPM_ACCESS_1 0x810 4

TPM_ACCESS_x register.

SPI_DEVICE.TPM_STS 0x814 4

TPM_STS_x register.

SPI_DEVICE.TPM_INTF_CAPABILITY 0x818 4

TPM_INTF_CAPABILITY

SPI_DEVICE.TPM_INT_ENABLE 0x81c 4

TPM_INT_ENABLE

SPI_DEVICE.TPM_INT_VECTOR 0x820 4

TPM_INT_VECTOR

SPI_DEVICE.TPM_INT_STATUS 0x824 4

TPM_INT_STATUS

SPI_DEVICE.TPM_DID_VID 0x828 4

TPM_DID/ TPM_VID register

SPI_DEVICE.TPM_RID 0x82c 4

TPM_RID

SPI_DEVICE.TPM_CMD_ADDR 0x830 4

TPM Command and Address buffer

SPI_DEVICE.TPM_READ_FIFO 0x834 4

TPM Read command return data FIFO.

SPI_DEVICE.TPM_WRITE_FIFO 0x838 4

TPM Write command received data FIFO.

SPI_DEVICE.buffer 0x1000 4096

SPI internal buffer.

SPI_DEVICE.INTR_STATE @ 0x0

Interrupt State Register

Reset default = 0x0, mask 0xfff
31302928272625242322212019181716
 
1514131211109876543210
  tpm_header_not_empty readbuf_flip readbuf_watermark upload_payload_overflow upload_payload_not_empty upload_cmdfifo_not_empty generic_tx_underflow generic_rx_overflow generic_rx_error generic_tx_watermark generic_rx_watermark generic_rx_full
BitsTypeResetNameDescription
0rw1c0x0generic_rx_full

RX SRAM FIFO Full

1rw1c0x0generic_rx_watermark

RX SRAM FIFO is above the level

2rw1c0x0generic_tx_watermark

TX SRAM FIFO is under the level

3rw1c0x0generic_rx_error

SDI in FwMode has error

4rw1c0x0generic_rx_overflow

RX Async FIFO overflow

5rw1c0x0generic_tx_underflow

TX Async FIFO underflow

6rw1c0x0upload_cmdfifo_not_empty

Upload Command FIFO is not empty

7rw1c0x0upload_payload_not_empty

Upload payload is not empty.

The event occurs after SPI transaction completed

8rw1c0x0upload_payload_overflow

Upload payload overflow event.

When a SPI Host system issues a command with payload more than 256B, this event is reported. When it happens, SW should read the last written payload index CSR to figure out the starting address of the last 256B.

9rw1c0x0readbuf_watermark

Read Buffer Threshold event.

The host system accesses greater than or equal to the threshold of a buffer.

10rw1c0x0readbuf_flip

Read buffer flipped event.

The host system accesses other side of buffer.

11rw1c0x0tpm_header_not_empty

TPM Header(Command/Address) buffer available


SPI_DEVICE.INTR_ENABLE @ 0x4

Interrupt Enable Register

Reset default = 0x0, mask 0xfff
31302928272625242322212019181716
 
1514131211109876543210
  tpm_header_not_empty readbuf_flip readbuf_watermark upload_payload_overflow upload_payload_not_empty upload_cmdfifo_not_empty generic_tx_underflow generic_rx_overflow generic_rx_error generic_tx_watermark generic_rx_watermark generic_rx_full
BitsTypeResetNameDescription
0rw0x0generic_rx_full

Enable interrupt when INTR_STATE.generic_rx_full is set.

1rw0x0generic_rx_watermark

Enable interrupt when INTR_STATE.generic_rx_watermark is set.

2rw0x0generic_tx_watermark

Enable interrupt when INTR_STATE.generic_tx_watermark is set.

3rw0x0generic_rx_error

Enable interrupt when INTR_STATE.generic_rx_error is set.

4rw0x0generic_rx_overflow

Enable interrupt when INTR_STATE.generic_rx_overflow is set.

5rw0x0generic_tx_underflow

Enable interrupt when INTR_STATE.generic_tx_underflow is set.

6rw0x0upload_cmdfifo_not_empty

Enable interrupt when INTR_STATE.upload_cmdfifo_not_empty is set.

7rw0x0upload_payload_not_empty

Enable interrupt when INTR_STATE.upload_payload_not_empty is set.

8rw0x0upload_payload_overflow

Enable interrupt when INTR_STATE.upload_payload_overflow is set.

9rw0x0readbuf_watermark

Enable interrupt when INTR_STATE.readbuf_watermark is set.

10rw0x0readbuf_flip

Enable interrupt when INTR_STATE.readbuf_flip is set.

11rw0x0tpm_header_not_empty

Enable interrupt when INTR_STATE.tpm_header_not_empty is set.


SPI_DEVICE.INTR_TEST @ 0x8

Interrupt Test Register

Reset default = 0x0, mask 0xfff
31302928272625242322212019181716
 
1514131211109876543210
  tpm_header_not_empty readbuf_flip readbuf_watermark upload_payload_overflow upload_payload_not_empty upload_cmdfifo_not_empty generic_tx_underflow generic_rx_overflow generic_rx_error generic_tx_watermark generic_rx_watermark generic_rx_full
BitsTypeResetNameDescription
0wo0x0generic_rx_full

Write 1 to force INTR_STATE.generic_rx_full to 1.

1wo0x0generic_rx_watermark

Write 1 to force INTR_STATE.generic_rx_watermark to 1.

2wo0x0generic_tx_watermark

Write 1 to force INTR_STATE.generic_tx_watermark to 1.

3wo0x0generic_rx_error

Write 1 to force INTR_STATE.generic_rx_error to 1.

4wo0x0generic_rx_overflow

Write 1 to force INTR_STATE.generic_rx_overflow to 1.

5wo0x0generic_tx_underflow

Write 1 to force INTR_STATE.generic_tx_underflow to 1.

6wo0x0upload_cmdfifo_not_empty

Write 1 to force INTR_STATE.upload_cmdfifo_not_empty to 1.

7wo0x0upload_payload_not_empty

Write 1 to force INTR_STATE.upload_payload_not_empty to 1.

8wo0x0upload_payload_overflow

Write 1 to force INTR_STATE.upload_payload_overflow to 1.

9wo0x0readbuf_watermark

Write 1 to force INTR_STATE.readbuf_watermark to 1.

10wo0x0readbuf_flip

Write 1 to force INTR_STATE.readbuf_flip to 1.

11wo0x0tpm_header_not_empty

Write 1 to force INTR_STATE.tpm_header_not_empty to 1.


SPI_DEVICE.ALERT_TEST @ 0xc

Alert Test Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  fatal_fault
BitsTypeResetNameDescription
0wo0x0fatal_fault

Write 1 to trigger one alert event of this kind.


SPI_DEVICE.CONTROL @ 0x10

Control register

Reset default = 0x80000010, mask 0x80030031
31302928272625242322212019181716
sram_clk_en   rst_rxfifo rst_txfifo
1514131211109876543210
  MODE   ABORT
BitsTypeResetNameDescription
0rw0x0ABORT

Abort pending TX data in Generic mode.

If TX_FIFO (Asynchronous) is full, the TXF waits indefinitely to push the next byte into the asynchronous FIFO. SW may reset the Async FIFO along with aborting the current task. SW should update the write pointer of the TXF in order not to push the byte to Asynchronous FIFO again by TXF logic.

3:1Reserved
5:4rw0x1MODE

SPI Device operation mode. Currently only FwMode is supported.

0x0fwmode

FW operation mode.

HW just dumps incoming data to SRAM and reads from SRAM and sends to SDO. This mode doesn't support Dual or Quad mode

0x1flashmode

SPI Flash Emulation mode.

In flash mode, SPI Device IP accepts SPI Flash commands and processes internally, then returns data for the read commands. HW processes the Status, JEDEC ID, SFDP commands.

The current version does not support Dual/Quad IO and QPI commands.

0x2passthrough

In passthrough mode, SPI Device IP forwards the incoming SPI flash traffics to the attached downstream flash device. HW may processes commands internally and returns data.

SW may configure the device to drop inadmissable commands.

Other values are reserved.

15:6Reserved
16rw0x0rst_txfifo

Reset Async TX_FIFO.

This only resets asynchronous fifo. If firmware wants to reset SRAM FIFO, it should write 0 into read/write pointers.

Note: This value should be controlled only when SPI interface is in Idle state as this reset signal doesn't have reset synchronizer.

17rw0x0rst_rxfifo

Reset Async RX_FIFO.

This only resets asynchronous fifo. If firmware wants to reset SRAM FIFO, it should write 0 into read pointer and write pointer.

Note: This value should be controlled only when SPI interface is in Idle state as this reset signal doesn't have reset synchronizer.

30:18Reserved
31rw0x1sram_clk_en

SRAM Clock Enable.

This controls the clock gating cell lying on DP SRAM clock. As the nature of absent of SPI_CLK in idle state, the clock mux for SRAM B port cannot be glitch-free MUX. So, it is up to SW to change the clock safely.

Programming sequence:

  1. Check if SPI line is idle
  2. Clear sram_clk_en to 0.
  3. Change mode to FwMode for peri clk, FlashMode or PassThrough for SPI_CLK.
  4. Set sram_clk_en to 1.


SPI_DEVICE.CFG @ 0x14

Configuration Register

Reset default = 0x7f00, mask 0x101ff0f
31302928272625242322212019181716
  mailbox_en   addr_4b_en
1514131211109876543210
timer_v   rx_order tx_order CPHA CPOL
BitsTypeResetNameDescription
0rw0x0CPOL

Clock polarity. 0 for normal SPI, 1 for negative edge latch

1rw0x0CPHA

Data phase. 0 for negative edge change, 1 for positive edge change

2rw0x0tx_order

TX bit order on SDO. 0 for MSB to LSB, 1 for LSB to MSB

3rw0x0rx_order

RX bit order on SDI. Module stores bitstream from MSB to LSB if value is 0.

7:4Reserved
15:8rw0x7ftimer_v

number of clocks for RXF to wait.

To reduce traffic to SRAM, RXF control module waits given clock cycle if it doesn't fill SRAM data width even if Async RX FIFO is empty.

16rw0x0addr_4b_en

4B Address Mode enable.

This field configures the internal module to receive 32 bits of the SPI commands. The affected commands are the SPI read commands except QPI, and program commands.

Even though Read SFDP command has address fields, the SFDP command is not affected by this field. The command always parse 24 bits on the SPI line 0 following the SPI command as the address field.

23:17Reserved
24rw0x0mailbox_en

Mailbox enable.

If 1, in the flash and passthrough mode, the IP checks the incoming address and return from the internal Mailbox buffer if the address falls into the MAILBOX range (MAILBOX_ADDR:MAILBOX_ADDR+MAILBOX_SIZE)}.


SPI_DEVICE.FIFO_LEVEL @ 0x18

RX/ TX FIFO levels.

Reset default = 0x80, mask 0xffffffff
31302928272625242322212019181716
txlvl
1514131211109876543210
rxlvl
BitsTypeResetNameDescription
15:0rw0x80rxlvl

RX FIFO level.

If RX SRAM FIFO level exceeds this value, it triggers interrupt.

31:16rw0x0txlvl

TX FIFO level.

If TX SRAM FIFO level drops below this value, it triggers interrupt.


SPI_DEVICE.ASYNC_FIFO_LEVEL @ 0x1c

RX/ TX Async FIFO levels between main clk and spi clock

Reset default = 0x0, mask 0xff00ff
31302928272625242322212019181716
  txlvl
1514131211109876543210
  rxlvl
BitsTypeResetNameDescription
7:0roxrxlvl

RX Async FIFO level.

This value shows the number of available entry in RX Async FIFO.

15:8Reserved
23:16roxtxlvl

TX Async FIFO level.

This value shows the number of available entry in TX Async FIFO. If the software writes message into SRAM FIFO and update FIFO write pointer but no clock from the host is given, the data stuck at this async fifo waiting host toggles SCK. This value represents the number of bytes.


SPI_DEVICE.STATUS @ 0x20

SPI Device status register

Reset default = 0x7a, mask 0x7f
31302928272625242322212019181716
 
1514131211109876543210
  tpm_csb csb abort_done txf_empty txf_full rxf_empty rxf_full
BitsTypeResetNameDescription
0roxrxf_full

RX FIFO full

1ro0x1rxf_empty

RX FIFO empty

2roxtxf_full

TX FIFO full

3ro0x1txf_empty

TX FIFO empty

4ro0x1abort_done

Abort process is completed.

Current version does not implement abort_done logic. It is tied to 1 always.

5ro0x1csb

Direct input of CSb signal

6ro0x1tpm_csb

Direct input of TPM CSb


SPI_DEVICE.RXF_PTR @ 0x24

Receiver FIFO (SRAM) pointers

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
WPTR
1514131211109876543210
RPTR
BitsTypeResetNameDescription
15:0rw0x0RPTR

Read pointer. bit x is for phase bit. check circular fifo description

31:16ro0x0WPTR

Write pointer. Bit x is phase bit.


SPI_DEVICE.TXF_PTR @ 0x28

Transmitter FIFO (SRAM) pointers

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
WPTR
1514131211109876543210
RPTR
BitsTypeResetNameDescription
15:0ro0x0RPTR

Read pointer. bit x is for phase bit. check circular fifo description

31:16rw0x0WPTR

Write pointer. Bit x is phase bit.


SPI_DEVICE.RXF_ADDR @ 0x2c

Receiver FIFO (SRAM) Addresses

Reset default = 0x1fc0000, mask 0xffffffff
31302928272625242322212019181716
limit
1514131211109876543210
base
BitsTypeResetNameDescription
15:0rw0x0base

Base offset in bytes in the SRAM. Lower 2 bits are ignored.

31:16rw0x1fclimit

Limit offset in bytes in the SRAM. Lower 2 bits are ignored.


SPI_DEVICE.TXF_ADDR @ 0x30

Transmitter FIFO (SRAM) Addresses

Reset default = 0x3fc0200, mask 0xffffffff
31302928272625242322212019181716
limit
1514131211109876543210
base
BitsTypeResetNameDescription
15:0rw0x200base

Base offset in bytes in the SRAM. Lower 2 bits are ignored.

31:16rw0x3fclimit

Limit offset in bytes in the SRAM. Lower 2 bits are ignored.


SPI_DEVICE.INTERCEPT_EN @ 0x34

Intercept Passthrough datapath.

Reset default = 0x0, mask 0xf
31302928272625242322212019181716
 
1514131211109876543210
  mbx sfdp jedec status
BitsTypeResetNameDescription
0rw0x0status

If set, Read Status is processed internally.

1rw0x0jedec

If set, Read JEDEC ID is processed internally.

2rw0x0sfdp

If set, Read SFDP is processed internally.

3rw0x0mbx

If set, Read Command to Mailbox region is processed internally.


SPI_DEVICE.LAST_READ_ADDR @ 0x38

Last Read Address

Reset default = 0x0, mask 0xffffffff

This register shows the last address accessed by the host system. It is updated by the HW when CSb is de-asserted.

31302928272625242322212019181716
addr...
1514131211109876543210
...addr
BitsTypeResetNameDescription
31:0roxaddr

Last address


SPI_DEVICE.FLASH_STATUS @ 0x3c

SPI Flash Status register.

Reset default = 0x0, mask 0xffffff

This register emulates the SPI Flash Status 3, 2, 1 registers. bit [7:0] is for Status register, bit [15:8] is for Status-2 register, and bit [23:16] is for Status-3 register. It is SW responsibility to maintain this register value up to date.

The HW latches the value when SPI Flash transaction begins. Any updates during the transaction will be updated after the transaction is completed.

31302928272625242322212019181716
  status...
1514131211109876543210
...status busy
BitsTypeResetNameDescription
0rw0cxbusy

BUSY signal is cleared when CSb is high. SW should read back the register to confirm the value is cleared.

23:1rwxstatus

Rest of the status register.

Fields other than the bit 0 (BUSY) and bit 1 (WEL) fields are SW-maintained fields. HW just reads and returns to the host system.

Bit 1 (WEL) is a SW modifiable and HW modifiable field. HW updates the WEL field when WRDI or WREN command is received.

  • [ 1]: WEL
  • [ 2]: BP0
  • [ 3]: BP1
  • [ 4]: BP2
  • [ 5]: TB
  • [ 6]: SEC
  • [ 7]: SRP0
  • [ 8]: SRP1
  • [ 9]: QE
  • [11]: LB1
  • [12]: LB2
  • [13]: LB3
  • [14]: CMP
  • [15]: SUS
  • [18]: WPS
  • [21]: DRV0
  • [22]: DRV1
  • [23]: HOLD /RST


SPI_DEVICE.JEDEC_CC @ 0x40

JEDEC Continuation Code configuration register.

Reset default = 0x7f, mask 0xffff

Read JEDEC ID must return the continuation code if the manufacturer ID is not shown in the first page of JEDEC table. This register controls the Continuation Code.

31302928272625242322212019181716
 
1514131211109876543210
num_cc cc
BitsTypeResetNameDescription
7:0rw0x7fcc

Continuation Code byte

15:8rw0x0num_cc

The number that Continuation Code repeats


SPI_DEVICE.JEDEC_ID @ 0x44

JEDEC ID register.

Reset default = 0x0, mask 0xffffff
31302928272625242322212019181716
  mf
1514131211109876543210
id
BitsTypeResetNameDescription
15:0rw0x0id

Device ID

23:16rw0x0mf

Manufacturer ID


SPI_DEVICE.READ_THRESHOLD @ 0x48

Read Buffer threshold register.

Reset default = 0x0, mask 0x3ff
31302928272625242322212019181716
 
1514131211109876543210
  threshold
BitsTypeResetNameDescription
9:0rw0x0threshold

If 0, disable the watermark. If non-zero, when the host access above or equal to the threshold, it reports an interrupt. The value is byte-granularity not SRAM index.


SPI_DEVICE.MAILBOX_ADDR @ 0x4c

Mailbox Base address register.

Reset default = 0x0, mask 0xffffffff

The mailbox size is fixed. In this version of IP, the size is 1kB. Lower 10 bits of the Mailbox address is tied to 0.

31302928272625242322212019181716
addr...
1514131211109876543210
...addr
BitsTypeResetNameDescription
31:0rw0x0addr

Mailbox Address. Lower 10 bits are ignored


SPI_DEVICE.UPLOAD_STATUS @ 0x50

Upload module status register.

Reset default = 0x0, mask 0x9f9f
31302928272625242322212019181716
 
1514131211109876543210
addrfifo_notempty   addrfifo_depth cmdfifo_notempty   cmdfifo_depth
BitsTypeResetNameDescription
4:0ro0x0cmdfifo_depth

Command FIFO Entry

6:5Reserved
7ro0x0cmdfifo_notempty

Upload Command FIFO Not Empty

12:8ro0x0addrfifo_depth

Address FIFO Entry

14:13Reserved
15ro0x0addrfifo_notempty

Upload Address FIFO Not Empty


SPI_DEVICE.UPLOAD_STATUS2 @ 0x54

Upload module status 2 register.

Reset default = 0x0, mask 0xff01ff

This register contains payload related status. payload_depth indicates the payload size (from 0 to 256 bytes).

payload_start_idx indicates the start of the 256B. This stays 0 usually. However, when the SPI host system issues more than 256B of payload in a command, this field may not be 0. For example, if the system issues 258B payload, the payload_depth is 256 (as the IP only holds 256B of payload), the payload_start_idx is 2. SW should read from 2 to 255 then 0 and 1.

31302928272625242322212019181716
  payload_start_idx
1514131211109876543210
  payload_depth
BitsTypeResetNameDescription
8:0ro0x0payload_depth

Payload buffer depth

15:9Reserved
23:16ro0x0payload_start_idx

Payload Start Index


SPI_DEVICE.UPLOAD_CMDFIFO @ 0x58

Command Fifo Read Port.

Reset default = 0x0, mask 0xff
31302928272625242322212019181716
 
1514131211109876543210
  data
BitsTypeResetNameDescription
7:0roxdata

read data


SPI_DEVICE.UPLOAD_ADDRFIFO @ 0x5c

Address Fifo Read Port.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
data...
1514131211109876543210
...data
BitsTypeResetNameDescription
31:0roxdata

read data


SPI_DEVICE.CMD_FILTER_0 @ 0x60

Command Filter

Reset default = 0x0, mask 0xffffffff

If a bit in this CSR is 1, then corresponding SPI command w.r.t the bit position among 256 bit is dropped in SPI Passthrough mode.

31302928272625242322212019181716
filter_31 filter_30 filter_29 filter_28 filter_27 filter_26 filter_25 filter_24 filter_23 filter_22 filter_21 filter_20 filter_19 filter_18 filter_17 filter_16
1514131211109876543210
filter_15 filter_14 filter_13 filter_12 filter_11 filter_10 filter_9 filter_8 filter_7 filter_6 filter_5 filter_4 filter_3 filter_2 filter_1 filter_0
BitsTypeResetNameDescription
0rw0x0filter_0

If 1, command will be filtered

1rw0x0filter_1

If 1, command will be filtered

2rw0x0filter_2

If 1, command will be filtered

3rw0x0filter_3

If 1, command will be filtered

4rw0x0filter_4

If 1, command will be filtered

5rw0x0filter_5

If 1, command will be filtered

6rw0x0filter_6

If 1, command will be filtered

7rw0x0filter_7

If 1, command will be filtered

8rw0x0filter_8

If 1, command will be filtered

9rw0x0filter_9

If 1, command will be filtered

10rw0x0filter_10

If 1, command will be filtered

11rw0x0filter_11

If 1, command will be filtered

12rw0x0filter_12

If 1, command will be filtered

13rw0x0filter_13

If 1, command will be filtered

14rw0x0filter_14

If 1, command will be filtered

15rw0x0filter_15

If 1, command will be filtered

16rw0x0filter_16

If 1, command will be filtered

17rw0x0filter_17

If 1, command will be filtered

18rw0x0filter_18

If 1, command will be filtered

19rw0x0filter_19

If 1, command will be filtered

20rw0x0filter_20

If 1, command will be filtered

21rw0x0filter_21

If 1, command will be filtered

22rw0x0filter_22

If 1, command will be filtered

23rw0x0filter_23

If 1, command will be filtered

24rw0x0filter_24

If 1, command will be filtered

25rw0x0filter_25

If 1, command will be filtered

26rw0x0filter_26

If 1, command will be filtered

27rw0x0filter_27

If 1, command will be filtered

28rw0x0filter_28

If 1, command will be filtered

29rw0x0filter_29

If 1, command will be filtered

30rw0x0filter_30

If 1, command will be filtered

31rw0x0filter_31

If 1, command will be filtered


SPI_DEVICE.CMD_FILTER_1 @ 0x64

Command Filter

Reset default = 0x0, mask 0xffffffff

If a bit in this CSR is 1, then corresponding SPI command w.r.t the bit position among 256 bit is dropped in SPI Passthrough mode.

31302928272625242322212019181716
filter_63 filter_62 filter_61 filter_60 filter_59 filter_58 filter_57 filter_56 filter_55 filter_54 filter_53 filter_52 filter_51 filter_50 filter_49 filter_48
1514131211109876543210
filter_47 filter_46 filter_45 filter_44 filter_43 filter_42 filter_41 filter_40 filter_39 filter_38 filter_37 filter_36 filter_35 filter_34 filter_33 filter_32
BitsTypeResetNameDescription
0rw0x0filter_32

For SPI_DEVICE1

1rw0x0filter_33

For SPI_DEVICE1

2rw0x0filter_34

For SPI_DEVICE1

3rw0x0filter_35

For SPI_DEVICE1

4rw0x0filter_36

For SPI_DEVICE1

5rw0x0filter_37

For SPI_DEVICE1

6rw0x0filter_38

For SPI_DEVICE1

7rw0x0filter_39

For SPI_DEVICE1

8rw0x0filter_40

For SPI_DEVICE1

9rw0x0filter_41

For SPI_DEVICE1

10rw0x0filter_42

For SPI_DEVICE1

11rw0x0filter_43

For SPI_DEVICE1

12rw0x0filter_44

For SPI_DEVICE1

13rw0x0filter_45

For SPI_DEVICE1

14rw0x0filter_46

For SPI_DEVICE1

15rw0x0filter_47

For SPI_DEVICE1

16rw0x0filter_48

For SPI_DEVICE1

17rw0x0filter_49

For SPI_DEVICE1

18rw0x0filter_50

For SPI_DEVICE1

19rw0x0filter_51

For SPI_DEVICE1

20rw0x0filter_52

For SPI_DEVICE1

21rw0x0filter_53

For SPI_DEVICE1

22rw0x0filter_54

For SPI_DEVICE1

23rw0x0filter_55

For SPI_DEVICE1

24rw0x0filter_56

For SPI_DEVICE1

25rw0x0filter_57

For SPI_DEVICE1

26rw0x0filter_58

For SPI_DEVICE1

27rw0x0filter_59

For SPI_DEVICE1

28rw0x0filter_60

For SPI_DEVICE1

29rw0x0filter_61

For SPI_DEVICE1

30rw0x0filter_62

For SPI_DEVICE1

31rw0x0filter_63

For SPI_DEVICE1


SPI_DEVICE.CMD_FILTER_2 @ 0x68

Command Filter

Reset default = 0x0, mask 0xffffffff

If a bit in this CSR is 1, then corresponding SPI command w.r.t the bit position among 256 bit is dropped in SPI Passthrough mode.

31302928272625242322212019181716
filter_95 filter_94 filter_93 filter_92 filter_91 filter_90 filter_89 filter_88 filter_87 filter_86 filter_85 filter_84 filter_83 filter_82 filter_81 filter_80
1514131211109876543210
filter_79 filter_78 filter_77 filter_76 filter_75 filter_74 filter_73 filter_72 filter_71 filter_70 filter_69 filter_68 filter_67 filter_66 filter_65 filter_64
BitsTypeResetNameDescription
0rw0x0filter_64

For SPI_DEVICE2

1rw0x0filter_65

For SPI_DEVICE2

2rw0x0filter_66

For SPI_DEVICE2

3rw0x0filter_67

For SPI_DEVICE2

4rw0x0filter_68

For SPI_DEVICE2

5rw0x0filter_69

For SPI_DEVICE2

6rw0x0filter_70

For SPI_DEVICE2

7rw0x0filter_71

For SPI_DEVICE2

8rw0x0filter_72

For SPI_DEVICE2

9rw0x0filter_73

For SPI_DEVICE2

10rw0x0filter_74

For SPI_DEVICE2

11rw0x0filter_75

For SPI_DEVICE2

12rw0x0filter_76

For SPI_DEVICE2

13rw0x0filter_77

For SPI_DEVICE2

14rw0x0filter_78

For SPI_DEVICE2

15rw0x0filter_79

For SPI_DEVICE2

16rw0x0filter_80

For SPI_DEVICE2

17rw0x0filter_81

For SPI_DEVICE2

18rw0x0filter_82

For SPI_DEVICE2

19rw0x0filter_83

For SPI_DEVICE2

20rw0x0filter_84

For SPI_DEVICE2

21rw0x0filter_85

For SPI_DEVICE2

22rw0x0filter_86

For SPI_DEVICE2

23rw0x0filter_87

For SPI_DEVICE2

24rw0x0filter_88

For SPI_DEVICE2

25rw0x0filter_89

For SPI_DEVICE2

26rw0x0filter_90

For SPI_DEVICE2

27rw0x0filter_91

For SPI_DEVICE2

28rw0x0filter_92

For SPI_DEVICE2

29rw0x0filter_93

For SPI_DEVICE2

30rw0x0filter_94

For SPI_DEVICE2

31rw0x0filter_95

For SPI_DEVICE2


SPI_DEVICE.CMD_FILTER_3 @ 0x6c

Command Filter

Reset default = 0x0, mask 0xffffffff

If a bit in this CSR is 1, then corresponding SPI command w.r.t the bit position among 256 bit is dropped in SPI Passthrough mode.

31302928272625242322212019181716
filter_127 filter_126 filter_125 filter_124 filter_123 filter_122 filter_121 filter_120 filter_119 filter_118 filter_117 filter_116 filter_115 filter_114 filter_113 filter_112
1514131211109876543210
filter_111 filter_110 filter_109 filter_108 filter_107 filter_106 filter_105 filter_104 filter_103 filter_102 filter_101 filter_100 filter_99 filter_98 filter_97 filter_96
BitsTypeResetNameDescription
0rw0x0filter_96

For SPI_DEVICE3

1rw0x0filter_97

For SPI_DEVICE3

2rw0x0filter_98

For SPI_DEVICE3

3rw0x0filter_99

For SPI_DEVICE3

4rw0x0filter_100

For SPI_DEVICE3

5rw0x0filter_101

For SPI_DEVICE3

6rw0x0filter_102

For SPI_DEVICE3

7rw0x0filter_103

For SPI_DEVICE3

8rw0x0filter_104

For SPI_DEVICE3

9rw0x0filter_105

For SPI_DEVICE3

10rw0x0filter_106

For SPI_DEVICE3

11rw0x0filter_107

For SPI_DEVICE3

12rw0x0filter_108

For SPI_DEVICE3

13rw0x0filter_109

For SPI_DEVICE3

14rw0x0filter_110

For SPI_DEVICE3

15rw0x0filter_111

For SPI_DEVICE3

16rw0x0filter_112

For SPI_DEVICE3

17rw0x0filter_113

For SPI_DEVICE3

18rw0x0filter_114

For SPI_DEVICE3

19rw0x0filter_115

For SPI_DEVICE3

20rw0x0filter_116

For SPI_DEVICE3

21rw0x0filter_117

For SPI_DEVICE3

22rw0x0filter_118

For SPI_DEVICE3

23rw0x0filter_119

For SPI_DEVICE3

24rw0x0filter_120

For SPI_DEVICE3

25rw0x0filter_121

For SPI_DEVICE3

26rw0x0filter_122

For SPI_DEVICE3

27rw0x0filter_123

For SPI_DEVICE3

28rw0x0filter_124

For SPI_DEVICE3

29rw0x0filter_125

For SPI_DEVICE3

30rw0x0filter_126

For SPI_DEVICE3

31rw0x0filter_127

For SPI_DEVICE3


SPI_DEVICE.CMD_FILTER_4 @ 0x70

Command Filter

Reset default = 0x0, mask 0xffffffff

If a bit in this CSR is 1, then corresponding SPI command w.r.t the bit position among 256 bit is dropped in SPI Passthrough mode.

31302928272625242322212019181716
filter_159 filter_158 filter_157 filter_156 filter_155 filter_154 filter_153 filter_152 filter_151 filter_150 filter_149 filter_148 filter_147 filter_146 filter_145 filter_144
1514131211109876543210
filter_143 filter_142 filter_141 filter_140 filter_139 filter_138 filter_137 filter_136 filter_135 filter_134 filter_133 filter_132 filter_131 filter_130 filter_129 filter_128
BitsTypeResetNameDescription
0rw0x0filter_128

For SPI_DEVICE4

1rw0x0filter_129

For SPI_DEVICE4

2rw0x0filter_130

For SPI_DEVICE4

3rw0x0filter_131

For SPI_DEVICE4

4rw0x0filter_132

For SPI_DEVICE4

5rw0x0filter_133

For SPI_DEVICE4

6rw0x0filter_134

For SPI_DEVICE4

7rw0x0filter_135

For SPI_DEVICE4

8rw0x0filter_136

For SPI_DEVICE4

9rw0x0filter_137

For SPI_DEVICE4

10rw0x0filter_138

For SPI_DEVICE4

11rw0x0filter_139

For SPI_DEVICE4

12rw0x0filter_140

For SPI_DEVICE4

13rw0x0filter_141

For SPI_DEVICE4

14rw0x0filter_142

For SPI_DEVICE4

15rw0x0filter_143

For SPI_DEVICE4

16rw0x0filter_144

For SPI_DEVICE4

17rw0x0filter_145

For SPI_DEVICE4

18rw0x0filter_146

For SPI_DEVICE4

19rw0x0filter_147

For SPI_DEVICE4

20rw0x0filter_148

For SPI_DEVICE4

21rw0x0filter_149

For SPI_DEVICE4

22rw0x0filter_150

For SPI_DEVICE4

23rw0x0filter_151

For SPI_DEVICE4

24rw0x0filter_152

For SPI_DEVICE4

25rw0x0filter_153

For SPI_DEVICE4

26rw0x0filter_154

For SPI_DEVICE4

27rw0x0filter_155

For SPI_DEVICE4

28rw0x0filter_156

For SPI_DEVICE4

29rw0x0filter_157

For SPI_DEVICE4

30rw0x0filter_158

For SPI_DEVICE4

31rw0x0filter_159

For SPI_DEVICE4


SPI_DEVICE.CMD_FILTER_5 @ 0x74

Command Filter

Reset default = 0x0, mask 0xffffffff

If a bit in this CSR is 1, then corresponding SPI command w.r.t the bit position among 256 bit is dropped in SPI Passthrough mode.

31302928272625242322212019181716
filter_191 filter_190 filter_189 filter_188 filter_187 filter_186 filter_185 filter_184 filter_183 filter_182 filter_181 filter_180 filter_179 filter_178 filter_177 filter_176
1514131211109876543210
filter_175 filter_174 filter_173 filter_172 filter_171 filter_170 filter_169 filter_168 filter_167 filter_166 filter_165 filter_164 filter_163 filter_162 filter_161 filter_160
BitsTypeResetNameDescription
0rw0x0filter_160

For SPI_DEVICE5

1rw0x0filter_161

For SPI_DEVICE5

2rw0x0filter_162

For SPI_DEVICE5

3rw0x0filter_163

For SPI_DEVICE5

4rw0x0filter_164

For SPI_DEVICE5

5rw0x0filter_165

For SPI_DEVICE5

6rw0x0filter_166

For SPI_DEVICE5

7rw0x0filter_167

For SPI_DEVICE5

8rw0x0filter_168

For SPI_DEVICE5

9rw0x0filter_169

For SPI_DEVICE5

10rw0x0filter_170

For SPI_DEVICE5

11rw0x0filter_171

For SPI_DEVICE5

12rw0x0filter_172

For SPI_DEVICE5

13rw0x0filter_173

For SPI_DEVICE5

14rw0x0filter_174

For SPI_DEVICE5

15rw0x0filter_175

For SPI_DEVICE5

16rw0x0filter_176

For SPI_DEVICE5

17rw0x0filter_177

For SPI_DEVICE5

18rw0x0filter_178

For SPI_DEVICE5

19rw0x0filter_179

For SPI_DEVICE5

20rw0x0filter_180

For SPI_DEVICE5

21rw0x0filter_181

For SPI_DEVICE5

22rw0x0filter_182

For SPI_DEVICE5

23rw0x0filter_183

For SPI_DEVICE5

24rw0x0filter_184

For SPI_DEVICE5

25rw0x0filter_185

For SPI_DEVICE5

26rw0x0filter_186

For SPI_DEVICE5

27rw0x0filter_187

For SPI_DEVICE5

28rw0x0filter_188

For SPI_DEVICE5

29rw0x0filter_189

For SPI_DEVICE5

30rw0x0filter_190

For SPI_DEVICE5

31rw0x0filter_191

For SPI_DEVICE5


SPI_DEVICE.CMD_FILTER_6 @ 0x78

Command Filter

Reset default = 0x0, mask 0xffffffff

If a bit in this CSR is 1, then corresponding SPI command w.r.t the bit position among 256 bit is dropped in SPI Passthrough mode.

31302928272625242322212019181716
filter_223 filter_222 filter_221 filter_220 filter_219 filter_218 filter_217 filter_216 filter_215 filter_214 filter_213 filter_212 filter_211 filter_210 filter_209 filter_208
1514131211109876543210
filter_207 filter_206 filter_205 filter_204 filter_203 filter_202 filter_201 filter_200 filter_199 filter_198 filter_197 filter_196 filter_195 filter_194 filter_193 filter_192
BitsTypeResetNameDescription
0rw0x0filter_192

For SPI_DEVICE6

1rw0x0filter_193

For SPI_DEVICE6

2rw0x0filter_194

For SPI_DEVICE6

3rw0x0filter_195

For SPI_DEVICE6

4rw0x0filter_196

For SPI_DEVICE6

5rw0x0filter_197

For SPI_DEVICE6

6rw0x0filter_198

For SPI_DEVICE6

7rw0x0filter_199

For SPI_DEVICE6

8rw0x0filter_200

For SPI_DEVICE6

9rw0x0filter_201

For SPI_DEVICE6

10rw0x0filter_202

For SPI_DEVICE6

11rw0x0filter_203

For SPI_DEVICE6

12rw0x0filter_204

For SPI_DEVICE6

13rw0x0filter_205

For SPI_DEVICE6

14rw0x0filter_206

For SPI_DEVICE6

15rw0x0filter_207

For SPI_DEVICE6

16rw0x0filter_208

For SPI_DEVICE6

17rw0x0filter_209

For SPI_DEVICE6

18rw0x0filter_210

For SPI_DEVICE6

19rw0x0filter_211

For SPI_DEVICE6

20rw0x0filter_212

For SPI_DEVICE6

21rw0x0filter_213

For SPI_DEVICE6

22rw0x0filter_214

For SPI_DEVICE6

23rw0x0filter_215

For SPI_DEVICE6

24rw0x0filter_216

For SPI_DEVICE6

25rw0x0filter_217

For SPI_DEVICE6

26rw0x0filter_218

For SPI_DEVICE6

27rw0x0filter_219

For SPI_DEVICE6

28rw0x0filter_220

For SPI_DEVICE6

29rw0x0filter_221

For SPI_DEVICE6

30rw0x0filter_222

For SPI_DEVICE6

31rw0x0filter_223

For SPI_DEVICE6


SPI_DEVICE.CMD_FILTER_7 @ 0x7c

Command Filter

Reset default = 0x0, mask 0xffffffff

If a bit in this CSR is 1, then corresponding SPI command w.r.t the bit position among 256 bit is dropped in SPI Passthrough mode.

31302928272625242322212019181716
filter_255 filter_254 filter_253 filter_252 filter_251 filter_250 filter_249 filter_248 filter_247 filter_246 filter_245 filter_244 filter_243 filter_242 filter_241 filter_240
1514131211109876543210
filter_239 filter_238 filter_237 filter_236 filter_235 filter_234 filter_233 filter_232 filter_231 filter_230 filter_229 filter_228 filter_227 filter_226 filter_225 filter_224
BitsTypeResetNameDescription
0rw0x0filter_224

For SPI_DEVICE7

1rw0x0filter_225

For SPI_DEVICE7

2rw0x0filter_226

For SPI_DEVICE7

3rw0x0filter_227

For SPI_DEVICE7

4rw0x0filter_228

For SPI_DEVICE7

5rw0x0filter_229

For SPI_DEVICE7

6rw0x0filter_230

For SPI_DEVICE7

7rw0x0filter_231

For SPI_DEVICE7

8rw0x0filter_232

For SPI_DEVICE7

9rw0x0filter_233

For SPI_DEVICE7

10rw0x0filter_234

For SPI_DEVICE7

11rw0x0filter_235

For SPI_DEVICE7

12rw0x0filter_236

For SPI_DEVICE7

13rw0x0filter_237

For SPI_DEVICE7

14rw0x0filter_238

For SPI_DEVICE7

15rw0x0filter_239

For SPI_DEVICE7

16rw0x0filter_240

For SPI_DEVICE7

17rw0x0filter_241

For SPI_DEVICE7

18rw0x0filter_242

For SPI_DEVICE7

19rw0x0filter_243

For SPI_DEVICE7

20rw0x0filter_244

For SPI_DEVICE7

21rw0x0filter_245

For SPI_DEVICE7

22rw0x0filter_246

For SPI_DEVICE7

23rw0x0filter_247

For SPI_DEVICE7

24rw0x0filter_248

For SPI_DEVICE7

25rw0x0filter_249

For SPI_DEVICE7

26rw0x0filter_250

For SPI_DEVICE7

27rw0x0filter_251

For SPI_DEVICE7

28rw0x0filter_252

For SPI_DEVICE7

29rw0x0filter_253

For SPI_DEVICE7

30rw0x0filter_254

For SPI_DEVICE7

31rw0x0filter_255

For SPI_DEVICE7


SPI_DEVICE.ADDR_SWAP_MASK @ 0x80

Address Swap Mask register.

Reset default = 0x0, mask 0xffffffff

This register is used in the SPI passthrough mode. If any of bits in this register is set, the corresponding address bit in the SPI Read commands is replaced with the data from ADDR_SWAP_DATA.

If 3B address mode is active, upper 8bit [31:24] is ignored.

31302928272625242322212019181716
mask...
1514131211109876543210
...mask
BitsTypeResetNameDescription
31:0rw0x0mask

When a bit is 1, the SPI read address to the downstream SPI Flash device is swapped to ADDR_SWAP_DATA.


SPI_DEVICE.ADDR_SWAP_DATA @ 0x84

The address value for the address swap feature.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
data...
1514131211109876543210
...data
BitsTypeResetNameDescription
31:0rw0x0data

Desired value to be swapped for the SPI read commands.


SPI_DEVICE.PAYLOAD_SWAP_MASK @ 0x88

Write Data Swap in the passthrough mode.

Reset default = 0x0, mask 0xffffffff

PAYLOAD_SWAP_MASK CSR provides the SW to change certain bits in the first 4 bytes of the write payload in the passthrough mode.

31302928272625242322212019181716
mask...
1514131211109876543210
...mask
BitsTypeResetNameDescription
31:0rw0x0mask

byte mask


SPI_DEVICE.PAYLOAD_SWAP_DATA @ 0x8c

Write Data Swap in the passthrough mode.

Reset default = 0x0, mask 0xffffffff

PAYLOAD_SWAP_DATA combined with PAYLOAD_SWAP_MASK provides the SW to change certain bits in the first 4 bytes of the write payload in the passthrough mode.

The register should be written in Little-Endian order. [7:0] bits are processed in the first received payload byte. [31:24] bits for the 4th byte.

31302928272625242322212019181716
data...
1514131211109876543210
...data
BitsTypeResetNameDescription
31:0rw0x0data

replaced data


SPI_DEVICE.CMD_INFO_0 @ 0x90

Command Info register.

Reset default = 0x7000, mask 0x833fffff
31302928272625242322212019181716
valid_0   busy_0 upload_0   payload_swap_en_0 payload_dir_0 payload_en_0
1514131211109876543210
dummy_en_0 dummy_size_0 mbyte_en_0 addr_swap_en_0 addr_mode_0 opcode_0
BitsTypeResetNameDescription
7:0rw0x0opcode_0

Command Opcode

9:8rw0x0addr_mode_0

Command address mode

A command can have four modes:

  • 0: Command does not have an address field
  • 1: CFG.addr_4b_en decides the address size (3B/4B)
  • 2: Address size is always 3B regardless of CFG.addr_4b_en
  • 3: Address size is always 4B regardless of CFG.addr_4b_en

0x0AddrDisabled

Address field does not exist

0x1AddrCfg

CFG.addr_4b_en determines the address size

0x2Addr3B

Address size in the command is always 3B.

0x3Addr4B

Address size in the command is always 4B.

10rw0x0addr_swap_en_0

This field is used in the passthrough logic. If this field is set to 1, the address in the passthrough command is replaced to the preconfigured value.

11rw0x0mbyte_en_0

If 1, the command has a MByte field following the address field. This is set to 1 for DualIO, QuadIO commands.

14:12rw0x7dummy_size_0

The number of dummy cycles -1 for the command

15rw0x0dummy_en_0

Set to 1 if the command has a dummy cycle following the address field.

19:16rw0x0payload_en_0

Payload Enable per SPI lane.

Set to non-zero if the command has payload at the end of the protocol. This field has four bits. Each bit represents the SPI line. If a command is a Single IO command and returns data to the host system, the data is returned on the MISO line (IO[1]). In this case, SW sets payload_en to 4'b 0010.

20rw0x0payload_dir_0

Set to 1 if the command returns data. If 0, the payload sends to the downstream Flash device.

0x0PayloadIn

From host to the downstream flash device

0x1PayloadOut

From the downstream flash device to the host

21rw0x0payload_swap_en_0

Swap the first byte of the write payload.

If payload_swap_en is set, the passthrough logic swaps the first byte of the write payload with DATA_SWAP CSR.

payload_swap_en only works with write data and SingleIO mode. payload_en must be 4'b 0001 and paylod_dir to be PayloadIn.

23:22Reserved
24rw0x0upload_0

Set to 1 to upload the command.

If upload field in the command info entry is set, the cmdparse activates the upload submodule when the opcode is received. addr_en, addr_4B_affected, and addr_4b_forced (TBD) affect the upload functionality. The three address related configs defines the command address field size.

The logic assumes the following SPI input stream as payload, which max size is 256B. If the command exceeds the maximum payload size 256B, the logic wraps the payload and overwrites.

25rw0x0busy_0

Set to 1 to set the BUSY bit in the FLASH_STATUS when the command is received. This bit is active only when upload bit is set.

30:26Reserved
31rw0x0valid_0

Set to 1 if the config in the register is valid


SPI_DEVICE.CMD_INFO_1 @ 0x94

Command Info register.

Reset default = 0x7000, mask 0x833fffff
31302928272625242322212019181716
valid_1   busy_1 upload_1   payload_swap_en_1 payload_dir_1 payload_en_1
1514131211109876543210
dummy_en_1 dummy_size_1 mbyte_en_1 addr_swap_en_1 addr_mode_1 opcode_1
BitsTypeResetNameDescription
7:0rw0x0opcode_1

For SPI_DEVICE1

9:8rw0x0addr_mode_1

For SPI_DEVICE1

10rw0x0addr_swap_en_1

For SPI_DEVICE1

11rw0x0mbyte_en_1

For SPI_DEVICE1

14:12rw0x7dummy_size_1

For SPI_DEVICE1

15rw0x0dummy_en_1

For SPI_DEVICE1

19:16rw0x0payload_en_1

For SPI_DEVICE1

20rw0x0payload_dir_1

For SPI_DEVICE1

21rw0x0payload_swap_en_1

For SPI_DEVICE1

23:22Reserved
24rw0x0upload_1

For SPI_DEVICE1

25rw0x0busy_1

For SPI_DEVICE1

30:26Reserved
31rw0x0valid_1

For SPI_DEVICE1


SPI_DEVICE.CMD_INFO_2 @ 0x98

Command Info register.

Reset default = 0x7000, mask 0x833fffff
31302928272625242322212019181716
valid_2   busy_2 upload_2   payload_swap_en_2 payload_dir_2 payload_en_2
1514131211109876543210
dummy_en_2 dummy_size_2 mbyte_en_2 addr_swap_en_2 addr_mode_2 opcode_2
BitsTypeResetNameDescription
7:0rw0x0opcode_2

For SPI_DEVICE2

9:8rw0x0addr_mode_2

For SPI_DEVICE2

10rw0x0addr_swap_en_2

For SPI_DEVICE2

11rw0x0mbyte_en_2

For SPI_DEVICE2

14:12rw0x7dummy_size_2

For SPI_DEVICE2

15rw0x0dummy_en_2

For SPI_DEVICE2

19:16rw0x0payload_en_2

For SPI_DEVICE2

20rw0x0payload_dir_2

For SPI_DEVICE2

21rw0x0payload_swap_en_2

For SPI_DEVICE2

23:22Reserved
24rw0x0upload_2

For SPI_DEVICE2

25rw0x0busy_2

For SPI_DEVICE2

30:26Reserved
31rw0x0valid_2

For SPI_DEVICE2


SPI_DEVICE.CMD_INFO_3 @ 0x9c

Command Info register.

Reset default = 0x7000, mask 0x833fffff
31302928272625242322212019181716
valid_3   busy_3 upload_3   payload_swap_en_3 payload_dir_3 payload_en_3
1514131211109876543210
dummy_en_3 dummy_size_3 mbyte_en_3 addr_swap_en_3 addr_mode_3 opcode_3
BitsTypeResetNameDescription
7:0rw0x0opcode_3

For SPI_DEVICE3

9:8rw0x0addr_mode_3

For SPI_DEVICE3

10rw0x0addr_swap_en_3

For SPI_DEVICE3

11rw0x0mbyte_en_3

For SPI_DEVICE3

14:12rw0x7dummy_size_3

For SPI_DEVICE3

15rw0x0dummy_en_3

For SPI_DEVICE3

19:16rw0x0payload_en_3

For SPI_DEVICE3

20rw0x0payload_dir_3

For SPI_DEVICE3

21rw0x0payload_swap_en_3

For SPI_DEVICE3

23:22Reserved
24rw0x0upload_3

For SPI_DEVICE3

25rw0x0busy_3

For SPI_DEVICE3

30:26Reserved
31rw0x0valid_3

For SPI_DEVICE3


SPI_DEVICE.CMD_INFO_4 @ 0xa0

Command Info register.

Reset default = 0x7000, mask 0x833fffff
31302928272625242322212019181716
valid_4   busy_4 upload_4   payload_swap_en_4 payload_dir_4 payload_en_4
1514131211109876543210
dummy_en_4 dummy_size_4 mbyte_en_4 addr_swap_en_4 addr_mode_4 opcode_4
BitsTypeResetNameDescription
7:0rw0x0opcode_4

For SPI_DEVICE4

9:8rw0x0addr_mode_4

For SPI_DEVICE4

10rw0x0addr_swap_en_4

For SPI_DEVICE4

11rw0x0mbyte_en_4

For SPI_DEVICE4

14:12rw0x7dummy_size_4

For SPI_DEVICE4

15rw0x0dummy_en_4

For SPI_DEVICE4

19:16rw0x0payload_en_4

For SPI_DEVICE4

20rw0x0payload_dir_4

For SPI_DEVICE4

21rw0x0payload_swap_en_4

For SPI_DEVICE4

23:22Reserved
24rw0x0upload_4

For SPI_DEVICE4

25rw0x0busy_4

For SPI_DEVICE4

30:26Reserved
31rw0x0valid_4

For SPI_DEVICE4


SPI_DEVICE.CMD_INFO_5 @ 0xa4

Command Info register.

Reset default = 0x7000, mask 0x833fffff
31302928272625242322212019181716
valid_5   busy_5 upload_5   payload_swap_en_5 payload_dir_5 payload_en_5
1514131211109876543210
dummy_en_5 dummy_size_5 mbyte_en_5 addr_swap_en_5 addr_mode_5 opcode_5
BitsTypeResetNameDescription
7:0rw0x0opcode_5

For SPI_DEVICE5

9:8rw0x0addr_mode_5

For SPI_DEVICE5

10rw0x0addr_swap_en_5

For SPI_DEVICE5

11rw0x0mbyte_en_5

For SPI_DEVICE5

14:12rw0x7dummy_size_5

For SPI_DEVICE5

15rw0x0dummy_en_5

For SPI_DEVICE5

19:16rw0x0payload_en_5

For SPI_DEVICE5

20rw0x0payload_dir_5

For SPI_DEVICE5

21rw0x0payload_swap_en_5

For SPI_DEVICE5

23:22Reserved
24rw0x0upload_5

For SPI_DEVICE5

25rw0x0busy_5

For SPI_DEVICE5

30:26Reserved
31rw0x0valid_5

For SPI_DEVICE5


SPI_DEVICE.CMD_INFO_6 @ 0xa8

Command Info register.

Reset default = 0x7000, mask 0x833fffff
31302928272625242322212019181716
valid_6   busy_6 upload_6   payload_swap_en_6 payload_dir_6 payload_en_6
1514131211109876543210
dummy_en_6 dummy_size_6 mbyte_en_6 addr_swap_en_6 addr_mode_6 opcode_6
BitsTypeResetNameDescription
7:0rw0x0opcode_6

For SPI_DEVICE6

9:8rw0x0addr_mode_6

For SPI_DEVICE6

10rw0x0addr_swap_en_6

For SPI_DEVICE6

11rw0x0mbyte_en_6

For SPI_DEVICE6

14:12rw0x7dummy_size_6

For SPI_DEVICE6

15rw0x0dummy_en_6

For SPI_DEVICE6

19:16rw0x0payload_en_6

For SPI_DEVICE6

20rw0x0payload_dir_6

For SPI_DEVICE6

21rw0x0payload_swap_en_6

For SPI_DEVICE6

23:22Reserved
24rw0x0upload_6

For SPI_DEVICE6

25rw0x0busy_6

For SPI_DEVICE6

30:26Reserved
31rw0x0valid_6

For SPI_DEVICE6


SPI_DEVICE.CMD_INFO_7 @ 0xac

Command Info register.

Reset default = 0x7000, mask 0x833fffff
31302928272625242322212019181716
valid_7   busy_7 upload_7   payload_swap_en_7 payload_dir_7 payload_en_7
1514131211109876543210
dummy_en_7 dummy_size_7 mbyte_en_7 addr_swap_en_7 addr_mode_7 opcode_7
BitsTypeResetNameDescription
7:0rw0x0opcode_7

For SPI_DEVICE7

9:8rw0x0addr_mode_7

For SPI_DEVICE7

10rw0x0addr_swap_en_7

For SPI_DEVICE7

11rw0x0mbyte_en_7

For SPI_DEVICE7

14:12rw0x7dummy_size_7

For SPI_DEVICE7

15rw0x0dummy_en_7

For SPI_DEVICE7

19:16rw0x0payload_en_7

For SPI_DEVICE7

20rw0x0payload_dir_7

For SPI_DEVICE7

21rw0x0payload_swap_en_7

For SPI_DEVICE7

23:22Reserved
24rw0x0upload_7

For SPI_DEVICE7

25rw0x0busy_7

For SPI_DEVICE7

30:26Reserved
31rw0x0valid_7

For SPI_DEVICE7


SPI_DEVICE.CMD_INFO_8 @ 0xb0

Command Info register.

Reset default = 0x7000, mask 0x833fffff
31302928272625242322212019181716
valid_8   busy_8 upload_8   payload_swap_en_8 payload_dir_8 payload_en_8
1514131211109876543210
dummy_en_8 dummy_size_8 mbyte_en_8 addr_swap_en_8 addr_mode_8 opcode_8
BitsTypeResetNameDescription
7:0rw0x0opcode_8

For SPI_DEVICE8

9:8rw0x0addr_mode_8

For SPI_DEVICE8

10rw0x0addr_swap_en_8

For SPI_DEVICE8

11rw0x0mbyte_en_8

For SPI_DEVICE8

14:12rw0x7dummy_size_8

For SPI_DEVICE8

15rw0x0dummy_en_8

For SPI_DEVICE8

19:16rw0x0payload_en_8

For SPI_DEVICE8

20rw0x0payload_dir_8

For SPI_DEVICE8

21rw0x0payload_swap_en_8

For SPI_DEVICE8

23:22Reserved
24rw0x0upload_8

For SPI_DEVICE8

25rw0x0busy_8

For SPI_DEVICE8

30:26Reserved
31rw0x0valid_8

For SPI_DEVICE8


SPI_DEVICE.CMD_INFO_9 @ 0xb4

Command Info register.

Reset default = 0x7000, mask 0x833fffff
31302928272625242322212019181716
valid_9   busy_9 upload_9   payload_swap_en_9 payload_dir_9 payload_en_9
1514131211109876543210
dummy_en_9 dummy_size_9 mbyte_en_9 addr_swap_en_9 addr_mode_9 opcode_9
BitsTypeResetNameDescription
7:0rw0x0opcode_9

For SPI_DEVICE9

9:8rw0x0addr_mode_9

For SPI_DEVICE9

10rw0x0addr_swap_en_9

For SPI_DEVICE9

11rw0x0mbyte_en_9

For SPI_DEVICE9

14:12rw0x7dummy_size_9

For SPI_DEVICE9

15rw0x0dummy_en_9

For SPI_DEVICE9

19:16rw0x0payload_en_9

For SPI_DEVICE9

20rw0x0payload_dir_9

For SPI_DEVICE9

21rw0x0payload_swap_en_9

For SPI_DEVICE9

23:22Reserved
24rw0x0upload_9

For SPI_DEVICE9

25rw0x0busy_9

For SPI_DEVICE9

30:26Reserved
31rw0x0valid_9

For SPI_DEVICE9


SPI_DEVICE.CMD_INFO_10 @ 0xb8

Command Info register.

Reset default = 0x7000, mask 0x833fffff
31302928272625242322212019181716
valid_10   busy_10 upload_10   payload_swap_en_10 payload_dir_10 payload_en_10
1514131211109876543210
dummy_en_10 dummy_size_10 mbyte_en_10 addr_swap_en_10 addr_mode_10 opcode_10
BitsTypeResetNameDescription
7:0rw0x0opcode_10

For SPI_DEVICE10

9:8rw0x0addr_mode_10

For SPI_DEVICE10

10rw0x0addr_swap_en_10

For SPI_DEVICE10

11rw0x0mbyte_en_10

For SPI_DEVICE10

14:12rw0x7dummy_size_10

For SPI_DEVICE10

15rw0x0dummy_en_10

For SPI_DEVICE10

19:16rw0x0payload_en_10

For SPI_DEVICE10

20rw0x0payload_dir_10

For SPI_DEVICE10

21rw0x0payload_swap_en_10

For SPI_DEVICE10

23:22Reserved
24rw0x0upload_10

For SPI_DEVICE10

25rw0x0busy_10

For SPI_DEVICE10

30:26Reserved
31rw0x0valid_10

For SPI_DEVICE10


SPI_DEVICE.CMD_INFO_11 @ 0xbc

Command Info register.

Reset default = 0x7000, mask 0x833fffff
31302928272625242322212019181716
valid_11   busy_11 upload_11   payload_swap_en_11 payload_dir_11 payload_en_11
1514131211109876543210
dummy_en_11 dummy_size_11 mbyte_en_11 addr_swap_en_11 addr_mode_11 opcode_11
BitsTypeResetNameDescription
7:0rw0x0opcode_11

For SPI_DEVICE11

9:8rw0x0addr_mode_11

For SPI_DEVICE11

10rw0x0addr_swap_en_11

For SPI_DEVICE11

11rw0x0mbyte_en_11

For SPI_DEVICE11

14:12rw0x7dummy_size_11

For SPI_DEVICE11

15rw0x0dummy_en_11

For SPI_DEVICE11

19:16rw0x0payload_en_11

For SPI_DEVICE11

20rw0x0payload_dir_11

For SPI_DEVICE11

21rw0x0payload_swap_en_11

For SPI_DEVICE11

23:22Reserved
24rw0x0upload_11

For SPI_DEVICE11

25rw0x0busy_11

For SPI_DEVICE11

30:26Reserved
31rw0x0valid_11

For SPI_DEVICE11


SPI_DEVICE.CMD_INFO_12 @ 0xc0

Command Info register.

Reset default = 0x7000, mask 0x833fffff
31302928272625242322212019181716
valid_12   busy_12 upload_12   payload_swap_en_12 payload_dir_12 payload_en_12
1514131211109876543210
dummy_en_12 dummy_size_12 mbyte_en_12 addr_swap_en_12 addr_mode_12 opcode_12
BitsTypeResetNameDescription
7:0rw0x0opcode_12

For SPI_DEVICE12

9:8rw0x0addr_mode_12

For SPI_DEVICE12

10rw0x0addr_swap_en_12

For SPI_DEVICE12

11rw0x0mbyte_en_12

For SPI_DEVICE12

14:12rw0x7dummy_size_12

For SPI_DEVICE12

15rw0x0dummy_en_12

For SPI_DEVICE12

19:16rw0x0payload_en_12

For SPI_DEVICE12

20rw0x0payload_dir_12

For SPI_DEVICE12

21rw0x0payload_swap_en_12

For SPI_DEVICE12

23:22Reserved
24rw0x0upload_12

For SPI_DEVICE12

25rw0x0busy_12

For SPI_DEVICE12

30:26Reserved
31rw0x0valid_12

For SPI_DEVICE12


SPI_DEVICE.CMD_INFO_13 @ 0xc4

Command Info register.

Reset default = 0x7000, mask 0x833fffff
31302928272625242322212019181716
valid_13   busy_13 upload_13   payload_swap_en_13 payload_dir_13 payload_en_13
1514131211109876543210
dummy_en_13 dummy_size_13 mbyte_en_13 addr_swap_en_13 addr_mode_13 opcode_13
BitsTypeResetNameDescription
7:0rw0x0opcode_13

For SPI_DEVICE13

9:8rw0x0addr_mode_13

For SPI_DEVICE13

10rw0x0addr_swap_en_13

For SPI_DEVICE13

11rw0x0mbyte_en_13

For SPI_DEVICE13

14:12rw0x7dummy_size_13

For SPI_DEVICE13

15rw0x0dummy_en_13

For SPI_DEVICE13

19:16rw0x0payload_en_13

For SPI_DEVICE13

20rw0x0payload_dir_13

For SPI_DEVICE13

21rw0x0payload_swap_en_13

For SPI_DEVICE13

23:22Reserved
24rw0x0upload_13

For SPI_DEVICE13

25rw0x0busy_13

For SPI_DEVICE13

30:26Reserved
31rw0x0valid_13

For SPI_DEVICE13


SPI_DEVICE.CMD_INFO_14 @ 0xc8

Command Info register.

Reset default = 0x7000, mask 0x833fffff
31302928272625242322212019181716
valid_14   busy_14 upload_14   payload_swap_en_14 payload_dir_14 payload_en_14
1514131211109876543210
dummy_en_14 dummy_size_14 mbyte_en_14 addr_swap_en_14 addr_mode_14 opcode_14
BitsTypeResetNameDescription
7:0rw0x0opcode_14

For SPI_DEVICE14

9:8rw0x0addr_mode_14

For SPI_DEVICE14

10rw0x0addr_swap_en_14

For SPI_DEVICE14

11rw0x0mbyte_en_14

For SPI_DEVICE14

14:12rw0x7dummy_size_14

For SPI_DEVICE14

15rw0x0dummy_en_14

For SPI_DEVICE14

19:16rw0x0payload_en_14

For SPI_DEVICE14

20rw0x0payload_dir_14

For SPI_DEVICE14

21rw0x0payload_swap_en_14

For SPI_DEVICE14

23:22Reserved
24rw0x0upload_14

For SPI_DEVICE14

25rw0x0busy_14

For SPI_DEVICE14

30:26Reserved
31rw0x0valid_14

For SPI_DEVICE14


SPI_DEVICE.CMD_INFO_15 @ 0xcc

Command Info register.

Reset default = 0x7000, mask 0x833fffff
31302928272625242322212019181716
valid_15   busy_15 upload_15   payload_swap_en_15 payload_dir_15 payload_en_15
1514131211109876543210
dummy_en_15 dummy_size_15 mbyte_en_15 addr_swap_en_15 addr_mode_15 opcode_15
BitsTypeResetNameDescription
7:0rw0x0opcode_15

For SPI_DEVICE15

9:8rw0x0addr_mode_15

For SPI_DEVICE15

10rw0x0addr_swap_en_15

For SPI_DEVICE15

11rw0x0mbyte_en_15

For SPI_DEVICE15

14:12rw0x7dummy_size_15

For SPI_DEVICE15

15rw0x0dummy_en_15

For SPI_DEVICE15

19:16rw0x0payload_en_15

For SPI_DEVICE15

20rw0x0payload_dir_15

For SPI_DEVICE15

21rw0x0payload_swap_en_15

For SPI_DEVICE15

23:22Reserved
24rw0x0upload_15

For SPI_DEVICE15

25rw0x0busy_15

For SPI_DEVICE15

30:26Reserved
31rw0x0valid_15

For SPI_DEVICE15


SPI_DEVICE.CMD_INFO_16 @ 0xd0

Command Info register.

Reset default = 0x7000, mask 0x833fffff
31302928272625242322212019181716
valid_16   busy_16 upload_16   payload_swap_en_16 payload_dir_16 payload_en_16
1514131211109876543210
dummy_en_16 dummy_size_16 mbyte_en_16 addr_swap_en_16 addr_mode_16 opcode_16
BitsTypeResetNameDescription
7:0rw0x0opcode_16

For SPI_DEVICE16

9:8rw0x0addr_mode_16

For SPI_DEVICE16

10rw0x0addr_swap_en_16

For SPI_DEVICE16

11rw0x0mbyte_en_16

For SPI_DEVICE16

14:12rw0x7dummy_size_16

For SPI_DEVICE16

15rw0x0dummy_en_16

For SPI_DEVICE16

19:16rw0x0payload_en_16

For SPI_DEVICE16

20rw0x0payload_dir_16

For SPI_DEVICE16

21rw0x0payload_swap_en_16

For SPI_DEVICE16

23:22Reserved
24rw0x0upload_16

For SPI_DEVICE16

25rw0x0busy_16

For SPI_DEVICE16

30:26Reserved
31rw0x0valid_16

For SPI_DEVICE16


SPI_DEVICE.CMD_INFO_17 @ 0xd4

Command Info register.

Reset default = 0x7000, mask 0x833fffff
31302928272625242322212019181716
valid_17   busy_17 upload_17   payload_swap_en_17 payload_dir_17 payload_en_17
1514131211109876543210
dummy_en_17 dummy_size_17 mbyte_en_17 addr_swap_en_17 addr_mode_17 opcode_17
BitsTypeResetNameDescription
7:0rw0x0opcode_17

For SPI_DEVICE17

9:8rw0x0addr_mode_17

For SPI_DEVICE17

10rw0x0addr_swap_en_17

For SPI_DEVICE17

11rw0x0mbyte_en_17

For SPI_DEVICE17

14:12rw0x7dummy_size_17

For SPI_DEVICE17

15rw0x0dummy_en_17

For SPI_DEVICE17

19:16rw0x0payload_en_17

For SPI_DEVICE17

20rw0x0payload_dir_17

For SPI_DEVICE17

21rw0x0payload_swap_en_17

For SPI_DEVICE17

23:22Reserved
24rw0x0upload_17

For SPI_DEVICE17

25rw0x0busy_17

For SPI_DEVICE17

30:26Reserved
31rw0x0valid_17

For SPI_DEVICE17


SPI_DEVICE.CMD_INFO_18 @ 0xd8

Command Info register.

Reset default = 0x7000, mask 0x833fffff
31302928272625242322212019181716
valid_18   busy_18 upload_18   payload_swap_en_18 payload_dir_18 payload_en_18
1514131211109876543210
dummy_en_18 dummy_size_18 mbyte_en_18 addr_swap_en_18 addr_mode_18 opcode_18
BitsTypeResetNameDescription
7:0rw0x0opcode_18

For SPI_DEVICE18

9:8rw0x0addr_mode_18

For SPI_DEVICE18

10rw0x0addr_swap_en_18

For SPI_DEVICE18

11rw0x0mbyte_en_18

For SPI_DEVICE18

14:12rw0x7dummy_size_18

For SPI_DEVICE18

15rw0x0dummy_en_18

For SPI_DEVICE18

19:16rw0x0payload_en_18

For SPI_DEVICE18

20rw0x0payload_dir_18

For SPI_DEVICE18

21rw0x0payload_swap_en_18

For SPI_DEVICE18

23:22Reserved
24rw0x0upload_18

For SPI_DEVICE18

25rw0x0busy_18

For SPI_DEVICE18

30:26Reserved
31rw0x0valid_18

For SPI_DEVICE18


SPI_DEVICE.CMD_INFO_19 @ 0xdc

Command Info register.

Reset default = 0x7000, mask 0x833fffff
31302928272625242322212019181716
valid_19   busy_19 upload_19   payload_swap_en_19 payload_dir_19 payload_en_19
1514131211109876543210
dummy_en_19 dummy_size_19 mbyte_en_19 addr_swap_en_19 addr_mode_19 opcode_19
BitsTypeResetNameDescription
7:0rw0x0opcode_19

For SPI_DEVICE19

9:8rw0x0addr_mode_19

For SPI_DEVICE19

10rw0x0addr_swap_en_19

For SPI_DEVICE19

11rw0x0mbyte_en_19

For SPI_DEVICE19

14:12rw0x7dummy_size_19

For SPI_DEVICE19

15rw0x0dummy_en_19

For SPI_DEVICE19

19:16rw0x0payload_en_19

For SPI_DEVICE19

20rw0x0payload_dir_19

For SPI_DEVICE19

21rw0x0payload_swap_en_19

For SPI_DEVICE19

23:22Reserved
24rw0x0upload_19

For SPI_DEVICE19

25rw0x0busy_19

For SPI_DEVICE19

30:26Reserved
31rw0x0valid_19

For SPI_DEVICE19


SPI_DEVICE.CMD_INFO_20 @ 0xe0

Command Info register.

Reset default = 0x7000, mask 0x833fffff
31302928272625242322212019181716
valid_20   busy_20 upload_20   payload_swap_en_20 payload_dir_20 payload_en_20
1514131211109876543210
dummy_en_20 dummy_size_20 mbyte_en_20 addr_swap_en_20 addr_mode_20 opcode_20
BitsTypeResetNameDescription
7:0rw0x0opcode_20

For SPI_DEVICE20

9:8rw0x0addr_mode_20

For SPI_DEVICE20

10rw0x0addr_swap_en_20

For SPI_DEVICE20

11rw0x0mbyte_en_20

For SPI_DEVICE20

14:12rw0x7dummy_size_20

For SPI_DEVICE20

15rw0x0dummy_en_20

For SPI_DEVICE20

19:16rw0x0payload_en_20

For SPI_DEVICE20

20rw0x0payload_dir_20

For SPI_DEVICE20

21rw0x0payload_swap_en_20

For SPI_DEVICE20

23:22Reserved
24rw0x0upload_20

For SPI_DEVICE20

25rw0x0busy_20

For SPI_DEVICE20

30:26Reserved
31rw0x0valid_20

For SPI_DEVICE20


SPI_DEVICE.CMD_INFO_21 @ 0xe4

Command Info register.

Reset default = 0x7000, mask 0x833fffff
31302928272625242322212019181716
valid_21   busy_21 upload_21   payload_swap_en_21 payload_dir_21 payload_en_21
1514131211109876543210
dummy_en_21 dummy_size_21 mbyte_en_21 addr_swap_en_21 addr_mode_21 opcode_21
BitsTypeResetNameDescription
7:0rw0x0opcode_21

For SPI_DEVICE21

9:8rw0x0addr_mode_21

For SPI_DEVICE21

10rw0x0addr_swap_en_21

For SPI_DEVICE21

11rw0x0mbyte_en_21

For SPI_DEVICE21

14:12rw0x7dummy_size_21

For SPI_DEVICE21

15rw0x0dummy_en_21

For SPI_DEVICE21

19:16rw0x0payload_en_21

For SPI_DEVICE21

20rw0x0payload_dir_21

For SPI_DEVICE21

21rw0x0payload_swap_en_21

For SPI_DEVICE21

23:22Reserved
24rw0x0upload_21

For SPI_DEVICE21

25rw0x0busy_21

For SPI_DEVICE21

30:26Reserved
31rw0x0valid_21

For SPI_DEVICE21


SPI_DEVICE.CMD_INFO_22 @ 0xe8

Command Info register.

Reset default = 0x7000, mask 0x833fffff
31302928272625242322212019181716
valid_22   busy_22 upload_22   payload_swap_en_22 payload_dir_22 payload_en_22
1514131211109876543210
dummy_en_22 dummy_size_22 mbyte_en_22 addr_swap_en_22 addr_mode_22 opcode_22
BitsTypeResetNameDescription
7:0rw0x0opcode_22

For SPI_DEVICE22

9:8rw0x0addr_mode_22

For SPI_DEVICE22

10rw0x0addr_swap_en_22

For SPI_DEVICE22

11rw0x0mbyte_en_22

For SPI_DEVICE22

14:12rw0x7dummy_size_22

For SPI_DEVICE22

15rw0x0dummy_en_22

For SPI_DEVICE22

19:16rw0x0payload_en_22

For SPI_DEVICE22

20rw0x0payload_dir_22

For SPI_DEVICE22

21rw0x0payload_swap_en_22

For SPI_DEVICE22

23:22Reserved
24rw0x0upload_22

For SPI_DEVICE22

25rw0x0busy_22

For SPI_DEVICE22

30:26Reserved
31rw0x0valid_22

For SPI_DEVICE22


SPI_DEVICE.CMD_INFO_23 @ 0xec

Command Info register.

Reset default = 0x7000, mask 0x833fffff
31302928272625242322212019181716
valid_23   busy_23 upload_23   payload_swap_en_23 payload_dir_23 payload_en_23
1514131211109876543210
dummy_en_23 dummy_size_23 mbyte_en_23 addr_swap_en_23 addr_mode_23 opcode_23
BitsTypeResetNameDescription
7:0rw0x0opcode_23

For SPI_DEVICE23

9:8rw0x0addr_mode_23

For SPI_DEVICE23

10rw0x0addr_swap_en_23

For SPI_DEVICE23

11rw0x0mbyte_en_23

For SPI_DEVICE23

14:12rw0x7dummy_size_23

For SPI_DEVICE23

15rw0x0dummy_en_23

For SPI_DEVICE23

19:16rw0x0payload_en_23

For SPI_DEVICE23

20rw0x0payload_dir_23

For SPI_DEVICE23

21rw0x0payload_swap_en_23

For SPI_DEVICE23

23:22Reserved
24rw0x0upload_23

For SPI_DEVICE23

25rw0x0busy_23

For SPI_DEVICE23

30:26Reserved
31rw0x0valid_23

For SPI_DEVICE23


SPI_DEVICE.CMD_INFO_EN4B @ 0xf0

Opcode for EN4B.

Reset default = 0x0, mask 0x800000ff

If the register is active, it affects in flash / passthrough modes.

31302928272625242322212019181716
valid  
1514131211109876543210
  opcode
BitsTypeResetNameDescription
7:0rw0x0opcode

EN4B opcode

30:8Reserved
31rw0x0valid

If 1, Opcode affects


SPI_DEVICE.CMD_INFO_EX4B @ 0xf4

Opcode for EX4B

Reset default = 0x0, mask 0x800000ff
31302928272625242322212019181716
valid  
1514131211109876543210
  opcode
BitsTypeResetNameDescription
7:0rw0x0opcode

EX4B opcode

30:8Reserved
31rw0x0valid

If 1, Opcode affects


SPI_DEVICE.CMD_INFO_WREN @ 0xf8

Opcode for Write Enable (WREN)

Reset default = 0x0, mask 0x800000ff
31302928272625242322212019181716
valid  
1514131211109876543210
  opcode
BitsTypeResetNameDescription
7:0rw0x0opcode

WREN opcode

30:8Reserved
31rw0x0valid

If 1, opcode affects


SPI_DEVICE.CMD_INFO_WRDI @ 0xfc

Opcode for Write Disable (WRDI)

Reset default = 0x0, mask 0x800000ff
31302928272625242322212019181716
valid  
1514131211109876543210
  opcode
BitsTypeResetNameDescription
7:0rw0x0opcode

WRDI opcode

30:8Reserved
31rw0x0valid

If 1, opcode affects


SPI_DEVICE.TPM_CAP @ 0x800

TPM HWIP Capability register.

Reset default = 0x660100, mask 0x7701ff

This register shows the features the current TPM HWIP supports.

31302928272625242322212019181716
  max_rd_size   max_wr_size
1514131211109876543210
  locality rev
BitsTypeResetNameDescription
7:0ro0x0rev

Revision of the TPM submodule

8ro0x1locality

If 1, the TPM submodule supports 5 Locality. If 0, only one Locality is provided

15:9Reserved
18:16ro0x6max_wr_size

The maximum write size in bytes the TPM submodule supports. The value is the exponent of the 2.

  • 3'b 010: Support up to 4B
  • 3'b 011: Support up to 8B
  • 3'b 100: Support up to 16B
  • 3'b 101: Support up to 32B
  • 3'b 110: Support up to 64B

All other values are reserved.

It is not recommended for SW to advertise TPM supporting more than max_wr_size to the South Bridge.

19Reserved
22:20ro0x6max_rd_size

The maximum read size in bytes the TPM submodule supports. The value is the exponent of the 2.

  • 3'b 010: Support up to 4B
  • 3'b 011: Support up to 8B
  • 3'b 100: Support up to 16B
  • 3'b 101: Support up to 32B
  • 3'b 110: Support up to 64B

All other values are reserved.

It is not recommended for SW to advertise TPM supporting more than max_rd_size to the South Bridge.


SPI_DEVICE.TPM_CFG @ 0x804

TPM Configuration register.

Reset default = 0x0, mask 0x1f
31302928272625242322212019181716
 
1514131211109876543210
  invalid_locality tpm_reg_chk_dis hw_reg_dis tpm_mode en
BitsTypeResetNameDescription
0rw0x0en

If 1, TPM submodule accepts the transactions over SPI

1rw0x0tpm_mode

Configure the TPM mode. 1 for CRB, 0 for FIFO.

If the SW set this field to 1, the HW logic always pushes the command/addr and write data to buffers. The logic does not compare the incoming address to the list of managed-by-HW register addresses.

The invalid locality check still runs based on the invalid_locality configuration.

2rw0x0hw_reg_dis

If 0, TPM submodule directly returns the return-by-HW registers for the read requests.

If 1, TPM submodule uploads the TPM command regardless of the address, and the SW may return the value through the read FIFO.

3rw0x0tpm_reg_chk_dis

If 1, the logic does not compare the upper 8 bit of the received address with the TpmAddr constant, D4h.

If this field is 0, the HW uploads the command, address, and write payload to the buffers in case of address that is not 0xD4_XXXX.

4rw0x0invalid_locality

If 1, TPM submodule returns the invalid data (0xFF) for the out of the max Locality request. If it is a write request, HW still uploads the command and address. SW needs to process the incoming invalid command.

If 0, TPM submodule uploads the TPM command and address. The SW may write 0xFF to the read FIFO.

Note: The TPM submodule uploads the TPM commands that do not fall into the FIFO registers (0xD4_XXXX) regardless of invalid_locality bit.


SPI_DEVICE.TPM_STATUS @ 0x808

TPM submodule state register.

Reset default = 0x0, mask 0x7f1f03

The TPM_STATUS CSR provides the current TPM status, mostly the buffer and FIFO status.

31302928272625242322212019181716
  wrfifo_depth
1514131211109876543210
  rdfifo_depth   rdfifo_notempty cmdaddr_notempty
BitsTypeResetNameDescription
0ro0x0cmdaddr_notempty

If 1, the TPM_CMD_ADDR has a valid data. This status is reported via the interrupt also.

1ro0x0rdfifo_notempty

If 1, the TPM_READ_FIFO still has pending data.

7:2Reserved
12:8ro0x0rdfifo_depth

This field represents the current read FIFO depth

15:13Reserved
22:16ro0x0wrfifo_depth

This field represents the current write FIFO depth.


SPI_DEVICE.TPM_ACCESS_0 @ 0x80c

TPM_ACCESS_x register.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
access_3 access_2
1514131211109876543210
access_1 access_0
BitsTypeResetNameDescription
7:0rw0x0access_0

TPM_ACCESS

15:8rw0x0access_1

TPM_ACCESS

23:16rw0x0access_2

TPM_ACCESS

31:24rw0x0access_3

TPM_ACCESS


SPI_DEVICE.TPM_ACCESS_1 @ 0x810

TPM_ACCESS_x register.

Reset default = 0x0, mask 0xff
31302928272625242322212019181716
 
1514131211109876543210
  access_4
BitsTypeResetNameDescription
7:0rw0x0access_4

For TPM1


SPI_DEVICE.TPM_STS @ 0x814

TPM_STS_x register.

Reset default = 0x0, mask 0xffffffff

The register is mirrored to all Localities. The value is returned to the host system only when the activeLocality in the TPM_ACCESS_x is matched to the current received Locality.

31302928272625242322212019181716
sts...
1514131211109876543210
...sts
BitsTypeResetNameDescription
31:0rw0x0sts

TPM_STS_x


SPI_DEVICE.TPM_INTF_CAPABILITY @ 0x818

TPM_INTF_CAPABILITY

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
intf_capability...
1514131211109876543210
...intf_capability
BitsTypeResetNameDescription
31:0rw0x0intf_capability

TPM_INTF_CAPABILITY


SPI_DEVICE.TPM_INT_ENABLE @ 0x81c

TPM_INT_ENABLE

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
int_enable...
1514131211109876543210
...int_enable
BitsTypeResetNameDescription
31:0rw0x0int_enable

TPM_INT_ENABLE


SPI_DEVICE.TPM_INT_VECTOR @ 0x820

TPM_INT_VECTOR

Reset default = 0x0, mask 0xff
31302928272625242322212019181716
 
1514131211109876543210
  int_vector
BitsTypeResetNameDescription
7:0rw0x0int_vector

TPM_INT_VECTOR


SPI_DEVICE.TPM_INT_STATUS @ 0x824

TPM_INT_STATUS

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
int_status...
1514131211109876543210
...int_status
BitsTypeResetNameDescription
31:0rw0x0int_status

TPM_INT_STATUS


SPI_DEVICE.TPM_DID_VID @ 0x828

TPM_DID/ TPM_VID register

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
did
1514131211109876543210
vid
BitsTypeResetNameDescription
15:0rw0x0vid

TPM_VID

31:16rw0x0did

TPM_DID


SPI_DEVICE.TPM_RID @ 0x82c

TPM_RID

Reset default = 0x0, mask 0xff
31302928272625242322212019181716
 
1514131211109876543210
  rid
BitsTypeResetNameDescription
7:0rw0x0rid

TPM_RID


SPI_DEVICE.TPM_CMD_ADDR @ 0x830

TPM Command and Address buffer

Reset default = 0x0, mask 0xffffffff

The SW may get the received TPM command and address by readin gthis CSR.

31302928272625242322212019181716
cmd addr...
1514131211109876543210
...addr
BitsTypeResetNameDescription
23:0roxaddr

received address

31:24roxcmd

received command


SPI_DEVICE.TPM_READ_FIFO @ 0x834

TPM Read command return data FIFO.

Reset default = 0x0, mask 0xffffffff

The write port of the read command FIFO.

31302928272625242322212019181716
value...
1514131211109876543210
...value
BitsTypeResetNameDescription
31:0woxvalue

write port of the read FIFO


SPI_DEVICE.TPM_WRITE_FIFO @ 0x838

TPM Write command received data FIFO.

Reset default = 0x0, mask 0xff
31302928272625242322212019181716
 
1514131211109876543210
  value
BitsTypeResetNameDescription
7:0roxvalue

Read only port of the write FIFO


SPI_DEVICE.buffer @ + 0x1000
1024 item rw window
Byte writes are not supported
310
+0x1000 
+0x1004 
 ...
+0x1ff8 
+0x1ffc 

SPI internal buffer.

In Generic mode, this buffer is used for RX/TX buffer. In Flash & Passthrough mode, lower 2kB is for Read content emulating eFlash. next 1kB is for Mailbox read/write buffer. The rest is 256B SFDP buffer, 32B of CmdFIFO, 32B of AddrFIFO, and 256B of payload FIFO.