Use default SRAM fifo setting. Seq:

• Write a word data to TX memory and update wptr
• Send a word SPI transfer
• Read a word data from RX memory and update rptr
• Compare the data and check no pending data in SRAM FIFO
• Repeat above steps

Verify the reset values as indicated in the RAL specification.

• Write all CSRs with a random value.
• Apply reset to the DUT as well as the RAL model.
• Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify accessibility of CSRs as indicated in the RAL specification.

• Loop through each CSR to write it with a random value.
• Read the CSR back and check for correctness while adhering to its access policies.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify no aliasing within individual bits of a CSR.

• Walk a 1 through each CSR by flipping 1 bit at a time.
• Read the CSR back and check for correctness while adhering to its access policies.
• This verify that writing a specific bit within the CSR did not affect any of the other bits.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify no aliasing within the CSR address space.

• Loop through each CSR to write it with a random value
• Shuffle and read ALL CSRs back.
• All CSRs except for the one that was written in this iteration should read back the previous value.
• The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify random reset during CSR/memory access.

• Run csr_rw sequence to randomly access CSRs
• If memory exists, run mem_partial_access in parallel with csr_rw
• Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.

Verify accessibility of all memories in the design.

• Run the standard UVM mem walk sequence on all memories in the RAL model.
• It is mandatory to run this test from all available interfaces the memories are accessible from.

Verify partial-accessibility of all memories in the design.

• Do partial reads and writes into the memories and verify the outcome for correctness.
• Also test outstanding access on memories

Create 3 parallel threads

• Write random data to TX memory unless fifo is full
• Send SPI transfer unless TX is empty or RX is full
• Read RX memory unless RX is empty

Increase the chance to have fifo full by following

• Reduce delay to write TX memory
• Increase delay to read RX memory

Override spi_device_txrx_vseq to send SPI transfer without checking TX/RX fifo, note:

• When TX is underflow, SW shouldn't update wptr if spi isn't idle, otherwise, spi may send mis-aligned data
• When RX is overflow, data will be lost and if SW update rptr, received data may be mis-aligned
• Ensure underflow/overflow is triggered correctly

Drive dummy sck without csb or drive dummy csb without sck, and test no impact on the design

Add extra delay between spi clock edge or extra delay between 2 words data This is to test host pause transfer for a while without turning off csb and then stream in data again

Reset TX async fifo when SPI interface is idle

• Fill TX SRAM FIFO with some data, which will be transfered to TX async FIFO
• Write 0 into read and write point of TX SRAM FIFO
• Program rst_txfifo to reset the async FIFO
• Check async_fifo_level.txlvl is 0
• Fill TX SRAM FIFO with some other data and enable SPI transfer
• Check SPI device sends and receives the correct data

Reset RX async fifo when SPI interface is idle

• Configure RX SRAM FIFO with a small size, so that it's easy to fill up
• Start SPI transfers to fill up the RX SRAM FIFO and at least part of the RX async FIFO
• Program rst_rxfifo to reset the async FIFO
• Check async_fifo_level.rxlvl is 0
• Write 0 into read and write point of RX SRAM FIFO
• Fill TX SRAM FIFO with some other data and start another SPI transfers
• Check SPI device sends and receives the correct data

Test all supported interrupts:

• tx/rx lvl
• rx full
• rx error
• overflow/underflow

• Fill TX FIFO without host traffic
• Issue Abort to control register
• Poll until abort_done in status register
• TBD additional checking

send spi transfer on byte granularity, and make sure the timer never expires

• Send spi transfer on byte granularity, and timer may expires
• Only check data in sequence level when timer expires. Monitor and scoreboard don't model the timer feature
• Note: Timeout only for RX

Send spi transfer on bit granularity

• If TX drives < 7 bits, this byte will be sent in next CSB.
• If TX drives 7 bits and set CSB to high, this byte won't be sent in next CSB

Set fifo size to 4 bytes(minimum), 2k-4bytes(maximum) and others

Run spi_device_fifi_full_vseq with very small delays

• Set TPM_CFG.TPM_MODE to 0 and set TPM_CFG.EN.
• Randomise other fields in TPM_CFG.
• Assert the tpm_csb.
• Send TPM read command over the SPI bus with a randomised address.
• Check TPM_CMD_ADDR.
• Confirm FIFO behaviour dictated by TPM_CFG.tpm_mode.
• Check TPM_STATUS.cmdaddr_notempty and INTR_STATE.tpm_header_notempty, they should be asserted if hw_reg_dis == 0.
• If hw_reg_dis == 0, the data is returned to the host via return-by-HW register, else the data is returned via read FIFO.
• Confirm that the TPM submodule sends WAIT until the read FIFO is available.
• Check the read FIFO.
• When available, confirm that the TPM submodule sends START followed by the register value.
• Compare this value with the expected value.

• Set TPM_CFG.TPM_MODE to 0 and set TPM_CFG.EN.
• Randomise other fields in TPM_CFG.
• Assert the tpm_csb.
• Send TPM write command with a randomised address.
• Check TPM_CMD_ADDR and write FIFO.
• Check TPM_STATUS.cmdaddr_notempty and INTR_STATE.tpm_header_notempty.
• Based on FIFO status, check SPI bus to confirm WAIT or START sent.
• Check that the TPM submodule accepts write data without the WAIT state if the write FIFO is empty.
• Otherwise, check WAIT until the write FIFO becomes available (empty).

• Make transactions of varying locality to the tpm submodule.
• Ensure that the data returned is correct for the given locality.
• Randomise TPM_CFG.invalid_locality and confirm response.

• Perform partial txrx over SPI with TPM_CFG.EN is set.
• Perform multiple partial TX/RX.

Verify common alert_test CSR that allows SW to mock-inject alert requests.

• Enable a random set of alert requests by writing random value to alert_test CSR.
• Check each alert_tx.alert_p pin to verify that only the requested alerts are triggered.
• During alert_handshakes, write alert_test CSR again to verify that: If alert_test writes to current ongoing alert handshake, the alert_test request will be ignored. If alert_test writes to current idle alert handshake, a new alert_handshake should be triggered.
• Wait for the alert handshakes to finish and verify alert_tx.alert_p pins all sets back to 0.
• Repeat the above steps a bunch of times.

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

• Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
• Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s).
• Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
• Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
• Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
• Repeat the above steps a bunch of times.

Access out of bounds address and verify correctness of response / behavior

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the [TLUL spec]({{< relref "hw/ip/tlul/doc/_index.md#explicit-error-cases" >}})

• TL-UL protocol error cases
  • invalid opcode
  • some mask bits not set when opcode is PutFullData
  • mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
  • mask and address misaligned, e.g. a_address = 0x01, a_mask = 'b0001
  • address and size aren't aligned, e.g. a_address = 0x01, a_size != 0
  • size is greater than 2
• OpenTitan defined error cases
  • access unmapped address, expect d_error = 1 when devmode_i == 1
  • write a CSR with unaligned address, e.g. a_address[1:0] != 0
  • write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
  • write a memory with a_mask != '1 when it doesn't support partial accesses
  • read a WO (write-only) memory
  • write a RO (read-only) memory

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

Verify that the data integrity check violation generates an alert.

Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.

Cover the correct abort functionality for all modes.

TODO: Functionality of abort to be clarified.

Cover all fsm states for RX/TX FIFO.

Cover all combinations of SPI_DEVICE.CFG.CPOL and SPI_DEVICE.CFG.CPHA.

Cover valid combinations for each mode.

Cover the SramAw local parameter to confirm all sizes 1 - 32kB.

Cover every combination of all possible modes:

• All modes perform tx/rx interleaved tpm tx/rx.

Cover all tpm states on the SPI bus (WAIT, INVALID, ETC).

Verify that data being tx/rx is valid regardless of bit order and that the functionality behaves as expected:

Cover all configurations of rx/tx order in SPI_DEVICE.CFG for all valid modes.

Cover the following error cases on TL-UL bus:

• TL-UL protocol error cases.
• OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.