SPI Device DV document

Goals

DV
- Verify all SPI Device IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the DV plan below towards closing code and functional coverage on the IP and all of its sub-modules
FPV
- Verify TileLink device protocol compliance with an SVA based testbench

Current status

Design features

For detailed information on SPI Device design features, please see the SPI_device design specification.

Testbench architecture

SPI Device testbench has been constructed based on the CIP testbench architecture.

Block diagram

Top level testbench

Top level testbench is located at hw/ip/spi_device/dv/tb/tb.sv. It instantiates the SPI Device DUT module hw/ip/spi_device/rtl/spi_device.sv. In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db:

Common DV utility components

The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

Global types & methods

All common types and methods defined at the package level can be found in spi_device_env_pkg. Some of them in use are:

parameter uint SRAM_OFFSET = 'h800;
parameter uint SRAM_SIZE   = 2048;

TL_agent

SPI Device instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into SPI Device.

SPI Device agent

spi agent is used to drive and monitor SPI items. Following special behavior is supported in spi_host_driver

Toggle clock when SPI is in idle state (csb=1)
During data transfer, there may be very long delay between each bit or byte of data

UVM RAL Model

The SPI Device RAL model is created with the ralgen FuseSoC generator script automatically when the simulation is at the build stage.

It can be created manually by invoking regtool:

Stimulus strategy

Test sequences

All test sequences reside in hw/ip/spi_device/dv/env/seq_lib. The spi_device_base_vseq virtual sequence is extended from cip_base_vseq and serves as a starting point. All test sequences are extended from spi_device_base_vseq. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. Some of the most commonly used tasks / functions are as follows:

spi_device_init: Fully randomize SPI Device control following CSRs and configure TX/RX SRAM FIFO size as following
- clock polarity/phase(CPOL, CPHA), bit direction(tx/rx_order), mode, fifo interrupt level(txlvl, rxlvl)
- TX/RX SRAM FIFO size: from 100 to 1900 and higher distribute for TX size / RX size = 1, 1/2 or 2/1
spi_host_xfer_bytes: Send bytes of data to DUT (SPI Device) through spi_host_driver
write_device_words_to_send: Write words of data to DUT CSR and update SRAM write pointer, which enables DUT to send data to SPI host.
read_tx/rx_avail_bytes: Read CSRs to get how many bytes of available space/data in SRAM memory

Functional coverage

To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:

common covergroup for interrupts hw/dv/sv/cip_lib/cip_base_env_cov.sv: Cover interrupt value, interrupt enable, intr_test, interrupt pin
TODO, add more

Self-checking strategy

Scoreboard

The spi_device_scoreboard is primarily used for end to end checking. It creates the following analysis fifos to retrieve the data monitored by corresponding interface agents:

tl_a_chan_fifo, tl_d_chan_fifo: These 2 fifos provide transaction items at the end of address channel and data channel respectively
host_spi_data_fifo, device_spi_data_fifo: These 2 fifos provides TX/RX words of data from spi_monitor

Assertions

TLUL assertions: The tb/spi_device_bind.sv binds the tlul_assert assertions to the IP to ensure TileLink interface protocol compliance.
Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.

Building and running tests

We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:

$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/spi_device/dv/spi_device_sim_cfg.hjson -i spi_device_smoke

DV plan

Milestone	Name	Description	Tests
V1	smoke	Use default SRAM fifo setting. Seq: Write a word data to TX memory and update wptr Send a word SPI transfer Read a word data from RX memory and update rptr Compare the data and check no pending data in SRAM FIFO Repeat above steps	spi_device_smoke
V1	csr_hw_reset	Verify the reset values as indicated in the RAL specification. Write all CSRs with a random value. Apply reset to the DUT as well as the RAL model. Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.	spi_device_csr_hw_reset
V1	csr_rw	Verify accessibility of CSRs as indicated in the RAL specification. Loop through each CSR to write it with a random value. Read the CSR back and check for correctness while adhering to its access policies. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.	spi_device_csr_rw
V1	csr_bit_bash	Verify no aliasing within individual bits of a CSR. Walk a 1 through each CSR by flipping 1 bit at a time. Read the CSR back and check for correctness while adhering to its access policies. This verify that writing a specific bit within the CSR did not affect any of the other bits. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.	spi_device_csr_bit_bash
V1	csr_aliasing	Verify no aliasing within the CSR address space. Loop through each CSR to write it with a random value Shuffle and read ALL CSRs back. All CSRs except for the one that was written in this iteration should read back the previous value. The CSR that was written in this iteration is checked for correctness while adhering to its access policies. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.	spi_device_csr_aliasing
V1	csr_mem_rw_with_rand_reset	Verify random reset during CSR/memory access. Run csr_rw sequence to randomly access CSRs If memory exists, run mem_partial_access in parallel with csr_rw Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value It is mandatory to run this test for all available interfaces the CSRs are accessible from.	spi_device_csr_mem_rw_with_rand_reset
V1	mem_walk	Verify accessibility of all memories in the design. Run the standard UVM mem walk sequence on all memories in the RAL model. It is mandatory to run this test from all available interfaces the memories are accessible from.	spi_device_mem_walk
V1	mem_partial_access	Verify partial-accessibility of all memories in the design. Do partial reads and writes into the memories and verify the outcome for correctness. Also test outstanding access on memories	spi_device_mem_partial_access
V2	base_random_seq	Create 3 parallel threads Write random data to TX memory unless fifo is full Send SPI transfer unless TX is empty or RX is full Read RX memory unless RX is empty	spi_device_txrx
V2	fifo_full	Increase the chance to have fifo full by following Reduce delay to write TX memory Increase delay to read RX memory	spi_device_fifo_full
V2	fifo_underflow_overflow	Override spi_device_txrx_vseq to send SPI transfer without checking TX/RX fifo, note: When TX is underflow, SW shouldn't update wptr if spi isn't idle, otherwise, spi may send mis-aligned data When RX is overflow, data will be lost and if SW update rptr, received data may be mis-aligned Ensure underflow/overflow is triggered correctly	spi_device_fifo_underflow_overflow
V2	dummy_sck_and_dummy_csb	Drive dummy sck without csb or drive dummy csb without sck, and test no impact on the design	spi_device_dummy_item_extra_dly
V2	extra_delay_on_spi	Add extra delay between spi clock edge or extra delay between 2 words data This is to test host pause transfer for a while without turning off csb and then stream in data again	spi_device_dummy_item_extra_dly
V2	async_fifo_reset	Reset async fifo when SPI interface is idle TODO: fifo may be fetching data from SRAM? What is the actual usage?	spi_device_async_fifo_reset
V2	interrupts	Test all supported interrupts: tx/rx lvl rx full rx error overflow/underflow	spi_device_interrupts
V2	abort	TODO: Need to clarify the behavior in spec	spi_device_abort
V2	byte_transfer_on_spi	send spi transfer on byte granularity, and make sure the timer never expires	spi_device_byte_transfer
V2	rx_timeout	Send spi transfer on byte granularity, and timer may expires Only check data in sequence level when timer expires. Monitor and scoreboard don't model the timer feature Note: Timeout only for RX	spi_device_rx_timeout
V2	bit_transfer_on_spi	Send spi transfer on bit granularity If TX drives < 7 bits, this byte will be sent in next CSB. If TX drives 7 bits and set CSB to high, this byte won't be sent in next CSB	spi_device_bit_transfer
V2	extreme_fifo_setting	Set fifo size to 4 bytes(minimum), 2k-4bytes(maximum) and others	spi_device_extreme_fifo_size
V2	mode	TODO :only support fw mode now	spi_device_mode
V2	mem_ecc	Backdoor hack memory data to test basic memory ECC behavior limitation: Just cover basic functionality and connectivity Complete verification will be done by PFV	spi_device_mem_ecc
V2	perf	Run spi_device_fifi_full_vseq with very small delays	spi_device_perf
V2	intr_test	Verify common intr_test CSRs that allows SW to mock-inject interrupts. Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s). Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s). Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR. Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set. Clear a random set of interrupts by writing a randomly value to intr_state CSR(s). Repeat the above steps a bunch of times.	spi_device_intr_test
V2	tl_d_oob_addr_access	Access out of bounds address and verify correctness of response / behavior	spi_device_tl_errors
V2	tl_d_illegal_access	Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested TL-UL protocol error cases Unsupported opcode. e.g a_opcode isn't Get, PutPartialData or PutFullData Mask isn't all active if opcode = PutFullData Mask isn't in enabled lanes, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010 Mask doesn't align with address, e.g. a_address = 0x01, a_mask = 'b0001 Address and size aren't aligned, e.g. a_address = 0x01, a_size != 0 Size is over 2. OpenTitan defined error cases Access unmapped address, return d_error = 1 when devmode_i == 1 Write CSR with unaligned address, e.g. a_address[1:0] != 0 Write CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte Write a memory without enabling all lanes (a_mask = '1) if memory doesn't support byte enabled write Read a WO (write-only) memory	spi_device_tl_errors
V2	tl_d_outstanding_access	Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.	spi_device_csr_hw_reset spi_device_csr_rw spi_device_csr_aliasing spi_device_same_csr_outstanding
V2	tl_d_partial_access	Access CSR with one or more bytes of data For read, expect to return all word value of the CSR For write, enabling bytes should cover all CSR valid fields	spi_device_csr_hw_reset spi_device_csr_rw spi_device_csr_aliasing spi_device_same_csr_outstanding