SPI Device DV Plan
- Verify all SPI Device IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
- Verify TileLink device protocol compliance with an SVA based testbench
For detailed information on SPI Device design features, please see the SPI_device design specification.
SPI Device testbench has been constructed based on the CIP testbench architecture.
Top level testbench
Top level testbench is located at
hw/ip/spi_device/dv/tb/tb.sv. It instantiates the SPI Device DUT module
In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into
Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
Global types & methods
All common types and methods defined at the package level can be found in
spi_device_env_pkg. Some of them in use are:
parameter uint SPI_DEVICE_ADDR_MAP_SIZE = 4096; parameter uint SRAM_OFFSET = 'h800; parameter uint SRAM_SIZE = 2048;
SPI Device instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into SPI Device.
SPI Device agent
spi agent is used to drive and monitor SPI items. Following special behavior is supported in spi_host_driver
- Toggle clock when SPI is in idle state (csb=1)
- During data transfer, there may be very long delay between each bit or byte of data
UVM RAL Model
The SPI Device RAL model is created with the
ralgen FuseSoC generator script automatically when the simulation is at the build stage.
It can be created manually (separately) by running
make in the the
All test sequences reside in
spi_device_base_vseq virtual sequence is extended from
cip_base_vseq and serves as a starting point.
All test sequences are extended from
It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:
- spi_device_init: Fully randomize SPI Device control following CSRs and configure TX/RX SRAM FIFO size as following
- clock polarity/phase(CPOL, CPHA), bit direction(tx/rx_order), mode, fifo interrupt level(txlvl, rxlvl)
- TX/RX SRAM FIFO size: from 100 to 1900 and higher distribute for TX size / RX size = 1, 1/2 or 2/1
- spi_host_xfer_bytes: Send bytes of data to DUT (SPI Device) through spi_host_driver
- write_device_words_to_send: Write words of data to DUT CSR and update SRAM write pointer, which enables DUT to send data to SPI host.
- read_tx/rx_avail_bytes: Read CSRs to get how many bytes of available space/data in SRAM memory
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:
- common covergroup for interrupts
hw/dv/sv/cip_lib/cip_base_env_cov.sv: Cover interrupt value, interrupt enable, intr_test, interrupt pin
- TODO, add more
spi_device_scoreboard is primarily used for end to end checking.
It creates the following analysis fifos to retrieve the data monitored by corresponding interface agents:
- tl_a_chan_fifo, tl_d_chan_fifo: These 2 fifos provide transaction items at the end of address channel and data channel respectively
- host_spi_data_fifo, device_spi_data_fifo: These 2 fifos provides TX/RX words of data from spi_monitor
- TLUL assertions: The
tlul_assertassertions to the IP to ensure TileLink interface protocol compliance.
- Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
Building and running tests
We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here's how to run a basic sanity test:
$ cd hw/ip/spi_device/dv $ make TEST_NAME=spi_device_sanity
|V1||sanity||<p>Use default SRAM fifo setting. Seq:</p> <ul> <li>Write a word data to TX memory and update wptr</li> <li>Send a word SPI transfer</li> <li>Read a word data from RX memory and update rptr</li> <li>Compare the data and check no pending data in SRAM FIFO</li> <li>Repeat above steps</li> </ul>||spi_device_sanity<br>|
|V1||csr_hw_reset||<p>Verify the reset values as indicated in the RAL specification.</p> <ul> <li>Write all CSRs with a random value.</li> <li>Apply reset to the DUT as well as the RAL model.</li> <li>Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.</li> <li>It is mandatory to run this test for all available interfaces the CSRs are accessible from.</li> <li>Shuffle the list of CSRs first to remove the effect of ordering.</li> </ul>||spi_device_csr_hw_reset<br>|
|V1||csr_rw||<p>Verify accessibility of CSRs as indicated in the RAL specification.</p> <ul> <li>Loop through each CSR to write it with a random value.</li> <li>Read the CSR back and check for correctness while adhering to its access policies.</li> <li>It is mandatory to run this test for all available interfaces the CSRs are accessible from.</li> <li>Shuffle the list of CSRs first to remove the effect of ordering.</li> </ul>||spi_device_csr_rw<br>|
|V1||csr_bit_bash||<p>Verify no aliasing within individual bits of a CSR.</p> <ul> <li>Walk a 1 through each CSR by flipping 1 bit at a time.</li> <li>Read the CSR back and check for correctness while adhering to its access policies.</li> <li>This verify that writing a specific bit within the CSR did not affect any of the other bits.</li> <li>It is mandatory to run this test for all available interfaces the CSRs are accessible from.</li> <li>Shuffle the list of CSRs first to remove the effect of ordering.</li> </ul>||spi_device_csr_bit_bash<br>|
|V1||csr_aliasing||<p>Verify no aliasing within the CSR address space.</p> <ul> <li>Loop through each CSR to write it with a random value</li> <li>Shuffle and read ALL CSRs back.</li> <li>All CSRs except for the one that was written in this iteration should read back the previous value.</li> <li>The CSR that was written in this iteration is checked for correctness while adhering to its access policies.</li> <li>It is mandatory to run this test for all available interfaces the CSRs are accessible from.</li> <li>Shuffle the list of CSRs first to remove the effect of ordering.</li> </ul>||spi_device_csr_aliasing<br>|
|V1||csr_mem_rw_with_rand_reset||<p>Verify random reset during CSR/memory access.</p> <ul> <li>Run csr_rw sequence to randomly access CSRs</li> <li>If memory exists, run mem_partial_access in parallel with csr_rw</li> <li>Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value</li> <li>It is mandatory to run this test for all available interfaces the CSRs are accessible from.</li> </ul>||spi_device_csr_mem_rw_with_rand_reset<br>|
|V1||mem_walk||<p>Verify accessibility of all memories in the design.</p> <ul> <li>Run the standard UVM mem walk sequence on all memories in the RAL model.</li> <li>It is mandatory to run this test from all available interfaces the memories are accessible from.</li> </ul>||spi_device_mem_walk<br>|
|V1||mem_partial_access||<p>Verify partial-accessibility of all memories in the design.</p> <ul> <li>Do partial reads and writes into the memories and verify the outcome for correctness.</li> <li>Also test outstanding access on memories</li> </ul>||spi_device_mem_partial_access<br>|
|V2||base_random_seq||<p>Create 3 parallel threads</p> <ul> <li>Write random data to TX memory unless fifo is full</li> <li>Send SPI transfer unless TX is empty or RX is full</li> <li>Read RX memory unless RX is empty</li> </ul>||spi_device_txrx<br>|
|V2||fifo_full||<p>Increase the chance to have fifo full by following</p> <ul> <li>Reduce delay to write TX memory</li> <li>Increase delay to read RX memory</li> </ul>||spi_device_fifo_full<br>|
|V2||fifo_underflow_overflow||<p>Override spi_device_txrx_vseq to send SPI transfer without checking TX/RX fifo, note:</p> <ul> <li>When TX is underflow, SW shouldn't update wptr if spi isn't idle, otherwise, spi may send mis-aligned data</li> <li>When RX is overflow, data will be lost and if SW update rptr, received data may be mis-aligned</li> <li>Ensure underflow/overflow is triggered correctly</li> </ul>||spi_device_fifo_underflow_overflow<br>|
|V2||dummy_sck_and_dummy_csb||<p>Drive dummy sck without csb or drive dummy csb without sck, and test no impact on the design</p>||spi_device_dummy_item_extra_dly<br>|
|V2||extra_delay_on_spi||<p>Add extra delay between spi clock edge or extra delay between 2 words data This is to test host pause transfer for a while without turning off csb and then stream in data again</p>||spi_device_dummy_item_extra_dly<br>|
|V2||async_fifo_reset||<p>Reset async fifo when SPI interface is idle TODO: fifo may be fetching data from SRAM? What is the actual usage?</p>||spi_device_async_fifo_reset<br>|
|V2||interrupts||<p>Test all supported interrupts:</p> <ul> <li>tx/rx lvl</li> <li>rx full</li> <li>rx error</li> <li>overflow/underflow</li> </ul>||spi_device_interrupts<br>|
|V2||abort||<p>TODO: Need to clarify the behavior in spec</p>||spi_device_abort<br>|
|V2||byte_transfer_on_spi||<p>send spi transfer on byte granularity, and make sure the timer never expires</p>||spi_device_byte_transfer<br>|
|V2||rx_timeout||<ul> <li>Send spi transfer on byte granularity, and timer may expires</li> <li>Only check data in sequence level when timer expires. Monitor and scoreboard don't model the timer feature</li> <li>Note: Timeout only for RX</li> </ul>||spi_device_rx_timeout<br>|
|V2||bit_transfer_on_spi||<p>Send spi transfer on bit granularity</p> <ul> <li>If TX drives < 7 bits, this byte will be sent in next CSB.</li> <li>If TX drives 7 bits and set CSB to high, this byte won't be sent in next CSB</li> </ul>||spi_device_bit_transfer<br>|
|V2||extreme_fifo_setting||<p>Set fifo size to 4 bytes(minimum), 2k-4bytes(maximum) and others</p>||spi_device_extreme_fifo_size<br>|
|V2||mode||<p>TODO :only support fw mode now</p>||spi_device_mode<br>|
|V2||mem_ecc||<p>Backdoor hack memory data to test basic memory ECC behavior limitation:</p> <ul> <li>Just cover basic functionality and connectivity</li> <li>Complete verification will be done by PFV</li> </ul>||spi_device_mem_ecc<br>|
|V2||perf||<p>Run spi_device_fifi_full_vseq with very small delays</p>||spi_device_perf<br>|
|V2||intr_test||<p>Verify common intr_test CSRs that allows SW to mock-inject interrupts.</p> <ul> <li>Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).</li> <li>Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s).</li> <li>Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.</li> <li>Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.</li> <li>Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).</li> <li>Repeat the above steps a bunch of times.</li> </ul>||spi_device_intr_test<br>|
|V2||oob_addr_access||<p>Access out of bounds address and verify correctness of response / behavior</p>||spi_device_tl_errors<br>|
|V2||illegal_access||<p>Drive unsupported requests via TL interface and verify correctness of response / behavior</p>||spi_device_tl_errors<br>|
|V2||outstanding_access||<p>Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.</p>||spi_device_csr_hw_reset<br> spi_device_csr_rw<br> spi_device_csr_aliasing<br> spi_device_same_csr_outstanding<br>|
|V2||partial_access||<p>Do partial accesses.</p>||spi_device_csr_hw_reset<br> spi_device_csr_rw<br> spi_device_csr_aliasing<br>|