SPI_HOST DV Plan

Goals

  • DV
    • Verify all SPI_HOST IP features by running dynamic simulations with a SV/UVM based testbench
    • Develop and run all tests based on the DV plan below towards closing code and functional coverage on the IP and all of its sub-modules
  • FPV
    • Verify TileLink device protocol compliance with an SVA based testbench

Current status

Design features

For detailed information on SPI_HOST design features, please see the SPI_HOST HWIP technical specification.

Testbench architecture

SPI_HOST testbench has been constructed based on the CIP testbench architecture.

Block diagram

Block diagram

Top level testbench

Top level testbench is located at hw/ip/spi_host/dv/tb/tb.sv. It instantiates the SPI_HOST DUT module hw/ip/spi_host/rtl/spi_host.sv. In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db:

Common DV utility components

The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

Compile-time configurations

[list compile time configurations, if any and what are they used for]

Global types & methods

All common types and methods defined at the package level can be found in spi_host_env_pkg. Some of them in use are:

TODO

TL_agent

SPI_HOST testbench instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into SPI_HOST device.

SPI Agent

SPI agent is configured to work host mode. The agent monitor captures data generated in channels then sends to the scoreboard for verification
Since the DUT does not require any response thus agent driver is fairly simple.

UVM RAL Model

The SPI_HOST RAL model is created with the ralgen FuseSoC generator script automatically when the simulation is at the build stage.

It can be created manually by invoking regtool:

Stimulus strategy

Test sequences

All test sequences reside in hw/ip/spi_host/dv/env/seq_lib. The spi_host_base_vseq virtual sequence is extended from cip_base_vseq and serves as a starting point. All test sequences are extended from spi_host_base_vseq. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. Some of the most commonly used tasks / functions are as follows:

  • task 1:
  • task 2:

Functional coverage

To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:

  • cg1:
  • cg2:

Self-checking strategy

Scoreboard

The spi_host_scoreboard is primarily used for end to end checking. It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:

  • analysis port1:
  • analysis port2:

Assertions

  • TLUL assertions: The tb/spi_host_bind.sv binds the tlul_assert assertions to the IP to ensure TileLink interface protocol compliance.
  • Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
  • assert prop 1:
  • assert prop 2:

Building and running tests

We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:

$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/spi_host/dv/spi_host_sim_cfg.hjson -i spi_host_smoke

Testplan

Milestone Name Description Tests
V1 smoke

SPI_HOST smoke test in which random (rd/wr) transactions are sent to the DUT and received asynchronously with scoreboard checks.

Stimulus:

  • Enable spi_host ip
  • Clear/enable interrupt (if needed)
  • Program configuration registers (CONTROL) to reset spi_fsm, reset/set watermark for the fifos
  • Program the CONFIGOPTS register to config spi_host channel operating in different modes (single, dual, or quad)
  • Randomize the content of COMMAND register
  • Program/retrive data in TXDATA/RXDATA register w.r.t transmitted/received transactions

Checking:

  • Ensure transactions are transmitted/received correctly
spi_host_smoke
V1 csr_hw_reset

Verify the reset values as indicated in the RAL specification.

  • Write all CSRs with a random value.
  • Apply reset to the DUT as well as the RAL model.
  • Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
spi_host_csr_hw_reset
V1 csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

  • Loop through each CSR to write it with a random value.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
spi_host_csr_rw
V1 csr_bit_bash

Verify no aliasing within individual bits of a CSR.

  • Walk a 1 through each CSR by flipping 1 bit at a time.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • This verify that writing a specific bit within the CSR did not affect any of the other bits.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
spi_host_csr_bit_bash
V1 csr_aliasing

Verify no aliasing within the CSR address space.

  • Loop through each CSR to write it with a random value
  • Shuffle and read ALL CSRs back.
  • All CSRs except for the one that was written in this iteration should read back the previous value.
  • The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
spi_host_csr_aliasing
V1 csr_mem_rw_with_rand_reset

Verify random reset during CSR/memory access.

  • Run csr_rw sequence to randomly access CSRs
  • If memory exists, run mem_partial_access in parallel with csr_rw
  • Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
spi_host_csr_mem_rw_with_rand_reset
V2 perf

Send/receive transactions at max bandwidth

Stimulus:

  • Program the content of timing fields of CONFIGOPTS to the min values
  • Programming TX1_CNT and TXN_CNT to issue read/write back-to-back transactions
  • Read/write rx_fifo/tx_fifo as soon as possible (avoid stalling transactions)

Checking:

  • Ensure transactions are transmitted/received correctly
spi_host_perf
V2 error_event_intr

This test includes multi tasks which verify error/event interrupt assertion (except TX OVERFLOW error interrupt is verified in separate test)

Stimulus:

  • Program ERROR_ENABLE/EVENT_ENABLE register to enable corresponding error/event interrupt assertion
  • Program transaction with proper constraints to assert error/event interrupts

Checking:

  • Ensure transactions are transmitted/received correctly
  • Ensure the matching between the bit-field values of ERROR_STATUS and ERROR_ENABLE respectively once the error interrupt pin is asserted
  • Ensure the matching between the bit-field values of ERROR_ENABLE once the event interrupt pin is asserted
spi_host_error_event_intr
V2 tx_overflow_error

Test TX OVERFLOW error is asserted by the spi_host

Stimulus:

  • Program ERROR_ENABLE register to enable the TXOVERFLOW interrupt
  • Program transaction with proper constraints to assert the TXOVERFLOW interrupts

Checking:

  • Ensure excess tx data is dropped
  • Ensure the matching between the value of OVERFLOW bit in the ERROR_STATUS and the ERROR_ENABLE register the once error interrupt pin is asserted
spi_host_tx_overflow_error
V2 component_reset

Test components (spi_fsm, rx_fifo, tx_fifo) are randomly reset

Stimulus:

  • Reset the components of spi_host randomly after a random number of data shows up on fifos

Checking:

  • Ensure that reads to RXDATA register yield 0s after the rx_fifo is reset
  • Ensure that transactions are dropped in both the scoreboard and spi_agent monitor after the tx_fifo or spi_fsm is reset
spi_host_component_reset
V2 clock_domain

TBD - Verify the function of clock-crossing domain for spi_host

Stimulus:

  • TBD

Checking:

  • TBD
spi_host_clock_domain
V2 special_modes

TBD - Verify the function of spi_host in special_modes (passthrough and manual_ctrl_cs)

Stimulus:

  • TBD

Checking:

  • TBD
spi_host_special_modes
V2 stress_all

Support vseq (context) switching with random reset in between.

Stimulus:

  • Combine the above sequences in one test to run sequentially except csr sequence and (requires zero_delays)
  • Randomly add reset between each sequence

Checking:

  • Ensure transactions are transmitted/received correctly
  • Ensure reset is handled correctly
spi_host_stress_all
V2 intr_test

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

  • Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
  • Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s).
  • Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
  • Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
  • Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
  • Repeat the above steps a bunch of times.
spi_host_intr_test
V2 tl_d_oob_addr_access

Access out of bounds address and verify correctness of response / behavior

spi_host_tl_errors
V2 tl_d_illegal_access

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested

  • TL-UL protocol error cases
    • Unsupported opcode. e.g a_opcode isn't Get, PutPartialData or PutFullData
    • Mask isn't all active if opcode = PutFullData
    • Mask isn't in enabled lanes, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
    • Mask doesn't align with address, e.g. a_address = 0x01, a_mask = 'b0001
    • Address and size aren't aligned, e.g. a_address = 0x01, a_size != 0
    • Size is over 2.
  • OpenTitan defined error cases
    • Access unmapped address, return d_error = 1 when devmode_i == 1
    • Write CSR with unaligned address, e.g. a_address[1:0] != 0
    • Write CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
    • Write a memory without enabling all lanes (a_mask = '1) if memory doesn't support byte enabled write
    • Read a WO (write-only) memory
spi_host_tl_errors
V2 tl_d_outstanding_access

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

spi_host_csr_hw_reset
spi_host_csr_rw
spi_host_csr_aliasing
spi_host_same_csr_outstanding
V2 tl_d_partial_access

Access CSR with one or more bytes of data For read, expect to return all word value of the CSR For write, enabling bytes should cover all CSR valid fields

spi_host_csr_hw_reset
spi_host_csr_rw
spi_host_csr_aliasing
spi_host_same_csr_outstanding