SPI_HOST DV Document

Goals

  • DV
    • Verify all SPI_HOST IP features by running dynamic simulations with a SV/UVM based testbench
    • Develop and run tests that exercise all testpoints in the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
  • FPV
    • Verify TileLink device protocol compliance with an SVA based testbench

Current status

Design features

For detailed information on SPI_HOST design features, please see the SPI_HOST HWIP technical specification.

Testbench architecture

SPI_HOST testbench has been constructed based on the CIP testbench architecture.

Block diagram

Block diagram

Top level testbench

Top level testbench is located at hw/ip/spi_host/dv/tb/tb.sv. It instantiates the SPI_HOST DUT module hw/ip/spi_host/rtl/spi_host.sv. In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db:

Common DV utility components

The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

Compile-time configurations

[list compile time configurations, if any and what are they used for]

TODO

Global types & methods

All common types and methods defined at the package level can be found in spi_host_env_pkg. Some of them in use are:

TODO

TL_agent

SPI_HOST testbench instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into SPI_HOST device. Transactions will be sampled by the monitor and passed on to the predictor in the scoreboard.

SPI Agent

SPI agent is configured to work in target mode. The agent monitor samples the pins and stores the data in a sequence item that is forwarded to the predictor in the scoreboard. The sequence item is then compared to a sequence item from the predictor generated on the stimulus from the TL_UL accesses.

UVM RAL Model

The SPI_HOST RAL model is created with the ralgen FuseSoC generator script automatically when the simulation is at the build stage.

It can be created manually by invoking regtool:

Stimulus strategy

Test sequences

All test sequences reside in hw/ip/spi_host/dv/env/seq_lib. The spi_host_base_vseq virtual sequence is extended from cip_base_vseq and serves as a starting point. All test sequences are extended from spi_host_base_vseq. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. Some of the most commonly used tasks / functions are as follows:

  • spi_read(int len, bit [3:0] addr)

    read len bytes from address addr

  • spi_write(int len, bit [3:0] addr)

    write len bytes to address addr

Functional coverage

To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. the list of functional coverpoints can be found under covergroups in the testplan

Self-checking strategy

Scoreboard

The spi_host_scoreboard is primarily used for end to end checking. It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:

TL_UL AGENT

  • tl_a_chan_fifo: tl address channel
  • tl_d_chan_fifo: tl data channel

SPI_AGENT

  • spi_channel: TBD - subject to change until env is in place

The tl_ul FIFOs provide the transaction items that will be converted to SPI transactions in the DUT. A predictor in the DUT will collect these transactions and convert them into SPI items with an address and data.

On the SPI channel transactions are received in segments. These segments are re-assembled into full SPI transactions and stored in SPI sequence items.

The generated item from the predictor and the re-assembled item from the SPI channel is then compared in the scoreboard to validate then transaction.

Assertions

  • TLUL assertions: The tb/spi_host_bind.sv binds the tlul_assert assertions to the IP to ensure TileLink interface protocol compliance.
  • Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.

Building and running tests

We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:

$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/spi_host/dv/spi_host_sim_cfg.hjson -i spi_host_smoke

Testplan

Testpoints

Milestone Name Tests Description
V1 smoke spi_host_smoke

SPI_HOST smoke test in which random (rd/wr) transactions are sent to the DUT and received asynchronously with scoreboard checks.

Stimulus:

  • Enable spi_host ip
  • Write data in standard mode - and read it back

Checking:

  • Ensure transactions are transmitted/received correctly
V1 csr_hw_reset spi_host_csr_hw_reset

Verify the reset values as indicated in the RAL specification.

  • Write all CSRs with a random value.
  • Apply reset to the DUT as well as the RAL model.
  • Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_rw spi_host_csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

  • Loop through each CSR to write it with a random value.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_bit_bash spi_host_csr_bit_bash

Verify no aliasing within individual bits of a CSR.

  • Walk a 1 through each CSR by flipping 1 bit at a time.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • This verify that writing a specific bit within the CSR did not affect any of the other bits.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_aliasing spi_host_csr_aliasing

Verify no aliasing within the CSR address space.

  • Loop through each CSR to write it with a random value
  • Shuffle and read ALL CSRs back.
  • All CSRs except for the one that was written in this iteration should read back the previous value.
  • The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_mem_rw_with_rand_resetspi_host_csr_mem_rw_with_rand_reset

Verify random reset during CSR/memory access.

  • Run csr_rw sequence to randomly access CSRs
  • If memory exists, run mem_partial_access in parallel with csr_rw
  • Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
V2 performance

Send/receive transactions at max bandwidth

Stimulus:

  • Program the content of timing fields of CONFIGOPTS to the min values
  • Programming TX1_CNT and TXN_CNT to issue read/write back-to-back transactions
  • Read/write rx_fifo/tx_fifo as soon as possible (avoid stalling transactions)

Checking:

  • Ensure transactions are transmitted/received correctly
V2 error_event_intr

This test includes multi tasks which verify error/event interrupt assertion (except TX OVERFLOW error interrupt is verified in separate test)

Stimulus:

  • Program ERROR_ENABLE/EVENT_ENABLE register to enable corresponding error/event interrupt assertion
  • Program transaction with proper constraints to assert error/event interrupts

Checking:

  • Ensure transactions are transmitted/received correctly
  • Ensure the matching between the bit-field values of ERROR_STATUS and ERROR_ENABLE respectively once the error interrupt pin is asserted
  • Ensure the matching between the bit-field values of ERROR_ENABLE once the event interrupt pin is asserted
V2 clock_rate

Stimulus:

  • select different settings for:
  • CONFIGOPTS_0.CSNIDLE_0
  • CONFIGOPTS_0.CSNLEAD_0
  • CONFIGOPTS_0.CSNTRAIL_0

Checking:

  • verify that merging of commands work correctly
  • verify that the DUT can handle different sck -> cs_n timings
V2 speed

Stimulus:

  • randomly select the DUT to run single/dual/quad mode

Checking:

  • verify that all speeds are supported
V2 chip_select_timing

Stimulus:

  • Randomly select a setting for the 16bit clock divider

Checking:

  • Check that the DUT operates correctly under different SPI clock speeds
V2 sw_reset

verify software reset behavior

Stimulus:

  • Reset the spi_host randomly after a random number of data shows up on fifos

Checking:

  • Ensure that reads to RXDATA register yield 0s after the rx_fifo is reset
  • Ensure that transactions are dropped in both the scoreboard and spi_agent monitor after the tx_fifo or spi_fsm is reset
V2 passthrough_mode
  • Verify the function of spi_host in passthrough_mode

Stimulus:

  • TBD Checking:
  • TBD
V2 cpol_cpha

Stimulus:

  • Randomly chip select for different polarity / phase

Checking:

  • Check that the DUT operates correctly under different cs_n settings
V2 full_cycle

Stimulus:

  • randomly select FULLCYC to be set

Checking:

  • Check that the data can be read one full cycle after the data was asserted
V2 endian

Stimulus:

  • set the compile time parameter to configure the DUT in both modes. if possible this should be randomized for all test to verify support in both modes

Checking:

  • Check all features are supported correctly in both little and big endian mode
V2 duplex

Stimulus:

  • in standard mode set the DUT to run full duplex

Checking:

  • verify that the DUT support both half and full duplex in standard mode.
V2 tx_rx_only

Stimulus:

  • in standard mode enable tx only and have the env send garbage back
  • in standard mode enable rx only and have the env ignore the incoming data

Checking:

  • verify that the DUT ignores rx line when in tx only mode
  • verify that the DUT does not drain the tx fifo in rx only mode
V2 stress_all

Support vseq (context) switching with random reset in between.

Stimulus:

  • Combine the above sequences in one test to run sequentially except csr sequence and (requires zero_delays)
  • Randomly add reset between each sequence

Checking:

  • Ensure transactions are transmitted/received correctly
  • Ensure reset is handled correctly
V2 alert_test spi_host_alert_test

Verify common alert_test CSR that allows SW to mock-inject alert requests.

  • Enable a random set of alert requests by writing random value to alert_test CSR.
  • Check each alert_tx.alert_p pin to verify that only the requested alerts are triggered.
  • During alert_handshakes, write alert_test CSR again to verify that: If alert_test writes to current ongoing alert handshake, the alert_test request will be ignored. If alert_test writes to current idle alert handshake, a new alert_handshake should be triggered.
  • Wait for the alert handshakes to finish and verify alert_tx.alert_p pins all sets back to 0.
  • Repeat the above steps a bunch of times.
V2 intr_test spi_host_intr_test

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

  • Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
  • Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s).
  • Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
  • Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
  • Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
  • Repeat the above steps a bunch of times.
V2 tl_d_oob_addr_access spi_host_tl_errors

Access out of bounds address and verify correctness of response / behavior

V2 tl_d_illegal_access spi_host_tl_errors

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the [TLUL spec]({{< relref "hw/ip/tlul/doc/_index.md#explicit-error-cases" >}})

  • TL-UL protocol error cases
    • invalid opcode
    • some mask bits not set when opcode is PutFullData
    • mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
    • mask and address misaligned, e.g. a_address = 0x01, a_mask = 'b0001
    • address and size aren't aligned, e.g. a_address = 0x01, a_size != 0
    • size is greater than 2
  • OpenTitan defined error cases
    • access unmapped address, expect d_error = 1 when devmode_i == 1
    • write a CSR with unaligned address, e.g. a_address[1:0] != 0
    • write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
    • write a memory with a_mask != '1 when it doesn't support partial accesses
    • read a WO (write-only) memory
    • write a RO (read-only) memory
V2 tl_d_outstanding_access spi_host_csr_hw_reset
spi_host_csr_rw
spi_host_csr_aliasing
spi_host_same_csr_outstanding

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

V2 tl_d_partial_access spi_host_csr_hw_reset
spi_host_csr_rw
spi_host_csr_aliasing
spi_host_same_csr_outstanding

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

V3 tl_intg_err spi_host_tl_intg_err

Verify that the data integrity check violation generates an alert.

Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.

Covergroups

Name Description
alert_cg

Collect coverage to verify all alerts are triggered correctly

cdc_cg

Collect coverage on the relationship between the core_clk and the spi_sck to verify that both scenarios with both a slow spi_sck, a very fast spi_sck (2x core_clk) and where the two clocks are very close has been tested

command_cg

Collect coverage that different commant settings, important cross:

  • Direction and SPEED
  • CSAAT and SPEED
config_opts_cg

Collect coverage on the config opts register, some important crosses:

  • CPOL and CPHA, check all 4 combinations are tested
  • CSNLEAD, CSNTRAIL and CSNIDLE
control_cg

Collect coverage on the control register to make sure all options are excercised

  • Tx and RX water mark should have a bin for min value, max value and one for everything in between
csid_cg

Collect coverage that different IDs are used.

duplex_cg

Collect coverage that we verified both duplex and half duplex

error_en_cg

Collect coverage that all possible errors was enabled

error_status_cg

Collect coverage that all possible errors was seen

event_en_cg

Collect coverage that all events was enabled and seen

interrupts_cg

Collect coverage that all types of interrupt was seen

long_commands_cg

Collect coverage to verify that both a read and write command longer than 4 bytes was seen

rx_fifo_underflow_cg

Collect coverage to verify that an attempt was made to underflow the RX FIFO by attempting to read from an empty FIFO

status_cg

Collect coverage on the status register to make sure all scenarios are checked

tl_errors_cg

Cover the following error cases on TL-UL bus:

  • TL-UL protocol error cases.
  • OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.
tl_intg_err_cg

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

tl_intg_err_mem_subword_cg

Cover the kinds of integrity errors with byte enabled write on memory.

Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.

tx_fifo_overflow_cg

Collect coverage to verify that an attempt was made to overflow the TX FIFO by attempting to write to a full FIFO

unaligned_data_cg

Collect coverage the alignment of writes to the data window to verify that all possible alignments was seen