SRAM_CTRL DV document

Goals

  • DV
    • Verify all SRAM_CTRL IP features by running dynamic simulations with a SV/UVM based testbench
    • Develop and run all tests based on the DV plan below towards closing code and functional coverage on the IP and all of its sub-modules
  • FPV
    • Verify TileLink device protocol compliance with an SVA based testbench

Current status

Design features

For detailed information on SRAM_CTRL design features, please see the SRAM_CTRL HWIP technical specification.

Testbench architecture

SRAM_CTRL testbench has been constructed based on the CIP testbench architecture.

Block diagram

Block diagram

Top level testbench

Top level testbench is located at hw/ip/sram_ctrl/dv/tb/tb.sv. It instantiates the SRAM_CTRL DUT module hw/ip/sram_ctrl/rtl/sram_ctrl.sv. In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db:

Common DV utility components

The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

Compile-time configurations

[list compile time configurations, if any and what are they used for]

Global types & methods

All common types and methods defined at the package level can be found in sram_ctrl_env_pkg. Some of them in use are:

[list a few parameters, types & methods; no need to mention all]

TL_agent

SRAM_CTRL testbench instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into SRAM_CTRL device.

UVC/agent 1

[Describe here or add link to its README]

UVC/agent 2

[Describe here or add link to its README]

UVM RAL Model

The SRAM_CTRL RAL model is created with the ralgen FuseSoC generator script automatically when the simulation is at the build stage.

It can be created manually by invoking regtool:

Reference models

[Describe reference models in use if applicable, example: SHA256/HMAC]

Stimulus strategy

Test sequences

All test sequences reside in hw/ip/sram_ctrl/dv/env/seq_lib. The sram_ctrl_base_vseq virtual sequence is extended from cip_base_vseq and serves as a starting point. All test sequences are extended from sram_ctrl_base_vseq. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. Some of the most commonly used tasks / functions are as follows:

  • task 1:
  • task 2:

Functional coverage

To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:

  • cg1:
  • cg2:

Self-checking strategy

Scoreboard

The sram_ctrl_scoreboard is primarily used for end to end checking. It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:

  • analysis port1:
  • analysis port2:

Assertions

  • TLUL assertions: The tb/sram_ctrl_bind.sv binds the tlul_assert assertions to the IP to ensure TileLink interface protocol compliance.
  • Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
  • assert prop 1:
  • assert prop 2:

Building and running tests

We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:

$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/sram_ctrl/dv/sram_ctrl_sim_cfg.hjson -i sram_ctrl_smoke

DV plan

Milestone Name Description Tests
V1 smoke

This test performs basic SRAM initialization procedure and tests basic memory function:

  • Initialize SRAM memory to zero
  • Perform some random memory operations, verify that they all succeed with an all-zero key and nonce
  • Request a new scrambling key from the OTP interface and verify that:
    • A valid key is received
    • The key seed used by OTP is valid
  • Perform a number of random memory accesses to the SRAM, verify that all accesses were executed correctly using the mem_bkdr_if
sram_ctrl_base_smoke
V1 csr_hw_reset

Verify the reset values as indicated in the RAL specification.

  • Write all CSRs with a random value.
  • Apply reset to the DUT as well as the RAL model.
  • Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
sram_ctrl_base_csr_hw_reset
V1 csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

  • Loop through each CSR to write it with a random value.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
sram_ctrl_base_csr_rw
V1 csr_bit_bash

Verify no aliasing within individual bits of a CSR.

  • Walk a 1 through each CSR by flipping 1 bit at a time.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • This verify that writing a specific bit within the CSR did not affect any of the other bits.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
sram_ctrl_base_csr_bit_bash
V1 csr_aliasing

Verify no aliasing within the CSR address space.

  • Loop through each CSR to write it with a random value
  • Shuffle and read ALL CSRs back.
  • All CSRs except for the one that was written in this iteration should read back the previous value.
  • The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
sram_ctrl_base_csr_aliasing
V1 csr_mem_rw_with_rand_reset

Verify random reset during CSR/memory access.

  • Run csr_rw sequence to randomly access CSRs
  • If memory exists, run mem_partial_access in parallel with csr_rw
  • Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
sram_ctrl_base_csr_mem_rw_with_rand_reset
V2 multiple_keys

In this test we request multiple scrambling keys from OTP and verify that the memory scrambling is performed correctly even with multiple seeds. Perform the following steps:

  • Initialize the memory to zero
  • Perform some random memory operations, verify that they succeed with an all-zero key and nonce
  • Repeat the following steps a number of times:
    • Get a scrambling key from the OTP interface
    • Perform a number of random memory accesses to the SRAM
  • Verify that all memory access succeed even if the scrambling key changes at arbitrary intervals
sram_ctrl_base_multiple_keys
V2 stress_pipeline

This test is the same as the multiple_keys_test but we now do a series of back-to-back memory accesses at each random address in order to create read/write conflicts and stress the encryption pipeline.

sram_ctrl_base_stress_pipeline
V2 bijection

In this test we iterate through each address in the SRAM memory. For each address write the current address to the SRAM.

After this is done, read every address and check that the stored data is equivalent to the current address.

This will verify that the SRAM encryption mechanism is actually bijective, and will not cause any address collisions.

e.g. if the encryption scheme causes addresses 0x1 and 0x2 to collide and we write 0x1 and 0x2 respectively, we will see a return value of 0x2 when we read from 0x1, instead of the expected 0x1.

This process will be repeated for a number of new key seeds.

sram_ctrl_base_bijection
V2 mem_tl_errors

This test will reuse the common tl_access_tests to run TLUL error sequences on the SRAM TLUL interface to verify that erroneous TLUL transactions are handled correctly.

sram_ctrl_base_mem_tl_errors
V2 access_during_key_req

This test is the same as the multiple_keys test, except we make sure to sequence some memory transactions while a key request to OTP is still pending. Verify that these transactions are completely ignored by the memory.

TODO: Behavior might change in future to throw an error instead of ignore, should be reflected in TB.

sram_ctrl_base_access_during_key_req
V2 lc_escalation

This test is the same as the multiple_keys test, except we now randomly assert the lifecycle escalation signal. Upon sending an escalation request, we verify that the DUT has properly latched it, and all scrambling state has been reset. In this state, we perform some memory accesses, they should all be blocked and not go through. We then issue a reset to the SRAM to get it out of the terminal state, and issue a couple of memory accesses just to make sure everything is still in working order.

sram_ctrl_base_lc_escalation
V2 parity

This test is the same as the multiple_keys test, except we randomly inject a parity error into the memory (TODO: figure out how exactly to do this). Verify that the SRAM reports the error and the faulty address correctly, and that the alert is sent out properly. We then perform some memory accesses and verify that none of them go through. This error is terminal, so like the lc_escalation test, issue a reset and then perform some memory accesses to make sure everything comes back online correctly.

sram_ctrl_base_parity
V2 alert_test

Verify common alert_test CSR that allows SW to mock-inject alert requests.

  • Enable a random set of alert requests by writing random value to alert_test CSR.
  • Check each alert_tx.alert_p pin to verify that only the requested alerts are triggered.
  • During alert_handshakes, write alert_test CSR again to verify that: If alert_test writes to current ongoing alert handshake, the alert_test request will be ignored. If alert_test writes to current idle alert handshake, a new alert_handshake should be triggered.
  • Wait for the alert handshakes to finish and verify alert_tx.alert_p pins all sets back to 0.
  • Repeat the above steps a bunch of times.
sram_ctrl_base_alert_test
V2 tl_d_oob_addr_access

Access out of bounds address and verify correctness of response / behavior

sram_ctrl_base_tl_errors
V2 tl_d_illegal_access

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested

  • TL-UL protocol error cases
    • Unsupported opcode. e.g a_opcode isn't Get, PutPartialData or PutFullData
    • Mask isn't all active if opcode = PutFullData
    • Mask isn't in enabled lanes, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
    • Mask doesn't align with address, e.g. a_address = 0x01, a_mask = 'b0001
    • Address and size aren't aligned, e.g. a_address = 0x01, a_size != 0
    • Size is over 2.
  • OpenTitan defined error cases
    • Access unmapped address, return d_error = 1 when devmode_i == 1
    • Write CSR with unaligned address, e.g. a_address[1:0] != 0
    • Write CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
    • Write a memory without enabling all lanes (a_mask = '1) if memory doesn't support byte enabled write
    • Read a WO (write-only) memory
sram_ctrl_base_tl_errors
V2 tl_d_outstanding_access

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

sram_ctrl_base_csr_hw_reset
sram_ctrl_base_csr_rw
sram_ctrl_base_csr_aliasing
sram_ctrl_base_same_csr_outstanding
V2 tl_d_partial_access

Access CSR with one or more bytes of data For read, expect to return all word value of the CSR For write, enabling bytes should cover all CSR valid fields

sram_ctrl_base_csr_hw_reset
sram_ctrl_base_csr_rw
sram_ctrl_base_csr_aliasing
sram_ctrl_base_same_csr_outstanding
V3 executable

TODO: This feature is not yet implemented, so this description will become more detailed at that time.

This test is meant to test executable SRAM (Ibex fetching data from SRAM).

This test is the same as the multiple_keys test, except now we randomly set the sram_fetch (name TBD) input(s) from the OTP controller.

Verify that in this scenario all memory transactions matching the Host user ID go through, but all transactions with mismatched user IDs error out.

sram_ctrl_base_executable