SRAM_CTRL DV document
Goals
- DV
- Verify all SRAM_CTRL IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules, except Pre-verified sub-modules.
- FPV
- Verify TileLink device protocol compliance with an SVA based testbench
Pre-verified sub-modules
The following sub-modules are pre-verified:
Only toggle coverage on the IOs of these sub-modules is enabled for coverage collection.
Current status
Design features
For detailed information on SRAM_CTRL design features, please see the SRAM_CTRL HWIP technical specification.
Testbench architecture
SRAM_CTRL testbench has been constructed based on the CIP testbench architecture. Note that there are 2 separate TLUL interfaces exposed to the rest of the OpenTitan system - one for CSR accesses, and one for accessing memory directly. This is because the “full” DUT consists of the actual SRAM memory controller (which contains the CSR file) connected to a scrambling RAM primitive, with a TLUL adapter module to convert TL requests on the memory TL interface into SRAM format for the RAM primitive.
Block diagram
Top level testbench
Top level testbench is located at hw/ip/sram_ctrl/dv/tb/tb.sv
. It instantiates the SRAM_CTRL DUT module hw/ip/sram_ctrl/rtl/sram_ctrl.sv
.
In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db
:
- Clock and reset interface
- TileLink host interface
- SRAM_CTRL IOs
- Interrupts (
pins_if
) - Alerts (
alert_esc_if
) - Devmode (
pins_if
)
Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
Compile-time configurations
Two compile-time configurations are tested:
sram_ctrl_main
- this configuration uses a 15-bit wide address space to emulate the main SRAM used in the full design and enables parameterINSTR_EXEC
to allow TLUL instruction fetching when some runtime conditions are met.sram_ctrl_ret
- this configuration uses a 10-bit-wide address space to emulate the retention SRAM used in the full design and turns off parameterINSTR_EXEC
to disable TLUL instruction fetching altogether.
A macro-define SRAM_ADDR_WIDTH
is defined as a build option in hw/ip/sram_ctrl/dv/sram_ctrl_base_sim_cfg.hjson
, which is used to set the correct compile-time settings for each configuration.
Global types & methods
All common types and methods defined at the package level can be found in
sram_ctrl_env_pkg
. Some of them in use are:
// number of bits in a full KDI transactions
parameter int KDI_DATA_SIZE = 1 + otp_ctrl_pkg::SramKeyWidth + otp_ctrl_pkg::SramNonceWidth;
// a completed KDI transaction takes 4 cycles to be fully synchronized into the
// SRAM clock domain
parameter int KDI_PROPAGATION_CYCLES = 4;
// a LC escalation request needs 3 cycles to be fully propagated through the DUT
parameter int LC_ESCALATION_PROPAGATION_CYCLES = 3;
typedef enum bit {
SramCtrlRenewScrKey = 0,
SramCtrlInit = 1
} sram_ctrl_e;
typedef enum bit [2:0] {
SramCtrlError = 0,
SramCtrlEscalated = 1,
SramCtrlScrKeyValid = 2,
SramCtrlScrKeySeedValid = 3,
SramCtrlInitDone = 4
} sram_ctrl_status_e;
TL_agent
SRAM_CTRL testbench instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into SRAM_CTRL device.
Alert agents
The SRAM_CTRL testbench instantiates 2 alert agents for:
- fatal_intg_error - signals a transmission integrity error
- fatal_parity_error - signals an internal parity error in the memory primitive
The alert agents provide the ability to independently drive and monitor both alert handshakes.
SRAM_CTRL_LC_IF
The SRAM_CTRL IP has a simple sideband interface to the LC_CTRL to receive escalation requests. This interface initializes the escalation bus and utilizes a simple task to drive escalation requests.
SRAM_CTRL_EXEC_IF
The SRAM_CTRL IP has an interface to enable instruction execution from SRAM - allowing the Icache to fetch instruction data from the SRAM for the CPU. This interface contains the necessary Lifecycle and OTP structs to enable and disable this functionality.
UVM RAL Model
The SRAM_CTRL RAL model is created with the ralgen
FuseSoC generator script automatically when the simulation is at the build stage.
It can be created manually by invoking regtool
:
Besides default RAL that provides the access to CSRs, there is another RAL for SRAM memory.
This RAL is in sram_ctrl_prim_ral_pkg.sv
, it is added manually and enabled with all the common CSR and memory tests, such as mem_walk, tl_errors, tl_intg_err, etc.
Reference models
There are 3 DV reference models used in this testbench.
- The SRAM_CTRL testbench uses a SystemVerilog golden model for its address and data scrambling to ensure that internal encryption and decryption perform correctly.
This golden model,
sram_scrambler_pkg
is tightly integrated with the mem_bkdr_util for ease of use such that we can choose to enable encryption on any backdoor access. - The frontdoor check
mem_model
is also enabled in cip_base_scoreboard. The model is invoked at the end of the transaction as follows:- If it’s write, store the data on the address in the memory array.
- If it’s read and the address has been written, compare read value with stored value.
- If it’s read and the address has NOT been written, skip checking.
There are some limitations in the frontdoor check as follows:
- Can’t check ECC if encoding and decoding match.
- Can’t check the read value if the address hasn’t been written after init or after key request.
- Can’t check the write value if the address isn’t read after the write.
- Not aware of any B2B hazard (such as RAW).
- The backdoor check
mem_bkdr_scb
is used to ensure frontdoor access matches with the backdoor expected value. Thesram_scrambler_pkg
is invoked inmem_bkdr_scb
This backdoor check covers all the limitations of frontdoor check. There is a limitation as follows, which can be covered by frontdoor check.- Can’t check when memory is modified unintentionally after the access is completed.
Stimulus strategy
Test sequences
All test sequences reside in hw/ip/sram_ctrl/dv/env/seq_lib
.
The sram_ctrl_base_vseq
virtual sequence is extended from cip_base_vseq
and serves as a starting point.
All test sequences are extended from sram_ctrl_base_vseq
.
It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:
- do_rand_ops: This task sends an arbitrary number of random TL transactions to the memory primitive.
- do_stress_ops: This task sends an arbitrary number of random TL transactions to the same word in memory, to stress the memory’s data forwarding functionalities.
Functional coverage
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:
- b2b_access_types_cg (imported from mem_bkdr_scb): Cover that all combinations of b2b read/write scenario (R/R, R/W, W/R, W/W) with or without using the same address.
- subword_access_cg: Cover all kinds of partial accesses.
Self-checking strategy
Scoreboard
The sram_ctrl_scoreboard
is primarily used for end to end checking.
It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:
- tl_a_chan_fifo: TL address channel for CSR accesses
- tl_d_chan_fifo: TL data channel for CSR accesses
- alert_fifos: Alert handshakes
- sram_tl_a_chan_fifo: TL address channel for memory accesses
- sram_tl_d_chan_fifo: TL data channel for memory accesses
- kdi_fifo: For key refresh operations from OTP_CTRL
All CSR accesses made to the SRAM_CTRL register file are tracked and predicted by the scoreboard.
Verifying memory accesses is somewhat involved, and makes heavy use of the mem_bkdr_util
.
At a high level, whenever a TL access is made to memory, all relevant information is stored in an sram_trans_t
struct.
Refer to section “Reference models” for the SRAM memory checking.
The testbench will also sporadically trigger the DUT to issue a request for a new key and nonce from the OTP controller. After receiving the fresh key and nonce from the KDI agent, those new values will then be used for all encryption/decryption accesses using the memory backdoor interface.
If a lifecycle escalation request is issued during SRAM operation, the scoreboard will detect it and then check that no further memory requests are accepted. The testbench will then issue a system-level reset, as a lifecycle escalation is a terminal state.
To check that the SRAM’s executable configurations are functioning correct is relatively more straightforward.
First, it’s important to note that all incoming TL memory transactions are tagged as either InstrType
or DataType
, indicating whether the transaction is fetching an instruction word or a data word.
If the scoreboard detects that an incoming transaction is tagged as InstrType
, we first check that the SRAM is properly configured in executable mode to accept InstrType
transactions.
If the DUT is configured correctly the scoreboard will let the memory transaction finish being checked, otherwise the scoreboard will discard that transaction - this approach makes it easy to check whether the design is behaving correctly as well.
Assertions
- TLUL assertions: The
tb/sram_ctrl_bind.sv
binds thetlul_assert
assertions to the IP to ensure TileLink interface protocol compliance. - Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
Building and running tests
We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:
$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/sram_ctrl/dv/sram_ctrl_sim_cfg.hjson -i sram_ctrl_smoke
Testplan
Testpoints
Milestone | Name | Tests | Description |
---|---|---|---|
V1 | smoke | sram_ctrl_smoke | This test performs basic SRAM initialization procedure and tests basic memory function:
|
V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | Verify the reset values as indicated in the RAL specification.
|
V1 | csr_rw | sram_ctrl_csr_rw | Verify accessibility of CSRs as indicated in the RAL specification.
|
V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | Verify no aliasing within individual bits of a CSR.
|
V1 | csr_aliasing | sram_ctrl_csr_aliasing | Verify no aliasing within the CSR address space.
|
V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | Verify random reset during CSR/memory access.
|
V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw sram_ctrl_csr_aliasing | Verify regwen CSR and its corresponding lockable CSRs.
Note:
This is only applicable if the block contains regwen and locakable CSRs. |
V1 | mem_walk | sram_ctrl_mem_walk | Verify accessibility of all memories in the design.
|
V1 | mem_partial_access | sram_ctrl_mem_partial_access | Verify partial-accessibility of all memories in the design.
|
V2 | multiple_keys | sram_ctrl_multiple_keys | In this test we request multiple scrambling keys from OTP and verify that the memory scrambling is performed correctly even with multiple seeds. Perform the following steps:
|
V2 | stress_pipeline | sram_ctrl_stress_pipeline | This test is the same as the multiple_keys_test but we now do a series of back-to-back memory accesses at each random address in order to create read/write conflicts and stress the encryption pipeline. |
V2 | bijection | sram_ctrl_bijection | In this test we iterate through each address in the SRAM memory. For each address write the current address to the SRAM. After this is done, read every address and check that the stored data is equivalent to the current address. This will verify that the SRAM encryption mechanism is actually bijective, and will not cause any address collisions. e.g. if the encryption scheme causes addresses 0x1 and 0x2 to collide and we write 0x1 and 0x2 respectively, we will see a return value of 0x2 when we read from 0x1, instead of the expected 0x1. This process will be repeated for a number of new key seeds. |
V2 | access_during_key_req | sram_ctrl_access_during_key_req | This test is the same as the multiple_keys test, except we make sure to sequence some memory transactions while a key request to OTP is still pending. Verify that these transactions are completely ignored by the memory. TODO: Behavior might change in future to throw an error instead of ignore, should be reflected in TB. |
V2 | lc_escalation | sram_ctrl_lc_escalation | This test is the same as the multiple_keys test, except we now randomly assert the lifecycle escalation signal. Upon sending an escalation request, we verify that the DUT has properly latched it, and all scrambling state has been reset. In this state, we perform some memory accesses, they should all be blocked and not go through. We then issue a reset to the SRAM to get it out of the terminal state, and issue a couple of memory accesses just to make sure everything is still in working order. |
V2 | executable | sram_ctrl_executable | This test is intended to test the "execute from SRAM" feature, in which TLUL memory
transactions tagged with the This behavior is enabled by either setting the If this functionality is disabled, any memory transaction NOT tagged as |
V2 | partial_access | sram_ctrl_partial_access sram_ctrl_partial_access_b2b | This test is intended to test a lot of partial accesses with random addresses or back-to-back accesses. Reuse the |
V2 | max_throughput | sram_ctrl_max_throughput sram_ctrl_throughput_w_partial_write | This test is intended to test the max throughput of the SRAM. Without partial write, if driver doesn't introduce any delay, it takes N+1 cycles to finish N SRAM read/write accesses. With partial write, it needs 2 extra cycles per partial write. |
V2 | regwen | sram_ctrl_regwen | This test is intended to test
Both |
V2 | stress_all | sram_ctrl_stress_all |
|
V2 | alert_test | sram_ctrl_alert_test | Verify common
|
V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | Access out of bounds address and verify correctness of response / behavior |
V2 | tl_d_illegal_access | sram_ctrl_tl_errors | Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the [TLUL spec]({{< relref "hw/ip/tlul/doc/_index.md#explicit-error-cases" >}})
|
V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset sram_ctrl_csr_rw sram_ctrl_csr_aliasing sram_ctrl_same_csr_outstanding | Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address. |
V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset sram_ctrl_csr_rw sram_ctrl_csr_aliasing sram_ctrl_same_csr_outstanding | Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields. |
V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | Verify data integrity is stored in the passthru memory rather than generated after a read.
|
V2S | tl_intg_err | sram_ctrl_tl_intg_err sram_ctrl_sec_cm | Verify that the data integrity check violation generates an alert.
|
V2S | prim_count_check | sram_ctrl_sec_cm | Verify that violating prim_count counter properties generate a fatal alert. Stimulus:
Checks:
|
V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | Verify the countermeasure(s) BUS.INTEGRITY. |
V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | Verify the countermeasure(s) CTRL.CONFIG.REGWEN. The
|
V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | Verify the countermeasure(s) EXEC.CONFIG.REGWEN. |
V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | Verify the countermeasure(s) EXEC.CONFIG.MUBI. Refer to the testpoint |
V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | Verify the countermeasure(s) EXEC.INTERSIG.MUBI. Refer to the testpoint |
V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | Verify the countermeasure(s) LC_HW_DEBUG_EN.INTERSIG.MUBI. Refer to the testpoint |
V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | Verify the countermeasure(s) LC_ESCALATE_EN.INTERSIG.MUBI. Refer to the testpoint |
V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | Verify the countermeasure(s) MEM.INTEGRITY. |
V2S | sec_cm_mem_scramble | sram_ctrl_smoke | Verify the countermeasure(s) MEM.SCRAMBLE. This is verified in all non-CSR tests. |
V2S | sec_cm_addr_scramble | sram_ctrl_smoke | Verify the countermeasure(s) ADDR.SCRAMBLE. This is verified in all non-CSR tests. |
V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | Verify the countermeasure(s) INSTR.BUS.LC_GATED." Refer to the testpoint |
V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | Verify the countermeasure(s) KEY.GLOBAL_ESC. |
V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | Verify the countermeasure(s) KEY.LOCAL_ESC. Besides the stimulus and checks mentioned in `prim_count_check``, also have following checks:
|
V2S | sec_cm_ctr_redun | sram_ctrl_sec_cm | Verify the countermeasure(s) CTR.REDUN. Besides the stimulus and checks mentioned in
|
V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | Verify the countermeasure(s) SCRAMBLE.KEY.SIDELOAD. Simulation can't really prove that the sideload key is unreachable by SW. However, from defined CSRs and memory returned data, there is no way to read scramble key by SW. |
V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers. |
Covergroups
Name | Description |
---|---|
access_during_key_req_cg | Covers that SRAM handles memory accesses during key requests. |
b2b_access_types_cg |
|
executable_cg | Covers the various important scenarios that can enable SRAM executability.
Crosses CSR |
key_seed_valid_cg | Covers SRAM receiving a key from OTP in Off/On states, with both valid and invalid key seeds. |
lc_escalation_idle_cg | Covers the assertion of LC escalation occurs during idle or SRAM memory access. |
regwen_val_when_new_value_written_cg | Cover each lockable reg field with these 2 cases:
This is only applicable if the block contains regwen and locakable CSRs. |
subword_access_cg | Covers that all possible types of subword accesses (both reads and writes) have been performed. |
tl_errors_cg | Cover the following error cases on TL-UL bus:
|
tl_intg_err_cg | Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check. Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied. |