SRAM_CTRL DV document
- Verify all SRAM_CTRL IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the DV plan below towards closing code and functional coverage on the IP and all of its sub-modules
- Verify TileLink device protocol compliance with an SVA based testbench
For detailed information on SRAM_CTRL design features, please see the SRAM_CTRL HWIP technical specification.
SRAM_CTRL testbench has been constructed based on the CIP testbench architecture.
Top level testbench
Top level testbench is located at
hw/ip/sram_ctrl/dv/tb/tb.sv. It instantiates the SRAM_CTRL DUT module
In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into
- Clock and reset interface
- TileLink host interface
- SRAM_CTRL IOs
- Interrupts (
- Alerts (
- Devmode (
Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
[list compile time configurations, if any and what are they used for]
Global types & methods
All common types and methods defined at the package level can be found in
sram_ctrl_env_pkg. Some of them in use are:
[list a few parameters, types & methods; no need to mention all]
SRAM_CTRL testbench instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into SRAM_CTRL device.
[Describe here or add link to its README]
[Describe here or add link to its README]
UVM RAL Model
The SRAM_CTRL RAL model is created with the
ralgen FuseSoC generator script automatically when the simulation is at the build stage.
It can be created manually by invoking
[Describe reference models in use if applicable, example: SHA256/HMAC]
All test sequences reside in
sram_ctrl_base_vseq virtual sequence is extended from
cip_base_vseq and serves as a starting point.
All test sequences are extended from
It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:
- task 1:
- task 2:
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:
sram_ctrl_scoreboard is primarily used for end to end checking.
It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:
- analysis port1:
- analysis port2:
- TLUL assertions: The
tlul_assertassertions to the IP to ensure TileLink interface protocol compliance.
- Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
- assert prop 1:
- assert prop 2:
Building and running tests
We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:
$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/sram_ctrl/dv/sram_ctrl_sim_cfg.hjson -i sram_ctrl_smoke
This test performs basic SRAM initialization procedure and tests basic memory function:
Verify the reset values as indicated in the RAL specification.
Verify accessibility of CSRs as indicated in the RAL specification.
Verify no aliasing within individual bits of a CSR.
Verify no aliasing within the CSR address space.
Verify random reset during CSR/memory access.
In this test we request multiple scrambling keys from OTP and verify that the memory scrambling is performed correctly even with multiple seeds. Perform the following steps:
This test is the same as the multiple_keys_test but we now do a series of back-to-back memory accesses at each random address in order to create read/write conflicts and stress the encryption pipeline.
In this test we iterate through each address in the SRAM memory. For each address write the current address to the SRAM.
After this is done, read every address and check that the stored data is equivalent to the current address.
This will verify that the SRAM encryption mechanism is actually bijective, and will not cause any address collisions.
e.g. if the encryption scheme causes addresses 0x1 and 0x2 to collide and we write 0x1 and 0x2 respectively, we will see a return value of 0x2 when we read from 0x1, instead of the expected 0x1.
This process will be repeated for a number of new key seeds.
This test will reuse the common tl_access_tests to run TLUL error sequences on the SRAM TLUL interface to verify that erroneous TLUL transactions are handled correctly.
This test is the same as the multiple_keys test, except we make sure to sequence some memory transactions while a key request to OTP is still pending. Verify that these transactions are completely ignored by the memory.
TODO: Behavior might change in future to throw an error instead of ignore, should be reflected in TB.
This test is the same as the multiple_keys test, except we now randomly assert the lifecycle escalation signal. Upon sending an escalation request, we verify that the DUT has properly latched it, and all scrambling state has been reset. In this state, we perform some memory accesses, they should all be blocked and not go through. We then issue a reset to the SRAM to get it out of the terminal state, and issue a couple of memory accesses just to make sure everything is still in working order.
This test is the same as the multiple_keys test, except we randomly inject a parity error into the memory (TODO: figure out how exactly to do this). Verify that the SRAM reports the error and the faulty address correctly, and that the alert is sent out properly. We then perform some memory accesses and verify that none of them go through. This error is terminal, so like the lc_escalation test, issue a reset and then perform some memory accesses to make sure everything comes back online correctly.
Access out of bounds address and verify correctness of response / behavior
Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested
Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.
Access CSR with one or more bytes of data For read, expect to return all word value of the CSR For write, enabling bytes should cover all CSR valid fields
TODO: This feature is not yet implemented, so this description will become more detailed at that time.
This test is meant to test executable SRAM (Ibex fetching data from SRAM).
This test is the same as the multiple_keys test, except now we randomly set the
Verify that in this scenario all memory transactions matching the Host user ID go through, but all transactions with mismatched user IDs error out.