System Reset Control (Chrome OS) Technical Specification

Overview

This document specifies the functionality of the System Reset Control (sysrst_ctrl) block which implements Chrome-OS-Platform-specific system and reset functionality. This IP block implements keyboard and button combination-triggered action and the Embedded Controller (EC) reset stretching and OpenTitan reset request logic. This module conforms to the Comportable guideline for peripheral functionality.. See that document for integration overview within the broader top level system.

Features

The IP block implements the following features:

  • Always-on: uses the always-on power and clock domain
  • EC reset pulse duration control and stretching
  • Keyboard and button combination (combo) triggered action
  • AC_present can trigger interrupt
  • Configuration registers can be set and locked until the next chip reset
  • Pin output override

Description

The sysrst_ctrl logic is very simple. It looks up the configuration registers to decide how long the EC reset pulse duration and how long the keyboard debounce timer should be. Also what actions to take (e.g. Interrupt, EC reset, OpenTitan reset request, disconnect the battery from the power tree).

Compatibility

The configuration programming interface is not based on any existing interface.

Theory of Operations

sysrst_ctrl Block Diagram

The block diagram above shows a conceptual view of the sysrst_ctrl block, which consists of 3 main modules: The first is the configuration and status registers, the second is the keyboard combo debounce and detection logic, and the third is the pinout override logic.

The sysrst_ctrl has four input pins (pwrb_in, key[0,1,2]_in) with corresponding output pins (pwrb_out, key[0,1,2]_out). During normal operation the sysrst_ctrl will pass the pin information directly from the input pins to the output pins with optional inversion. Combinations of the inputs being active for a specified time can be detected and used to trigger actions. The override logic allows the output to be overridden (i.e. not follow the corresponding input) based either on trigger or software settings. This allows the security chip to take over the inputs for its own use without disturbing the main user.

The sysrst_ctrl also controls two active-low open-drain I/Os named flash_wp_out_l and ec_rst_in_l / ec_rst_out_l. The ec_rst_in_l / ec_rst_out_l signals are connected to the same bidirectional pin of the OpenTitan chip, and are used to either reset the embedded controller (EC), or to detect self-reset of the EC and stretch the reset pulse (hence the bidirectional nature of this pin). This output is always asserted when sysrst_ctrl is reset (allowing its use as a power-on reset) and remains asserted until released by software. The flash write-protect output flash_wp_out_l is typically connected to the BIOS flash chip in the system. This output is always asserted when the sysrst_ctrl block is reset and remains asserted until released by software.

Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module sysrst_ctrl has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: clk_aon_i

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO:

Pin namedirectionDescription
ac_presentinput

A/C power is present

key0_ininput

VolUp button in tablet; column output from the EC in a laptop

key1_ininput

VolDown button in tablet; row input from keyboard matrix in a laptop

key2_ininput

TBD button in tablet; row input from keyboard matrix in a laptop

pwrb_ininput

Power button in both tablet and laptop

lid_openinput

Lid is open

bat_disableoutput

Battery is disconnected

flash_wp_loutput

flash_wp_l as an output to the open drain IO

key0_outoutput

Passthrough from key0_in, can be configured to invert

key1_outoutput

Passthrough from key1_in, can be configured to invert

key2_outoutput

Passthrough from key2_in, can be configured to invert

pwrb_outoutput

Passthrough from pwrb_in, can be configured to invert

z3_wakeupoutput

To enter Z3 mode and exit from Z4 sleep mode

ec_rst_linout

ec_rst_l as an inout to/from the open drain IO

Interrupts:

Interrupt NameDescription
sysrst_ctrl

common interrupt triggered by combo or keyboard actions

Security Alerts:

Alert NameDescription
fatal_fault

This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Signals

The table below lists the sysrst_ctrl intermodule signals.

Signal Direction Type Description
aon_ot_wkup_req_o output logic OpenTitan wake request signal to pwrmgr (running on AON clock).
aon_ot_rst_req_o output logic OpenTitan reset request to rstmgr (running on AON clock).
intr_sysrst_ctrl_o output logic Interrupt request to PLIC (running on bus clock).

Combo detection

Software can program the sysrst_ctrl block to detect certain button combos and for how long they have to be asserted until they trigger a programmable action. Let’s use the “Power button + Esc + Refresh” combo as an example:

  1. Software can define the three key values pwrb_in==0, key0_in==0 and key1_in==0 as trigger combination in the COM_SEL_CTL_0 register.
  2. The combo duration for which the above combo should be pressed (e.g. 10 seconds) can be configured via the COM_DET_CTL_0 register.
  3. Actions such as asserting ec_rst_out_l and raising an interrupt can be configured via the COM_OUT_CTL_0 register.
  4. The pulse width of the ec_rst_out_l pulse can be set in the EC_RST_CTL register.
  5. The software can optionally lock the sysrst_ctrl configuration via REGWEN

Once the above configuration is active, sysrst_ctrl will start the timer when a combo high (logic 1) to low (logic 0) transition is detected. Once the timing condition is met (10 seconds), sysrst_ctrl will assert ec_rst_out_l, the interrupt request and set the interrupt status register COMBO_INTR_STATUS to indicate the interrupt cause. The software interrupt handler should then read COMBO_INTR_STATUS register and clear the interrupt.

Auto-block key outputs

Software can program the sysrst_ctrl block to override the output value of specific passthrough signals, depending on whether certain input signals are asserted or not. Let’s use the “Power button + Esc + Refresh” combo as an example. When pwrb_in is asserted, key1_out (row) should be overridden so that sysrst_ctrl can detect if key0_in (column) is Refresh.

  1. The software enables the auto block feature and sets an appropriate debounce timer value in the AUTO_BLOCK_DEBOUNCE_CTL register.
  2. The software then defines the key outputs to auto override and their override values in the AUTO_BLOCK_OUT_CTL register.

Once the above configuration is active, sysrst_ctrl will detect a high (logic 1) to low (logic 0) transition on pwrb_in and check whether the key pwrb_in stays low for the programmed duration. If this condition is met, sysrst_ctrl will drive key1_out to the value programmed in AUTO_BLOCK_OUT_CTL.

Keyboard and input triggered interrupt

Software can program the sysrst_ctrl block to detect edge transitions on the pwrb_in, key0_in, key1_in, key2_in, ac_present_in and ec_rst_in_l signals and trigger an interrupt:

  1. Software first defines the input signal and the edge transition to detect (H->L or L->H) via the KEY_INTR_CTL register.
  2. The software then programs an appropriate debounce timer value to the KEY_INTR_DEBOUNCE_CTL register.

For example, when the power button is pressed, pwrb_in goes from logic 1 to logic 0 which would amount to an H->L transition. Likewise, when the power button is released, pwrb_in goes from logic 0 to logic 1 which would amount to an L->H transition. When sysrst_ctrl detects a transition (H->L or L->H) as specified in KEY_INTR_CTL and it meets the debounce requirement in KEY_INTR_DEBOUNCE_CTL, sysrst_ctrl sets the KEY_INTR_STATUS register to indicate the interrupt cause and send out a consolidated interrupt to the PLIC. The software interrupt handler should then read KEY_INTR_STATUS register and clear the interrupt.

Pin input value accessibility

sysrst_ctrl allows the software to read the raw input pin values via the PIN_IN_VALUE register like GPIOs. To this end, the hardware samples the raw input values of pwrb_in, key[0,1,2]_in, ac_present_in, ec_rst_in_l before they are being inverted, and synchronizes them onto the bus clock domain.

Pin output and keyboard inversion control

Software can optionally override all output signals, and change the signal polarity of some of the input and output signals. The output signal override feature always has higher priority than any of the combo pattern detection mechanisms described above.

The selection of output signals to override, and the override values are programmable and lockable via the PIN_LEGAL_CTL register. For example, PIN_LEGAL_CTL.EC_RST_L_0 to 1 and PIN_LEGAL_CTL.EC_RST_L_1 to 0 means that software allows ec_rst_out_l to be overridden with logic 0, but not with logic 1. If the SW locks the configuration with REGWEN, PIN_LEGAL_CTL cannot be modified until the next OpenTitan reset.

When the system is up and running, the software can modify PIN_OUT_CTL and PIN_OUT_VALUE to enable or disable the feature. For example, to release ec_rst_out_l after OpenTitan completes the reset, software can set PIN_OUT_CTL to 0 to stop the hardware from driving ec_rst_out_l to 0.

The input / output signal inversions can be programmed via the KEY_INVERT_CTL register. Input signals will be inverted before the combo detection logic, while output signals will be inverted after the output signal override logic.

EC and Power-on-reset

OpenTitan and EC will be reset together during power-on. When OpenTitan is in reset, ec_rst_out_l will be asserted (active low). The power-on-reset value of PIN_LEGAL_CTL.EC_RST_L_1 and PIN_OUT_CTL.EC_RST_L will guarantee that ec_rst_out_l remains asserted after OpenTitan reset is released. The software can release ec_rst_out_l explicitly by setting PIN_OUT_CTL.EC_RST_L to 0 during boot in order to complete the OpenTitan and EC power-on-reset sequence.

Note that since the sysrst_ctrl does not have control over the pad open-drain settings, software should properly initialize the pad attributes of the corresponding pad in the pinmux configuration before releasing ec_rst_out_l.

Flash Write Protect Output

Upon reset, the flash_wp_out_l signal will be asserted active low. The software can release flash_wp_out_l explicitly by setting PIN_OUT_CTL.FLASH_WP_L to 0 when needed. The flash_wp_out_l signal does not have a corresponding input signal such as the pwrb_in or key[0,1,2]_in. Hence, the value of flash_wp_out_l defaults to logic 0 when it is not explicitly driven via the override function.

Note that since the sysrst_ctrl does not have control over the pad open-drain settings, software should properly initialize the pad attributes of the corresponding pad in the pinmux configuration before releasing flash_wp_out_l.

Registers

sysrst_ctrl.INTR_STATE @ 0x0

Interrupt State Register

Reset default = 0x0, mask 0x1
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  sysrst_ctrl
BitsTypeResetNameDescription
0rw1c0x0sysrst_ctrl

common interrupt triggered by combo or keyboard actions


sysrst_ctrl.INTR_ENABLE @ 0x4

Interrupt Enable Register

Reset default = 0x0, mask 0x1
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  sysrst_ctrl
BitsTypeResetNameDescription
0rw0x0sysrst_ctrl

Enable interrupt when INTR_STATE.sysrst_ctrl is set.


sysrst_ctrl.INTR_TEST @ 0x8

Interrupt Test Register

Reset default = 0x0, mask 0x1
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  sysrst_ctrl
BitsTypeResetNameDescription
0wo0x0sysrst_ctrl

Write 1 to force INTR_STATE.sysrst_ctrl to 1.


sysrst_ctrl.ALERT_TEST @ 0xc

Alert Test Register

Reset default = 0x0, mask 0x1
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  fatal_fault
BitsTypeResetNameDescription
0wo0x0fatal_fault

Write 1 to trigger one alert event of this kind.


sysrst_ctrl.REGWEN @ 0x10

Configuration write enable control register

Reset default = 0x1, mask 0x1
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  write_en
BitsTypeResetNameDescription
0rw0c0x1write_en

config write enable. 0: cfg is locked(not writable); 1: cfg is not locked(writable)


sysrst_ctrl.EC_RST_CTL @ 0x14

EC reset control register

Reset default = 0x7d0, mask 0xffff
Register enable = REGWEN
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ec_rst_pulse
BitsTypeResetNameDescription
15:0rw0x7d0ec_rst_pulse

Configure the pulse width of ec_rst_l. 10-200ms, each step is 5us(200KHz clock)


sysrst_ctrl.ULP_AC_DEBOUNCE_CTL @ 0x18

Ultra low power AC debounce control register

Reset default = 0x1f40, mask 0xffff
Register enable = REGWEN
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ulp_ac_debounce_timer
BitsTypeResetNameDescription
15:0rw0x1f40ulp_ac_debounce_timer

Configure the debounce timer. 10-200ms, each step is 5us(200KHz clock)


sysrst_ctrl.ULP_LID_DEBOUNCE_CTL @ 0x1c

Ultra low power lid debounce control register

Reset default = 0x1f40, mask 0xffff
Register enable = REGWEN
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ulp_lid_debounce_timer
BitsTypeResetNameDescription
15:0rw0x1f40ulp_lid_debounce_timer

Configure the debounce timer. 10-200ms, each step is 5us(200KHz clock)


sysrst_ctrl.ULP_PWRB_DEBOUNCE_CTL @ 0x20

Ultra low power pwrb debounce control register

Reset default = 0x1f40, mask 0xffff
Register enable = REGWEN
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ulp_pwrb_debounce_timer
BitsTypeResetNameDescription
15:0rw0x1f40ulp_pwrb_debounce_timer

Configure the debounce timer. 10-200ms, each step is 5us(200KHz clock)


sysrst_ctrl.ULP_CTL @ 0x24

Ultra low power control register

Reset default = 0x0, mask 0x1
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  ulp_enable
BitsTypeResetNameDescription
0rw0x0ulp_enable

0: disable ULP wakeup feature and reset the ULP FSM; 1: enable ULP wakeup feature


sysrst_ctrl.ULP_STATUS @ 0x28

Ultra low power status

Reset default = 0x0, mask 0x1
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  ulp_wakeup
BitsTypeResetNameDescription
0rw1c0x0ulp_wakeup

0: ULP wakeup not detected; 1: ULP wakeup event is detected


sysrst_ctrl.WKUP_STATUS @ 0x2c

wakeup status

Reset default = 0x0, mask 0x1
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  wakeup_sts
BitsTypeResetNameDescription
0rw1c0x0wakeup_sts

0: wakeup event not detected; 1: wakeup event is detected


sysrst_ctrl.KEY_INVERT_CTL @ 0x30

configure key input output invert property

Reset default = 0x0, mask 0xfff
Register enable = REGWEN
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  z3_wakeup lid_open bat_disable ac_present pwrb_out pwrb_in key2_out key2_in key1_out key1_in key0_out key0_in
BitsTypeResetNameDescription
0rw0x0key0_in

0: don't invert; 1: invert

1rw0x0key0_out

0: don't invert; 1: invert

2rw0x0key1_in

0: don't invert; 1: invert

3rw0x0key1_out

0: don't invert; 1: invert

4rw0x0key2_in

0: don't invert; 1: invert

5rw0x0key2_out

0: don't invert; 1: invert

6rw0x0pwrb_in

0: don't invert; 1: invert

7rw0x0pwrb_out

0: don't invert; 1: invert

8rw0x0ac_present

0: don't invert; 1: invert

9rw0x0bat_disable

0: don't invert; 1: invert

10rw0x0lid_open

0: don't invert; 1: invert

11rw0x0z3_wakeup

0: don't invert; 1: invert


sysrst_ctrl.PIN_ALLOWED_CTL @ 0x34

This register determines which override values are allowed for a given output. If an override value programmed via PIN_OUT_VALUE is not configured as an allowed value, it will not have any effect.

Reset default = 0x82, mask 0xffff
Register enable = REGWEN
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flash_wp_l_1 z3_wakeup_1 key2_out_1 key1_out_1 key0_out_1 pwrb_out_1 ec_rst_l_1 bat_disable_1 flash_wp_l_0 z3_wakeup_0 key2_out_0 key1_out_0 key0_out_0 pwrb_out_0 ec_rst_l_0 bat_disable_0
BitsTypeResetNameDescription
0rw0x0bat_disable_0

0: not allowed; 1: allowed

1rw0x1ec_rst_l_0

0: not allowed; 1: allowed

2rw0x0pwrb_out_0

0: not allowed; 1: allowed

3rw0x0key0_out_0

0: not allowed; 1: allowed

4rw0x0key1_out_0

0: not allowed; 1: allowed

5rw0x0key2_out_0

0: not allowed; 1: allowed

6rw0x0z3_wakeup_0

0: not allowed; 1: allowed

7rw0x1flash_wp_l_0

1: not allowed; 1: allowed

8rw0x0bat_disable_1

0: not allowed; 1: allowed

9rw0x0ec_rst_l_1

0: not allowed; 1: allowed

10rw0x0pwrb_out_1

0: not allowed; 1: allowed

11rw0x0key0_out_1

0: not allowed; 1: allowed

12rw0x0key1_out_1

0: not allowed; 1: allowed

13rw0x0key2_out_1

0: not allowed; 1: allowed

14rw0x0z3_wakeup_1

0: not allowed; 1: allowed

15rw0x0flash_wp_l_1

0: not allowed; 1: allowed


sysrst_ctrl.PIN_OUT_CTL @ 0x38

Enables the override function for a specific pin.

Reset default = 0x82, mask 0xff
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  flash_wp_l z3_wakeup key2_out key1_out key0_out pwrb_out ec_rst_l bat_disable
BitsTypeResetNameDescription
0rw0x0bat_disable

0: disable override; 1: enable override

1rw0x1ec_rst_l

0: disable override; 1: enable override

2rw0x0pwrb_out

0: disable override; 1: enable override

3rw0x0key0_out

0: disable override; 1: enable override

4rw0x0key1_out

0: disable override; 1: enable override

5rw0x0key2_out

0: disable override; 1: enable override

6rw0x0z3_wakeup

0: disable override; 1: enable override

7rw0x1flash_wp_l

1: disable override; 1: enable override


sysrst_ctrl.PIN_OUT_VALUE @ 0x3c

Sets the pin override value. Note that only the values configured as 'allowed' in PIN_ALLOWED_CTL will have an effect. Otherwise the pin value will not be overridden.

Reset default = 0x0, mask 0xff
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  flash_wp_l z3_wakeup key2_out key1_out key0_out pwrb_out ec_rst_l bat_disable
BitsTypeResetNameDescription
0rw0x0bat_disable

0: override to 1b0; 1: override to 1b1

1rw0x0ec_rst_l

0: override to 1b0; 1: override to 1b1

2rw0x0pwrb_out

0: override to 1b0; 1: override to 1b1

3rw0x0key0_out

0: override to 1b0; 1: override to 1b1

4rw0x0key1_out

0: override to 1b0; 1: override to 1b1

5rw0x0key2_out

0: override to 1b0; 1: override to 1b1

6rw0x0z3_wakeup

0: override to 1b0; 1: override to 1b1

7rw0x0flash_wp_l

0: override to 1b0; 1: override to 1b1


sysrst_ctrl.PIN_IN_VALUE @ 0x40

For SW to read the sysrst_ctrl inputs like GPIO

Reset default = 0x0, mask 0x7f
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  lid_open key2_in key1_in key0_in pwrb_in ec_rst_l ac_present
BitsTypeResetNameDescription
0ro0x0ac_present

raw ac_present value; before the invert logic

1ro0x0ec_rst_l

raw ec_rst_l value; before the invert logic

2ro0x0pwrb_in

raw pwrb_in value; before the invert logic

3ro0x0key0_in

raw key0_in value; before the invert logic

4ro0x0key1_in

raw key1_in value; before the invert logic

5ro0x0key2_in

raw key2_in value; before the invert logic

6ro0x0lid_open

raw lid_open value; before the invert logic


sysrst_ctrl.KEY_INTR_CTL @ 0x44

Define the keys or inputs that can trigger the interrupt

Reset default = 0x0, mask 0x3f3f
Register enable = REGWEN
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  ec_rst_l_L2H ac_present_L2H key2_in_L2H key1_in_L2H key0_in_L2H pwrb_in_L2H   ec_rst_l_H2L ac_present_H2L key2_in_H2L key1_in_H2L key0_in_H2L pwrb_in_H2L
BitsTypeResetNameDescription
0rw0x0pwrb_in_H2L

0: disable, 1: enable

1rw0x0key0_in_H2L

0: disable, 1: enable

2rw0x0key1_in_H2L

0: disable, 1: enable

3rw0x0key2_in_H2L

0: disable, 1: enable

4rw0x0ac_present_H2L

0: disable, 1: enable

5rw0x0ec_rst_l_H2L

0: disable, 1: enable

7:6Reserved
8rw0x0pwrb_in_L2H

0: disable, 1: enable

9rw0x0key0_in_L2H

0: disable, 1: enable

10rw0x0key1_in_L2H

0: disable, 1: enable

11rw0x0key2_in_L2H

0: disable, 1: enable

12rw0x0ac_present_L2H

0: disable, 1: enable

13rw0x0ec_rst_l_L2H

0: disable, 1: enable


sysrst_ctrl.KEY_INTR_DEBOUNCE_CTL @ 0x48

Debounce timer control register for key-triggered interrupt

Reset default = 0x0, mask 0xffff
Register enable = REGWEN
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debounce_timer
BitsTypeResetNameDescription
15:0rw0x0debounce_timer

Define the timer value so that the key or input is not oscillating for 0-200ms, each step is 5us(200KHz clock)


sysrst_ctrl.AUTO_BLOCK_DEBOUNCE_CTL @ 0x4c

Debounce timer control register for pwrb_in H2L transition

Reset default = 0x0, mask 0x1ffff
Register enable = REGWEN
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  auto_block_enable
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debounce_timer
BitsTypeResetNameDescription
15:0rw0x0debounce_timer

Define the timer value so that pwrb_in is not oscillating for 0-200ms, each step is 5us(200KHz clock)

16rw0x0auto_block_enable

0: disable, 1: enable


sysrst_ctrl.AUTO_BLOCK_OUT_CTL @ 0x50

confiure the key outputs to auto-override and their value

Reset default = 0x0, mask 0x77
Register enable = REGWEN
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  key2_out_value key1_out_value key0_out_value   key2_out_sel key1_out_sel key0_out_sel
BitsTypeResetNameDescription
0rw0x0key0_out_sel

0: disable auto-block; 1: enable auto-block

1rw0x0key1_out_sel

0: disable auto-block; 1: enable auto-block

2rw0x0key2_out_sel

0: disable auto-block; 1: enable auto-block

3Reserved
4rw0x0key0_out_value

0: override to 1'b0; 1: override to 1'b1

5rw0x0key1_out_value

0: override to 1'b0; 1: override to 1'b1

6rw0x0key2_out_value

0: override to 1'b0; 1: override to 1'b1


sysrst_ctrl.COM_SEL_CTL_0 @ 0x54

To define the keys that trigger the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will detect H2L transition in the combo use case

Reset default = 0x0, mask 0x1f
Register enable = REGWEN
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  ac_present_sel_0 pwrb_in_sel_0 key2_in_sel_0 key1_in_sel_0 key0_in_sel_0
BitsTypeResetNameDescription
0rw0x0key0_in_sel_0

0: disable, 1: enable

1rw0x0key1_in_sel_0

0: disable, 1: enable

2rw0x0key2_in_sel_0

0: disable, 1: enable

3rw0x0pwrb_in_sel_0

0: disable, 1: enable

4rw0x0ac_present_sel_0

0: disable, 1: enable


sysrst_ctrl.COM_SEL_CTL_1 @ 0x58

To define the keys that trigger the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will detect H2L transition in the combo use case

Reset default = 0x0, mask 0x1f
Register enable = REGWEN
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  ac_present_sel_1 pwrb_in_sel_1 key2_in_sel_1 key1_in_sel_1 key0_in_sel_1
BitsTypeResetNameDescription
0rw0x0key0_in_sel_1

For sysrst_ctrl1

1rw0x0key1_in_sel_1

For sysrst_ctrl1

2rw0x0key2_in_sel_1

For sysrst_ctrl1

3rw0x0pwrb_in_sel_1

For sysrst_ctrl1

4rw0x0ac_present_sel_1

For sysrst_ctrl1


sysrst_ctrl.COM_SEL_CTL_2 @ 0x5c

To define the keys that trigger the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will detect H2L transition in the combo use case

Reset default = 0x0, mask 0x1f
Register enable = REGWEN
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  ac_present_sel_2 pwrb_in_sel_2 key2_in_sel_2 key1_in_sel_2 key0_in_sel_2
BitsTypeResetNameDescription
0rw0x0key0_in_sel_2

For sysrst_ctrl2

1rw0x0key1_in_sel_2

For sysrst_ctrl2

2rw0x0key2_in_sel_2

For sysrst_ctrl2

3rw0x0pwrb_in_sel_2

For sysrst_ctrl2

4rw0x0ac_present_sel_2

For sysrst_ctrl2


sysrst_ctrl.COM_SEL_CTL_3 @ 0x60

To define the keys that trigger the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will detect H2L transition in the combo use case

Reset default = 0x0, mask 0x1f
Register enable = REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  ac_present_sel_3 pwrb_in_sel_3 key2_in_sel_3 key1_in_sel_3 key0_in_sel_3
BitsTypeResetNameDescription
0rw0x0key0_in_sel_3

For sysrst_ctrl3

1rw0x0key1_in_sel_3

For sysrst_ctrl3

2rw0x0key2_in_sel_3

For sysrst_ctrl3

3rw0x0pwrb_in_sel_3

For sysrst_ctrl3

4rw0x0ac_present_sel_3

For sysrst_ctrl3


sysrst_ctrl.COM_DET_CTL_0 @ 0x64

To define the duration that the combo should be pressed 0-60s, each step is 5us(200KHz clock)

Reset default = 0x0, mask 0xffffffff
Register enable = REGWEN
31302928272625242322212019181716
detection_timer_0...
1514131211109876543210
...detection_timer_0
BitsTypeResetNameDescription
31:0rw0x0detection_timer_0

0-60s, each step is 5us(200KHz clock)


sysrst_ctrl.COM_DET_CTL_1 @ 0x68

To define the duration that the combo should be pressed 0-60s, each step is 5us(200KHz clock)

Reset default = 0x0, mask 0xffffffff
Register enable = REGWEN
31302928272625242322212019181716
detection_timer_1...
1514131211109876543210
...detection_timer_1
BitsTypeResetNameDescription
31:0rw0x0detection_timer_1

For sysrst_ctrl1


sysrst_ctrl.COM_DET_CTL_2 @ 0x6c

To define the duration that the combo should be pressed 0-60s, each step is 5us(200KHz clock)

Reset default = 0x0, mask 0xffffffff
Register enable = REGWEN
31302928272625242322212019181716
detection_timer_2...
1514131211109876543210
...detection_timer_2
BitsTypeResetNameDescription
31:0rw0x0detection_timer_2

For sysrst_ctrl2


sysrst_ctrl.COM_DET_CTL_3 @ 0x70

To define the duration that the combo should be pressed 0-60s, each step is 5us(200KHz clock)

Reset default = 0x0, mask 0xffffffff
Register enable = REGWEN
31302928272625242322212019181716
detection_timer_3...
1514131211109876543210
...detection_timer_3
BitsTypeResetNameDescription
31:0rw0x0detection_timer_3

For sysrst_ctrl3


sysrst_ctrl.COM_OUT_CTL_0 @ 0x74

To define the actions once the combo is detected [0]: bat_disable [1]: interrupt (to OpenTitan processor) [2]: ec_rst (for Embedded Controller) [3]: rst_req (to OpenTitan reset manager)

Reset default = 0x0, mask 0xf
Register enable = REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  rst_req_0 ec_rst_0 interrupt_0 bat_disable_0
BitsTypeResetNameDescription
0rw0x0bat_disable_0

0: disable, 1: enable

1rw0x0interrupt_0

0: disable, 1: enable

2rw0x0ec_rst_0

0: disable, 1: enable

3rw0x0rst_req_0

0: disable, 1: enable


sysrst_ctrl.COM_OUT_CTL_1 @ 0x78

To define the actions once the combo is detected [0]: bat_disable [1]: interrupt (to OpenTitan processor) [2]: ec_rst (for Embedded Controller) [3]: rst_req (to OpenTitan reset manager)

Reset default = 0x0, mask 0xf
Register enable = REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  rst_req_1 ec_rst_1 interrupt_1 bat_disable_1
BitsTypeResetNameDescription
0rw0x0bat_disable_1

For sysrst_ctrl1

1rw0x0interrupt_1

For sysrst_ctrl1

2rw0x0ec_rst_1

For sysrst_ctrl1

3rw0x0rst_req_1

For sysrst_ctrl1


sysrst_ctrl.COM_OUT_CTL_2 @ 0x7c

To define the actions once the combo is detected [0]: bat_disable [1]: interrupt (to OpenTitan processor) [2]: ec_rst (for Embedded Controller) [3]: rst_req (to OpenTitan reset manager)

Reset default = 0x0, mask 0xf
Register enable = REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  rst_req_2 ec_rst_2 interrupt_2 bat_disable_2
BitsTypeResetNameDescription
0rw0x0bat_disable_2

For sysrst_ctrl2

1rw0x0interrupt_2

For sysrst_ctrl2

2rw0x0ec_rst_2

For sysrst_ctrl2

3rw0x0rst_req_2

For sysrst_ctrl2


sysrst_ctrl.COM_OUT_CTL_3 @ 0x80

To define the actions once the combo is detected [0]: bat_disable [1]: interrupt (to OpenTitan processor) [2]: ec_rst (for Embedded Controller) [3]: rst_req (to OpenTitan reset manager)

Reset default = 0x0, mask 0xf
Register enable = REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  rst_req_3 ec_rst_3 interrupt_3 bat_disable_3
BitsTypeResetNameDescription
0rw0x0bat_disable_3

For sysrst_ctrl3

1rw0x0interrupt_3

For sysrst_ctrl3

2rw0x0ec_rst_3

For sysrst_ctrl3

3rw0x0rst_req_3

For sysrst_ctrl3


sysrst_ctrl.COMBO_INTR_STATUS @ 0x84

combo interrupt source

Reset default = 0x0, mask 0xf
31302928272625242322212019181716
 
1514131211109876543210
  combo3_H2L combo2_H2L combo1_H2L combo0_H2L
BitsTypeResetNameDescription
0rw1c0x0combo0_H2L

0: case not detected;1: case detected

1rw1c0x0combo1_H2L

0: case not detected;1: case detected

2rw1c0x0combo2_H2L

0: case not detected;1: case detected

3rw1c0x0combo3_H2L

0: case not detected;1: case detected


sysrst_ctrl.KEY_INTR_STATUS @ 0x88

key interrupt source

Reset default = 0x0, mask 0xfff
31302928272625242322212019181716
 
1514131211109876543210
  ec_rst_l_L2H ac_present_L2H key2_in_L2H key1_in_L2H key0_in_L2H pwrb_L2H ec_rst_l_H2L ac_present_H2L key2_in_H2L key1_in_H2L key0_in_H2L pwrb_H2L
BitsTypeResetNameDescription
0rw1c0x0pwrb_H2L

0: case not detected;1: case detected

1rw1c0x0key0_in_H2L

0: case not detected;1: case detected

2rw1c0x0key1_in_H2L

0: case not detected;1: case detected

3rw1c0x0key2_in_H2L

0: case not detected;1: case detected

4rw1c0x0ac_present_H2L

0: case not detected;1: case detected

5rw1c0x0ec_rst_l_H2L

0: case not detected;1: case detected

6rw1c0x0pwrb_L2H

0: case not detected;1: case detected

7rw1c0x0key0_in_L2H

0: case not detected;1: case detected

8rw1c0x0key1_in_L2H

0: case not detected;1: case detected

9rw1c0x0key2_in_L2H

0: case not detected;1: case detected

10rw1c0x0ac_present_L2H

0: case not detected;1: case detected

11rw1c0x0ec_rst_l_L2H

0: case not detected;1: case detected