SysRst_Ctrl--Chrome OS platform reset related functionality

Overview

This document specifies the Chrome OS reset and system related functionality. This IP block implements keyboard and button combo triggered action and EC+GSC reset logic. This module conforms to the Comportable guideline for peripheral functionality.. See that document for integration overview within the broader top level system.

Features

The IP block implements the following features:

  • Always on: uses the always-on power and clock domain
  • EC reset pulse duration control and stretching
  • Keyboard and button combo triggered action
  • AC_present can trigger interrupt
  • Configuration registers can be set and locked until the next chip reset
  • Pin output override

Description

The sysrst_ctrl logic is very simple. It looks up the configuration registers to decide how long the EC reset pulse duration and how long the keyboard debounce timer should be. Also what actions to take (e.g. Interrupt, EC reset, GSC reset, disconnect the battery from the power tree).

Compatibility

The configuration programming interface is not based on any existing interface.

Theory of Operations

The block diagram shows a conceptual view of the sysrst_ctrl building blocks. There are 3 main modules. The first is the configuration and status registers. The second is the keyboard combo debounce and detection logic. The third is the pinout override logic.

The sysrst_ctrl has four input pins (pwrb_in, key0,1,2_in) with corresponding output pins (pwrb_out, key0,1,2_out). During normal operation the sysrst_ctrl will pass the pin information directly from the input pins to the output pins with optional inversion. Combinations of the inputs being active for a specified time can be detected and used to trigger actions. The override logic allows the output to be overridden (i.e. not follow the corresponding input) based either on trigger or software settings. This allows the security chip to take over the inputs for its own use without disturbing the main user.

The sysrst_ctrl also controls an active low open drain reset I/O ec_rst_l (typically used for the embedded controller reset). This output is always asserted when the IP block is reset (allowing its use as a power-on reset) and remains asserted until released by software. A pulse width is configured for the reset signal. Trigger actions may cause the sysrst_ctrl to assert ec_rst_l for the specified width. If the ec_rst_l is asserted by some other agent in the system then the sysrst_ctrl will extend the assertion to ensure the minimum pulse width is generated.

Block Diagram

sysrst_ctrl Block Diagram

Combo detection

Let’s use the Power button+Esc+Refresh combo as an example. The SW defines three keys (e.g. pwrb==0 && key0_in==0 && key1_in==0) as trigger in the configuration (com0_sel_ctl). The SW defines the duration (e.g. 10 seconds) that the above combo should be pressed in the configuration (com0_det_ctl). The SW defines the actions such as asserting ec_rst_l and raising interrupt in the configuration (com0_out_ctl). The SW defines the ec_rst_l pulse width in the configuration (ec_rst_ctl). The SW locks the configuration (no write is allowed) with cfg_wen_ctl. sysrst_ctrl will detect the high (logic 1) to low (logic 0) transition on the combo and start the timer. If the timing condition is met (10 second), sysrst_ctrl will assert ec_rst_l, sysrst_ctrl_intr and set the interrupt status register (intr_status) with the source. The interrupt handler will read intr_status and write “logic 1” to clear the interrupt.

Auto-block key outputs

Let’s use the Power button+Esc+Refresh combo as an example. When pwrb is pressed, key1_out (row) should be overridden so that sysrst_ctrl can detect if key0_in (column) is Refresh. The SW enables the auto_block feature and defines the timer value in auto_block_debounce_ctl. The SW defines the key outputs to auto-override and their value in auto_block_out_ctl. When sysrst_ctrl detects a high (logic 1) to low (logic 0) transition in pwrb_in and the key (pwrb_in == 0) stay low for the duration defined in auto_block_debounce_ctl, sysrst_ctrl will drive key1_out based on the value set in auto_block_out_ctl.

Keyboard and input triggered interrupt

Pwrb, key0, key1, key2, ac_present and ec_rst_l can trigger interrupt on rising or falling edges. The SW defines the buttons, keys or inputs and their edges (H->L or L->H) that can trigger the interrupt in key_intr_ctl. For example, when the power button is pressed, pwrb goes from logic 1 to logic 0 and it is a H->L transition. When the power button is released, pwrb goes from logic 0 to logic 1 and it is a L->H transition. The SW defines the debounce timer in key_intr_debounce_ctl When sysrst_ctrl detects a transition (H->L or L->H) as specified in key_intr_ctl and it meets the debounce requirement in key_intr_debounce_ctl, sysrst_ctrl sets the intr_status to indicate the source. It is possible for SW to program both H->L and L->H transition detection so that it can monitor that a button is pressed first and then released. sysrst_ctrl will drive the consolidated interrupt to PLIC. The interrupt handler will read intr_status and write “logic 1” to clear the interrupt.

Pin input value accessibility

sysrst_ctrl allows the SW to read the raw input pin value (before the invert logic). The hardware writes into pin_in_value for pwrb_in, key0/1/2_in, ac_present, ec_rst_l. The software can read them like GPIO.

Pin output and keyboard inversion control

sysrst_ctrl allows the SW to change the keyboard’s polarity on the inputs and outputs. It also provides the output pin override feature. In other words, SW can override the hardware state machine. The assertion has higher priority. Which output pins to override and the value to drive are configurable and lockable. The SW defines the allowed output pin override value in pin_allowed_ctl. For example, ec_rst_l_0=1’b1 and ec_rst_l_1=1’b0 means SW allows ec_rst_l to be overridden with logic 0, not logic 1. If the SW locks the configuration with cfg_wen_ctl, pin_allowed_ctl cannot be modified until GSC is reset When the system is up and running, the SW can modify pin_out_ctl and pin_out_value to enable or disable the feature. For example, to release ec_rst_l after GSC completes the reset, SW will program pin_out_ctl[1]=1’b0. The hardware will stop driving ec_rst_l=1’b0. The SW defines the keyboard polarity in key_invert_ctl. For inputs, it will be inverted before the combo logic. For outputs, it will be inverted after the pinout override logic.

EC and Power-on-reset

GSC and EC will be reset together during power-on. When GSC is in reset, ec_rst_l will be asserted (active low). When GSC exits from reset, ec_rst_l should still be asserted. The power-on-reset value of pin_allowed_ctl[1] and pin_out_ctl[1] will guarantee ec_rst_l=1’b0 after GSC reset. The SW will release ec_rst_l explicitly by writing pin_out_ctl[1]=1’b0 after we enter the GSC-RW boot stage. Now both GSC and EC complete the power-on-reset.

Registers

sysrst_ctrl.INTR_STATE @ 0x0

Interrupt State Register

Reset default = 0x0, mask 0x1
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  sysrst_ctrl
BitsTypeResetNameDescription
0rw1c0x0sysrst_ctrl

common interrupt triggered by combo or keyboard actions


sysrst_ctrl.INTR_ENABLE @ 0x4

Interrupt Enable Register

Reset default = 0x0, mask 0x1
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  sysrst_ctrl
BitsTypeResetNameDescription
0rw0x0sysrst_ctrl

Enable interrupt when INTR_STATE.sysrst_ctrl is set.


sysrst_ctrl.INTR_TEST @ 0x8

Interrupt Test Register

Reset default = 0x0, mask 0x1
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  sysrst_ctrl
BitsTypeResetNameDescription
0wo0x0sysrst_ctrl

Write 1 to force INTR_STATE.sysrst_ctrl to 1.


sysrst_ctrl.ALERT_TEST @ 0xc

Alert Test Register

Reset default = 0x0, mask 0x1
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  fatal_fault
BitsTypeResetNameDescription
0wo0x0fatal_fault

Write 1 to trigger one alert event of this kind.


sysrst_ctrl.REGWEN @ 0x10

Configuration write enable control register

Reset default = 0x1, mask 0x1
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  write_en
BitsTypeResetNameDescription
0rw0c0x1write_en

config write enable. 0: cfg is locked(not writable); 1: cfg is not locked(writable)


sysrst_ctrl.ec_rst_ctl @ 0x14

EC reset control register

Reset default = 0x7d0, mask 0xffff
Register enable = REGWEN
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ec_rst_pulse
BitsTypeResetNameDescription
15:0rw0x7d0ec_rst_pulse

Configure the pulse width of ec_rst_l. 10-200ms, each step is 5us(200KHz clock)


sysrst_ctrl.ulp_ac_debounce_ctl @ 0x18

Ultra low power AC debounce control register

Reset default = 0x1f40, mask 0xffff
Register enable = REGWEN
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ulp_ac_debounce_timer
BitsTypeResetNameDescription
15:0rw0x1f40ulp_ac_debounce_timer

Configure the debounce timer. 10-200ms, each step is 5us(200KHz clock)


sysrst_ctrl.ulp_lid_debounce_ctl @ 0x1c

Ultra low power lid debounce control register

Reset default = 0x1f40, mask 0xffff
Register enable = REGWEN
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ulp_lid_debounce_timer
BitsTypeResetNameDescription
15:0rw0x1f40ulp_lid_debounce_timer

Configure the debounce timer. 10-200ms, each step is 5us(200KHz clock)


sysrst_ctrl.ulp_pwrb_debounce_ctl @ 0x20

Ultra low power pwrb debounce control register

Reset default = 0x1f40, mask 0xffff
Register enable = REGWEN
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ulp_pwrb_debounce_timer
BitsTypeResetNameDescription
15:0rw0x1f40ulp_pwrb_debounce_timer

Configure the debounce timer. 10-200ms, each step is 5us(200KHz clock)


sysrst_ctrl.ulp_ctl @ 0x24

Ultra low power control register

Reset default = 0x0, mask 0x1
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  ulp_enable
BitsTypeResetNameDescription
0rw0x0ulp_enable

0: disable ULP wakeup feature and reset the ULP FSM; 1: enable ULP wakeup feature


sysrst_ctrl.ulp_status @ 0x28

Ultra low power status

Reset default = 0x0, mask 0x1
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  ulp_wakeup
BitsTypeResetNameDescription
0rw1c0x0ulp_wakeup

0: ULP wakeup not detected; 1: ULP wakeup event is detected


sysrst_ctrl.wk_status @ 0x2c

wakeup status

Reset default = 0x0, mask 0x1
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  wakeup_sts
BitsTypeResetNameDescription
0rw1c0x0wakeup_sts

0: wakeup event not detected; 1: wakeup event is detected


sysrst_ctrl.key_invert_ctl @ 0x30

configure key input output invert property

Reset default = 0x0, mask 0xfff
Register enable = REGWEN
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  z3_wakeup lid_open bat_disable ac_present pwrb_out pwrb_in key2_out key2_in key1_out key1_in key0_out key0_in
BitsTypeResetNameDescription
0rw0x0key0_in

0: don't invert; 1: invert

1rw0x0key0_out

0: don't invert; 1: invert

2rw0x0key1_in

0: don't invert; 1: invert

3rw0x0key1_out

0: don't invert; 1: invert

4rw0x0key2_in

0: don't invert; 1: invert

5rw0x0key2_out

0: don't invert; 1: invert

6rw0x0pwrb_in

0: don't invert; 1: invert

7rw0x0pwrb_out

0: don't invert; 1: invert

8rw0x0ac_present

0: don't invert; 1: invert

9rw0x0bat_disable

0: don't invert; 1: invert

10rw0x0lid_open

0: don't invert; 1: invert

11rw0x0z3_wakeup

0: don't invert; 1: invert


sysrst_ctrl.pin_allowed_ctl @ 0x34

configure the allowed pinout override value

Reset default = 0x2, mask 0x3fff
Register enable = REGWEN
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  z3_wakeup_1 key2_out_1 key1_out_1 key0_out_1 pwrb_out_1 ec_rst_l_1 bat_disable_1 z3_wakeup_0 key2_out_0 key1_out_0 key0_out_0 pwrb_out_0 ec_rst_l_0 bat_disable_0
BitsTypeResetNameDescription
0rw0x0bat_disable_0

0: disable; 1: enable

1rw0x1ec_rst_l_0

0: disable; 1: enable

2rw0x0pwrb_out_0

0: disable; 1: enable

3rw0x0key0_out_0

0: disable; 1: enable

4rw0x0key1_out_0

0: disable; 1: enable

5rw0x0key2_out_0

0: disable; 1: enable

6rw0x0z3_wakeup_0

0: disable; 1: enable

7rw0x0bat_disable_1

0: disable; 1: enable

8rw0x0ec_rst_l_1

0: disable; 1: enable

9rw0x0pwrb_out_1

0: disable; 1: enable

10rw0x0key0_out_1

0: disable; 1: enable

11rw0x0key1_out_1

0: disable; 1: enable

12rw0x0key2_out_1

0: disable; 1: enable

13rw0x0z3_wakeup_1

0: disable; 1: enable


sysrst_ctrl.pin_out_ctl @ 0x38

configure the pin out directly to override the function

Reset default = 0x2, mask 0x7f
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  z3_wakeup key2_out key1_out key0_out pwrb_out ec_rst_l bat_disable
BitsTypeResetNameDescription
0rw0x0bat_disable

0: disable override; 1: enable override

1rw0x1ec_rst_l

0: disable override; 1: enable override

2rw0x0pwrb_out

0: disable override; 1: enable override

3rw0x0key0_out

0: disable override; 1: enable override

4rw0x0key1_out

0: disable override; 1: enable override

5rw0x0key2_out

0: disable override; 1: enable override

6rw0x0z3_wakeup

0: disable override; 1: enable override


sysrst_ctrl.pin_out_value @ 0x3c

confiure the pin out value directly to override the function

Reset default = 0x0, mask 0x7f
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  z3_wakeup key2_out key1_out key0_out pwrb_out ec_rst_l bat_disable
BitsTypeResetNameDescription
0rw0x0bat_disable

0: override to 1b0; 1: override to 1b1

1rw0x0ec_rst_l

0: override to 1b0; 1: override to 1b1

2rw0x0pwrb_out

0: override to 1b0; 1: override to 1b1

3rw0x0key0_out

0: override to 1b0; 1: override to 1b1

4rw0x0key1_out

0: override to 1b0; 1: override to 1b1

5rw0x0key2_out

0: override to 1b0; 1: override to 1b1

6rw0x0z3_wakeup

0: override to 1b0; 1: override to 1b1


sysrst_ctrl.pin_in_value @ 0x40

For SW to read the sysrst_ctrl inputs like GPIO

Reset default = 0x0, mask 0x7f
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  lid_open key2_in key1_in key0_in pwrb_in ec_rst_l ac_present
BitsTypeResetNameDescription
0ro0x0ac_present

raw ac_present value; before the invert logic

1ro0x0ec_rst_l

raw ec_rst_l value; before the invert logic

2ro0x0pwrb_in

raw pwrb_in value; before the invert logic

3ro0x0key0_in

raw key0_in value; before the invert logic

4ro0x0key1_in

raw key1_in value; before the invert logic

5ro0x0key2_in

raw key2_in value; before the invert logic

6ro0x0lid_open

raw lid_open value; before the invert logic


sysrst_ctrl.key_intr_ctl @ 0x44

Define the keys or inputs that can trigger the interrupt

Reset default = 0x0, mask 0x3f3f
Register enable = REGWEN
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  ec_rst_l_L2H ac_present_L2H key2_in_L2H key1_in_L2H key0_in_L2H pwrb_in_L2H   ec_rst_l_H2L ac_present_H2L key2_in_H2L key1_in_H2L key0_in_H2L pwrb_in_H2L
BitsTypeResetNameDescription
0rw0x0pwrb_in_H2L

0: disable, 1: enable

1rw0x0key0_in_H2L

0: disable, 1: enable

2rw0x0key1_in_H2L

0: disable, 1: enable

3rw0x0key2_in_H2L

0: disable, 1: enable

4rw0x0ac_present_H2L

0: disable, 1: enable

5rw0x0ec_rst_l_H2L

0: disable, 1: enable

7:6Reserved
8rw0x0pwrb_in_L2H

0: disable, 1: enable

9rw0x0key0_in_L2H

0: disable, 1: enable

10rw0x0key1_in_L2H

0: disable, 1: enable

11rw0x0key2_in_L2H

0: disable, 1: enable

12rw0x0ac_present_L2H

0: disable, 1: enable

13rw0x0ec_rst_l_L2H

0: disable, 1: enable


sysrst_ctrl.key_intr_debounce_ctl @ 0x48

Debounce timer control register for key-triggered interrupt

Reset default = 0x0, mask 0xffff
Register enable = REGWEN
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debounce_timer
BitsTypeResetNameDescription
15:0rw0x0debounce_timer

Define the timer valure so that the key or input is not oscillating for 0-200ms, each step is 5us(200KHz clock)


sysrst_ctrl.auto_block_debounce_ctl @ 0x4c

Debounce timer control register for pwrb_in H2L transition

Reset default = 0x0, mask 0x1ffff
Register enable = REGWEN
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  auto_block_enable
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debounce_timer
BitsTypeResetNameDescription
15:0rw0x0debounce_timer

Define the timer valure so that pwrb_in is not oscillating for 0-200ms, each step is 5us(200KHz clock)

16rw0x0auto_block_enable

0: disable, 1: enable


sysrst_ctrl.auto_block_out_ctl @ 0x50

confiure the key outputs to auto-override and their value

Reset default = 0x0, mask 0x77
Register enable = REGWEN
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  key2_out_value key1_out_value key0_out_value   key2_out_sel key1_out_sel key0_out_sel
BitsTypeResetNameDescription
0rw0x0key0_out_sel

0: disable auto-block; 1: enable auto-block

1rw0x0key1_out_sel

0: disable auto-block; 1: enable auto-block

2rw0x0key2_out_sel

0: disable auto-block; 1: enable auto-block

3Reserved
4rw0x0key0_out_value

0: override to 1'b0; 1: override to 1'b1

5rw0x0key1_out_value

0: override to 1'b0; 1: override to 1'b1

6rw0x0key2_out_value

0: override to 1'b0; 1: override to 1'b1


sysrst_ctrl.com_sel_ctl_0 @ 0x54

To define the keys that trigger the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will detect H2L transition in the combo use case

Reset default = 0x0, mask 0x1f
Register enable = REGWEN
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  ac_present_sel_0 pwrb_in_sel_0 key2_in_sel_0 key1_in_sel_0 key0_in_sel_0
BitsTypeResetNameDescription
0rw0x0key0_in_sel_0

0: disable, 1: enable

1rw0x0key1_in_sel_0

0: disable, 1: enable

2rw0x0key2_in_sel_0

0: disable, 1: enable

3rw0x0pwrb_in_sel_0

0: disable, 1: enable

4rw0x0ac_present_sel_0

0: disable, 1: enable


sysrst_ctrl.com_sel_ctl_1 @ 0x58

To define the keys that trigger the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will detect H2L transition in the combo use case

Reset default = 0x0, mask 0x1f
Register enable = REGWEN
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  ac_present_sel_1 pwrb_in_sel_1 key2_in_sel_1 key1_in_sel_1 key0_in_sel_1
BitsTypeResetNameDescription
0rw0x0key0_in_sel_1

For sysrst_ctrl1

1rw0x0key1_in_sel_1

For sysrst_ctrl1

2rw0x0key2_in_sel_1

For sysrst_ctrl1

3rw0x0pwrb_in_sel_1

For sysrst_ctrl1

4rw0x0ac_present_sel_1

For sysrst_ctrl1


sysrst_ctrl.com_sel_ctl_2 @ 0x5c

To define the keys that trigger the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will detect H2L transition in the combo use case

Reset default = 0x0, mask 0x1f
Register enable = REGWEN
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  ac_present_sel_2 pwrb_in_sel_2 key2_in_sel_2 key1_in_sel_2 key0_in_sel_2
BitsTypeResetNameDescription
0rw0x0key0_in_sel_2

For sysrst_ctrl2

1rw0x0key1_in_sel_2

For sysrst_ctrl2

2rw0x0key2_in_sel_2

For sysrst_ctrl2

3rw0x0pwrb_in_sel_2

For sysrst_ctrl2

4rw0x0ac_present_sel_2

For sysrst_ctrl2


sysrst_ctrl.com_sel_ctl_3 @ 0x60

To define the keys that trigger the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will detect H2L transition in the combo use case

Reset default = 0x0, mask 0x1f
Register enable = REGWEN
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  ac_present_sel_3 pwrb_in_sel_3 key2_in_sel_3 key1_in_sel_3 key0_in_sel_3
BitsTypeResetNameDescription
0rw0x0key0_in_sel_3

For sysrst_ctrl3

1rw0x0key1_in_sel_3

For sysrst_ctrl3

2rw0x0key2_in_sel_3

For sysrst_ctrl3

3rw0x0pwrb_in_sel_3

For sysrst_ctrl3

4rw0x0ac_present_sel_3

For sysrst_ctrl3


sysrst_ctrl.com_det_ctl_0 @ 0x64

To define the duration that the combo should be pressed 0-60s, each step is 5us(200KHz clock)

Reset default = 0x0, mask 0xffffffff
Register enable = REGWEN
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detection_timer_0...
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...detection_timer_0
BitsTypeResetNameDescription
31:0rw0x0detection_timer_0

0-60s, each step is 5us(200KHz clock)


sysrst_ctrl.com_det_ctl_1 @ 0x68

To define the duration that the combo should be pressed 0-60s, each step is 5us(200KHz clock)

Reset default = 0x0, mask 0xffffffff
Register enable = REGWEN
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detection_timer_1...
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...detection_timer_1
BitsTypeResetNameDescription
31:0rw0x0detection_timer_1

For sysrst_ctrl1


sysrst_ctrl.com_det_ctl_2 @ 0x6c

To define the duration that the combo should be pressed 0-60s, each step is 5us(200KHz clock)

Reset default = 0x0, mask 0xffffffff
Register enable = REGWEN
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detection_timer_2...
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...detection_timer_2
BitsTypeResetNameDescription
31:0rw0x0detection_timer_2

For sysrst_ctrl2


sysrst_ctrl.com_det_ctl_3 @ 0x70

To define the duration that the combo should be pressed 0-60s, each step is 5us(200KHz clock)

Reset default = 0x0, mask 0xffffffff
Register enable = REGWEN
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detection_timer_3...
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...detection_timer_3
BitsTypeResetNameDescription
31:0rw0x0detection_timer_3

For sysrst_ctrl3


sysrst_ctrl.com_out_ctl_0 @ 0x74

To define the actions once the combo is detected [0]: bat_disable [1]: interrupt [2]: ec_rst [3]: gsc_rst

Reset default = 0x0, mask 0xf
Register enable = REGWEN
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  gsc_rst_0 ec_rst_0 interrupt_0 bat_disable_0
BitsTypeResetNameDescription
0rw0x0bat_disable_0

0: disable, 1: enable

1rw0x0interrupt_0

0: disable, 1: enable

2rw0x0ec_rst_0

0: disable, 1: enable

3rw0x0gsc_rst_0

0: disable, 1: enable


sysrst_ctrl.com_out_ctl_1 @ 0x78

To define the actions once the combo is detected [0]: bat_disable [1]: interrupt [2]: ec_rst [3]: gsc_rst

Reset default = 0x0, mask 0xf
Register enable = REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  gsc_rst_1 ec_rst_1 interrupt_1 bat_disable_1
BitsTypeResetNameDescription
0rw0x0bat_disable_1

For sysrst_ctrl1

1rw0x0interrupt_1

For sysrst_ctrl1

2rw0x0ec_rst_1

For sysrst_ctrl1

3rw0x0gsc_rst_1

For sysrst_ctrl1


sysrst_ctrl.com_out_ctl_2 @ 0x7c

To define the actions once the combo is detected [0]: bat_disable [1]: interrupt [2]: ec_rst [3]: gsc_rst

Reset default = 0x0, mask 0xf
Register enable = REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  gsc_rst_2 ec_rst_2 interrupt_2 bat_disable_2
BitsTypeResetNameDescription
0rw0x0bat_disable_2

For sysrst_ctrl2

1rw0x0interrupt_2

For sysrst_ctrl2

2rw0x0ec_rst_2

For sysrst_ctrl2

3rw0x0gsc_rst_2

For sysrst_ctrl2


sysrst_ctrl.com_out_ctl_3 @ 0x80

To define the actions once the combo is detected [0]: bat_disable [1]: interrupt [2]: ec_rst [3]: gsc_rst

Reset default = 0x0, mask 0xf
Register enable = REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  gsc_rst_3 ec_rst_3 interrupt_3 bat_disable_3
BitsTypeResetNameDescription
0rw0x0bat_disable_3

For sysrst_ctrl3

1rw0x0interrupt_3

For sysrst_ctrl3

2rw0x0ec_rst_3

For sysrst_ctrl3

3rw0x0gsc_rst_3

For sysrst_ctrl3


sysrst_ctrl.combo_intr_status @ 0x84

combo interrupt source

Reset default = 0x0, mask 0xf
31302928272625242322212019181716
 
1514131211109876543210
  combo3_H2L combo2_H2L combo1_H2L combo0_H2L
BitsTypeResetNameDescription
0rw1c0x0combo0_H2L

0: case not detected;1: case detected

1rw1c0x0combo1_H2L

0: case not detected;1: case detected

2rw1c0x0combo2_H2L

0: case not detected;1: case detected

3rw1c0x0combo3_H2L

0: case not detected;1: case detected


sysrst_ctrl.key_intr_status @ 0x88

key interrupt source

Reset default = 0x0, mask 0xfff
31302928272625242322212019181716
 
1514131211109876543210
  ec_rst_l_L2H ac_present_L2H key2_in_L2H key1_in_L2H key0_in_L2H pwrb_L2H ec_rst_l_H2L ac_present_H2L key2_in_H2L key1_in_H2L key0_in_H2L pwrb_H2L
BitsTypeResetNameDescription
0rw1c0x0pwrb_H2L

0: case not detected;1: case detected

1rw1c0x0key0_in_H2L

0: case not detected;1: case detected

2rw1c0x0key1_in_H2L

0: case not detected;1: case detected

3rw1c0x0key2_in_H2L

0: case not detected;1: case detected

4rw1c0x0ac_present_H2L

0: case not detected;1: case detected

5rw1c0x0ec_rst_l_H2L

0: case not detected;1: case detected

6rw1c0x0pwrb_L2H

0: case not detected;1: case detected

7rw1c0x0key0_in_L2H

0: case not detected;1: case detected

8rw1c0x0key1_in_L2H

0: case not detected;1: case detected

9rw1c0x0key2_in_L2H

0: case not detected;1: case detected

10rw1c0x0ac_present_L2H

0: case not detected;1: case detected

11rw1c0x0ec_rst_l_L2H

0: case not detected;1: case detected