SYSRST_CTRL DV document
Goals
- DV
- Verify all SYSRST_CTRL IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
- FPV
- Verify TileLink device protocol compliance with an SVA based testbench
Current status
Design features
For detailed information on SYSRST_CTRL design features, please see the SYSRST_CTRL HWIP technical specification.
Testbench architecture
SYSRST_CTRL testbench has been constructed based on the CIP testbench architecture.
Block diagram
Top level testbench
The top level testbench is located at hw/ip/sysrst_ctrl/dv/tb.sv
.
It instantiates the SYSRST_CTRL DUT module hw/ip/sysrst_ctrl/rtl/sysrst_ctrl.sv
.
In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db
:
- Clock and reset interface
- TileLink host interface
- SYSRST_CTRL IOs
- Interrupts (
pins_if
) - Alerts (
alert_esc_if
) - Devmode (
pins_if
)
Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
Compile-time configurations
[list compile time configurations, if any and what are they used for]
Global types & methods
All common types and methods defined at the package level can be found in
sysrst_ctrl_env_pkg
.
TL_agent
The SYSRST_CTRL testbench instantiates (already handled in CIP base env) tl_agent. This provides the ability to drive and independently monitor random traffic via the TL host interface into the SYSRST_CTRL device.
Alert_agents
SYSRST_CTRL testbench instantiates (already handled in CIP base env) alert_agents: [list alert names]. The alert_agents provide the ability to drive and independently monitor alert handshakes via alert interfaces in SYSRST_CTRL device.
UVM RAL Model
The SYSRST_CTRL RAL model is created with the ralgen
FuseSoC generator script automatically when the simulation is at the build stage.
It can be created manually by invoking regtool
:
Stimulus strategy
Test sequences
The test sequences reside in hw/ip/sysrst_ctrl/dv/env/seq_lib
.
All test sequences are extended from sysrst_ctrl_base_vseq
, which is extended from cip_base_vseq
and serves as a starting point.
It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
Functional coverage
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:
- sysrst_ctrl_combo_detect_action_cg: This covergroup will cover all the combo detect actions for combo detect register set 0-3.
- sysrst_ctrl_combo_detect_sel_cg: This covergroup will sample the input selected for combo detect.
- sysrst_ctrl_combo_detect_det_cg: This covergroup will cover the combo detect debounce timer value.
- sysrst_ctrl_auto_block_debounce_ctl_cg: This will cover the auto block enable/disable feature, debounce timer value.
- sysrst_ctrl_combo_intr_status_cg: This covergroup will capture the combo detect interrupt status.
- sysrst_ctrl_key_intr_status_cg: This covergroup will capture the edge detect status for all the inputs.
- sysrst_ctrl_ulp_status_cg: This covergroup will cover the ultra low power status.
- sysrst_ctrl_wkup_status_cg: This will capture the wakeup status event after the low power event is triggered.
- sysrst_ctrl_pin_in_value_cg: This covergroup will cover the raw input values of all the input pins.
- sysrst_ctrl_auto_blk_out_ctl_cg: This covergroup will cover the input selected for auto block and the output value status for the selected input pin.
- pin_cfg_cg: This is the generic covergroup to cover the override and allowed values for the selected input and output values. An array of this covergroup is created for all the input pins.
- debounce_timer_cg: This is the generic covergroup to cover the debounce timer values for the below register. key_intr_debounce_ctl ulp_ac_debounce_ctl ulp_pwrb_debounce_ctl ulp_lid_debounce_ctl ec_rst_ctl
- sysrst_ctrl_key_invert_ctl_cg: This covergroup will cover which input/output pins are allowed to invert their values.The invert values are crossed with the input/output values.
Self-checking strategy
Scoreboard
The sysrst_ctrl_scoreboard
is primarily used for end to end checking.
Assertions
- TLUL assertions: The
sva/sysrst_ctrl_bind.sv
file binds thetlul_assert
assertions to the IP to ensure TileLink interface protocol compliance. - Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
- Assertions in
tb.sv
- CheckFlashWrProtRst: Checks flash_wp_l output pin is asserted active low which it is in reset.
- CheckEcPwrOnRst: Checks ec_rst_l_o is asserted active low when it is in reset.
Building and running tests
We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:
$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/sysrst_ctrl/dv/sysrst_ctrl_sim_cfg.hjson -i sysrst_ctrl_smoke
Testplan
Testpoints
Stage | Name | Tests | Description |
---|---|---|---|
V1 | smoke | sysrst_ctrl_smoke | Verify end to end data transfer in normal operation mode.
|
V1 | input_output_inverted | sysrst_ctrl_in_out_inverted | Verify end to end data transfer with inverted input and inverted output.
|
V1 | combo_detect_ec_rst | sysrst_ctrl_combo_detect_ec_rst | Verify the combo detection with ec_rst action.
|
V1 | csr_hw_reset | sysrst_ctrl_csr_hw_reset | Verify the reset values as indicated in the RAL specification.
|
V1 | csr_rw | sysrst_ctrl_csr_rw | Verify accessibility of CSRs as indicated in the RAL specification.
|
V1 | csr_bit_bash | sysrst_ctrl_csr_bit_bash | Verify no aliasing within individual bits of a CSR.
|
V1 | csr_aliasing | sysrst_ctrl_csr_aliasing | Verify no aliasing within the CSR address space.
|
V1 | csr_mem_rw_with_rand_reset | sysrst_ctrl_csr_mem_rw_with_rand_reset | Verify random reset during CSR/memory access.
|
V1 | regwen_csr_and_corresponding_lockable_csr | sysrst_ctrl_csr_rw sysrst_ctrl_csr_aliasing | Verify regwen CSR and its corresponding lockable CSRs.
Note:
This is only applicable if the block contains regwen and locakable CSRs. |
V2 | combo_detect | sysrst_ctrl_combo_detect | Verify the combo detection with random action.
|
V2 | auto_block_key_outputs | sysrst_ctrl_auto_blk_key_output | Verify the auto block key output feature.
|
V2 | keyboard_input_triggered_interrupt | sysrst_ctrl_edge_detect | Verify the keyboard and input triggered interrupt feature by detecting the edge transitions on input pins.
|
V2 | pin_output_keyboard_inversion_control | sysrst_ctrl_override_test | Verify the keyboard inversion feature by override logic.
|
V2 | pin_input_value_accessibility | sysrst_ctrl_pin_access_test | Verify the pin input value accessibilty.
|
V2 | ec_power_on_reset | sysrst_ctrl_ec_pwr_on_rst | Verify the EC and power on reset.
|
V2 | flash_write_protect_output | sysrst_ctrl_flash_wr_prot_out | Verify the flash write protect.
|
V2 | ultra_low_power_test | sysrst_ctrl_ultra_low_pwr | Verify the ultra low power feature.
|
V2 | stress_all | sysrst_ctrl_stress_all | Test all the sequences randomly in one sequence.
|
V2 | alert_test | sysrst_ctrl_alert_test | Verify common
|
V2 | intr_test | sysrst_ctrl_intr_test | Verify common intr_test CSRs that allows SW to mock-inject interrupts.
|
V2 | tl_d_oob_addr_access | sysrst_ctrl_tl_errors | Access out of bounds address and verify correctness of response / behavior |
V2 | tl_d_illegal_access | sysrst_ctrl_tl_errors | Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the [TLUL spec]({{< relref "hw/ip/tlul/doc/_index.md#explicit-error-cases" >}})
|
V2 | tl_d_outstanding_access | sysrst_ctrl_csr_hw_reset sysrst_ctrl_csr_rw sysrst_ctrl_csr_aliasing sysrst_ctrl_same_csr_outstanding | Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address. |
V2 | tl_d_partial_access | sysrst_ctrl_csr_hw_reset sysrst_ctrl_csr_rw sysrst_ctrl_csr_aliasing sysrst_ctrl_same_csr_outstanding | Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields. |
V2S | tl_intg_err | sysrst_ctrl_tl_intg_err sysrst_ctrl_sec_cm | Verify that the data integrity check violation generates an alert.
|
V2S | sec_cm_bus_integrity | sysrst_ctrl_tl_intg_err | Verify the countermeasure(s) BUS.INTEGRITY. |
V3 | stress_all_with_rand_reset | sysrst_ctrl_stress_all_with_rand_reset | This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers. |
Covergroups
Name | Description |
---|---|
debounce_timer_cg | Cover the debounce timer of the following registers
|
pin_cfg_cg | Cover the override enable/disable of all the inputs. Cover the override values of all the input values. Cover the allowed value 0 and 1 of all the inputs. Cross all the above coverpoints. |
regwen_val_when_new_value_written_cg | Cover each lockable reg field with these 2 cases:
This is only applicable if the block contains regwen and locakable CSRs. |
sysrst_ctrl_auto_blk_out_ctl_cg | Cover the auto blk input select and their values. Cross the key outputs selected to override with their override values. Sample the covergroup when the event occurs. |
sysrst_ctrl_auto_block_debounce_ctl_cg | Cover the auto block enable/disable feature. Cover the auto block debounce timer. |
sysrst_ctrl_combo_detect_action_cg | Cover all the combo detect actions. Create 4 instance to cover the combo detect register [0-3]. Sample the covergroup when the event occurs. Cross the covergroup with combo_detect_sel_cg to cover all the input combination with all the possible combo_detect actions. |
sysrst_ctrl_combo_detect_det_cg | Cover the combo detect debounce timer. Create 4 instance to cover the combo detect register [0-3]. |
sysrst_ctrl_combo_detect_sel_cg | Cover all the combo detect input select. Cross all the inputs to cover all the combos. Create 4 instance to cover the combo detect register [0-3]. Sample the covergroup when the event occurs. Cross the covergroup with combo_detect_action_cg to cover all the input combination with all the possible combo_detect actions. |
sysrst_ctrl_combo_intr_status_cg | Cover the combo detect status of all 4 set of combo registers. Cover all the input combinations has generated selected outcome actions and cross with the status generated. |
sysrst_ctrl_key_intr_status_cg | Cover the H2L/L2H edge detect event of all the inputs. |
sysrst_ctrl_key_invert_ctl_cg | Cover the invert values of all input and output values. |
sysrst_ctrl_pin_in_value_cg | Cover the raw input values before inversion for all inputs. |
sysrst_ctrl_ulp_status_cg | Cover the ultra low power event triggered. Cover the following condition triggers the ultra low power event:
|
sysrst_ctrl_wkup_event_cg | Cover the ultra low power wakeup event and status. Cover the wkup event could occur due to following condition:
|
tl_errors_cg | Cover the following error cases on TL-UL bus:
|
tl_intg_err_cg | Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check. Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied. |