• UART smoke test with few bytes transmitted and received asynchronously and in parallel with scoreboard checks
• TX and RX have 2 independent threads respectively.
  • program one Tx item in register and wait for it to complete at uart interface, before send another one
  • sequencally send one Rx byte, then immediately read from register and check it

Verify the reset values as indicated in the RAL specification.

• Write all CSRs with a random value.
• Apply reset to the DUT as well as the RAL model.
• Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify accessibility of CSRs as indicated in the RAL specification.

• Loop through each CSR to write it with a random value.
• Read the CSR back and check for correctness while adhering to its access policies.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify no aliasing within individual bits of a CSR.

• Walk a 1 through each CSR by flipping 1 bit at a time.
• Read the CSR back and check for correctness while adhering to its access policies.
• This verify that writing a specific bit within the CSR did not affect any of the other bits.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify no aliasing within the CSR address space.

• Loop through each CSR to write it with a random value
• Shuffle and read ALL CSRs back.
• All CSRs except for the one that was written in this iteration should read back the previous value.
• The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify random reset during CSR/memory access.

• Run csr_rw sequence to randomly access CSRs
• If memory exists, run mem_partial_access in parallel with csr_rw
• Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.

• This is the basic sequence that is extended by most of random sequence.
• TX and RX have 2 independent threads respectively.
  • TX: keep programming csr wdata with random delay when fifo isn't full
  • RX: 2 processes. One is to send item through uart interface when fifo isn't full and the other is to read csr rdata when fifo isn't empty

Send / receive bytes with parity and odd parity enabled randomly.

• Enable parity and randomly set even/odd parity
• Inject parity error randomly on data sent from rx and ensure the interrupt is raised

• Program random tx/rx fifo watermark level and keep sending random tx/rx data to fifo.
• As the number of pending data entries in the tx/rx fifo reaches the programmed watermark level (fifo size >= watermark level), ensure that the watermark interrupt is asserted
• Ensure interrupt stays asserted until cleared as well as fifo level dropped. The tx/rx watermark interrupt is sticky

Send over 32 bytes of data but stop when fifo is full

• Keep sending over 32 bytes of data over tx/rx fifo
• Ensure excess data bytes are dropped and check overflow interrupt
• This uart_fifo_overflow_vseq is extent from uart_fifo_full_vseq and override the constraint to be able to send data over fifo size

• Fill up the tx/rx fifo. After a random number of bytes shows up on fifo, reset the fifo and ensure that the remaining data bytes do not show up
• this sequence is extent from uart_fifo_overflow_vseq, so it can also reset when fifo is at any level, including full or overflow

• Inject frame error in parity and non-parity cases by not setting stop bit = 1
• Ensure the interrupt gets asserted

• Program random number of break detection characters
• create a frame error scenario and send random number of 0 bytes
• If that random number exceeds the programmed break characters
• Ensure that the break_err interrupt is asserted

• Program timeout_ctrl register to randomize the timeout. Send random number of data over rx
• Wait until it's about to timeout, then check timeout interrupt doesn't fire. Wait for timeout and check timeout interrupt fires
• Wait until it's about to timeout, then use either read csr rdata or send RX item through uart interface to reset timeout timer in order to ensure timeout never fires

Run fifo_full_vseq with very small delays

• Enable system looback, then drive uart TX and data will be loopbacked through RX
• After loopback is done, uart.RDATA will be equal to the data programmed to uart.WDATA

• Enable line loopback and drive uart_rx with random data and random delay
• Check uart_tx has same value as uart_rx. There is not synchronizer register between uart_rx and uart_tx during line loopback

• Use 16x fast clk to sample it, data on uart_rx need to be stable for 3 clocks, otherwise, data change won't be taken
• Enable noise filter and drive many glitches. Each glitch doesn't lasts less than 3 clocks
• Ensure the noise will be filterred out and it doesn't affect next normal transaction

• Start bit should last for at least half baud clock, otherwise, it will be dropped
• It's always enabled. Drive start bit for less than half cycle.
• Ensure the start bit will be dropped

Enable override control and use register programming to drive uart output directly.

• Use 16x baud clock to sample uart rx
• Drive uart rx with 16 bits value, using 16x baud clock
• Read RX oversampled value and ensure it's same as driven value

• Reduce delay to fill TX fifo and read RX fifo to ensure back2back transfers
• Use long back2back transfer to ensure clock difference won't be accumulated across transactions
• Uart monitor checks the clock offset between sender and receiver is never over 1/4 of the period

• Combine above sequences in one test to run sequentially, except csr sequence and uart_rx_oversample_vseq (requires zero_delays)
• Randomly add reset between each sequence

Have random reset in parallel with stress_all and tl_errors sequences

Verify common alert_test CSR that allows SW to mock-inject alert requests.

• Enable a random set of alert requests by writing random value to alert_test CSR.
• Check each alert_tx.alert_p pin to verify that only the requested alerts are triggered.
• During alert_handshakes, write alert_test CSR again to verify that: If alert_test writes to current ongoing alert handshake, the alert_test request will be ignored. If alert_test writes to current idle alert handshake, a new alert_handshake should be triggered.
• Wait for the alert handshakes to finish and verify alert_tx.alert_p pins all sets back to 0.
• Repeat the above steps a bunch of times.

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

• Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
• Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s).
• Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
• Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
• Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
• Repeat the above steps a bunch of times.

Access out of bounds address and verify correctness of response / behavior

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the [TLUL spec]({{< relref "hw/ip/tlul/doc/_index.md#explicit-error-cases" >}})

• TL-UL protocol error cases
  • invalid opcode
  • some mask bits not set when opcode is PutFullData
  • mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
  • mask and address misaligned, e.g. a_address = 0x01, a_mask = 'b0001
  • address and size aren't aligned, e.g. a_address = 0x01, a_size != 0
  • size is greater than 2
• OpenTitan defined error cases
  • access unmapped address, expect d_error = 1 when devmode_i == 1
  • write a CSR with unaligned address, e.g. a_address[1:0] != 0
  • write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
  • write a memory with a_mask != '1 when it doesn't support partial accesses
  • read a WO (write-only) memory
  • write a RO (read-only) memory

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

Verify that the data integrity check violation generates an alert.

Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.

Cover the following error cases on TL-UL bus:

• TL-UL protocol error cases.
• OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

Cover the kinds of integrity errors with byte enabled write on memory.

Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.