UART DV document
Goals
- DV
- Verify all UART IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
- FPV
- Verify TileLink device protocol compliance with an SVA based testbench
Current status
Design features
For detailed information on UART design features, please see the UART design specification.
Testbench architecture
UART testbench has been constructed based on the CIP testbench architecture.
Block diagram
Top level testbench
Top level testbench is located at hw/ip/uart/dv/tb/tb.sv
. It instantiates the UART DUT module hw/ip/uart/rtl/uart.sv
.
In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db
:
- Clock and reset interface
- TileLink host interface
- UART IOs
- Interrupts (
pins_if
)
Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
Global types & methods
All common types and methods defined at the package level can be found in
uart_env_pkg
. Some of them in use are:
parameter uint UART_FIFO_DEPTH = 32;
TL_agent
UART instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into UART device.
UART agent
UART agent is used to drive and monitor UART items, which also provides basic coverage on data, parity, baud rate etc. These baud rates are supported: 9600, 115200, 230400, 1Mbps(1048576), 2Mbps(2097152)
UVM RAL Model
The UART RAL model is created with the ralgen
FuseSoC generator script automatically when the simulation is at the build stage.
It can be created manually by invoking regtool
:
Stimulus strategy
Test sequences
All test sequences reside in hw/ip/uart/dv/env/seq_lib
.
The uart_base_vseq
virtual sequence is extended from cip_base_vseq
and serves as a starting point.
All test sequences are extended from uart_base_vseq
.
It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:
- uart_init: Configure uart control and fifo related csr with random values
- send_tx_byte: Program one TX byte to enable DUT to send a TX byte to UART interface
- send_rx_byte: Drive a RX byte to DUT through UART interface
Functional coverage
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:
- common covergroup for interrupts
hw/dv/sv/cip_lib/cip_base_env_cov.sv
: Cover interrupt value, interrupt enable, intr_test, interrup pin - uart_cg in uart_agent_cov
hw/dv/sv/uart_agent/uart_agent_cov.sv
: Cover direction, uart data, en_parity, odd_parity and baud rate - fifo_level_cg
hw/ip/uart/dv/env/uart_env_cov.sv
: Cover all fifo level with fifo reset for both TX and RX
Self-checking strategy
Scoreboard
The uart_scoreboard
is primarily used for end to end checking.
It creates the following analysis fifos to retrieve the data monitored by corresponding interface agents:
- tl_a_chan_fifo, tl_d_chan_fifo: These 2 fifos provides transaction items at the end of address channel and data channel respectively
- uart_tx_fifo, uart_rx_fifo: These 2 fifos provides UART TX and RX item when its transfer completes
Assertions
- TLUL assertions: The
tb/uart_bind.sv
binds thetlul_assert
assertions to the IP to ensure TileLink interface protocol compliance. - Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
Building and running tests
We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:
$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/uart/dv/uart_sim_cfg.hjson -i uart_smoke
Testplan
Testpoints
Milestone | Name | Tests | Description |
---|---|---|---|
V1 | smoke | uart_smoke |
|
V1 | csr_hw_reset | uart_csr_hw_reset | Verify the reset values as indicated in the RAL specification.
|
V1 | csr_rw | uart_csr_rw | Verify accessibility of CSRs as indicated in the RAL specification.
|
V1 | csr_bit_bash | uart_csr_bit_bash | Verify no aliasing within individual bits of a CSR.
|
V1 | csr_aliasing | uart_csr_aliasing | Verify no aliasing within the CSR address space.
|
V1 | csr_mem_rw_with_rand_reset | uart_csr_mem_rw_with_rand_reset | Verify random reset during CSR/memory access.
|
V1 | regwen_csr_and_corresponding_lockable_csr | uart_csr_rw uart_csr_aliasing | Verify regwen CSR and its corresponding lockable CSRs.
Note:
This is only applicable if the block contains regwen and locakable CSRs. |
V2 | base_random_seq | uart_tx_rx |
|
V2 | parity | uart_smoke uart_tx_rx | Send / receive bytes with parity and odd parity enabled randomly. |
V2 | parity_error | uart_rx_parity_err uart_intr |
|
V2 | watermark | uart_tx_rx uart_intr |
|
V2 | fifo_full | uart_fifo_full | Send over 32 bytes of data but stop when fifo is full |
V2 | fifo_overflow | uart_fifo_overflow |
|
V2 | fifo_reset | uart_fifo_reset |
|
V2 | rx_frame_err | uart_intr |
|
V2 | rx_break_err | uart_intr |
|
V2 | rx_timeout | uart_intr |
|
V2 | perf | uart_perf | Run fifo_full_vseq with very small delays |
V2 | sys_loopback | uart_loopback |
|
V2 | line_loopback | uart_loopback |
|
V2 | rx_noise_filter | uart_noise_filter |
|
V2 | rx_start_bit_filter | uart_rx_start_bit_filter |
|
V2 | tx_overide | uart_tx_ovrd | Enable override control and use register programming to drive uart output directly. |
V2 | rx_oversample | uart_rx_oversample |
|
V2 | long_b2b_transfer | uart_long_xfer_wo_dly |
|
V2 | stress_all | uart_stress_all |
|
V2 | stress_all_with_reset | uart_stress_all_with_rand_reset | Have random reset in parallel with stress_all and tl_errors sequences |
V2 | alert_test | uart_alert_test | Verify common
|
V2 | intr_test | uart_intr_test | Verify common intr_test CSRs that allows SW to mock-inject interrupts.
|
V2 | tl_d_oob_addr_access | uart_tl_errors | Access out of bounds address and verify correctness of response / behavior |
V2 | tl_d_illegal_access | uart_tl_errors | Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the [TLUL spec]({{< relref "hw/ip/tlul/doc/_index.md#explicit-error-cases" >}})
|
V2 | tl_d_outstanding_access | uart_csr_hw_reset uart_csr_rw uart_csr_aliasing uart_same_csr_outstanding | Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address. |
V2 | tl_d_partial_access | uart_csr_hw_reset uart_csr_rw uart_csr_aliasing uart_same_csr_outstanding | Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields. |
V2S | tl_intg_err | uart_tl_intg_err uart_sec_cm | Verify that the data integrity check violation generates an alert.
|
V2S | sec_cm_bus_integrity | Verify the countermeasure(s) BUS.INTEGRITY. |
Covergroups
Name | Description |
---|---|
foo_cg | |
regwen_val_when_new_value_written_cg | Cover each lockable reg field with these 2 cases:
This is only applicable if the block contains regwen and locakable CSRs. |
tl_errors_cg | Cover the following error cases on TL-UL bus:
|
tl_intg_err_cg | Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check. Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied. |