UART DV Plan

Goals

  • DV
    • Verify all UART IP features by running dynamic simulations with a SV/UVM based testbench
    • Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
  • FPV
    • Verify TileLink device protocol compliance with an SVA based testbench

Current status

Design features

For detailed information on UART design features, please see the UART design specification.

Testbench architecture

UART testbench has been constructed based on the CIP testbench architecture.

Block diagram

Block diagram

Top level testbench

Top level testbench is located at hw/ip/uart/dv/tb/tb.sv. It instantiates the UART DUT module hw/ip/uart/rtl/uart.sv. In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db:

Common DV utility components

The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

Global types & methods

All common types and methods defined at the package level can be found in uart_env_pkg. Some of them in use are:

parameter uint UART_FIFO_DEPTH    = 32;

TL_agent

UART instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into UART device.

UART agent

UART agent is used to drive and monitor UART items, which also provides basic coverage on data, parity, baud rate etc. These baud rates are supported: 9600, 115200, 230400, 1Mbps(1048576), 2Mbps(2097152)

UVM RAL Model

The UART RAL model is created with the ralgen FuseSoC generator script automatically when the simulation is at the build stage.

It can be created manually by invoking regtool:

Stimulus strategy

Test sequences

All test sequences reside in hw/ip/uart/dv/env/seq_lib. The uart_base_vseq virtual sequence is extended from cip_base_vseq and serves as a starting point. All test sequences are extended from uart_base_vseq. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. Some of the most commonly used tasks / functions are as follows:

  • uart_init: Configure uart control and fifo related csr with random values
  • send_tx_byte: Program one TX byte to enable DUT to send a TX byte to UART interface
  • send_rx_byte: Drive a RX byte to DUT through UART interface

Functional coverage

To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:

  • common covergroup for interrupts hw/dv/sv/cip_lib/cip_base_env_cov.sv: Cover interrupt value, interrupt enable, intr_test, interrup pin
  • uart_cg in uart_agent_cov hw/dv/sv/uart_agent/uart_agent_cov.sv: Cover direction, uart data, en_parity, odd_parity and baud rate
  • fifo_level_cg hw/ip/uart/dv/env/uart_env_cov.sv: Cover all fifo level with fifo reset for both TX and RX

Self-checking strategy

Scoreboard

The uart_scoreboard is primarily used for end to end checking. It creates the following analysis fifos to retrieve the data monitored by corresponding interface agents:

  • tl_a_chan_fifo, tl_d_chan_fifo: These 2 fifos provides transaction items at the end of address channel and data channel respectively
  • uart_tx_fifo, uart_rx_fifo: These 2 fifos provides UART TX and RX item when its transfer completes

Assertions

  • TLUL assertions: The tb/uart_bind.sv binds the tlul_assert assertions to the IP to ensure TileLink interface protocol compliance.
  • Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.

Building and running tests

We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a basic sanity test:

$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/uart/dv/uart_sim_cfg.hjson -i uart_sanity

Testplan

Milestone Name Description Tests
V1 sanity
  • Basic UART sanity test with few bytes transmitted and received asynchronously and in parallel with scoreboard checks
  • TX and RX have 2 independent threads respectively.
    • program one Tx item in register and wait for it to complete at uart interface, before send another one
    • sequencally send one Rx byte, then immediately read from register and check it
uart_sanity
V1 csr_hw_reset

Verify the reset values as indicated in the RAL specification.

  • Write all CSRs with a random value.
  • Apply reset to the DUT as well as the RAL model.
  • Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
uart_csr_hw_reset
V1 csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

  • Loop through each CSR to write it with a random value.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
uart_csr_rw
V1 csr_bit_bash

Verify no aliasing within individual bits of a CSR.

  • Walk a 1 through each CSR by flipping 1 bit at a time.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • This verify that writing a specific bit within the CSR did not affect any of the other bits.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
uart_csr_bit_bash
V1 csr_aliasing

Verify no aliasing within the CSR address space.

  • Loop through each CSR to write it with a random value
  • Shuffle and read ALL CSRs back.
  • All CSRs except for the one that was written in this iteration should read back the previous value.
  • The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
uart_csr_aliasing
V1 csr_mem_rw_with_rand_reset

Verify random reset during CSR/memory access.

  • Run csr_rw sequence to randomly access CSRs
  • If memory exists, run mem_partial_access in parallel with csr_rw
  • Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
uart_csr_mem_rw_with_rand_reset
V2 base_random_seq
  • This is the basic sequence that is extended by most of random sequence.
  • TX and RX have 2 independent threads respectively.
    • TX: keep programming csr wdata with random delay when fifo isn't full
    • RX: 2 processes. One is to send item through uart interface when fifo isn't full and the other is to read csr rdata when fifo isn't empty
uart_tx_rx
V2 parity

Send / receive bytes with parity and odd parity enabled randomly.

uart_sanity
uart_tx_rx
V2 parity_error
  • Enable parity and randomly set even/odd parity
  • Inject parity error randomly on data sent from rx and ensure the interrupt is raised
uart_rx_parity_err
uart_intr
V2 watermark
  • Program random tx/rx fifo watermark level and keep sending random tx/rx data to fifo.
  • As the number of pending data entries in the tx/rx fifo reaches the programmed watermark level (fifo size >= watermark level), ensure that the watermark interrupt is asserted
  • Ensure interrupt stays asserted until cleared as well as fifo level dropped. The tx/rx watermark interrupt is sticky
uart_tx_rx
uart_intr
V2 fifo_full

Send over 32 bytes of data but stop when fifo is full

uart_fifo_full
V2 fifo_overflow
  • Keep sending over 32 bytes of data over tx/rx fifo
  • Ensure excess data bytes are dropped and check overflow interrupt
  • This uart_fifo_overflow_vseq is extent from uart_fifo_full_vseq and override the constraint to be able to send data over fifo size
uart_fifo_overflow
V2 fifo_reset
  • Fill up the tx/rx fifo. After a random number of bytes shows up on fifo, reset the fifo and ensure that the remaining data bytes do not show up
  • this sequence is extent from uart_fifo_overflow_vseq, so it can also reset when fifo is at any level, including full or overflow
uart_fifo_reset
V2 rx_frame_err
  • Inject frame error in parity and non-parity cases by not setting stop bit = 1
  • Ensure the interrupt gets asserted
uart_intr
V2 rx_break_err
  • Program random number of break detection characters
  • create a frame error scenario and send random number of 0 bytes
  • If that random number exceeds the programmed break characters
  • Ensure that the break_err interrupt is asserted
uart_intr
V2 rx_timeout
  • Program timeout_ctrl register to randomize the timeout. Send random number of data over rx
  • Wait until it's about to timeout, then check timeout interrupt doesn't fire. Wait for timeout and check timeout interrupt fires
  • Wait until it's about to timeout, then use either read csr rdata or send RX item through uart interface to reset timeout timer in order to ensure timeout never fires
uart_intr
V2 perf

Run fifo_full_vseq with very small delays

uart_perf
V2 sys_loopback
  • Enable system looback, then drive uart TX and data will be loopbacked through RX
  • After loopback is done, uart.RDATA will be equal to the data programmed to uart.WDATA
uart_loopback
V2 line_loopback
  • Enable line loopback and drive uart_rx with random data and random delay
  • Check uart_tx has same value as uart_rx. There is not synchronizer register between uart_rx and uart_tx during line loopback
uart_loopback
V2 rx_noise_filter
  • Use 16x fast clk to sample it, data on uart_rx need to be stable for 3 clocks, otherwise, data change won't be taken
  • Enable noise filter and drive many glitches. Each glitch doesn't lasts less than 3 clocks
  • Ensure the noise will be filterred out and it doesn't affect next normal transaction
uart_noise_filter
V2 rx_start_bit_filter
  • Start bit should last for at least half baud clock, otherwise, it will be dropped
  • It's always enabled. Drive start bit for less than half cycle.
  • Ensure the start bit will be dropped
uart_rx_start_bit_filter
V2 tx_overide

Enable override control and use register programming to drive uart output directly.

uart_tx_ovrd
V2 rx_oversample
  • Use 16x baud clock to sample uart rx
  • Drive uart rx with 16 bits value, using 16x baud clock
  • Read RX oversampled value and ensure it's same as driven value
uart_rx_oversample
V2 stress_all
  • Combine above sequences in one test to run sequentially, except csr sequence and uart_rx_oversample_vseq (requires zero_delays)
  • Randomly add reset between each sequence
uart_stress_all
V2 stress_all_with_reset

Have random reset in parallel with stress_all and tl_errors sequences

uart_stress_all_with_rand_reset
V2 intr_test

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

  • Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
  • Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s).
  • Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
  • Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
  • Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
  • Repeat the above steps a bunch of times.
uart_intr_test
V2 tl_d_oob_addr_access

Access out of bounds address and verify correctness of response / behavior

uart_tl_errors
V2 tl_d_illegal_access

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested

  • TL-UL protocol error cases
    • Unsupported opcode. e.g a_opcode isn't Get, PutPartialData or PutFullData
    • Mask isn't all active if opcode = PutFullData
    • Mask isn't in enabled lanes, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
    • Mask doesn't align with address, e.g. a_address = 0x01, a_mask = 'b0001
    • Address and size aren't aligned, e.g. a_address = 0x01, a_size != 0
    • Size is over 2.
  • OpenTitan defined error cases
    • Access unmapped address, return d_error = 1 when devmode_i == 1
    • Write CSR with unaligned address, e.g. a_address[1:0] != 0
    • Write CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
    • Write a memory without enabling all lanes (a_mask = '1) if memory doesn't support byte enabled write
    • Read a WO (write-only) memory
uart_tl_errors
V2 tl_d_outstanding_access

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

uart_csr_hw_reset
uart_csr_rw
uart_csr_aliasing
uart_same_csr_outstanding
V2 tl_d_partial_access

Access CSR with one or more bytes of data For read, expect to return all word value of the CSR For write, enabling bytes should cover all CSR valid fields

uart_csr_hw_reset
uart_csr_rw
uart_csr_aliasing
uart_same_csr_outstanding