USB 2.0 Full-Speed Device HWIP Technical Specification

Overview

This document specifies the USB device hardware IP functionality. This IP block implements a Full-Speed device according to the USB 2.0 specification. It is attached to the chip interconnect bus as a peripheral module and conforms to the Comportable guideline for peripheral functionality.

Features

The IP block implements the following features:

  • USB 2.0 Full-Speed (12 Mbps) Device interface
  • 2 kB interface buffer
  • Up to 12 endpoints (including required Endpoint 0), configurable using a compile-time Verilog parameter
  • Support for USB packet sizes up to 64 bytes
  • Support SETUP, IN and OUT transactions
  • Support for Bulk, Control, Interrupt and Isochronous endpoints and transactions
  • Streaming possible through software
  • Interrupts for packet reception and transmission
  • Flippable D+/D- pins, configurable via software, useful if it helps routing the PCB or if D+/D- are mapped to SBU1/SBU2 pins of USB-C

Isochronous transfers larger than 64 bytes are currently not supported. This feature might be added in a later version of this IP.

Description

The USB device module is a simple software-driven generic USB device interface for Full-Speed USB 2.0 operation. The IP includes the physical layer interface, the low level USB protocol and a packet buffer interface to the software. The physical layer interface features both differential and single-ended transmit and receive paths to allow interfacing with a variety of USB PHYs or regular 3.3V IO pads for FPGA prototyping.

Compatibility

The USB device programming interface is not based on any existing interface.

Theory of Operations

A useful quick reference for USB Full-Speed is USB Made Simple, Part 3 - Data Flow.

The block diagram shows a high level view of the USB device including the main register access paths.

Block Diagram

Clocking

The USB Full-Speed interface runs at a data rate of 12 MHz. The interface runs at four times this frequency and must be clocked from an accurate 48 MHz clock source. The USB specification for a Full-Speed device requires the average bit rate is 12 Mbps +/- 0.25%, so the clock needs to support maximum error of 2,500 ppm. The maximum allowable integrated jitter is +/- 1 ns over 1 to 7 bit periods.

This module features the following output signals to provide a reference for synchronizing the 48 MHz clock source:

  • usb_ref_pulse_o indicates the reception of a start of frame (SOF) packet. The host is required to send a SOF packet every 1 ms.
  • usb_ref_val_o serves as a valid signal for usb_ref_pulse_o. It is set to one after the first SOF packet is received and remains high as long as usb_ref_pulse_o continues to behave as expected. As soon as it is detected that SOF will not be received as expected (usually because the link is no longer active), usb_ref_val_o deasserts to zero until after the next usb_ref_pulse_o.

Both these signals are synchronous to the 48 MHz clock. They can be forced to zero by setting phy_config.usb_ref_disable to 1.

To successfully receive SOF packets without errors and thereby enabling clock synchronization, the initial accuracy of the 48 MHz clock source should be within 3.2% or 32,000 ppm. This requirement comes from the fact that the SOF packet has a length of 24 bits (plus 8-bit sync field). The first 8 bits are used to transfer the SOF packet ID (8’b01011010). Internally, the USB device dynamically adjusts the sampling point based on observed line transitions. Assuming the last bit of the SOF packet ID is sampled in the middle of the eye, the drift over the remaining 16 bits of the packet must be lower than half a bit (10^6 * (0.5/16) = 32,000 ppm).

To externally monitor the 48 MHz clock, the USB device supports an oscillator test mode which can be enabled by setting phy_config.tx_osc_test_mode to 1. In this mode, the device constantly transmits a J/K pattern but no longer receives SOF packets. Consequently, it does not generate reference pulses for clock synchronization. The clock might drift off.

Control transfers pass through asynchronous FIFOs or have a ready bit synchronized across the clock domain boundary. A dual-port asynchronous buffer SRAM is used for data transfers between the bus clock and USB clock domains.

USB Interface Pins

Full-Speed USB uses a bidirectional serial interface as shown in Figure 7-24 of the USB 2.0 Full-Speed specification. For reasons of flexibility, this IP block features both differential and single-ended transmit and receive paths.

For better receive sensitivity, lower transmit jitter and to be standard compliant, a dedicated, differential USB transceiver such as the USB1T11A or the USB1T20 must be used (see Section 7.1.4.1 of the USB 2.0 specification). Depending on the selected USB transceiver, either the differential or the single-ended transmit and receive paths or a combination of the two can be used to interface the IP block with the transceiver.

When prototyping on FPGAs (here the interface can be implemented with pseudo-differential 3.3V GPIO pins and an oversampling receiver for recovery of the bitstream and clock alignment), the single-ended signal pairs can be used. External to the IP, these should be combined to drive the actual pins when transmit is enabled and receive otherwise. Using standard 3.3V IO pads allows use on most FPGAs although the drive strength and series termination resistors may need to be adjusted to meet the USB signal eye. On a Xilinx Artix-7 (and less well tested Spartan-7) part, setting the driver to the 8mA, FAST setting seems to work well with a 22R series termination (and with a 0R series termination).

The following sections describe how the various input/output signals relate to the USB interface pins for the different receive and transmit configurations.

Data Transmit

The IP block supports both differential and single-ended transmission (TX). The TX mode can be selected by setting the tx_differential_mode bit in phy_config to either 1 (differential) or 0 (single ended).

The following table summarizes how the different output signals relate to the USB interface pins.

External Pins Internal Signals Notes
D+, D- d_o Data output for interfacing with a differential USB transceiver.
" se0_o Signal Single-Ended Zero (SE0) link state to a differential USB transceiver.
" dp_o, dn_o Single-ended data output signals. These can be used to interface to regular IO cells for prototyping on an FPGA, but such an interface will probably not be USB compliant.
[TX Mode] tx_mode_se_o Indicates the selected TX mode: single-ended (1) or differential (0) operation.

Note that according to the Comportable guideline for peripheral functionality, every output signal name_o has a dedicated output enable name_en_o. For TX data, these separate signals d_en_o, dp_en_o and dn_en_o all correspond to the same TX or output enable signal (OE in the USB spec).

Data Receive

The IP block supports both differential and single-ended reception (RX). The RX mode can be selected by setting the rx_differential_mode bit in phy_config to either 1 (differential) or 0 (single ended).

The following table summarizes how the different input signals relate to the USB interface pins.

External Pins Internal Signals Notes
D+, D- d_i Data input for interfacing with a differential USB transceiver. Used in differential RX mode only.
" dp_i, dn_i Single-ended data input signals. These signals are used to detect the SE0 link state in differential RX mode. They can further be used to interface to regular IO cells for prototyping on an FPGA, but such an interface will probably not be USB compliant.

Non-Data Pins

The USB device features the following non-data pins.

External Pins Internal Signals Notes
sense (VBUS) sense_i The sense pin indicates the presence of VBUS from the USB host.
[pullup] dp_pullup_o, dn_pullup_o When dp_pullup_o or dn_pullup_o asserts a 1.5k pullup resistor should be connected to D+ or D-, respectively. This can be done inside the chip or with an external pin. A permanently connected resistor could be used if the pin flip feature is not needed, but this is not recommended because there is then no way to force the device to appear to unplug. Only one of the pullup signals can be asserted at any time. The selection is based on the pinflip bit in phy_config. Because this is a Full-Speed device the resistor must be on the D+ pin, so when pinflip is zero, dp_pullup_o is used.
[suspend] suspend_o The suspend pin indicates to the USB transceiver that a constant idle has been detected on the link and the device is in the Suspend state (see Section 7.1.7.6 of the USB 2.0 specification).

The USB host will identify itself to the device by enabling the 5V VBUS power. It may do a hard reset of a port by removing and reasserting VBUS (the Linux driver will do this when it finds a port in an inconsistent state or a port that generates errors during enumeration). The IP block detects VBUS through the sense pin. This pin is always an input and should be externally connected to detect the state of the VBUS. Note that this may require a resistor divider or (for USB-C where VBUS can be up to 20V) active level translation to an acceptable voltage for the input pin.

A Full-Speed device identifies itself by providing a 1.5k pullup resistor (to 3.3V) on the D+ line. The IP block produces a signal dp_pullup_o that is asserted when this resistor should be presented. This signal will be asserted whenever the interface is enabled. In an FPGA implementation, this signal can drive a 3.3V output pin that is driven high when the signal is asserted and set high impedance when the signal is deasserted, and the output pin used to drive a 1.5k resistor connected on the board to the D+ line. Alternatively, it can be used to enable an internal 1.5k pullup on the D+ pin.

This USB device supports the flipping of D+/D-. If the pinflip bit in phy_config is set, the data pins are flipped internally, meaning the 1.5k pullup resistor needs to be on the external D- line. To control the pullup on the D- line, this USB device features dn_pullup_o signal. Of the two pullup signals dp_pullup_o and dn_pullup_o, only one can be enabled at any time. As this is a Full-Speed device, dp_pullup_o, i.e., the pullup on D+ is used by default (pinflip equals zero).

FPGA Board Implementation With PMOD

The interface was developed using the Digilent Nexys Video board with a PMOD card attached. A PMOD interface with direct connection to the SoC should be used (some PMOD interfaces include 100R series resistors which break the signal requirements for USB). The PMOD card includes two USB micro-B connectors and allows two USB interfaces to be used. The D+ and D- signals have 22R series resistors (in line with the USB spec) and there is a 1.5k pullup on D+ to the pullup enable signal. There is a resistive divider to set the sense pin at half of the VBUS voltage which enables detection on the FPGA without overvoltage on the pin.

PMOD Schematic

The PMOD PCB is available from OSH Park.

The PMOD design files for KiCad version 5 are in the usbdev/pmod directory. The BOM can be filled by parts from Digikey.

Item Qty Reference(s) Value LibPart Footprint Datasheet Category DK_Datasheet_Link DK_Detail_Page Description Digi-Key_PN Family MPN Manufacturer Status
1 2 J1, J2 10118193-0001LF dualpmod-rescue:10118193-0001LF-dk_USB-DVI-HDMI-Connectors digikey-footprints:USB_Micro_B_Female_10118193-0001LF http://www.amphenol-icc.com/media/wysiwyg/files/drawing/10118193.pdf Connectors, Interconnects http://www.amphenol-icc.com/media/wysiwyg/files/drawing/10118193.pdf /product-detail/en/amphenol-icc-fci/10118193-0001LF/609-4616-1-ND/2785380 CONN RCPT USB2.0 MICRO B SMD R/A 609-4616-1-ND USB, DVI, HDMI Connectors 10118193-0001LF Amphenol ICC (FCI) Active
2 1 J3 68021-412HLF dualpmod-rescue:68021-412HLF-dk_Rectangular-Connectors-Headers-Male-Pins digikey-footprints:PinHeader_6x2_P2.54mm_Horizontal https://cdn.amphenol-icc.com/media/wysiwyg/files/drawing/68020.pdf Connectors, Interconnects https://cdn.amphenol-icc.com/media/wysiwyg/files/drawing/68020.pdf /product-detail/en/amphenol-icc-fci/68021-412HLF/609-3355-ND/1878558 CONN HEADER R/A 12POS 2.54MM 609-3355-ND Rectangular Connectors - Headers, Male Pins 68021-412HLF Amphenol ICC (FCI) Active
3 4 R1, R2, R7, R8 5k1 Device:R_Small_US Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder ~ A126379CT-ND
4 4 R3, R4, R5, R6 22R Device:R_Small_US Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder ~ A126352CT-ND
5 2 R9, R10 1k5 Device:R_Small_US Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder ~ A106057CT-ND

Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module usbdev has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks:

Bus Device Interface: tlul

Bus Host Interface: none

Peripheral Pins for Chip IO:

Pin namedirectionDescription
senseinputUSB host VBUS sense
se0outputUSB single-ended zero link state
dp_pullupoutputUSB D+ pullup control
dn_pullupoutputUSB D- pullup control
tx_mode_seoutputUSB single-ended transmit mode control
suspendoutputUSB link suspend state
dinoutUSB data differential
dpinoutUSB data D+
dninoutUSB data D-

Interrupts:

Interrupt NameDescription
pkt_receivedRaised if a packet was received using an OUT or SETUP transaction.
pkt_sentRaised if a packet was sent as part of an IN transaction.
disconnectedRaised if VBUS is lost thus the link is disconnected.
host_lostRaised if link is active but SOF was not received from host for 4.096 ms. The SOF should be every 1 ms.
link_resetRaised if the link is at SE0 longer than 3 us indicating a link reset (host asserts for min 10 ms, device can react after 2.5 us).
link_suspendRaised if the line has signaled J for longer than 3ms and is therefore in suspend state.
link_resumeRaised when the link becomes active again after being suspended.
av_emptyRaised when a transaction is NACKed because the Available Buffer FIFO for OUT or SETUP transactions is empty.
rx_fullRaised when a transaction is NACKed because the Received Buffer FIFO for OUT or SETUP transactions is full.
av_overflowRaised if a write was done to the Available Buffer FIFO when the FIFO was full.
link_in_errRaised if a packet to an IN endpoint started to be received but was then dropped due to an error. After transmitting the IN payload, the USB device expects a valid ACK handshake packet. This error is raised if either the packet or CRC is invalid or a different token was received.
rx_crc_errRaised if a CRC error occured.
rx_pid_errRaised if an invalid packed identifier (PID) was received.
rx_bitstuff_errRaised if an invalid bitstuffing was received.
frameRaised when the USB frame number is updated with a valid SOF.
connectedRaised if VBUS is applied.
link_out_errRaised if a packet to an OUT endpoint started to be received but was then dropped due to an error. This error is raised if either the data toggle, token, packet or CRC is invalid or if there is no buffer available in the Received Buffer FIFO.

Security Alerts:

Alert NameDescription

The USB link has a number of states. These are detected and reported in usbstat.link_state and state changes are reported using interrupts. The FSM implements a subset of the USB device state diagram shown in Figure 9-1 of the USB 2.0 specification.

State Description
Disconnect The link is disconnected. This is signaled when the VBUS is not driven by the host, which results in the sense input pin being low. An interrupt is raised on entering this state.
Powered The device has been powered as VBUS is being driven by the host, but has not been reset yet. The link is reset whenever the D+ and D- are both low (an SE0 condition) for an extended period. The host will assert reset for a minimum of 10 ms, but the USB specification allows the device to detect and respond to a reset after 2.5 us. The implementation here will report the reset state and raise an interrupt when the link is in SE0 for 3 us.
Powered Suspend The link is suspended when at idle (a J condition) for more than 3 ms. An interrupt is generated when the suspend is detected and a resume interrupt is generated when the link exits the suspend state. This state is entered, if the device has not been reset yet.
Active The link is active when it is running normally.
Suspend Similar to ‘Powered Suspend’, but the device was in the active state before being suspended.
Link Events Description
Disconnect VBUS has been lost.
Link Reset The link has been in the SE0 state for 3 us.
Link Suspend The link has been in the J state for more than 3 ms, upon which we have to enter the Suspend state.
Link Resume The link has been driven to a non-J state after being in Suspend.
Host Lost Signaled using an interrupt if the link is active but a start of frame (SOF) packet has not been received from the host in 4.096 ms. The host is required to send a SOF packet every 1 ms. This is not an expected condition.

USB Protocol Engine

The USB 2.0 Full-Speed Protocol Engine is provided by the common USB interface code and is, strictly speaking, not part of this USB device module.

At the lowest level of the USB stack the transmit bitstream is serialized, converted to non-return-to-zero inverted (NRZI) encoding with bit-stuffing and sent to the transmitter. The received bitstream is recovered, clock aligned and decoded and has bit-stuffing removed. The recovered clock alignment is used for transmission.

The higher level protocol engine forms the bitstream into packets, performs CRC checking and recognizes IN, OUT and SETUP transactions. These are presented to this module without buffering. This means the USB device module must accept or provide data when requested. The protocol engine may cancel a transaction because of a bad cyclic redundancy check (CRC) or request a retry if an acknowledgment (ACK) was not received.

Buffer Interface

A 2 kB SRAM is used as a packet buffer to hold data between the system and the USB interface. This is divided up into 32 buffers each containing 64 bytes. This is an asynchronous dual-port SRAM with software accessing from the bus clock domain and the USB interface accessing from the USB 48 MHz clock domain.

Reception

Software provides buffers for packet reception through a 4-entry Available Buffer FIFO. (More study needed but four seems about right: one just returned to software, one being filled, one ready to be filled, and one for luck.) The rxenable_out and rxenable_setup registers is used to indicate which endpoints will accept data from the host using OUT or SETUP transactions, respectively. When a packet is transferred from the host to the device (using an OUT or SETUP transaction) and reception of that type of transaction is enabled for the requested endpoint, the next buffer ID is pulled from the Available Buffer FIFO. The packet data is written to the corresponding buffer in the packet buffer (the 2 kB SRAM). If the packet is correctly received, an ACK is returned to the host. In addition, the buffer ID, the packet size, an out/setup flag and the endpoint ID are passed back to software using the Received Buffer FIFO and a pkt_received interrupt is raised.

Software should immediately provide a free buffer for future reception by writing the corresponding buffer ID to the Available Buffer FIFO. It can then process the packet and eventually return the received buffer to the free pool. This allows streaming on a single endpoint or across a number of endpoints. If the packets cannot be consumed at the rate they are received, software can implement selective flow control by disabling OUT or SETUP transactions for a particular endpoint, which will result in a request to that endpoint being NACKed (negative acknowledgment). In the unfortunate event that the Available Buffer FIFO is empty or the Received Buffer FIFO is full, all OUT and SETUP transactions are NACKed.

Transmission

To send data to the host in response to an IN transaction, software first writes the data into a free buffer. Then, it writes the buffer ID, data length and rdy flag to the configin register of the corresponding endpoint. When the host next does an IN transaction to that endpoint, the data will be sent from the buffer. On receipt of the ACK from the host, the rdy bit in the configin register will be cleared, and the bit corresponding to the endpoint ID will be set in the in_sent register causing a pkt_sent interrupt to be raised. Software can return the buffer to the free pool and write a 1 to clear the endpoint bit in the in_sent register. Note that streaming can be achieved if the next buffer has been prepared and is written to the configin register when the interrupt is received.

A Control transfer may need an IN data transfer. Therefore, when a SETUP transaction is received for an endpoint, any buffers that are waiting to be sent out to the host from that endpoint are canceled by clearing the rdy bit in the corresponding configin register. To keep track of such canceled buffers, the pend bit in the same register is set. The transfer must be queued again after the Control transfer is completed.

Similarly, a Link Reset cancels any waiting IN transactions by clearing the rdy bit in the configin register of all endpoints. The pend bit in the configin register is set for all endpoints with a pending IN transaction.

Buffer Count and Size

Under high load, the 32 buffers of the packet buffer (2 kB SRAM) are allocated as follows:

  • 1 is being processed following reception,
  • 4 are in the Available Buffer FIFO, and
  • 12 (worst case) waiting transmissions in the configin registers. This leaves 15 buffers for preparation of future transmissions (which would need 12 in the worst case of one per endpoint) and the free pool.

The size of 64 bytes per buffer satisfies the maximum USB packet size for a Full-Speed interface for Control transfers (max may be 8, 16, 32 or 64 bytes), Bulk Transfers (max is 64 bytes) and Interrupt transfers (max is 64 bytes). It is small for Isochronous transfers (which have a max size of 1023 bytes). The interface will need extending for high rate isochronous use (a possible option would be to allow up to 8 or 16 64-byte buffers to be aggregated as the isochronous buffer).

Design Details

Programmers Guide

Initialization

The basic hardware initialization is to (in any order) fill the Available Buffer FIFO, enable reception of SETUP and OUT packets on Endpoint 0 (this is the control endpoint that the host will use to configure the interface), enable reception of SETUP and OUT packets on any endpoints that accept them and enable any required interrupts. Finally, the interface is enabled by setting the enable bit in the usbctrl register. Setting this bit causes the USB device to assert the pullup on the D+ line, which is used by the host to detect the device. There is no need to configure the device ID in (usbctrl.device_address) at this point – the line remains in reset and the hardware forces the device ID to zero.

The second stage of initialization is done under control of the host, which will use control transfers (always beginning with SETUP transactions) to Endpoint 0. Initially these will be sent to device ID 0. When a Set Address request is received, the device ID received must be stored in the usbctrl.device_address register. Note that device 0 is used for the entire control transaction setting the new device ID, so writing the new ID to the register should not be done until the ACK for the Status stage has been received (see USB 2.0 specification).

Buffers

Software needs to manage the buffers in the packet buffer (2 kB SRAM). Each buffer can hold the maximum length packet for a Full-Speed interface (64 bytes). Other than for data movement, the management is most likely done based on their buffer ID which is a small integer between zero and (SRAM size in bytes)/(max packet size in bytes).

In order to avoid unintentional stalling the interface, there must be buffers available when the host sends data to the device (an OUT or STATUS transaction). Software needs to ensure (1) there are always buffer IDs in the Available Buffer FIFO, and (2) the Received Buffer FIFO is not full. If the Available Buffer FIFO is empty or the Received Buffer FIFO is full when data is received, a NACK will be returned to the host, requesting the packet be retried later. Generating NACK with this mechanism is generally to be avoided (for example the host expects a device will always accept STATUS packets to Endpoint 0).

Keeping the Available Buffer FIFO full can be done with a simple loop, adding buffer IDs from the software-managed free pool until the FIFO is full. A simpler policy of just adding a buffer ID to the Available Buffer FIFO whenever a buffer ID is removed from the Received Buffer FIFO should work on average, but performance will be slightly worse when bursts of packets are received.

Flow control (using NACKs) may be done on a per-endpoint basis using the rxenable_out and rxenable_setup registers. If this does not indicate OUT/SETUP packet reception is enabled, then any packet will receive a NACK to request a retry later. This should only be done for short durations or the host may timeout the transaction.

Reception

The host will send OUT or SETUP transactions when it wants to transfer data to the device. The data packets are directed to a particular endpoint, and the maximum packet size is set per-endpoint in its Endpoint Descriptor (this must be the same or smaller than the maximum packet size supported by the device). A pkt_received interrupt is raised whenever there is one or more packets in the Received Buffer FIFO. Software should pop the information from the Received Buffer FIFO by reading the rxfifo register, which gives (1) the buffer ID that the data was received in, (2) the data length received in bytes, (3) the endpoint to which the packet was sent, and (4) an indication if the packet was sent with an OUT or STATUS transaction. Note that the data length could be between zero and the maximum packet size – in some situations a zero length packet is used as an acknowledgment or end of transmission.

The data length does not include the packet CRC. (The CRC bytes are written to the buffer if they fit within the maximum buffer size.) Packets with a bad CRC will not be transferred to the Received Buffer FIFO, the hardware will request a retry.

Transmission

Data is transferred to the host based on the host requesting a transfer with an IN transaction. The host will only generate IN requests if the endpoint is declared as an IN endpoint in its Endpoint Descriptor (note that two descriptors are needed if the same endpoint is used for both IN and OUT transfers). The Endpoint Descriptor also includes a description of the frequency the endpoint should be polled.

Data is queued for transmission by writing the corresponding configin register with the buffer ID containing the data, the length in bytes of data (0 to maximum packet length) and setting the rdy bit. This data (with the packet CRC) will be sent as a response to the next IN transaction on the corresponding endpoint. When the host ACKs the data, the rdy bit is cleared, the corresponding endpoint bit is set in the in_sent register, and a pkt_sent interrupt is raised. If the host does not ACK the data, the packet will be retried. When the packet transmission has been noted by software, the corresponding endpoint bit should be cleared in the in_sent register (by writing a 1 to this very bit).

Note that the configin for an endpoint is a single register, so no new data packet should be queued until the previous packet has been ACKed. If an enabled SETUP transaction is received on an endpoint that has a transmission pending, the hardware will clear the rdy bit and set the pend bit in the configin register of that endpoint. Software must remember the pending transmission and, after the Control transaction is complete, write it back to the configin register with the rdy bit set.

Stalling

The stall registers are used for endpoint stalling. There is one dedicated register per endpoint. Stalling is used to signal that the host should not retry a particular transmission or to signal certain error conditions (functional stall). Control endpoints also use a STALL to indicate unsupported requests (protocol stall). Unused endpoints can have their stall register left clear, so in many cases there is no need to use the stall register. If the stall register is set for an endpoint then the STALL response will be provided to all IN/OUT requests on that endpoint.

In the case of a protocol stall, the device must send a STALL for all IN/OUT requests until the next SETUP token is received. To support this, software sets the stall register for an endpoint when the host requests an unsupported transfer. The hardware will then send a STALL response to all IN/OUT transactions until the next SETUP is received for this endpoint. Receiving the SETUP token clears the stall register for that endpoint. The hardware then sends NACKs to any IN/OUT requests until the software has decided what action to take for the new SETUP request.

Register Table

usbdev.INTR_STATE @ + 0x0
Interrupt State Register
Reset default = 0x0, mask 0x1ffff
31302928272625242322212019181716
  link_out_err
1514131211109876543210
connected frame rx_bitstuff_err rx_pid_err rx_crc_err link_in_err av_overflow rx_full av_empty link_resume link_suspend link_reset host_lost disconnected pkt_sent pkt_received
BitsTypeResetNameDescription
0rw1c0x0pkt_receivedRaised if a packet was received using an OUT or SETUP transaction.
1rw1c0x0pkt_sentRaised if a packet was sent as part of an IN transaction.
2rw1c0x0disconnectedRaised if VBUS is lost thus the link is disconnected.
3rw1c0x0host_lostRaised if link is active but SOF was not received from host for 4.096 ms. The SOF should be every 1 ms.
4rw1c0x0link_resetRaised if the link is at SE0 longer than 3 us indicating a link reset (host asserts for min 10 ms, device can react after 2.5 us).
5rw1c0x0link_suspendRaised if the line has signaled J for longer than 3ms and is therefore in suspend state.
6rw1c0x0link_resumeRaised when the link becomes active again after being suspended.
7rw1c0x0av_emptyRaised when a transaction is NACKed because the Available Buffer FIFO for OUT or SETUP transactions is empty.
8rw1c0x0rx_fullRaised when a transaction is NACKed because the Received Buffer FIFO for OUT or SETUP transactions is full.
9rw1c0x0av_overflowRaised if a write was done to the Available Buffer FIFO when the FIFO was full.
10rw1c0x0link_in_errRaised if a packet to an IN endpoint started to be received but was then dropped due to an error. After transmitting the IN payload, the USB device expects a valid ACK handshake packet. This error is raised if either the packet or CRC is invalid or a different token was received.
11rw1c0x0rx_crc_errRaised if a CRC error occured.
12rw1c0x0rx_pid_errRaised if an invalid packed identifier (PID) was received.
13rw1c0x0rx_bitstuff_errRaised if an invalid bitstuffing was received.
14rw1c0x0frameRaised when the USB frame number is updated with a valid SOF.
15rw1c0x0connectedRaised if VBUS is applied.
16rw1c0x0link_out_errRaised if a packet to an OUT endpoint started to be received but was then dropped due to an error. This error is raised if either the data toggle, token, packet or CRC is invalid or if there is no buffer available in the Received Buffer FIFO.


usbdev.INTR_ENABLE @ + 0x4
Interrupt Enable Register
Reset default = 0x0, mask 0x1ffff
31302928272625242322212019181716
  link_out_err
1514131211109876543210
connected frame rx_bitstuff_err rx_pid_err rx_crc_err link_in_err av_overflow rx_full av_empty link_resume link_suspend link_reset host_lost disconnected pkt_sent pkt_received
BitsTypeResetNameDescription
0rw0x0pkt_receivedEnable interrupt when INTR_STATE.pkt_received is set
1rw0x0pkt_sentEnable interrupt when INTR_STATE.pkt_sent is set
2rw0x0disconnectedEnable interrupt when INTR_STATE.disconnected is set
3rw0x0host_lostEnable interrupt when INTR_STATE.host_lost is set
4rw0x0link_resetEnable interrupt when INTR_STATE.link_reset is set
5rw0x0link_suspendEnable interrupt when INTR_STATE.link_suspend is set
6rw0x0link_resumeEnable interrupt when INTR_STATE.link_resume is set
7rw0x0av_emptyEnable interrupt when INTR_STATE.av_empty is set
8rw0x0rx_fullEnable interrupt when INTR_STATE.rx_full is set
9rw0x0av_overflowEnable interrupt when INTR_STATE.av_overflow is set
10rw0x0link_in_errEnable interrupt when INTR_STATE.link_in_err is set
11rw0x0rx_crc_errEnable interrupt when INTR_STATE.rx_crc_err is set
12rw0x0rx_pid_errEnable interrupt when INTR_STATE.rx_pid_err is set
13rw0x0rx_bitstuff_errEnable interrupt when INTR_STATE.rx_bitstuff_err is set
14rw0x0frameEnable interrupt when INTR_STATE.frame is set
15rw0x0connectedEnable interrupt when INTR_STATE.connected is set
16rw0x0link_out_errEnable interrupt when INTR_STATE.link_out_err is set


usbdev.INTR_TEST @ + 0x8
Interrupt Test Register
Reset default = 0x0, mask 0x1ffff
31302928272625242322212019181716
  link_out_err
1514131211109876543210
connected frame rx_bitstuff_err rx_pid_err rx_crc_err link_in_err av_overflow rx_full av_empty link_resume link_suspend link_reset host_lost disconnected pkt_sent pkt_received
BitsTypeResetNameDescription
0wo0x0pkt_receivedWrite 1 to force INTR_STATE.pkt_received to 1
1wo0x0pkt_sentWrite 1 to force INTR_STATE.pkt_sent to 1
2wo0x0disconnectedWrite 1 to force INTR_STATE.disconnected to 1
3wo0x0host_lostWrite 1 to force INTR_STATE.host_lost to 1
4wo0x0link_resetWrite 1 to force INTR_STATE.link_reset to 1
5wo0x0link_suspendWrite 1 to force INTR_STATE.link_suspend to 1
6wo0x0link_resumeWrite 1 to force INTR_STATE.link_resume to 1
7wo0x0av_emptyWrite 1 to force INTR_STATE.av_empty to 1
8wo0x0rx_fullWrite 1 to force INTR_STATE.rx_full to 1
9wo0x0av_overflowWrite 1 to force INTR_STATE.av_overflow to 1
10wo0x0link_in_errWrite 1 to force INTR_STATE.link_in_err to 1
11wo0x0rx_crc_errWrite 1 to force INTR_STATE.rx_crc_err to 1
12wo0x0rx_pid_errWrite 1 to force INTR_STATE.rx_pid_err to 1
13wo0x0rx_bitstuff_errWrite 1 to force INTR_STATE.rx_bitstuff_err to 1
14wo0x0frameWrite 1 to force INTR_STATE.frame to 1
15wo0x0connectedWrite 1 to force INTR_STATE.connected to 1
16wo0x0link_out_errWrite 1 to force INTR_STATE.link_out_err to 1


usbdev.usbctrl @ + 0xc
USB Control
Reset default = 0x0, mask 0x7f0001
31302928272625242322212019181716
  device_address
1514131211109876543210
  enable
BitsTypeResetNameDescription
0rw0x0enableSet to enable the USB interface and assert the pullup.
15:1Reserved
22:16rw0x0device_addressDevice address set by host (this should be copied from the Set Device ID SETUP packet). This will be zeroed by the hardware when the link resets.


usbdev.usbstat @ + 0x10
USB Status
Reset default = 0x80000000, mask 0x8787ffff
31302928272625242322212019181716
rx_empty   rx_depth av_full   av_depth
1514131211109876543210
sense link_state host_lost frame
BitsTypeResetNameDescription
10:0ro0x0frameFrame index received from host. On an active link, this will increment every milisecond.
11ro0x0host_lostStart of frame not received from host for 4.096 ms and the line is active.
14:12ro0x0link_stateState of USB link, decoded from line.
0disconnectLink disconnected (no VBUS)
1poweredLink powered, but not reset yet
2powered_suspendLink suspended (constant idle/J for > 3 ms), but not reset yet
3activeLink active
4suspendLink suspended (constant idle for > 3 ms), was active before becoming suspended
5active_nosofLink active but no SOF has been received since the last reset.
Other values are reserved.
15ro0x0senseReflects the state of the sense pin. 1 indicates that the host is providing VBUS. Note that this bit always shows the state of the actual pin and does not take account of the override control.
18:16ro0x0av_depthNumber of buffers in the Available Buffer FIFO. These buffers are available for receiving packets.
22:19Reserved
23ro0x0av_fullAvailable Buffer FIFO is full.
26:24ro0x0rx_depthNumber of buffers in the Received Buffer FIFO. These buffers have packets that have been received and should be popped from the FIFO and processed.
30:27Reserved
31ro0x1rx_emptyReceived Buffer FIFO is empty.


usbdev.avbuffer @ + 0x14
Available Buffer FIFO
Reset default = 0x0, mask 0x0
31302928272625242322212019181716
 
1514131211109876543210
  buffer
BitsTypeResetNameDescription
4:0woxbufferThis field contains the buffer ID being passed to the USB receive engine. If the Available Buffer FIFO is full, any write operations are discarded.


usbdev.rxfifo @ + 0x18
Received Buffer FIFO
Reset default = 0x0, mask 0xf87f1f
31302928272625242322212019181716
  ep setup  
1514131211109876543210
  size   buffer
BitsTypeResetNameDescription
4:0ro0x0bufferThis field contains the buffer ID that data was received into. On read the buffer ID is popped from the Received Buffer FIFO and returned to software.
7:5Reserved
14:8ro0x0sizeThis field contains the data lenght in bytes of the packet written to the buffer.
18:15Reserved
19ro0x0setupThis bit indicates if the received transaction is of type SETUP (1) or OUT (0).
23:20ro0x0epThis field contains the endpoint ID to which the packet was directed.


usbdev.rxenable_setup @ + 0x1c
Receive SETUP transaction enable
Reset default = 0x0, mask 0xfff
31302928272625242322212019181716
 
1514131211109876543210
  setup_11 setup_10 setup_9 setup_8 setup_7 setup_6 setup_5 setup_4 setup_3 setup_2 setup_1 setup_0
BitsTypeResetNameDescription
0rw0x0setup_0This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP request will be responded to with a NACK.
1rw0x0setup_1For Endpoint1
2rw0x0setup_2For Endpoint2
3rw0x0setup_3For Endpoint3
4rw0x0setup_4For Endpoint4
5rw0x0setup_5For Endpoint5
6rw0x0setup_6For Endpoint6
7rw0x0setup_7For Endpoint7
8rw0x0setup_8For Endpoint8
9rw0x0setup_9For Endpoint9
10rw0x0setup_10For Endpoint10
11rw0x0setup_11For Endpoint11


usbdev.rxenable_out @ + 0x20
Receive OUT transaction enable
Reset default = 0x0, mask 0xfff
31302928272625242322212019181716
 
1514131211109876543210
  out_11 out_10 out_9 out_8 out_7 out_6 out_5 out_4 out_3 out_2 out_1 out_0
BitsTypeResetNameDescription
0rw0x0out_0This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NACK.
1rw0x0out_1For Endpoint1
2rw0x0out_2For Endpoint2
3rw0x0out_3For Endpoint3
4rw0x0out_4For Endpoint4
5rw0x0out_5For Endpoint5
6rw0x0out_6For Endpoint6
7rw0x0out_7For Endpoint7
8rw0x0out_8For Endpoint8
9rw0x0out_9For Endpoint9
10rw0x0out_10For Endpoint10
11rw0x0out_11For Endpoint11


usbdev.in_sent @ + 0x24
IN Transaction Sent
Reset default = 0x0, mask 0xfff
31302928272625242322212019181716
 
1514131211109876543210
  sent_11 sent_10 sent_9 sent_8 sent_7 sent_6 sent_5 sent_4 sent_3 sent_2 sent_1 sent_0
BitsTypeResetNameDescription
0rw1c0x0sent_0This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.
1rw1c0x0sent_1For Endpoint1
2rw1c0x0sent_2For Endpoint2
3rw1c0x0sent_3For Endpoint3
4rw1c0x0sent_4For Endpoint4
5rw1c0x0sent_5For Endpoint5
6rw1c0x0sent_6For Endpoint6
7rw1c0x0sent_7For Endpoint7
8rw1c0x0sent_8For Endpoint8
9rw1c0x0sent_9For Endpoint9
10rw1c0x0sent_10For Endpoint10
11rw1c0x0sent_11For Endpoint11


usbdev.stall @ + 0x28
Endpoint STALL control
Reset default = 0x0, mask 0xfff
31302928272625242322212019181716
 
1514131211109876543210
  stall_11 stall_10 stall_9 stall_8 stall_7 stall_6 stall_5 stall_4 stall_3 stall_2 stall_1 stall_0
BitsTypeResetNameDescription
0rw0x0stall_0If this bit is set then an IN or OUT transaction to this endpoint will be responded to with a STALL return. This is used when the endpoint is disabled (functional stall) or when a control transfer is not supported (protocol stall). SETUP transactions are always accepted and a SETUP will clear the stall flag (this is necessary for protocol stalls, to avoid sending stalls on subsequent IN/OUT transfers).
1rw0x0stall_1For Endpoint1
2rw0x0stall_2For Endpoint2
3rw0x0stall_3For Endpoint3
4rw0x0stall_4For Endpoint4
5rw0x0stall_5For Endpoint5
6rw0x0stall_6For Endpoint6
7rw0x0stall_7For Endpoint7
8rw0x0stall_8For Endpoint8
9rw0x0stall_9For Endpoint9
10rw0x0stall_10For Endpoint10
11rw0x0stall_11For Endpoint11


usbdev.configin_0 @ + 0x2c
Configure IN Transaction
Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy_0 pend_0  
1514131211109876543210
  size_0   buffer_0
BitsTypeResetNameDescription
4:0rw0x0buffer_0The buffer ID containing the data to send when an IN transaction is received on the endpoint.
7:5Reserved
14:8rw0x0size_0The number of bytes to send from the buffer. If this is 0 then a CRC only packet is sent. If this is greater than 64 then 64 bytes are sent.
29:15Reserved
30rw1c0x0pend_0This bit indicates a pending transaction was canceled by the hardware. The bit is set when the rdy bit is cleared by hardware because of a SETUP packet being received or a link reset being detected. The bit remains set until cleared by being written with a 1.
31rw0x0rdy_0This bit should be set to indicate the buffer is ready for sending. It will be cleared when the ACK is received indicating the host has accepted the data. This bit will also be cleared if an enabled SETUP transaction is received on the endpoint. This allows use of the IN channel for transfer of SETUP information. The original buffer must be resubmitted after the SETUP sequence is complete. A link reset also clears the bit. In either of the cases where the hardware cancels the transaction it will also set the pend bit.


usbdev.configin_1 @ + 0x30
Configure IN Transaction
Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy_1 pend_1  
1514131211109876543210
  size_1   buffer_1
BitsTypeResetNameDescription
4:0rw0x0buffer_1For Endpoint1
7:5Reserved
14:8rw0x0size_1For Endpoint1
29:15Reserved
30rw1c0x0pend_1For Endpoint1
31rw0x0rdy_1For Endpoint1


usbdev.configin_2 @ + 0x34
Configure IN Transaction
Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy_2 pend_2  
1514131211109876543210
  size_2   buffer_2
BitsTypeResetNameDescription
4:0rw0x0buffer_2For Endpoint2
7:5Reserved
14:8rw0x0size_2For Endpoint2
29:15Reserved
30rw1c0x0pend_2For Endpoint2
31rw0x0rdy_2For Endpoint2


usbdev.configin_3 @ + 0x38
Configure IN Transaction
Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy_3 pend_3  
1514131211109876543210
  size_3   buffer_3
BitsTypeResetNameDescription
4:0rw0x0buffer_3For Endpoint3
7:5Reserved
14:8rw0x0size_3For Endpoint3
29:15Reserved
30rw1c0x0pend_3For Endpoint3
31rw0x0rdy_3For Endpoint3


usbdev.configin_4 @ + 0x3c
Configure IN Transaction
Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy_4 pend_4  
1514131211109876543210
  size_4   buffer_4
BitsTypeResetNameDescription
4:0rw0x0buffer_4For Endpoint4
7:5Reserved
14:8rw0x0size_4For Endpoint4
29:15Reserved
30rw1c0x0pend_4For Endpoint4
31rw0x0rdy_4For Endpoint4


usbdev.configin_5 @ + 0x40
Configure IN Transaction
Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy_5 pend_5  
1514131211109876543210
  size_5   buffer_5
BitsTypeResetNameDescription
4:0rw0x0buffer_5For Endpoint5
7:5Reserved
14:8rw0x0size_5For Endpoint5
29:15Reserved
30rw1c0x0pend_5For Endpoint5
31rw0x0rdy_5For Endpoint5


usbdev.configin_6 @ + 0x44
Configure IN Transaction
Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy_6 pend_6  
1514131211109876543210
  size_6   buffer_6
BitsTypeResetNameDescription
4:0rw0x0buffer_6For Endpoint6
7:5Reserved
14:8rw0x0size_6For Endpoint6
29:15Reserved
30rw1c0x0pend_6For Endpoint6
31rw0x0rdy_6For Endpoint6


usbdev.configin_7 @ + 0x48
Configure IN Transaction
Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy_7 pend_7  
1514131211109876543210
  size_7   buffer_7
BitsTypeResetNameDescription
4:0rw0x0buffer_7For Endpoint7
7:5Reserved
14:8rw0x0size_7For Endpoint7
29:15Reserved
30rw1c0x0pend_7For Endpoint7
31rw0x0rdy_7For Endpoint7


usbdev.configin_8 @ + 0x4c
Configure IN Transaction
Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy_8 pend_8  
1514131211109876543210
  size_8   buffer_8
BitsTypeResetNameDescription
4:0rw0x0buffer_8For Endpoint8
7:5Reserved
14:8rw0x0size_8For Endpoint8
29:15Reserved
30rw1c0x0pend_8For Endpoint8
31rw0x0rdy_8For Endpoint8


usbdev.configin_9 @ + 0x50
Configure IN Transaction
Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy_9 pend_9  
1514131211109876543210
  size_9   buffer_9
BitsTypeResetNameDescription
4:0rw0x0buffer_9For Endpoint9
7:5Reserved
14:8rw0x0size_9For Endpoint9
29:15Reserved
30rw1c0x0pend_9For Endpoint9
31rw0x0rdy_9For Endpoint9


usbdev.configin_10 @ + 0x54
Configure IN Transaction
Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy_10 pend_10  
1514131211109876543210
  size_10   buffer_10
BitsTypeResetNameDescription
4:0rw0x0buffer_10For Endpoint10
7:5Reserved
14:8rw0x0size_10For Endpoint10
29:15Reserved
30rw1c0x0pend_10For Endpoint10
31rw0x0rdy_10For Endpoint10


usbdev.configin_11 @ + 0x58
Configure IN Transaction
Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy_11 pend_11  
1514131211109876543210
  size_11   buffer_11
BitsTypeResetNameDescription
4:0rw0x0buffer_11For Endpoint11
7:5Reserved
14:8rw0x0size_11For Endpoint11
29:15Reserved
30rw1c0x0pend_11For Endpoint11
31rw0x0rdy_11For Endpoint11


usbdev.iso @ + 0x5c
Endpoint ISO setting
Reset default = 0x0, mask 0xfff
31302928272625242322212019181716
 
1514131211109876543210
  iso_11 iso_10 iso_9 iso_8 iso_7 iso_6 iso_5 iso_4 iso_3 iso_2 iso_1 iso_0
BitsTypeResetNameDescription
0rw0x0iso_0If this bit is set then the endpoint will be treated as an ISO endpoint. No handshake packet will be sent for an OUT transaction and no handshake packet will be expected for an IN transaction.
1rw0x0iso_1For Endpoint1
2rw0x0iso_2For Endpoint2
3rw0x0iso_3For Endpoint3
4rw0x0iso_4For Endpoint4
5rw0x0iso_5For Endpoint5
6rw0x0iso_6For Endpoint6
7rw0x0iso_7For Endpoint7
8rw0x0iso_8For Endpoint8
9rw0x0iso_9For Endpoint9
10rw0x0iso_10For Endpoint10
11rw0x0iso_11For Endpoint11


usbdev.data_toggle_clear @ + 0x60
Clear the data toggle flag
Reset default = 0x0, mask 0x0
31302928272625242322212019181716
 
1514131211109876543210
  clear_11 clear_10 clear_9 clear_8 clear_7 clear_6 clear_5 clear_4 clear_3 clear_2 clear_1 clear_0
BitsTypeResetNameDescription
0woxclear_0Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.
1woxclear_1For Endpoint1
2woxclear_2For Endpoint2
3woxclear_3For Endpoint3
4woxclear_4For Endpoint4
5woxclear_5For Endpoint5
6woxclear_6For Endpoint6
7woxclear_7For Endpoint7
8woxclear_8For Endpoint8
9woxclear_9For Endpoint9
10woxclear_10For Endpoint10
11woxclear_11For Endpoint11


usbdev.phy_pins_sense @ + 0x64
USB PHY pins sense. This register can be used to read out the state of the USB device inputs and outputs from software. This is designed to be used for debugging purposes or during chip testing.
Reset default = 0x0, mask 0x13f07
31302928272625242322212019181716
  pwr_sense
1514131211109876543210
  suspend_o tx_oe_o tx_se0_o tx_d_o tx_dn_o tx_dp_o   rx_d_i rx_dn_i rx_dp_i
BitsTypeResetNameDescription
0ro0x0rx_dp_iUSB D+ input.
1ro0x0rx_dn_iUSB D- input.
2ro0x0rx_d_iUSB differential input.
7:3Reserved
8ro0x0tx_dp_oUSB D+ output (readback).
9ro0x0tx_dn_oUSB D- output (readback).
10ro0x0tx_d_oUSB differential output (readback).
11ro0x0tx_se0_oUSB SE0 output (readback).
12ro0x0tx_oe_oUSB OE output (readback).
13ro0x0suspend_oUSB suspend output (readback).
15:14Reserved
16ro0x0pwr_senseUSB power sense signal.


usbdev.phy_pins_drive @ + 0x68
USB PHY pins drive. This register can be used to control the USB device inputs and outputs from software. This is designed to be used for debugging purposes or during chip testing.
Reset default = 0x0, mask 0x101ff
31302928272625242322212019181716
  en
1514131211109876543210
  suspend_o dn_pullup_en_o dp_pullup_en_o tx_mode_se_o oe_o se0_o d_o dn_o dp_o
BitsTypeResetNameDescription
0rw0x0dp_oUSB D+ output.
1rw0x0dn_oUSB D- output.
2rw0x0d_oUSB differential output.
3rw0x0se0_oUSB SE0 output.
4rw0x0oe_oUSB OE output.
5rw0x0tx_mode_se_oUSB TX mode. 0: Differential, 1: Single-ended.
6rw0x0dp_pullup_en_oUSB D+ pullup enable output.
7rw0x0dn_pullup_en_oUSB D- pullup enable output.
8rw0x0suspend_oUSB suspend output.
15:9Reserved
16rw0x0en0: Outputs are controlled by the hardware block. 1: Outputs are controlled with this register.


usbdev.phy_config @ + 0x6c
USB PHY Configuration
Reset default = 0x4, mask 0xff
31302928272625242322212019181716
 
1514131211109876543210
  tx_osc_test_mode usb_ref_disable pinflip override_pwr_sense_val override_pwr_sense_en eop_single_bit tx_differential_mode rx_differential_mode
BitsTypeResetNameDescription
0rw0x0rx_differential_modeUse the differential RX signal instead of the single-ended signals. Currently only 0 (single-ended operation) is supported.
1rw0x0tx_differential_modeUse the differential TX signal instead of the single-ended signals. Currently only 0 (single-ended operation) is supported.
2rw0x1eop_single_bitRecognize a single SE0 bit as an end of packet, otherwise two successive bits are required.
3rw0x0override_pwr_sense_enOverride the USB power sense value with override_pwr_sense_val.
4rw0x0override_pwr_sense_val0: USB power not present, 1: present.
5rw0x0pinflipFlip the D+/D- pins. Particularly useful if D+/D- are mapped to SBU1/SBU2 pins of USB-C.
6rw0x0usb_ref_disable0: Enable reference signal generation for clock synchronization, 1: disable it by forcing the associated signals to zero.
7rw0x0tx_osc_test_modeDisable (0) or enable (1) oscillator test mode. If enabled, the device constantly transmits a J/K pattern, which is useful for testing the USB clock. Note that while in oscillator test mode, the device no longer receives SOFs and consequently does not generate the reference signal for clock synchronization. The clock might drift off.


usbdev.buffer @ + 0x800
512 item rw window
Byte writes are not supported
310
+0x800 
+0x804 
 ...
+0xff8 
+0xffc 
2 kB packet buffer. Divided into 32 64-byte buffers. The packet buffer is used for sending and receiveing packets.