Simple USB Full Speed Device IP Technical Specification

Overview

Features

  • USB Full-Speed (12Mbps) Device interface

  • 2kbyte Interface buffer

  • Up to 12 Endpoints (including required Endpoint 0)

  • Support for USB packet size up to 64 bytes

  • Support SETUP, IN and OUT transactions

  • Support for Bulk, Control, Interrupt and Isochronous endpoints and transactions

  • Initial version does not support Isochronous transfers larger than 64 bytes (later extension)

  • Streaming possible through software

  • Interrupts for packet reception and transmission

Description

The USB device module is a simple software-driven gneric USB device interface for Full-Speed USB operation. The IP includes the physical layer interface (switchable between regular 3.3V I/O pads, or a differential USB transceiver), the low level USB protocol and a packet buffer interface to the software.

Compatibility

The USB device programming interface is not based on any existing interface.

Theory of Operations

A useful quick reference for USB Full-Speed is http://www.usbmadesimple.co.uk/ums_3.htm

The block diagram shows a high level view of the simple USB Device including the main register access paths.

Block Diagram

Clocking

The USB Full-Speed interface runs at a 12MHz datarate. The interface runs at four times this and must be clocked from an accurate 48MHz clock source. The USB specification for a Full-Speed device requires the average bit-rate is 12Mbps +/- 0.25%, so the clock needs to support maximum error of 2,500ppm.
The maximum allowable integrated jitter is +/- 1ns over 1 to 7 bit-periods.

Control transfers pass through asynchronous FIFOs or have a ready bit synchronized across the clock domain boundary. A dual-port asynchronous buffer SRAM is used for data transfers between the bus clock and USB clock domains.

USB Interface Pins

Full-Speed USB uses a bidirectional serial interface as shown in Figure 7-24 of the USB 2.0 Full-Speed specification. For reasons of flexibility, this IP block features both differential and single-ended transmit and receive paths.

For better receive sensitivity, lower transmit jitter and to be standard compliant, a dedicated, differential USB transceiver such as the USB1T11A or the USB1T20 must be used (see Section 7.1.4.1 of the USB 2.0 specification). Depending on the selected USB transceiver, either the differential or the single-ended transmit and receive paths or a combination of the two can be used to interface the IP block with the transceiver.

When prototyping on FPGAs (here the interface can be implemented with pseudo-differential 3.3V GPIO pins and an oversampling receiver for recovery of the bitstream and clock alignment), the single-ended signal pairs can be used. External to the IP, these should be combined to drive the actual pins when transmit is enabled and receive otherwise. Using standard 3.3V IO pads allows use on most FPGAs although the drive strength and series termination resistors may need to be adjusted to meet the USB signal eye. On a Xilinx Artix-7 (and less well tested Spartan-7) part, setting the driver to the 8mA, FAST setting seems to work well with a 22R series termination (and with a 0R series termination).

The following sections describe how the various input/output signals relate to the USB interface pins for the different receive and transmit configurations.

Data Transmit

The IP block supports both differential and single-ended transmission (TX). The TX mode can be selected by setting the tx_differential_mode bit in phy_config to either 1 (differential) or 0 (single ended).

The following table summarizes how the different output signals relate to the USB interface pins.

External Pins Internal Signals Notes
D+, D- d_o Data output for interfacing with a differential USB transceiver.
" se0_o Signal Single-Ended Zero (SE0) link state to a differential USB transceiver.
" dp_o, dn_o Single-ended data output signals. These can be used to interface to regular IO cells for prototyping on an FPGA, but such an interface will probably not be USB compliant.
[TX Mode] tx_mode_se_o Indicates the selected TX mode: single-ended (1) or differential (0) operation.

Note that according to the Comportable guideline for peripheral functionality, every output signal name_o has a dedicated output enable name_en_o. For TX data, these separate signals d_en_o, dp_en_o and dn_en_o all correspond to the same TX or output enable signal (OE in the USB spec).

Data Receive

The IP block supports both differential and single-ended reception (RX). The RX mode can be selected by setting the rx_differential_mode bit in phy_config to either 1 (differential) or 0 (single ended).

The following table summarizes how the different input signals relate to the USB interface pins.

External Pins Internal Signals Notes
D+, D- d_i Data input for interfacing with a differential USB transceiver. Used in differential RX mode only.
" dp_i, dn_i Single-ended data input signals. These signals are used to detect the SE0 link state in differential RX mode. They can further be used to interface to regular IO cells for prototyping on an FPGA, but such an interface will probably not be USB compliant.

Non-Data Pins

The USB device features the following non-data pins.

External Pins Internal Signals Notes
sense (VBUS) sense_i The sense pin indicates the presence of VBUS from the USB host.
[pullup] pullup_o When the pullup_o asserts a 1.5k pullup resistor should be connected to D+. This can be done inside the chip or with an external pin. A permanently connected resistor can also be used.
[suspend] suspend_o The suspend pin indicates to the USB transceiver that a constant idle has been detected on the link and the device is in the Suspended state (see Section 7.1.7.6 of the USB 2.0 specification).

The USB host will identify itself to the device by enabling the 5V VBUS power. It may do a hard reset of a port by removing and reasserting VBUS (the Linux driver will do this when it finds a port in an inconsistent state or a port that generates errors during enumeration). The IP block detects VBUS through the sense pin. This pin is always an input and should be externally connected to detect the state of the VBUS. Note that this may require a resistor divider or (for USB-C where VBUS can be up to 20V) active level translation to an acceptable voltage for the input pin.

A Full-Speed device identifies itself by providing a 1.5k pullup resistor (to 3.3V) on the D+ line. The IP block produces a signal pullup_o that is asserted when this resistor should be presented. This signal will be asserted whenever the interface is enabled. In an FPGA implementation, this signal can drive a 3.3V output pin that is driven high when the signal is asserted and set high impedance when the signal is deasserted, and the output pin used to drive a 1.5k resistor connected on the board to the D+ line. Alternatively, it can be used to enable an internal 1.5k pullup on the D+ pin.

Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module usbdev has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks:

Bus Device Interface: tlul

Bus Host Interface: none

Peripheral Pins for Chip IO:

Pin namedirectionDescription
senseinputUSB host VBUS sense
se0outputUSB single-ended zero link state
pullupoutputUSB pullup control
tx_mode_seoutputUSB single-ended transmit mode control
suspendoutputUSB link suspend state
dinoutUSB data differential
dpinoutUSB data D+
dninoutUSB data D-

Interrupts:

Interrupt NameDescription
pkt_receivedraised if a packet was received using an OUT or SETUP transaction.
pkt_sentraised if a packet was sent as part of an IN transaction.
disconnectedRaised if VBUS is lost thus the link is disconnected
host_lostRaised if link is active but start of frame not received from host for 4.096ms. The SOF should be every 1ms.
link_resetRaised if the link is at SE0 longer than 3us indicating a link reset (host asserts for min 10ms, device can react after 2.5us).
link_suspendRaised if the line has signalled J for longer than 3ms and is therefore in suspend state.
link_resumeRaised when the link becomes active again after being suspended.
av_emptyRaised when a transaction is NACKed because the AVBuffer FIFO for OUT or SETUP transactions is empty.
rx_fullRaised when a transaction is NACKed because the Receive FIFO for OUT or SETUP transactions is full.
av_overflowRaised if a write was done to the AVBuffer fifo when the FIFO was full.
link_in_errRaised if a packet to an IN endpoint started to be received but was then dropped due to an error. After transmitting the IN payload, the USB device expects a valid ACK handshake packet. This error is raised if either the packet or CRC is invalid or a different token was received.
rx_crc_errRaised if a CRC error occured.
rx_pid_errRaised if an invalid PID was received.
rx_bitstuff_errRaised if an invalid bitstuffing was received.
frameRaised when the USB frame number is updated with a valid SOF frame.
connectedRaised if VBUS is applied.

Security Alerts: none

The USB link has a number of states. These are detected and reported in usbstat.link_state and state changes are reported using interrupts. The FSM implements a subset of the USB device state diagram shown in Figure 9-1 of the USB 2.0 specification.

State Description
Disconnected The link is disconnected. This is signalled when the VBUS is not driven by the host, which results in the sense input pin being low. An interrupt is raised on entering this state.
Powered The device has been powered as VBUS is being driven by the host, but has not been reset yet. The link is reset whenever the D+ and D- are both low (an SE0 condition) for an extended period. The host will assert reset for a minumum of 10ms, but the USB specification allows the device to detect and respond to a reset after 2.5us. The implementation here will report the reset state and raise an interrupt when the link is in SE0 for 3us.
Powered Suspend The link is suspended when at idle (a J condition) for more than 3ms. An interrupt is generated when the suspend is detected and a resume interrupt is generated when the link exits the suspend state. This state is entered, if the device has not been reset yet.
Active The link is active when it is running normally
Suspened Similar to ‘Powered Suspend’, but the device was in the active state before being suspended.
Link Events Description
Disconnect VBUS has been lost.
Link Reset The link has been in the SE0 state for 3us.
Link Suspend The link has been in the J state for more than 3ms, upon which we have to enter the suspend state.
Link Resume The link has been driven to a non-J state after being in suspend.
Host Lost The host lost interrupt will be signalled if the link is active but a start of frame has not been received from the host in 4.096ms. The host is required to send a SOF every 1ms. This is not an expected condition.

USB Protocol Engine

The USB 2.0 Full Speed Protocol Engine is provided by the common USB interface code and is not part of this module.

At the lowest level of the USB stack the transmit bitstream is serialized, converted to NRZI encoding with bit-stuffing and sent to the transmitter. The received bitstream is recovered, clock aligned and decoded and has bit-stuffing removed. The recovered clock alignment is used for transmission.

The higher level protocol engine forms the bitstream into packets, performs CRC checking and recognizes IN, OUT and SETUP transactions. These are presented without buffering to this module which must accept or provide data when requested. The protocol engine may cancel a transaction because of a bad CRC or request a retry if an ACK was not received.

Buffer Interface

A 2k Byte SRAM is used to hold data between the system and the USB interface. This is divided up into 32 buffers each containing 64 bytes. This is an asynchronous dual-port SRAM with the software accessing from the bus clock domain and the USB interface accessing from the USB 48MHz clock domain.

The 64 byte size for the buffers satisfies the maximum USB packet size for a Full Speed interface for Control transfers (max may be 8, 16, 32 or 64 bytes), Bulk Transfers (max is 64 bytes) and Interrupt transfers (max is 64 bytes). It is small for Isochronous transfers (which have a max of 1023 bytes) and the interface will need extending for high rate isochronous use (would probably allow up to 8 or 16 buffers to be aggregated as the isoc buffer).

The software provides buffers for packet reception through a 4-entry available-buffer FIFO. (More study needed but 4 seems about right: one just returned to software, one being filled, one ready to be filled and one for luck.) The RxEnable register is used to indicate which endpoints will accept data from the host using SETUP or OUT transactions. When a packet is transferred from the host to the device (using an OUT or SETUP transaction) and reception of that type of transaction is enabled for the requested endpoint, the next receive buffer is pulled from the FIFO and will be filled with the data from the packet. If the packet is correctly received then an ACK is returned to the host and the buffer number, the packet size, an out/setup flag and the endpoint number are passed back to software using the receive FIFO and a pkt_received interrupt raised. The driver should immediately provide a free buffer for future reception by writing its buffer number to the available-buffer FIFO, then can process the packet and eventually return the received buffer to the free pool. This allows streaming on a single endpoint or across a number of endpoints. If the packets cannot be consumed at the rate they are received then software can implement selective flow-control by disabling OUT or SETUP transactions for a particular endpoint, which will result in a request to that endpoint being NACKed. In the unfortunate event that the available-buffer FIFO is empty or receive FIFO is full then all OUT/SETUP transactions are NACKed.

To send data to the host in response to an IN transaction the software writes the data into a free buffer and writes the buffer number, data length and a ready flag to the configin register for the endpoint that the data is from. When the host next does an IN transaction to that endpoint the data will be sent from the buffer. On receipt of the ACK from the host the ready flag in the configin register will be cleared and the bit corresponding to the endpoint number will be set in the in_sent register which will cause a pkt_sent interrupt. Software can return the buffer to the free pool and write a 1 to clear the bit in the in_sent register. Note that streaming can be achieved if the next buffer has been prepared and is written to the configin register when the interrupt is received.

A Control transfer may need an IN data transfer. Therefore when a SETUP transaction is received for an endpoint the ready bit is cleared in configin to cancel any buffer that was pending being sent to the host from the Endpoint. When this is done the pending bit will be set. The transfer must be queued again after the Control transfer is completed.

A link level reset will also cancel pending IN transactions by clearing the ready bit and setting the pending bit.

In general the 32 buffers will be allocated with one being processed following reception, 4 in the available-buffer FIFO and 12 (worst case) waiting transmission in the configin registers. This leaves 15 for preparation of next transmission (which would need 12 in the worst case of one per endpoint) and the free pool.

Design Details

Programmers Guide

Initialization

The basic hardware initialization is to (in any order) fill the Available buffer FIFO, enable reception of SETUP and OUT packets on Endpoint 0 (this is the control endpoint that the host will use to configure the interface), enable reception of SETUP and OUT packets on any endpoints that accept them and enable any required interrupts. Finally the interface is enabled by setting the usbctrl.enable bit. Setting this bit will cause the USB device to assert the Full-Speed pullup on the D+ line, which is used by the host to detect the device. In most cases there is no need to configure the device ID (usbctrl.device_address) at this point – the line will be in reset and the hardware will have forced the device ID to zero.

The second stage of initialization is done under control of the host, which will use control transfers (always beginning with SETUP transactions) to Endpoint 0. Initially these will be sent to device ID 0. When a Set Address request is received the device ID received must be stored in the usbctrl.device_address register. Note that device 0 is used for the entire control transaction setting the new device ID, so writing the new ID to the register should not be done until the ACK for the Status stage (see USB specification) has been received.

Buffers

The driver needs to manage the buffers in the interface SRAM. Each buffer can hold the maximum length packet (64 bytes). Other than for data movement this is most likely done based on their buffer identifier which is a small integer between zero and (SRAM size-in-bytes)/(MaxPacket-in-bytes).

In order to avoid unintentionally stalling the interface there must be buffers available when the host sends data to the device (an OUT or STATUS transaction). The driver needs to ensure (1) there are always buffer identifiers in the Available buffer FIFO (2) the receive FIFO is not full. If the AV FIFO is empty or the RX FIFO is full when data is received a NAK will be returned to the host, requesting the packet be retried later. Generating NAK with this mechanism is generally to be avoided (for example the host expects a device will always accept STATUS packets to endpoint 0).

Keeping the AV FIFO full can be done with a simple loop, adding buffers from the software managed free-pool until the FIFO is full. A simpler policy of just adding a buffer to the AV FIFO everytime one is removed from the RX FIFO should work on average, but will be slightly worse when a burst of packets are received.

Flow control (using NAKs) may be done per-endpoint using the rxenable register. If this does not indicate OUT packet reception is enabled then any packet will receive a NAK to request a retry later. This should only be done for short durations or the host may timeout the transaction.

Reception

The host will send OUT or SETUP transactions when it wants to transfer data to the device. The data packets are directed to a particular endpoint, and the maximum packet size is set per-endpoint in its Endpoint Descriptor (this must be the same or smaller than the maximum packet size supported by the device). A received interrupt is raised whenever there is one or more packets in the RX FIFO. The driver should pop the information from the FIFO by reading the rxfifo register, which gives (a) the buffer ID that the data was received in (b) the data length, in bytes, received (c) the endpoint to which the packet was sent (d) an indication if the packet was sent with an OUT or STATUS transaction. Note that the data length could be between 0 and the maximum packet size – in some situations a zero length packet is used as an acknowledgement or end of transmission.

The data length does not include the packet CRC. (The CRC bytes are written to the buffer if they fit within the maximum buffer size.) Packets with a bad CRC will not be transferred to the RX FIFO, the hardware will request a retry.

Transmission

Data is transferred to the host based on the host requesting a transfer with an IN transaction. The host will only generate IN requests if the endpoint is declared as an IN endpoint in its Endpoint Descriptor (note that two descriptors are needed if the same endpoint is used for both IN and OUT transfers). The Endpoint Descriptor also includes a description of the frequency the endpoint should be polled.

Data is queued for transmission by writing the corresponding configin register with the buffer ID containing the data, the length in bytes of data (0 to maximum packet length) and setting the Rdy bit. This data (with the packet CRC) will be sent as a response to the next IN transaction on the endpoint. When the host ACKs the data the Rdy bit is cleared, the bit corresponding to the endpoint is set in the in_sent register and a transmit interrupt is raised. If the host does not ACK the data then the packet will be retried. When the packet transmission has been noted by the driver the endpoint bit should be cleared by writing a 1 to it in the in_sent register.

Note that the configin for an endpoint is a single register, so no new data packet should be queued until the previous packet has been acknowledged. This causes a problem if a Control Transaction is received on an endpoint with a transmission pending because the Control Transaction may require an IN packet. Therefore the hardware will clear the rdy bit if an enabled SETUP transaction is received on any endpoint and set the pending bit if there was data pending. The driver must remember the pending transfer and, after the Control transaction is complete, write it back to the configin register with the rdy bit set.

Stall

The stall register is used to Stall an endpoint. This is used if it is shutdown for some reason, or to signal certain error conditions (functional stall). Control endpoints also use a STALL to indicate unsupported requests (protocol stall). This register is used in both cases. Unused endpoints can have their stall register bit left clear, so in many cases there is no need to use the stall register. If the stall bit is set for an endpoint then the STALL response will be provided to all IN or OUT requests on that endpoint.

In the case of a protocol stall, the device must send a STALL for all IN and OUT requests until the next SETUP token is received. To support this, the software sets the STALL bit for an endpoint when an unsupported transfer is requested. The hardware will then send a STALL response to all IN/OUT transactions until the next SETUP is received for this endpoint. Receiving the SETUP token then clears the STALL flag for the endpoint. The hardware then sends NAKs to any IN/OUT requets until the software has decided what action to take for the new SETUP request.

Register Table

usbdev.INTR_STATE @ + 0x0
Interrupt State Register
Reset default = 0x0, mask 0xffff
31302928272625242322212019181716
 
1514131211109876543210
connected frame rx_bitstuff_err rx_pid_err rx_crc_err link_in_err av_overflow rx_full av_empty link_resume link_suspend link_reset host_lost disconnected pkt_sent pkt_received
BitsTypeResetNameDescription
0rw1c0x0pkt_receivedraised if a packet was received using an OUT or SETUP transaction.
1rw1c0x0pkt_sentraised if a packet was sent as part of an IN transaction.
2rw1c0x0disconnectedRaised if VBUS is lost thus the link is disconnected
3rw1c0x0host_lostRaised if link is active but start of frame not received from host for 4.096ms. The SOF should be every 1ms.
4rw1c0x0link_resetRaised if the link is at SE0 longer than 3us indicating a link reset (host asserts for min 10ms, device can react after 2.5us).
5rw1c0x0link_suspendRaised if the line has signalled J for longer than 3ms and is therefore in suspend state.
6rw1c0x0link_resumeRaised when the link becomes active again after being suspended.
7rw1c0x0av_emptyRaised when a transaction is NACKed because the AVBuffer FIFO for OUT or SETUP transactions is empty.
8rw1c0x0rx_fullRaised when a transaction is NACKed because the Receive FIFO for OUT or SETUP transactions is full.
9rw1c0x0av_overflowRaised if a write was done to the AVBuffer fifo when the FIFO was full.
10rw1c0x0link_in_errRaised if a packet to an IN endpoint started to be received but was then dropped due to an error. After transmitting the IN payload, the USB device expects a valid ACK handshake packet. This error is raised if either the packet or CRC is invalid or a different token was received.
11rw1c0x0rx_crc_errRaised if a CRC error occured.
12rw1c0x0rx_pid_errRaised if an invalid PID was received.
13rw1c0x0rx_bitstuff_errRaised if an invalid bitstuffing was received.
14rw1c0x0frameRaised when the USB frame number is updated with a valid SOF frame.
15rw1c0x0connectedRaised if VBUS is applied.


usbdev.INTR_ENABLE @ + 0x4
Interrupt Enable Register
Reset default = 0x0, mask 0xffff
31302928272625242322212019181716
 
1514131211109876543210
connected frame rx_bitstuff_err rx_pid_err rx_crc_err link_in_err av_overflow rx_full av_empty link_resume link_suspend link_reset host_lost disconnected pkt_sent pkt_received
BitsTypeResetNameDescription
0rw0x0pkt_receivedEnable interrupt when INTR_STATE.pkt_received is set
1rw0x0pkt_sentEnable interrupt when INTR_STATE.pkt_sent is set
2rw0x0disconnectedEnable interrupt when INTR_STATE.disconnected is set
3rw0x0host_lostEnable interrupt when INTR_STATE.host_lost is set
4rw0x0link_resetEnable interrupt when INTR_STATE.link_reset is set
5rw0x0link_suspendEnable interrupt when INTR_STATE.link_suspend is set
6rw0x0link_resumeEnable interrupt when INTR_STATE.link_resume is set
7rw0x0av_emptyEnable interrupt when INTR_STATE.av_empty is set
8rw0x0rx_fullEnable interrupt when INTR_STATE.rx_full is set
9rw0x0av_overflowEnable interrupt when INTR_STATE.av_overflow is set
10rw0x0link_in_errEnable interrupt when INTR_STATE.link_in_err is set
11rw0x0rx_crc_errEnable interrupt when INTR_STATE.rx_crc_err is set
12rw0x0rx_pid_errEnable interrupt when INTR_STATE.rx_pid_err is set
13rw0x0rx_bitstuff_errEnable interrupt when INTR_STATE.rx_bitstuff_err is set
14rw0x0frameEnable interrupt when INTR_STATE.frame is set
15rw0x0connectedEnable interrupt when INTR_STATE.connected is set


usbdev.INTR_TEST @ + 0x8
Interrupt Test Register
Reset default = 0x0, mask 0xffff
31302928272625242322212019181716
 
1514131211109876543210
connected frame rx_bitstuff_err rx_pid_err rx_crc_err link_in_err av_overflow rx_full av_empty link_resume link_suspend link_reset host_lost disconnected pkt_sent pkt_received
BitsTypeResetNameDescription
0wo0x0pkt_receivedWrite 1 to force INTR_STATE.pkt_received to 1
1wo0x0pkt_sentWrite 1 to force INTR_STATE.pkt_sent to 1
2wo0x0disconnectedWrite 1 to force INTR_STATE.disconnected to 1
3wo0x0host_lostWrite 1 to force INTR_STATE.host_lost to 1
4wo0x0link_resetWrite 1 to force INTR_STATE.link_reset to 1
5wo0x0link_suspendWrite 1 to force INTR_STATE.link_suspend to 1
6wo0x0link_resumeWrite 1 to force INTR_STATE.link_resume to 1
7wo0x0av_emptyWrite 1 to force INTR_STATE.av_empty to 1
8wo0x0rx_fullWrite 1 to force INTR_STATE.rx_full to 1
9wo0x0av_overflowWrite 1 to force INTR_STATE.av_overflow to 1
10wo0x0link_in_errWrite 1 to force INTR_STATE.link_in_err to 1
11wo0x0rx_crc_errWrite 1 to force INTR_STATE.rx_crc_err to 1
12wo0x0rx_pid_errWrite 1 to force INTR_STATE.rx_pid_err to 1
13wo0x0rx_bitstuff_errWrite 1 to force INTR_STATE.rx_bitstuff_err to 1
14wo0x0frameWrite 1 to force INTR_STATE.frame to 1
15wo0x0connectedWrite 1 to force INTR_STATE.connected to 1


usbdev.usbctrl @ + 0xc
USB Control
Reset default = 0x0, mask 0x7f0001
31302928272625242322212019181716
  device_address
1514131211109876543210
  enable
BitsTypeResetNameDescription
0rw0x0enableSet to enable the USB interface and assert the FS pullup.
15:1Reserved
22:16rw0x0device_addressDevice address set by host (this should be copied from the Set Device ID SETUP packet). This will be zeroed by the hardware when the link resets.


usbdev.usbstat @ + 0x10
USB Status
Reset default = 0x80000000, mask 0x8787ffff
31302928272625242322212019181716
rx_empty   rx_depth av_full   av_depth
1514131211109876543210
sense link_state host_lost frame
BitsTypeResetNameDescription
10:0ro0x0frameFrame index received from host. On an active link this will increment every milisecond.
11ro0x0host_lostStart of frame not received from host for 4.096ms and the line is active.
14:12ro0x0link_stateState of USB link, decoded from line.
0disconnectLink disconnected (no VBUS)
1poweredLink powered, but not reset yet
2powered_suspendLink suspended (constant idle for > 3ms), but not reset yet
3activeLink active
4suspendLink suspended (constant idle for > 3ms)
Other values are reserved.
15ro0x0senseRefelects the state of the sense pin. 1 indicates that the host is providing VBUS.
18:16ro0x0av_depthNumber of buffers in the Available-Buffer FIFO. These buffers are available for receiving packets.
22:19Reserved
23ro0x0av_fullAvailable buffers FIFO is full
26:24ro0x0rx_depthNumber of buffers in the Receive FIFO. These buffers have packets that have been received and should be popped from the FIFO and processed.
30:27Reserved
31ro0x1rx_emptyReceive FIFO is empty


usbdev.avbuffer @ + 0x14
Available Buffer FIFO
Reset default = 0x0, mask 0x0
31302928272625242322212019181716
 
1514131211109876543210
  buffer
BitsTypeResetNameDescription
4:0woxbufferThis field contains the buffer number being passed to the USB receive engine. If the FIFO is full then the write is discarded.


usbdev.rxfifo @ + 0x18
Received packet FIFO
Reset default = 0x0, mask 0xf87f1f
31302928272625242322212019181716
  ep setup  
1514131211109876543210
  size   buffer
BitsTypeResetNameDescription
4:0ro0x0bufferThis field contains the buffer number that data was received into. On read the buffer is popped from the FIFO and returned to software.
7:5Reserved
14:8ro0x0sizeThis field contains the size in bytes of the packet written to the buffer.
18:15Reserved
19ro0x0setupThis field indicates the type of transaction received. It is set for a SETUP transaction and clear for an OUT transaction.
23:20ro0x0epThis field contains the Endpoint to which the packet was directed.


usbdev.rxenable_setup @ + 0x1c
Receive SETUP transaction enable
Reset default = 0x0, mask 0xfff
31302928272625242322212019181716
 
1514131211109876543210
  setup11 setup10 setup9 setup8 setup7 setup6 setup5 setup4 setup3 setup2 setup1 setup0
BitsTypeResetNameDescription
0rw0x0setup0This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP request will be responded to with a NACK. for Endpoint0
11:1for Endpoint1..Endpoint11


usbdev.rxenable_out @ + 0x20
Receive OUT transaction enable
Reset default = 0x0, mask 0xfff
31302928272625242322212019181716
 
1514131211109876543210
  out11 out10 out9 out8 out7 out6 out5 out4 out3 out2 out1 out0
BitsTypeResetNameDescription
0rw0x0out0This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NACK. for Endpoint0
11:1for Endpoint1..Endpoint11


usbdev.in_sent @ + 0x24
IN Transaction Sent
Reset default = 0x0, mask 0xfff
31302928272625242322212019181716
 
1514131211109876543210
  sent11 sent10 sent9 sent8 sent7 sent6 sent5 sent4 sent3 sent2 sent1 sent0
BitsTypeResetNameDescription
0rw1c0x0sent0This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction. for Endpoint0
11:1for Endpoint1..Endpoint11


usbdev.stall @ + 0x28
Endpoint STALL control
Reset default = 0x0, mask 0xfff
31302928272625242322212019181716
 
1514131211109876543210
  stall11 stall10 stall9 stall8 stall7 stall6 stall5 stall4 stall3 stall2 stall1 stall0
BitsTypeResetNameDescription
0rw0x0stall0If this bit is set then an IN or OUT transaction to this endpoint will be responded to with a STALL return. This is used when the endpoint is disabled (functional stall) or when a control transfer is not supported (protocol stall). SETUP transactions are always accepted and a SETUP will clear the stall flag (this is necessary for protocol stalls, to avoid sending stalls on subsequent IN/OUT transfers). for Endpoint0
11:1for Endpoint1..Endpoint11


usbdev.configin0 @ + 0x2c
Configure IN Transaction
Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy0 pend0  
1514131211109876543210
  size0   buffer0
BitsTypeResetNameDescription
4:0rw0x0buffer0The buffer number containing the data to send when an IN transaction is received on the Endpoint. for Endpoint0
7:5Reserved
14:8rw0x0size0The number of bytes to send from the buffer. If this is 0 then a CRC only packet is sent. If this is greater than 64 then 64 bytes are sent. for Endpoint0
29:15Reserved
30rw1c0x0pend0This bit indicates a pending transaction was canceled by the hardware. The bit is set when the rdy bit is cleared by hardware because of a SETUP packet being received or a link reset being detected. The bit remains set until cleared by being written with a 1. for Endpoint0
31rw0x0rdy0This bit should be set to indicate the buffer is ready for sending. It will be cleared when the ACK is received indicating the host has accepted the data. This bit will also be cleared if an enabled SETUP transaction is received on the Endpoint. This allows use of the IN channel for transfer of SETUP information. The original buffer must be resubmitted after the SETUP sequence is complete. A link reset also clears the bit. In either of the cases where the hardware cancels the transaction it will also set the pend bit. for Endpoint0


usbdev.configin1 @ + 0x30
Configure IN Transaction
Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy1 pend1  
1514131211109876543210
  size1   buffer1
BitsTypeResetNameDescription
4:0rw0x0buffer1The buffer number containing the data to send when an IN transaction is received on the Endpoint. for Endpoint1
7:5Reserved
14:8rw0x0size1The number of bytes to send from the buffer. If this is 0 then a CRC only packet is sent. If this is greater than 64 then 64 bytes are sent. for Endpoint1
29:15Reserved
30rw1c0x0pend1This bit indicates a pending transaction was canceled by the hardware. The bit is set when the rdy bit is cleared by hardware because of a SETUP packet being received or a link reset being detected. The bit remains set until cleared by being written with a 1. for Endpoint1
31rw0x0rdy1This bit should be set to indicate the buffer is ready for sending. It will be cleared when the ACK is received indicating the host has accepted the data. This bit will also be cleared if an enabled SETUP transaction is received on the Endpoint. This allows use of the IN channel for transfer of SETUP information. The original buffer must be resubmitted after the SETUP sequence is complete. A link reset also clears the bit. In either of the cases where the hardware cancels the transaction it will also set the pend bit. for Endpoint1


usbdev.configin2 @ + 0x34
Configure IN Transaction
Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy2 pend2  
1514131211109876543210
  size2   buffer2
BitsTypeResetNameDescription
4:0rw0x0buffer2The buffer number containing the data to send when an IN transaction is received on the Endpoint. for Endpoint2
7:5Reserved
14:8rw0x0size2The number of bytes to send from the buffer. If this is 0 then a CRC only packet is sent. If this is greater than 64 then 64 bytes are sent. for Endpoint2
29:15Reserved
30rw1c0x0pend2This bit indicates a pending transaction was canceled by the hardware. The bit is set when the rdy bit is cleared by hardware because of a SETUP packet being received or a link reset being detected. The bit remains set until cleared by being written with a 1. for Endpoint2
31rw0x0rdy2This bit should be set to indicate the buffer is ready for sending. It will be cleared when the ACK is received indicating the host has accepted the data. This bit will also be cleared if an enabled SETUP transaction is received on the Endpoint. This allows use of the IN channel for transfer of SETUP information. The original buffer must be resubmitted after the SETUP sequence is complete. A link reset also clears the bit. In either of the cases where the hardware cancels the transaction it will also set the pend bit. for Endpoint2


usbdev.configin3 @ + 0x38
Configure IN Transaction
Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy3 pend3  
1514131211109876543210
  size3   buffer3
BitsTypeResetNameDescription
4:0rw0x0buffer3The buffer number containing the data to send when an IN transaction is received on the Endpoint. for Endpoint3
7:5Reserved
14:8rw0x0size3The number of bytes to send from the buffer. If this is 0 then a CRC only packet is sent. If this is greater than 64 then 64 bytes are sent. for Endpoint3
29:15Reserved
30rw1c0x0pend3This bit indicates a pending transaction was canceled by the hardware. The bit is set when the rdy bit is cleared by hardware because of a SETUP packet being received or a link reset being detected. The bit remains set until cleared by being written with a 1. for Endpoint3
31rw0x0rdy3This bit should be set to indicate the buffer is ready for sending. It will be cleared when the ACK is received indicating the host has accepted the data. This bit will also be cleared if an enabled SETUP transaction is received on the Endpoint. This allows use of the IN channel for transfer of SETUP information. The original buffer must be resubmitted after the SETUP sequence is complete. A link reset also clears the bit. In either of the cases where the hardware cancels the transaction it will also set the pend bit. for Endpoint3


usbdev.configin4 @ + 0x3c
Configure IN Transaction
Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy4 pend4  
1514131211109876543210
  size4   buffer4
BitsTypeResetNameDescription
4:0rw0x0buffer4The buffer number containing the data to send when an IN transaction is received on the Endpoint. for Endpoint4
7:5Reserved
14:8rw0x0size4The number of bytes to send from the buffer. If this is 0 then a CRC only packet is sent. If this is greater than 64 then 64 bytes are sent. for Endpoint4
29:15Reserved
30rw1c0x0pend4This bit indicates a pending transaction was canceled by the hardware. The bit is set when the rdy bit is cleared by hardware because of a SETUP packet being received or a link reset being detected. The bit remains set until cleared by being written with a 1. for Endpoint4
31rw0x0rdy4This bit should be set to indicate the buffer is ready for sending. It will be cleared when the ACK is received indicating the host has accepted the data. This bit will also be cleared if an enabled SETUP transaction is received on the Endpoint. This allows use of the IN channel for transfer of SETUP information. The original buffer must be resubmitted after the SETUP sequence is complete. A link reset also clears the bit. In either of the cases where the hardware cancels the transaction it will also set the pend bit. for Endpoint4


usbdev.configin5 @ + 0x40
Configure IN Transaction
Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy5 pend5  
1514131211109876543210
  size5   buffer5
BitsTypeResetNameDescription
4:0rw0x0buffer5The buffer number containing the data to send when an IN transaction is received on the Endpoint. for Endpoint5
7:5Reserved
14:8rw0x0size5The number of bytes to send from the buffer. If this is 0 then a CRC only packet is sent. If this is greater than 64 then 64 bytes are sent. for Endpoint5
29:15Reserved
30rw1c0x0pend5This bit indicates a pending transaction was canceled by the hardware. The bit is set when the rdy bit is cleared by hardware because of a SETUP packet being received or a link reset being detected. The bit remains set until cleared by being written with a 1. for Endpoint5
31rw0x0rdy5This bit should be set to indicate the buffer is ready for sending. It will be cleared when the ACK is received indicating the host has accepted the data. This bit will also be cleared if an enabled SETUP transaction is received on the Endpoint. This allows use of the IN channel for transfer of SETUP information. The original buffer must be resubmitted after the SETUP sequence is complete. A link reset also clears the bit. In either of the cases where the hardware cancels the transaction it will also set the pend bit. for Endpoint5


usbdev.configin6 @ + 0x44
Configure IN Transaction
Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy6 pend6  
1514131211109876543210
  size6   buffer6
BitsTypeResetNameDescription
4:0rw0x0buffer6The buffer number containing the data to send when an IN transaction is received on the Endpoint. for Endpoint6
7:5Reserved
14:8rw0x0size6The number of bytes to send from the buffer. If this is 0 then a CRC only packet is sent. If this is greater than 64 then 64 bytes are sent. for Endpoint6
29:15Reserved
30rw1c0x0pend6This bit indicates a pending transaction was canceled by the hardware. The bit is set when the rdy bit is cleared by hardware because of a SETUP packet being received or a link reset being detected. The bit remains set until cleared by being written with a 1. for Endpoint6
31rw0x0rdy6This bit should be set to indicate the buffer is ready for sending. It will be cleared when the ACK is received indicating the host has accepted the data. This bit will also be cleared if an enabled SETUP transaction is received on the Endpoint. This allows use of the IN channel for transfer of SETUP information. The original buffer must be resubmitted after the SETUP sequence is complete. A link reset also clears the bit. In either of the cases where the hardware cancels the transaction it will also set the pend bit. for Endpoint6


usbdev.configin7 @ + 0x48
Configure IN Transaction
Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy7 pend7  
1514131211109876543210
  size7   buffer7
BitsTypeResetNameDescription
4:0rw0x0buffer7The buffer number containing the data to send when an IN transaction is received on the Endpoint. for Endpoint7
7:5Reserved
14:8rw0x0size7The number of bytes to send from the buffer. If this is 0 then a CRC only packet is sent. If this is greater than 64 then 64 bytes are sent. for Endpoint7
29:15Reserved
30rw1c0x0pend7This bit indicates a pending transaction was canceled by the hardware. The bit is set when the rdy bit is cleared by hardware because of a SETUP packet being received or a link reset being detected. The bit remains set until cleared by being written with a 1. for Endpoint7
31rw0x0rdy7This bit should be set to indicate the buffer is ready for sending. It will be cleared when the ACK is received indicating the host has accepted the data. This bit will also be cleared if an enabled SETUP transaction is received on the Endpoint. This allows use of the IN channel for transfer of SETUP information. The original buffer must be resubmitted after the SETUP sequence is complete. A link reset also clears the bit. In either of the cases where the hardware cancels the transaction it will also set the pend bit. for Endpoint7


usbdev.configin8 @ + 0x4c
Configure IN Transaction
Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy8 pend8  
1514131211109876543210
  size8   buffer8
BitsTypeResetNameDescription
4:0rw0x0buffer8The buffer number containing the data to send when an IN transaction is received on the Endpoint. for Endpoint8
7:5Reserved
14:8rw0x0size8The number of bytes to send from the buffer. If this is 0 then a CRC only packet is sent. If this is greater than 64 then 64 bytes are sent. for Endpoint8
29:15Reserved
30rw1c0x0pend8This bit indicates a pending transaction was canceled by the hardware. The bit is set when the rdy bit is cleared by hardware because of a SETUP packet being received or a link reset being detected. The bit remains set until cleared by being written with a 1. for Endpoint8
31rw0x0rdy8This bit should be set to indicate the buffer is ready for sending. It will be cleared when the ACK is received indicating the host has accepted the data. This bit will also be cleared if an enabled SETUP transaction is received on the Endpoint. This allows use of the IN channel for transfer of SETUP information. The original buffer must be resubmitted after the SETUP sequence is complete. A link reset also clears the bit. In either of the cases where the hardware cancels the transaction it will also set the pend bit. for Endpoint8


usbdev.configin9 @ + 0x50
Configure IN Transaction
Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy9 pend9  
1514131211109876543210
  size9   buffer9
BitsTypeResetNameDescription
4:0rw0x0buffer9The buffer number containing the data to send when an IN transaction is received on the Endpoint. for Endpoint9
7:5Reserved
14:8rw0x0size9The number of bytes to send from the buffer. If this is 0 then a CRC only packet is sent. If this is greater than 64 then 64 bytes are sent. for Endpoint9
29:15Reserved
30rw1c0x0pend9This bit indicates a pending transaction was canceled by the hardware. The bit is set when the rdy bit is cleared by hardware because of a SETUP packet being received or a link reset being detected. The bit remains set until cleared by being written with a 1. for Endpoint9
31rw0x0rdy9This bit should be set to indicate the buffer is ready for sending. It will be cleared when the ACK is received indicating the host has accepted the data. This bit will also be cleared if an enabled SETUP transaction is received on the Endpoint. This allows use of the IN channel for transfer of SETUP information. The original buffer must be resubmitted after the SETUP sequence is complete. A link reset also clears the bit. In either of the cases where the hardware cancels the transaction it will also set the pend bit. for Endpoint9


usbdev.configin10 @ + 0x54
Configure IN Transaction
Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy10 pend10  
1514131211109876543210
  size10   buffer10
BitsTypeResetNameDescription
4:0rw0x0buffer10The buffer number containing the data to send when an IN transaction is received on the Endpoint. for Endpoint10
7:5Reserved
14:8rw0x0size10The number of bytes to send from the buffer. If this is 0 then a CRC only packet is sent. If this is greater than 64 then 64 bytes are sent. for Endpoint10
29:15Reserved
30rw1c0x0pend10This bit indicates a pending transaction was canceled by the hardware. The bit is set when the rdy bit is cleared by hardware because of a SETUP packet being received or a link reset being detected. The bit remains set until cleared by being written with a 1. for Endpoint10
31rw0x0rdy10This bit should be set to indicate the buffer is ready for sending. It will be cleared when the ACK is received indicating the host has accepted the data. This bit will also be cleared if an enabled SETUP transaction is received on the Endpoint. This allows use of the IN channel for transfer of SETUP information. The original buffer must be resubmitted after the SETUP sequence is complete. A link reset also clears the bit. In either of the cases where the hardware cancels the transaction it will also set the pend bit. for Endpoint10


usbdev.configin11 @ + 0x58
Configure IN Transaction
Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy11 pend11  
1514131211109876543210
  size11   buffer11
BitsTypeResetNameDescription
4:0rw0x0buffer11The buffer number containing the data to send when an IN transaction is received on the Endpoint. for Endpoint11
7:5Reserved
14:8rw0x0size11The number of bytes to send from the buffer. If this is 0 then a CRC only packet is sent. If this is greater than 64 then 64 bytes are sent. for Endpoint11
29:15Reserved
30rw1c0x0pend11This bit indicates a pending transaction was canceled by the hardware. The bit is set when the rdy bit is cleared by hardware because of a SETUP packet being received or a link reset being detected. The bit remains set until cleared by being written with a 1. for Endpoint11
31rw0x0rdy11This bit should be set to indicate the buffer is ready for sending. It will be cleared when the ACK is received indicating the host has accepted the data. This bit will also be cleared if an enabled SETUP transaction is received on the Endpoint. This allows use of the IN channel for transfer of SETUP information. The original buffer must be resubmitted after the SETUP sequence is complete. A link reset also clears the bit. In either of the cases where the hardware cancels the transaction it will also set the pend bit. for Endpoint11


usbdev.iso @ + 0x5c
Endpoint ISO setting
Reset default = 0x0, mask 0xfff
31302928272625242322212019181716
 
1514131211109876543210
  iso11 iso10 iso9 iso8 iso7 iso6 iso5 iso4 iso3 iso2 iso1 iso0
BitsTypeResetNameDescription
0rw0x0iso0If this bit is set then the endpoint will be treated as an ISO endpoint. No handshake packet will be sent for an OUT transaction and no handshake packet will be expected for an IN transaction. for Endpoint0
11:1for Endpoint1..Endpoint11


usbdev.data_toggle_clear @ + 0x60
Clear the data toggle flag
Reset default = 0x0, mask 0x0
31302928272625242322212019181716
 
1514131211109876543210
  clear11 clear10 clear9 clear8 clear7 clear6 clear5 clear4 clear3 clear2 clear1 clear0
BitsTypeResetNameDescription
0woxclear0Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns. for Endpoint0
11:1for Endpoint1..Endpoint11


usbdev.phy_config @ + 0x64
USB PHY Configuration
Reset default = 0x4, mask 0x1f
31302928272625242322212019181716
 
1514131211109876543210
  override_pwr_sense_val override_pwr_sense_en eop_single_bit tx_differential_mode rx_differential_mode
BitsTypeResetNameDescription
0rw0x0rx_differential_modeUse the differential RX signal instead of the single ended signals. Currently only 0 (single-ended operation) is supported.
1rw0x0tx_differential_modeUse the differential TX signal instead of the single ended signals. Currently only 0 (single-ended operation) is supported.
2rw0x1eop_single_bitRecognize a single SE0 bit as an end of packet, otherwise two successive bits are required.
3rw0x0override_pwr_sense_enOverride the USB Power sense value with override_pwr_sense_val.
4rw0x0override_pwr_sense_val0: USB power not present, 1: present.


usbdev.buffer @ + 0x800
512 item rw window
Byte writes are not supported
310
+0x800 
+0x804 
 ...
+0xff8 
+0xffc 
2kB packet buffer. Divided into 32 64-byte packets. The packet buffer is used for sending and receiveing packets.