# Overview

This document specifies the USB device hardware IP functionality. This IP block implements a Full-Speed device according to the USB 2.0 specification. It is attached to the chip interconnect bus as a peripheral module and conforms to the Comportable guideline for peripheral functionality.

## Features

The IP block implements the following features:

• USB 2.0 Full-Speed (12 Mbps) Device interface
• 2 kB interface buffer
• Up to 12 endpoints (including required Endpoint 0), configurable using a compile-time Verilog parameter
• Support for USB packet sizes up to 64 bytes
• Support SETUP, IN and OUT transactions
• Support for Bulk, Control, Interrupt and Isochronous endpoints and transactions
• Streaming possible through software
• Interrupts for packet reception and transmission
• Flippable D+/D- pins, configurable via software, useful if it helps routing the PCB or if D+/D- are mapped to SBU1/SBU2 pins of USB-C

Isochronous transfers larger than 64 bytes are currently not supported. This feature might be added in a later version of this IP.

## Description

The USB device module is a simple software-driven generic USB device interface for Full-Speed USB 2.0 operation. The IP includes the physical layer interface, the low level USB protocol and a packet buffer interface to the software. The physical layer interface features multiple transmit and receive paths to allow interfacing with a variety of USB PHYs or regular 3.3V IO pads for FPGA prototyping.

## Compatibility

The USB device programming interface is not based on any existing interface.

# Theory of Operations

A useful quick reference for USB Full-Speed is USB Made Simple, Part 3 - Data Flow.

The block diagram shows a high level view of the USB device including the main register access paths.

## Clocking

The USB Full-Speed interface runs at a data rate of 12 MHz. The interface runs at four times this frequency and must be clocked from an accurate 48 MHz clock source. The USB specification for a Full-Speed device requires the average bit rate is 12 Mbps +/- 0.25%, so the clock needs to support maximum error of 2,500 ppm. The maximum allowable integrated jitter is +/- 1 ns over 1 to 7 bit periods.

This module features the following output signals to provide a reference for synchronizing the 48 MHz clock source:

• usb_ref_pulse_o indicates the reception of a start of frame (SOF) packet. The host is required to send a SOF packet every 1 ms.
• usb_ref_val_o serves as a valid signal for usb_ref_pulse_o. It is set to one after the first SOF packet is received and remains high as long as usb_ref_pulse_o continues to behave as expected. As soon as it is detected that SOF will not be received as expected (usually because the link is no longer active), usb_ref_val_o deasserts to zero until after the next usb_ref_pulse_o.

Both these signals are synchronous to the 48 MHz clock. They can be forced to zero by setting phy_config.usb_ref_disable to 1.

To successfully receive SOF packets without errors and thereby enabling clock synchronization, the initial accuracy of the 48 MHz clock source should be within 3.2% or 32,000 ppm. This requirement comes from the fact that the SOF packet has a length of 24 bits (plus 8-bit sync field). The first 8 bits are used to transfer the SOF packet ID (8’b01011010). Internally, the USB device dynamically adjusts the sampling point based on observed line transitions. Assuming the last bit of the SOF packet ID is sampled in the middle of the eye, the drift over the remaining 16 bits of the packet must be lower than half a bit (10^6 * (0.5/16) = 32,000 ppm).

To externally monitor the 48 MHz clock, the USB device supports an oscillator test mode which can be enabled by setting phy_config.tx_osc_test_mode to 1. In this mode, the device constantly transmits a J/K pattern but no longer receives SOF packets. Consequently, it does not generate reference pulses for clock synchronization. The clock might drift off.

Control transfers pass through synchronous FIFOs or have a ready bit synchronized across the clock domain boundary. A dual-port synchronous buffer SRAM is used for data transfers, and the bus clock and USB clock come from the same 48 MHz input. The wake detection module is clocked by a separate clock, and a couple registers are used to interface with it. Any bus-related clock domain crossings must happen outside the core, except for the transition between the 48 MHz clock and the wake detection module’s clock. The 48 MHz clock must be enabled to reach the registers in usbdev.

## USB Interface Pins

Full-Speed USB uses a bidirectional serial interface as shown in Figure 7-24 of the USB 2.0 Full-Speed specification. For reasons of flexibility, this IP block features multiple transmit and receive paths for interfacing with various transceivers.

The following sections describe how the various input/output signals relate to the USB interface pins for the different receive and transmit configurations.

### Data Transmit

The IP block supports two different encodings, driving out on separate TX interfaces. The default encoding looks like the USB bus, with D+ and D- values driven on usb_dp_o and usb_dn_o pins. The alternate encoding uses usb_se0_o to indicate a single-ended zero (SE0), and usb_d_o encodes K/J (when usb_se0_o is low). The TX mode can be selected by setting the use_tx_d_se0 bit in phy_config to either 1 (alternate, using d/se0) or 0 (default, using dp/dn).

The following table summarizes how the different output signals relate to the USB interface pins.

External Pins Internal Signals Notes
D+, D- dp_o, dn_o Data output with an encoding like the USB bus, intended to go directly to pads for supported targets. On an FPGA, the components should be used with a USB transceiver, as the regular bidirectional I/O cells will likely not be USB compliant.
[Alt TX Data] se0_o Signal Single-Ended Zero (SE0) link state to a USB transceiver.
[Alt TX Data] d_o Data output used for encoding K and J, for interfacing with a USB transceiver.
[TX Mode] tx_use_d_se0_o Indicates the selected TX interface: use dp_o and dn_o (0) or use d_o and se0_o (1).

Note that according to the Comportable guideline for peripheral functionality, every output signal name_o has a dedicated output enable name_en_o. For TX data, these separate signals dp_en_o and dn_en_o all correspond to the same TX or output enable signal (OE in the USB spec). The other signals listed are of the “intersignal” variety, and they do not go directly to pads or have dedicated output enable signals.

The IP block supports recovery of the differential K and J symbols from the output of an external differential receiver or directly from the D+/D- pair. The RX mode can be selected to use a differential receiver’s output by setting the use_diff_rcvr bit in phy_config. The D+/D- pair is always used to detect the single-ended zero (SE0) state.

The following table summarizes how the different input signals relate to the USB interface pins.

External Pins Internal Signals Notes
D+, D- dp_i, dn_i D+ and D- signals passing into the IP single-ended, intended to go directly to pads for supported targets. These signals are used to detect the SE0 link state, and if a differential receiver is not present, they are also used for K and J symbols. On an FPGA, the components should be used with a USB transceiver, as the bidirectional regular IO cells will likely not be USB compliant.
[Diff Rcvr Out] d_i Data input for interfacing with a differential receiver, which is required for this input.

### Non-Data Pins

The USB device features the following non-data pins.

External Pins Internal Signals Notes
sense (VBUS) sense_i The sense pin indicates the presence of VBUS from the USB host.
[pullup] dp_pullup_o, dn_pullup_o When dp_pullup_o or dn_pullup_o asserts a 1.5k pullup resistor should be connected to D+ or D-, respectively. This can be done inside the chip or with an external pin. A permanently connected resistor could be used if the pin flip feature is not needed, but this is not recommended because there is then no way to force the device to appear to unplug. Only one of the pullup signals can be asserted at any time. The selection is based on the pinflip bit in phy_config. Because this is a Full-Speed device the resistor must be on the D+ pin, so when pinflip is zero, dp_pullup_o is used.
[suspend] suspend_o The suspend pin indicates to the USB transceiver that a constant idle has been detected on the link and the device is in the Suspend state (see Section 7.1.7.6 of the USB 2.0 specification).
[rx_enable] rx_enable_o The rx_enable pin turns on/off a differential receiver. It is enabled via a CSR and automatically disabled when the device suspends.

The USB host will identify itself to the device by enabling the 5V VBUS power. It may do a hard reset of a port by removing and reasserting VBUS (the Linux driver will do this when it finds a port in an inconsistent state or a port that generates errors during enumeration). The IP block detects VBUS through the sense pin. This pin is always an input and should be externally connected to detect the state of the VBUS. Note that this may require a resistor divider or (for USB-C where VBUS can be up to 20V) active level translation to an acceptable voltage for the input pin.

A Full-Speed device identifies itself by providing a 1.5k pullup resistor (to 3.3V) on the D+ line. The IP block produces a signal dp_pullup_o that is asserted when this resistor should be presented. This signal will be asserted whenever the interface is enabled and VBUS is present. In an FPGA implementation, this signal can drive a 3.3V output pin that is driven high when the signal is asserted and set high impedance when the signal is deasserted, and the output pin used to drive a 1.5k resistor connected on the board to the D+ line. Alternatively, it can be used to enable an internal 1.5k pullup on the D+ pin.

This USB device supports the flipping of D+/D-. If the pinflip bit in phy_config is set, the data pins are flipped internally, meaning the 1.5k pullup resistor needs to be on the external D- line. To control the pullup on the D- line, this USB device features dn_pullup_o signal. Of the two pullup signals dp_pullup_o and dn_pullup_o, only one can be enabled at any time. As this is a Full-Speed device, dp_pullup_o, i.e., the pullup on D+ is used by default (pinflip equals zero).

## Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module usbdev has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: clk_aon_i

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO:

Pin namedirectionDescription
senseinput

USB host VBUS sense

usb_dpinout

USB data D+

usb_dninout

USB data D-

Inter-Module Signals: Reference

Inter-Module Signals
Port Name Package::Struct Type Act Width Description
usb_rx_d logic uni rcv 1 USB RX data from an external differential receiver, if available
usb_tx_d logic uni req 1 USB transmit data value (not used if usb_tx_se0 is set)
usb_tx_se0 logic uni req 1 Force transmission of a USB single-ended zero (i.e. both D+ and D- are low) regardless of usb_tx_d
usb_tx_use_d_se0 logic uni req 1 Use the usb_tx_d and usb_tx_se0 TX interface, instead of usb_dp_o and usb_dn_o
usb_dp_pullup logic uni req 1 USB D+ pullup control
usb_dn_pullup logic uni req 1 USB D- pullup control
usb_rx_enable logic uni req 1 USB differential receiver enable
usb_ref_val logic uni req 1
usb_ref_pulse logic uni req 1
usb_aon_suspend_req logic uni req 1
usb_aon_wake_ack logic uni req 1
usb_aon_bus_reset logic uni rcv 1
usb_aon_sense_lost logic uni rcv 1
usb_aon_wake_detect_active logic uni rcv 1
ram_cfg prim_ram_2p_pkg::ram_2p_cfg uni rcv 1
tl tlul_pkg::tl req_rsp rsp 1

Interrupts:

Interrupt NameTypeDescription

Raised if a packet was received using an OUT or SETUP transaction. This interrupt is directly tied to whether the RX FIFO is empty, so it should be cleared only after handling the FIFO entry.

pkt_sentEvent

Raised if a packet was sent as part of an IN transaction. This interrupt is directly tied to whether a sent packet has not been acknowledged in the in_sent register. It should be cleared only after clearing all bits in the in_sent register.

disconnectedEvent

Raised if VBUS is lost thus the link is disconnected.

host_lostEvent

Raised if link is active but SOF was not received from host for 4.096 ms. The SOF should be every 1 ms.

Raised if the link is at SE0 longer than 3 us indicating a link reset (host asserts for min 10 ms, device can react after 2.5 us).

Raised if the line has signaled J for longer than 3ms and is therefore in suspend state.

Raised when the link becomes active again after being suspended.

av_emptyEvent

Raised when the AV FIFO is empty and the device interface is enabled. This interrupt is directly tied to the FIFO status, so the AV FIFO must be provided a free buffer before the interrupt is cleared. If the condition is not cleared, the interrupt can re-assert.

rx_fullEvent

Raised when the RX FIFO is full and the device interface is enabled. This interrupt is directly tied to the FIFO status, so the RX FIFO must have an entry removed before the interrupt is cleared. If the condition is not cleared, the interrupt can re-assert.

av_overflowEvent

Raised if a write was done to the Available Buffer FIFO when the FIFO was full.

Raised if a packet to an IN endpoint started to be received but was then dropped due to an error. After transmitting the IN payload, the USB device expects a valid ACK handshake packet. This error is raised if either the packet or CRC is invalid or a different token was received.

rx_crc_errEvent

Raised if a CRC error occured.

rx_pid_errEvent

Raised if an invalid packed identifier (PID) was received.

rx_bitstuff_errEvent

Raised if an invalid bitstuffing was received.

frameEvent

Raised when the USB frame number is updated with a valid SOF.

poweredEvent

Raised if VBUS is applied.

Raised if a packet to an OUT endpoint started to be received but was then dropped due to an error. This error is raised if either the data toggle, token, packet or CRC is invalid or if there is no buffer available in the Received Buffer FIFO.

fatal_fault

This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures:

Countermeasure IDDescription
USBDEV.BUS.INTEGRITY

End-to-end bus integrity scheme.

The USB link has a number of states. These are detected and reported in usbstat.link_state and state changes are reported using interrupts. The FSM implements a subset of the USB device state diagram shown in Figure 9-1 of the USB 2.0 specification.

State Description
Disconnected The link is disconnected. This is signaled when the VBUS is not driven by the host, which results in the sense input pin being low, or when the user has not connected the pull-up by enabling the interface. An interrupt is raised on entering this state.
Powered The device has been powered as VBUS is being driven by the host and the user has connected the pull-up, but the device has not been reset yet. The link is reset whenever the D+ and D- are both low (an SE0 condition) for an extended period. The host will assert reset for a minimum of 10 ms, but the USB specification allows the device to detect and respond to a reset after 2.5 us. The implementation here will report the reset state and raise an interrupt when the link is in SE0 for 3 us.
Powered Suspended The link is suspended when at idle (a J condition) for more than 3 ms. An interrupt is generated when the suspend is detected and a resume interrupt is generated when the link exits the suspend state. This state is entered, if the device has not been reset yet.
Active No SOF The link has been reset and can begin receiving packets, but no Start-of-Frame packets have yet been seen.
Active The link is active when it is running normally.
Suspended Similar to ‘Powered Suspended’, but the device was in the active state before being suspended.
Resuming The link is awaiting the end of resume signaling before transitioning to the Active No SOF state.
Disconnect VBUS has been lost.
Link Reset The link has been in the SE0 state for 3 us.
Link Suspend The link has been in the J state for more than 3 ms, upon which we have to enter the Suspend state.
Link Resume The link has been driven to a non-J state after being in Suspend. For the case of resuming to active link states, the end of resume signaling has occurred.
Host Lost Signaled using an interrupt if the link is active but a start of frame (SOF) packet has not been received from the host in 4 frames. The host is required to send a SOF packet every 1 ms. This is not an expected condition.

## USB Protocol Engine

The USB 2.0 Full-Speed Protocol Engine is provided by the common USB interface code and is, strictly speaking, not part of this USB device module.

At the lowest level of the USB stack the transmit bitstream is serialized, converted to non-return-to-zero inverted (NRZI) encoding with bit-stuffing and sent to the transmitter. The received bitstream is recovered, clock aligned and decoded and has bit-stuffing removed. The recovered clock alignment is used for transmission.

The higher level protocol engine forms the bitstream into packets, performs CRC checking and recognizes IN, OUT and SETUP transactions. These are presented to this module without buffering. This means the USB device module must accept or provide data when requested. The protocol engine may cancel a transaction because of a bad cyclic redundancy check (CRC) or request a retry if an acknowledgment (ACK) was not received.

## Buffer Interface

A 2 kB SRAM is used as a packet buffer to hold data between the system and the USB interface. This is divided up into 32 buffers each containing 64 bytes. This is an asynchronous dual-port SRAM with software accessing from the bus clock domain and the USB interface accessing from the USB 48 MHz clock domain.

### Reception

Software provides buffers for packet reception through a 4-entry Available Buffer FIFO. (More study needed but four seems about right: one just returned to software, one being filled, one ready to be filled, and one for luck.) The rxenable_out and rxenable_setup registers is used to indicate which endpoints will accept data from the host using OUT or SETUP transactions, respectively. When a packet is transferred from the host to the device (using an OUT or SETUP transaction) and reception of that type of transaction is enabled for the requested endpoint, the next buffer ID is pulled from the Available Buffer FIFO. The packet data is written to the corresponding buffer in the packet buffer (the 2 kB SRAM). If the packet is correctly received, an ACK is returned to the host. In addition, the buffer ID, the packet size, an out/setup flag and the endpoint ID are passed back to software using the Received Buffer FIFO and a pkt_received interrupt is raised.

Software should immediately provide a free buffer for future reception by writing the corresponding buffer ID to the Available Buffer FIFO. It can then process the packet and eventually return the received buffer to the free pool. This allows streaming on a single endpoint or across a number of endpoints. If the packets cannot be consumed at the rate they are received, software can implement selective flow control by clearing rxenable_out for a particular endpoint, which will result in a request to that endpoint being NAKed (negative acknowledgment). In the unfortunate event that the Available Buffer FIFO is empty or the Received Buffer FIFO is full, all OUT transactions are NAKed and SETUP transactions are ignored. In that event, the host will retry the transaction (up to some maximum attempts or time).

There are two options for a given OUT endpoint’s flow control, controlled by the set_nak_out register. If set_nak_out is 0 for the endpoint, it will accept packets as long as there are buffers available in the Available Buffer FIFO and space available in the Received Buffer FIFO. For timing, this option implies that software may not be able to affect the response to a given transaction, and buffer availability is the only needed factor. If set_nak_out is 1 for the endpoint, it will clear its corresponding bit in the rxenable_out register, forcing NAK responses to OUT transactions to that endpoint until software can intervene. That option uses NAK to defer the host, and this enables software to implement features that require protocol-level control at transaction boundaries, such as when implementing the functional stall.

### Transmission

To send data to the host in response to an IN transaction, software first writes the data into a free buffer. Then, it writes the buffer ID, data length and rdy flag to the configin register of the corresponding endpoint. When the host next does an IN transaction to that endpoint, the data will be sent from the buffer. On receipt of the ACK from the host, the rdy bit in the configin register will be cleared, and the bit corresponding to the endpoint ID will be set in the in_sent register causing a pkt_sent interrupt to be raised. Software can return the buffer to the free pool and write a 1 to clear the endpoint bit in the in_sent register. Note that streaming can be achieved if the next buffer has been prepared and is written to the configin register when the interrupt is received.

A Control transfer requires one or more IN transactions, either during the data stage or the status stage. Therefore, when a SETUP transaction is received for an endpoint, any buffers that are waiting to be sent out to the host from that endpoint are canceled by clearing the rdy bit in the corresponding configin register. To keep track of such canceled buffers, the pend bit in the same register is set. The transfer must be queued again after the Control transfer is completed.

Similarly, a Link Reset cancels any waiting IN transactions by clearing the rdy bit in the configin register of all endpoints. The pend bit in the configin register is set for all endpoints with a pending IN transaction.

### Buffer Count and Size

Under high load, the 32 buffers of the packet buffer (2 kB SRAM) are allocated as follows:

• 1 is being processed following reception,
• 4 are in the Available Buffer FIFO, and
• 12 (worst case) waiting transmissions in the configin registers. This leaves 15 buffers for preparation of future transmissions (which would need 12 in the worst case of one per endpoint) and the free pool.

The size of 64 bytes per buffer satisfies the maximum USB packet size for a Full-Speed interface for Control transfers (max may be 8, 16, 32 or 64 bytes), Bulk Transfers (max is 64 bytes) and Interrupt transfers (max is 64 bytes). It is small for Isochronous transfers (which have a max size of 1023 bytes). The interface will need extending for high rate isochronous use (a possible option would be to allow up to 8 or 16 64-byte buffers to be aggregated as the isochronous buffer).

# Programmers Guide

## Initialization

The basic hardware initialization is to (in any order) configure the physical interface for the implementation via the phy_config register, fill the Available Buffer FIFO, enable IN and OUT endpoints with ID 0 (this is the control endpoint that the host will use to configure the interface), enable reception of SETUP and OUT packets on OUT Endpoint 0, and enable any required interrupts. Finally, the interface is enabled by setting the enable bit in the usbctrl register. Setting this bit causes the USB device to assert the pullup on the D+ line, which is used by the host to detect the device. There is no need to configure the device ID in ( usbctrl.device_address) at this point – the line remains in reset and the hardware forces the device ID to zero.

The second stage of initialization is done under control of the host, which will use control transfers (always beginning with SETUP transactions) to Endpoint 0. Initially these will be sent to device ID 0. When a Set Address request is received, the device ID received must be stored in the usbctrl.device_address register. Note that device 0 is used for the entire control transaction setting the new device ID, so writing the new ID to the register should not be done until the ACK for the Status stage has been received (see USB 2.0 specification).

The host will then issue additional control transfers to Endpoint 0 to configure the device, now to the device’s configured address. In response to the Set Configuration request, software should set up the rest of the endpoints for that configuration, including configuring the flow control behavior for OUT endpoints via the set_nak_out register, configuring the endpoint type via the rxenable_setup register (for a control endpoint) and the out_iso and in_iso registers (for isochronous OUT and IN endpoints, respectively). Finally, software should enable the configured endpoints via the ep_out_enable and ep_in_enable registers. The status stage of the Set Configuration request should not be allowed to complete until all endpoints are set up.

## Buffers

Software needs to manage the buffers in the packet buffer (2 kB SRAM). Each buffer can hold the maximum length packet for a Full-Speed interface (64 bytes). Other than for data movement, the management is most likely done based on their buffer ID which is a small integer between zero and (SRAM size in bytes)/(max packet size in bytes).

In order to avoid unintentionally deferring transactions, there must be buffers available when the host sends data to the device (an OUT or SETUP transaction). Software needs to ensure (1) there are always buffer IDs in the Available Buffer FIFO, and (2) the Received Buffer FIFO is not full. For OUT transactions, if the Available Buffer FIFO is empty or the Received Buffer FIFO is full when data is received, a NAK will be returned to the host, requesting the packet be retried later. For SETUP transactions under the same conditions, the request will be dropped and a handshake will not be sent, indicating an error to the host and provoking a retry. These conditions cause the bus to be busy and perform no work, lowering performance for this device and potentially others on the same bus. Timely management of buffers may have a significant impact on throughput.

Keeping the Available Buffer FIFO full can be done with a simple loop, adding buffer IDs from the software-managed free pool until the FIFO is full. A simpler policy of just adding a buffer ID to the Available Buffer FIFO whenever a buffer ID is removed from the Received Buffer FIFO should work on average, but performance will be slightly worse when bursts of packets are received.

Flow control (using NAKs) may be done on a per-endpoint basis using the rxenable_out register. If this does not indicate OUT packet reception is enabled, then any OUT packet will receive a NAK to request a retry later. This should only be done for short durations or the host may timeout the transaction.

## Reception

The host will send OUT or SETUP transactions when it wants to transfer data to the device. The data packets are directed to a particular endpoint, and the maximum packet size is set per-endpoint in its Endpoint Descriptor (this must be the same or smaller than the maximum packet size supported by the device). A pkt_received interrupt is raised whenever there are one or more packets in the Received Buffer FIFO. Software should pop the information from the Received Buffer FIFO by reading the rxfifo register, which gives (1) the buffer ID that the data was received in, (2) the data length received in bytes, (3) the endpoint to which the packet was sent, and (4) an indication if the packet was sent with an OUT or SETUP transaction. Note that the data length could be between zero and the maximum packet size – in some situations a zero length packet is used as an acknowledgment or end of transfer.

The data length does not include the packet CRC. (The CRC bytes are written to the buffer if they fit within the maximum buffer size.) Packets with a bad CRC will not be transferred to the Received Buffer FIFO; the hardware will drop the transaction without a handshake, indicating an error to the host. For non-isochronous endpoints, this typically results in the host retrying the transaction.

## Transmission

Data is transferred to the host based on the host requesting a transfer with an IN transaction. The host will only generate IN requests if the endpoint is declared as an IN endpoint in its Endpoint Descriptor (note that two descriptors are needed if the same endpoint is used for both IN and OUT transfers). The Endpoint Descriptor also includes a description of the frequency the endpoint should be polled (for isochronous and interrupt endpoints).

Data is queued for transmission by writing the corresponding configin register with the buffer ID containing the data, the length in bytes of data (0 to maximum packet length) and setting the rdy bit. This data (with the packet CRC) will be sent as a response to the next IN transaction on the corresponding endpoint. When the host ACKs the data, the rdy bit is cleared, the corresponding endpoint bit is set in the in_sent register, and a pkt_sent interrupt is raised. If the host does not ACK the data, the packet will be retried. When the packet transmission has been noted by software, the corresponding endpoint bit should be cleared in the in_sent register (by writing a 1 to this very bit).

Note that the configin for an endpoint is a single register, so no new data packet should be queued until the previous packet has been ACKed. If a SETUP transaction is received on a control endpoint that has a transmission pending, the hardware will clear the rdy bit and set the pend bit in the configin register of that endpoint. Software must remember the pending transmission and, after the Control transaction is complete, write it back to the configin register with the rdy bit set.

## Stalling

The out_stall and in_stall registers are used for endpoint stalling. There is one dedicated register per endpoint. Stalling is used to signal that the host should not retry a particular transmission or to signal certain error conditions (functional stall). Control endpoints also use a STALL to indicate unsupported requests (protocol stall). Unused endpoints can have their in_stall or out_stall register left clear, so in many cases there is no need to use the register. If the stall register is set for an enabled endpoint then the STALL response will be provided to all IN or OUT requests on that endpoint.

In the case of a protocol stall, the device must send a STALL for all IN/OUT requests until the next SETUP token is received. To support this, software sets the in_stall and out_stall register for an endpoint when the host requests an unsupported transfer. The hardware will then send a STALL response to all IN/OUT transactions until the next SETUP is received for this endpoint. Receiving the SETUP token clears the in_stall and out_stall registers for that endpoint. If either a control endpoint’s set_nak_out bit is set or software has cleared the rxenable_out bit before this transfer began, the hardware will send NAKs to any IN/OUT requests until the software has decided what action to take for the new SETUP request.

## Device Interface Functions (DIFs)

To use this DIF, include the following C header:

#include "sw/device/lib/dif/dif_usbdev.h"

This header provides the following device interface functions:

## Register Table

Summary
Name Offset Length Description
usbdev.INTR_STATE 0x0 4

Interrupt State Register

usbdev.INTR_ENABLE 0x4 4

Interrupt Enable Register

usbdev.INTR_TEST 0x8 4

Interrupt Test Register

usbdev.usbctrl 0x10 4

USB Control

usbdev.ep_out_enable 0x14 4

Enable an endpoint to respond to transactions in the downstream direction. Note that as the default endpoint, endpoint 0 must be enabled in both the IN and OUT directions before enabling the USB interface to connect.

usbdev.ep_in_enable 0x18 4

Enable an endpoint to respond to transactions in the upstream direction. Note that as the default endpoint, endpoint 0 must be enabled in both the IN and OUT directions before enabling the USB interface to connect.

usbdev.usbstat 0x1c 4

USB Status

usbdev.avbuffer 0x20 4

Available Buffer FIFO

usbdev.rxfifo 0x24 4

usbdev.rxenable_setup 0x28 4

usbdev.rxenable_out 0x2c 4

usbdev.set_nak_out 0x30 4

Set NAK after OUT transactions

usbdev.in_sent 0x34 4

IN Transaction Sent

usbdev.out_stall 0x38 4

OUT Endpoint STALL control

usbdev.in_stall 0x3c 4

IN Endpoint STALL control

usbdev.configin_0 0x40 4

Configure IN Transaction

usbdev.configin_1 0x44 4

Configure IN Transaction

usbdev.configin_2 0x48 4

Configure IN Transaction

usbdev.configin_3 0x4c 4

Configure IN Transaction

usbdev.configin_4 0x50 4

Configure IN Transaction

usbdev.configin_5 0x54 4

Configure IN Transaction

usbdev.configin_6 0x58 4

Configure IN Transaction

usbdev.configin_7 0x5c 4

Configure IN Transaction

usbdev.configin_8 0x60 4

Configure IN Transaction

usbdev.configin_9 0x64 4

Configure IN Transaction

usbdev.configin_10 0x68 4

Configure IN Transaction

usbdev.configin_11 0x6c 4

Configure IN Transaction

usbdev.out_iso 0x70 4

OUT Endpoint isochronous setting

usbdev.in_iso 0x74 4

IN Endpoint isochronous setting

usbdev.data_toggle_clear 0x78 4

Clear the data toggle flag

usbdev.phy_pins_sense 0x7c 4

USB PHY pins sense. This register can be used to read out the state of the USB device inputs and outputs from software. This is designed to be used for debugging purposes or during chip testing.

usbdev.phy_pins_drive 0x80 4

USB PHY pins drive. This register can be used to control the USB device inputs and outputs from software. This is designed to be used for debugging purposes or during chip testing.

usbdev.phy_config 0x84 4

USB PHY Configuration

usbdev.wake_control 0x88 4

USB wake module control for suspend / resume

usbdev.wake_events 0x8c 4

USB wake module events and debug

usbdev.buffer 0x800 2048

2 kB packet buffer. Divided into 32 64-byte buffers.

usbdev.INTR_STATE @ 0x0

Interrupt State Register

Reset default = 0x0, mask 0x1ffff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 link_out_err 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 powered frame rx_bitstuff_err rx_pid_err rx_crc_err link_in_err av_overflow rx_full av_empty link_resume link_suspend link_reset host_lost disconnected pkt_sent pkt_received
BitsTypeResetNameDescription

Raised if a packet was received using an OUT or SETUP transaction. This interrupt is directly tied to whether the RX FIFO is empty, so it should be cleared only after handling the FIFO entry.

1rw1c0x0pkt_sent

Raised if a packet was sent as part of an IN transaction. This interrupt is directly tied to whether a sent packet has not been acknowledged in the in_sent register. It should be cleared only after clearing all bits in the in_sent register.

2rw1c0x0disconnected

Raised if VBUS is lost thus the link is disconnected.

3rw1c0x0host_lost

Raised if link is active but SOF was not received from host for 4.096 ms. The SOF should be every 1 ms.

Raised if the link is at SE0 longer than 3 us indicating a link reset (host asserts for min 10 ms, device can react after 2.5 us).

Raised if the line has signaled J for longer than 3ms and is therefore in suspend state.

Raised when the link becomes active again after being suspended.

7rw1c0x0av_empty

Raised when the AV FIFO is empty and the device interface is enabled. This interrupt is directly tied to the FIFO status, so the AV FIFO must be provided a free buffer before the interrupt is cleared. If the condition is not cleared, the interrupt can re-assert.

8rw1c0x0rx_full

Raised when the RX FIFO is full and the device interface is enabled. This interrupt is directly tied to the FIFO status, so the RX FIFO must have an entry removed before the interrupt is cleared. If the condition is not cleared, the interrupt can re-assert.

9rw1c0x0av_overflow

Raised if a write was done to the Available Buffer FIFO when the FIFO was full.

Raised if a packet to an IN endpoint started to be received but was then dropped due to an error. After transmitting the IN payload, the USB device expects a valid ACK handshake packet. This error is raised if either the packet or CRC is invalid or a different token was received.

11rw1c0x0rx_crc_err

Raised if a CRC error occured.

12rw1c0x0rx_pid_err

Raised if an invalid packed identifier (PID) was received.

13rw1c0x0rx_bitstuff_err

Raised if an invalid bitstuffing was received.

14rw1c0x0frame

Raised when the USB frame number is updated with a valid SOF.

15rw1c0x0powered

Raised if VBUS is applied.

Raised if a packet to an OUT endpoint started to be received but was then dropped due to an error. This error is raised if either the data toggle, token, packet or CRC is invalid or if there is no buffer available in the Received Buffer FIFO.

usbdev.INTR_ENABLE @ 0x4

Interrupt Enable Register

Reset default = 0x0, mask 0x1ffff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 link_out_err 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 powered frame rx_bitstuff_err rx_pid_err rx_crc_err link_in_err av_overflow rx_full av_empty link_resume link_suspend link_reset host_lost disconnected pkt_sent pkt_received
BitsTypeResetNameDescription

Enable interrupt when INTR_STATE.pkt_received is set.

1rw0x0pkt_sent

Enable interrupt when INTR_STATE.pkt_sent is set.

2rw0x0disconnected

Enable interrupt when INTR_STATE.disconnected is set.

3rw0x0host_lost

Enable interrupt when INTR_STATE.host_lost is set.

Enable interrupt when INTR_STATE.link_reset is set.

Enable interrupt when INTR_STATE.link_suspend is set.

Enable interrupt when INTR_STATE.link_resume is set.

7rw0x0av_empty

Enable interrupt when INTR_STATE.av_empty is set.

8rw0x0rx_full

Enable interrupt when INTR_STATE.rx_full is set.

9rw0x0av_overflow

Enable interrupt when INTR_STATE.av_overflow is set.

Enable interrupt when INTR_STATE.link_in_err is set.

11rw0x0rx_crc_err

Enable interrupt when INTR_STATE.rx_crc_err is set.

12rw0x0rx_pid_err

Enable interrupt when INTR_STATE.rx_pid_err is set.

13rw0x0rx_bitstuff_err

Enable interrupt when INTR_STATE.rx_bitstuff_err is set.

14rw0x0frame

Enable interrupt when INTR_STATE.frame is set.

15rw0x0powered

Enable interrupt when INTR_STATE.powered is set.

Enable interrupt when INTR_STATE.link_out_err is set.

usbdev.INTR_TEST @ 0x8

Interrupt Test Register

Reset default = 0x0, mask 0x1ffff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 link_out_err 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 powered frame rx_bitstuff_err rx_pid_err rx_crc_err link_in_err av_overflow rx_full av_empty link_resume link_suspend link_reset host_lost disconnected pkt_sent pkt_received
BitsTypeResetNameDescription

Write 1 to force INTR_STATE.pkt_received to 1.

1wo0x0pkt_sent

Write 1 to force INTR_STATE.pkt_sent to 1.

2wo0x0disconnected

Write 1 to force INTR_STATE.disconnected to 1.

3wo0x0host_lost

Write 1 to force INTR_STATE.host_lost to 1.

Write 1 to force INTR_STATE.link_reset to 1.

Write 1 to force INTR_STATE.link_suspend to 1.

Write 1 to force INTR_STATE.link_resume to 1.

7wo0x0av_empty

Write 1 to force INTR_STATE.av_empty to 1.

8wo0x0rx_full

Write 1 to force INTR_STATE.rx_full to 1.

9wo0x0av_overflow

Write 1 to force INTR_STATE.av_overflow to 1.

Write 1 to force INTR_STATE.link_in_err to 1.

11wo0x0rx_crc_err

Write 1 to force INTR_STATE.rx_crc_err to 1.

12wo0x0rx_pid_err

Write 1 to force INTR_STATE.rx_pid_err to 1.

13wo0x0rx_bitstuff_err

Write 1 to force INTR_STATE.rx_bitstuff_err to 1.

14wo0x0frame

Write 1 to force INTR_STATE.frame to 1.

15wo0x0powered

Write 1 to force INTR_STATE.powered to 1.

Write 1 to force INTR_STATE.link_out_err to 1.

Reset default = 0x0, mask 0x1
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 fatal_fault
BitsTypeResetNameDescription
0wo0x0fatal_fault

Write 1 to trigger one alert event of this kind.

usbdev.usbctrl @ 0x10

USB Control

Reset default = 0x0, mask 0x7f0003
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 device_address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 resume_link_active enable
BitsTypeResetNameDescription
0rw0x0enable

Set to connect the USB interface (i.e. assert the pullup).

Write a 1 to this bit to instruct usbdev to jump to the LinkResuming state. The write will only have an effect when the device is in the LinkPowered state. Its intention is to handle a resume-from-suspend event after the IP has been powered down.

15:2Reserved

Device address set by host (this should be copied from the Set Device ID SETUP packet).

This will be zeroed by the hardware when the link resets.

usbdev.ep_out_enable @ 0x14

Enable an endpoint to respond to transactions in the downstream direction. Note that as the default endpoint, endpoint 0 must be enabled in both the IN and OUT directions before enabling the USB interface to connect.

Reset default = 0x0, mask 0xfff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 enable_11 enable_10 enable_9 enable_8 enable_7 enable_6 enable_5 enable_4 enable_3 enable_2 enable_1 enable_0
BitsTypeResetNameDescription
0rw0x0enable_0

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

1rw0x0enable_1

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

2rw0x0enable_2

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

3rw0x0enable_3

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

4rw0x0enable_4

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

5rw0x0enable_5

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

6rw0x0enable_6

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

7rw0x0enable_7

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

8rw0x0enable_8

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

9rw0x0enable_9

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

10rw0x0enable_10

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

11rw0x0enable_11

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

usbdev.ep_in_enable @ 0x18

Enable an endpoint to respond to transactions in the upstream direction. Note that as the default endpoint, endpoint 0 must be enabled in both the IN and OUT directions before enabling the USB interface to connect.

Reset default = 0x0, mask 0xfff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 enable_11 enable_10 enable_9 enable_8 enable_7 enable_6 enable_5 enable_4 enable_3 enable_2 enable_1 enable_0
BitsTypeResetNameDescription
0rw0x0enable_0

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

1rw0x0enable_1

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

2rw0x0enable_2

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

3rw0x0enable_3

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

4rw0x0enable_4

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

5rw0x0enable_5

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

6rw0x0enable_6

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

7rw0x0enable_7

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

8rw0x0enable_8

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

9rw0x0enable_9

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

10rw0x0enable_10

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

11rw0x0enable_11

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

usbdev.usbstat @ 0x1c

USB Status

Reset default = 0x80000000, mask 0x8787ffff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rx_empty rx_depth av_full av_depth 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sense link_state host_lost frame
BitsTypeResetNameDescription
10:0roxframe

Frame index received from host. On an active link, this will increment every milisecond.

11roxhost_lost

Start of frame not received from host for 4.096 ms and the line is active.

State of USB link, decoded from line.

 0x0 disconnected Link disconnected (no VBUS or no pull-up connected) 0x1 powered Link powered and connected, but not reset yet 0x2 powered_suspended Link suspended (constant idle/J for > 3 ms), but not reset yet 0x3 active Link active 0x4 suspended Link suspended (constant idle for > 3 ms), was active before becoming suspended 0x5 active_nosof Link active but no SOF has been received since the last reset. 0x6 resuming Link resuming to an active state, pending the end of resume signaling

Other values are reserved.

15roxsense

Reflects the state of the sense pin. 1 indicates that the host is providing VBUS. Note that this bit always shows the state of the actual pin and does not take account of the override control.

18:16roxav_depth

Number of buffers in the Available Buffer FIFO.

These buffers are available for receiving packets.

22:19Reserved
23roxav_full

Available Buffer FIFO is full.

26:24roxrx_depth

Number of buffers in the Received Buffer FIFO.

These buffers have packets that have been received and should be popped from the FIFO and processed.

30:27Reserved
31ro0x1rx_empty

usbdev.avbuffer @ 0x20

Available Buffer FIFO

Reset default = 0x0, mask 0x1f
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 buffer
BitsTypeResetNameDescription
4:0wo0x0buffer

This field contains the buffer ID being passed to the USB receive engine.

If the Available Buffer FIFO is full, any write operations are discarded.

usbdev.rxfifo @ 0x24

Reset default = 0x0, mask 0xf87f1f
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ep setup 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 size buffer
BitsTypeResetNameDescription
4:0roxbuffer

This field contains the buffer ID that data was received into. On read the buffer ID is popped from the Received Buffer FIFO and returned to software.

7:5Reserved
14:8roxsize

This field contains the data length in bytes of the packet written to the buffer.

18:15Reserved
19roxsetup

This bit indicates if the received transaction is of type SETUP (1) or OUT (0).

23:20roxep

This field contains the endpoint ID to which the packet was directed.

usbdev.rxenable_setup @ 0x28

Reset default = 0x0, mask 0xfff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 setup_11 setup_10 setup_9 setup_8 setup_7 setup_6 setup_5 setup_4 setup_3 setup_2 setup_1 setup_0
BitsTypeResetNameDescription
0rw0x0setup_0

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

1rw0x0setup_1

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

2rw0x0setup_2

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

3rw0x0setup_3

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

4rw0x0setup_4

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

5rw0x0setup_5

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

6rw0x0setup_6

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

7rw0x0setup_7

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

8rw0x0setup_8

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

9rw0x0setup_9

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

10rw0x0setup_10

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

11rw0x0setup_11

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

usbdev.rxenable_out @ 0x2c

Reset default = 0x0, mask 0xfff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 out_11 out_10 out_9 out_8 out_7 out_6 out_5 out_4 out_3 out_2 out_1 out_0
BitsTypeResetNameDescription
0rw0x0out_0

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

1rw0x0out_1

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

2rw0x0out_2

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

3rw0x0out_3

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

4rw0x0out_4

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

5rw0x0out_5

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

6rw0x0out_6

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

7rw0x0out_7

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

8rw0x0out_8

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

9rw0x0out_9

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

10rw0x0out_10

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

11rw0x0out_11

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

usbdev.set_nak_out @ 0x30

Set NAK after OUT transactions

Reset default = 0x0, mask 0xfff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 enable_11 enable_10 enable_9 enable_8 enable_7 enable_6 enable_5 enable_4 enable_3 enable_2 enable_1 enable_0
BitsTypeResetNameDescription
0rw0x0enable_0

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

1rw0x0enable_1

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

2rw0x0enable_2

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

3rw0x0enable_3

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

4rw0x0enable_4

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

5rw0x0enable_5

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

6rw0x0enable_6

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

7rw0x0enable_7

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

8rw0x0enable_8

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

9rw0x0enable_9

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

10rw0x0enable_10

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

11rw0x0enable_11

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

usbdev.in_sent @ 0x34

IN Transaction Sent

Reset default = 0x0, mask 0xfff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sent_11 sent_10 sent_9 sent_8 sent_7 sent_6 sent_5 sent_4 sent_3 sent_2 sent_1 sent_0
BitsTypeResetNameDescription
0rw1c0x0sent_0

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

1rw1c0x0sent_1

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

2rw1c0x0sent_2

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

3rw1c0x0sent_3

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

4rw1c0x0sent_4

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

5rw1c0x0sent_5

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

6rw1c0x0sent_6

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

7rw1c0x0sent_7

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

8rw1c0x0sent_8

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

9rw1c0x0sent_9

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

10rw1c0x0sent_10

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

11rw1c0x0sent_11

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

usbdev.out_stall @ 0x38

OUT Endpoint STALL control

Reset default = 0x0, mask 0xfff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 endpoint_11 endpoint_10 endpoint_9 endpoint_8 endpoint_7 endpoint_6 endpoint_5 endpoint_4 endpoint_3 endpoint_2 endpoint_1 endpoint_0
BitsTypeResetNameDescription
0rw0x0endpoint_0

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

1rw0x0endpoint_1

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

2rw0x0endpoint_2

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

3rw0x0endpoint_3

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

4rw0x0endpoint_4

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

5rw0x0endpoint_5

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

6rw0x0endpoint_6

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

7rw0x0endpoint_7

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

8rw0x0endpoint_8

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

9rw0x0endpoint_9

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

10rw0x0endpoint_10

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

11rw0x0endpoint_11

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

usbdev.in_stall @ 0x3c

IN Endpoint STALL control

Reset default = 0x0, mask 0xfff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 endpoint_11 endpoint_10 endpoint_9 endpoint_8 endpoint_7 endpoint_6 endpoint_5 endpoint_4 endpoint_3 endpoint_2 endpoint_1 endpoint_0
BitsTypeResetNameDescription
0rw0x0endpoint_0

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

1rw0x0endpoint_1

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

2rw0x0endpoint_2

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

3rw0x0endpoint_3

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

4rw0x0endpoint_4

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

5rw0x0endpoint_5

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

6rw0x0endpoint_6

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

7rw0x0endpoint_7

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

8rw0x0endpoint_8

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

9rw0x0endpoint_9

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

10rw0x0endpoint_10

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

11rw0x0endpoint_11

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

usbdev.configin_0 @ 0x40

Configure IN Transaction

Reset default = 0x0, mask 0xc0007f1f
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rdy_0 pend_0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 size_0 buffer_0
BitsTypeResetNameDescription
4:0rw0x0buffer_0

The buffer ID containing the data to send when an IN transaction is received on the endpoint.

7:5Reserved
14:8rw0x0size_0

The number of bytes to send from the buffer.

If this is 0 then a CRC only packet is sent.

If this is greater than 64 then 64 bytes are sent.

29:15Reserved
30rw1c0x0pend_0

This bit indicates a pending transaction was canceled by the hardware.

The bit is set when the rdy bit is cleared by hardware because of a SETUP packet being received or a link reset being detected.

The bit remains set until cleared by being written with a 1.

31rw0x0rdy_0

This bit should be set to indicate the buffer is ready for sending. It will be cleared when the ACK is received indicating the host has accepted the data.

This bit will also be cleared if an enabled SETUP transaction is received on the endpoint. This allows use of the IN channel for transfer of SETUP information. The original buffer must be resubmitted after the SETUP sequence is complete. A link reset also clears the bit. In either of the cases where the hardware cancels the transaction it will also set the pend bit.

usbdev.configin_1 @ 0x44

Configure IN Transaction

Reset default = 0x0, mask 0xc0007f1f
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rdy_1 pend_1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 size_1 buffer_1
BitsTypeResetNameDescription
4:0rw0x0buffer_1

For Endpoint1

7:5Reserved
14:8rw0x0size_1

For Endpoint1

29:15Reserved
30rw1c0x0pend_1

For Endpoint1

31rw0x0rdy_1

For Endpoint1

usbdev.configin_2 @ 0x48

Configure IN Transaction

Reset default = 0x0, mask 0xc0007f1f
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rdy_2 pend_2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 size_2 buffer_2
BitsTypeResetNameDescription
4:0rw0x0buffer_2

For Endpoint2

7:5Reserved
14:8rw0x0size_2

For Endpoint2

29:15Reserved
30rw1c0x0pend_2

For Endpoint2

31rw0x0rdy_2

For Endpoint2

usbdev.configin_3 @ 0x4c

Configure IN Transaction

Reset default = 0x0, mask 0xc0007f1f
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rdy_3 pend_3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 size_3 buffer_3
BitsTypeResetNameDescription
4:0rw0x0buffer_3

For Endpoint3

7:5Reserved
14:8rw0x0size_3

For Endpoint3

29:15Reserved
30rw1c0x0pend_3

For Endpoint3

31rw0x0rdy_3

For Endpoint3

usbdev.configin_4 @ 0x50

Configure IN Transaction

Reset default = 0x0, mask 0xc0007f1f
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rdy_4 pend_4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 size_4 buffer_4
BitsTypeResetNameDescription
4:0rw0x0buffer_4

For Endpoint4

7:5Reserved
14:8rw0x0size_4

For Endpoint4

29:15Reserved
30rw1c0x0pend_4

For Endpoint4

31rw0x0rdy_4

For Endpoint4

usbdev.configin_5 @ 0x54

Configure IN Transaction

Reset default = 0x0, mask 0xc0007f1f
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rdy_5 pend_5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 size_5 buffer_5
BitsTypeResetNameDescription
4:0rw0x0buffer_5

For Endpoint5

7:5Reserved
14:8rw0x0size_5

For Endpoint5

29:15Reserved
30rw1c0x0pend_5

For Endpoint5

31rw0x0rdy_5

For Endpoint5

usbdev.configin_6 @ 0x58

Configure IN Transaction

Reset default = 0x0, mask 0xc0007f1f
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rdy_6 pend_6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 size_6 buffer_6
BitsTypeResetNameDescription
4:0rw0x0buffer_6

For Endpoint6

7:5Reserved
14:8rw0x0size_6

For Endpoint6

29:15Reserved
30rw1c0x0pend_6

For Endpoint6

31rw0x0rdy_6

For Endpoint6

usbdev.configin_7 @ 0x5c

Configure IN Transaction

Reset default = 0x0, mask 0xc0007f1f
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rdy_7 pend_7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 size_7 buffer_7
BitsTypeResetNameDescription
4:0rw0x0buffer_7

For Endpoint7

7:5Reserved
14:8rw0x0size_7

For Endpoint7

29:15Reserved
30rw1c0x0pend_7

For Endpoint7

31rw0x0rdy_7

For Endpoint7

usbdev.configin_8 @ 0x60

Configure IN Transaction

Reset default = 0x0, mask 0xc0007f1f
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rdy_8 pend_8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 size_8 buffer_8
BitsTypeResetNameDescription
4:0rw0x0buffer_8

For Endpoint8

7:5Reserved
14:8rw0x0size_8

For Endpoint8

29:15Reserved
30rw1c0x0pend_8

For Endpoint8

31rw0x0rdy_8

For Endpoint8

usbdev.configin_9 @ 0x64

Configure IN Transaction

Reset default = 0x0, mask 0xc0007f1f
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rdy_9 pend_9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 size_9 buffer_9
BitsTypeResetNameDescription
4:0rw0x0buffer_9

For Endpoint9

7:5Reserved
14:8rw0x0size_9

For Endpoint9

29:15Reserved
30rw1c0x0pend_9

For Endpoint9

31rw0x0rdy_9

For Endpoint9

usbdev.configin_10 @ 0x68

Configure IN Transaction

Reset default = 0x0, mask 0xc0007f1f
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rdy_10 pend_10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 size_10 buffer_10
BitsTypeResetNameDescription
4:0rw0x0buffer_10

For Endpoint10

7:5Reserved
14:8rw0x0size_10

For Endpoint10

29:15Reserved
30rw1c0x0pend_10

For Endpoint10

31rw0x0rdy_10

For Endpoint10

usbdev.configin_11 @ 0x6c

Configure IN Transaction

Reset default = 0x0, mask 0xc0007f1f
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rdy_11 pend_11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 size_11 buffer_11
BitsTypeResetNameDescription
4:0rw0x0buffer_11

For Endpoint11

7:5Reserved
14:8rw0x0size_11

For Endpoint11

29:15Reserved
30rw1c0x0pend_11

For Endpoint11

31rw0x0rdy_11

For Endpoint11

usbdev.out_iso @ 0x70

OUT Endpoint isochronous setting

Reset default = 0x0, mask 0xfff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 iso_11 iso_10 iso_9 iso_8 iso_7 iso_6 iso_5 iso_4 iso_3 iso_2 iso_1 iso_0
BitsTypeResetNameDescription
0rw0x0iso_0

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

1rw0x0iso_1

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

2rw0x0iso_2

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

3rw0x0iso_3

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

4rw0x0iso_4

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

5rw0x0iso_5

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

6rw0x0iso_6

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

7rw0x0iso_7

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

8rw0x0iso_8

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

9rw0x0iso_9

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

10rw0x0iso_10

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

11rw0x0iso_11

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

usbdev.in_iso @ 0x74

IN Endpoint isochronous setting

Reset default = 0x0, mask 0xfff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 iso_11 iso_10 iso_9 iso_8 iso_7 iso_6 iso_5 iso_4 iso_3 iso_2 iso_1 iso_0
BitsTypeResetNameDescription
0rw0x0iso_0

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

1rw0x0iso_1

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

2rw0x0iso_2

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

3rw0x0iso_3

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

4rw0x0iso_4

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

5rw0x0iso_5

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

6rw0x0iso_6

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

7rw0x0iso_7

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

8rw0x0iso_8

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

9rw0x0iso_9

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

10rw0x0iso_10

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

11rw0x0iso_11

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

usbdev.data_toggle_clear @ 0x78

Clear the data toggle flag

Reset default = 0x0, mask 0xfff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 clear_11 clear_10 clear_9 clear_8 clear_7 clear_6 clear_5 clear_4 clear_3 clear_2 clear_1 clear_0
BitsTypeResetNameDescription
0wo0x0clear_0

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

1wo0x0clear_1

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

2wo0x0clear_2

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

3wo0x0clear_3

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

4wo0x0clear_4

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

5wo0x0clear_5

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

6wo0x0clear_6

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

7wo0x0clear_7

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

8wo0x0clear_8

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

9wo0x0clear_9

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

10wo0x0clear_10

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

11wo0x0clear_11

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

usbdev.phy_pins_sense @ 0x7c

USB PHY pins sense. This register can be used to read out the state of the USB device inputs and outputs from software. This is designed to be used for debugging purposes or during chip testing.

Reset default = 0x0, mask 0x11f07
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 pwr_sense 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tx_oe_o tx_se0_o tx_d_o tx_dn_o tx_dp_o rx_d_i rx_dn_i rx_dp_i
BitsTypeResetNameDescription
0roxrx_dp_i

USB D+ input.

1roxrx_dn_i

USB D- input.

2roxrx_d_i

USB data input from an external differential receiver, if available.

7:3Reserved
8roxtx_dp_o

9roxtx_dn_o

10roxtx_d_o

11roxtx_se0_o

12roxtx_oe_o

15:13Reserved
16roxpwr_sense

USB power sense signal.

usbdev.phy_pins_drive @ 0x80

USB PHY pins drive. This register can be used to control the USB device inputs and outputs from software. This is designed to be used for debugging purposes or during chip testing.

Reset default = 0x0, mask 0x100ff
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 en 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dn_pullup_en_o dp_pullup_en_o rx_enable_o oe_o se0_o d_o dn_o dp_o
BitsTypeResetNameDescription
0rw0x0dp_o

USB transmit D+ output, used with dn_o.

1rw0x0dn_o

USB transmit D- output, used with dp_o.

2rw0x0d_o

USB transmit data output, encoding K and J when se0_o is 0.

3rw0x0se0_o

USB single-ended zero output.

4rw0x0oe_o

USB OE output.

5rw0x0rx_enable_o

6rw0x0dp_pullup_en_o

USB D+ pullup enable output.

7rw0x0dn_pullup_en_o

USB D- pullup enable output.

15:8Reserved
16rw0x0en

0: Outputs are controlled by the hardware block. 1: Outputs are controlled with this register.

usbdev.phy_config @ 0x84

USB PHY Configuration

Reset default = 0x4, mask 0xe7
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tx_osc_test_mode usb_ref_disable pinflip eop_single_bit tx_use_d_se0 use_diff_rcvr
BitsTypeResetNameDescription
0rw0x0use_diff_rcvr

Detect received K and J symbols from the usb_rx_d signal, which must be driven from an external differential receiver. If 1, make use of the usb_rx_d input. If 0, the usb_rx_d input is ignored and the usb_rx_dp and usb_rx_dn pair are used to detect K and J (useful for some environments, but will be unlikely to pass full USB compliance). Regardless of the state of this field usb_rx_dp and usb_rx_dn are always used to detect SE0. This bit also feeds the rx_enable pin, activating the receiver when the device is not suspended.

1rw0x0tx_use_d_se0

If 1, select the d and se0 TX interface. If 0, select the dp and dn TX interface. This directly controls the output pin of the same name. It is intended to be used to enable the use of a variety of external transceivers, to select an encoding that matches the transceiver.

2rw0x1eop_single_bit

Recognize a single SE0 bit as an end of packet, otherwise two successive bits are required.

4:3Reserved
5rw0x0pinflip

Flip the D+/D- pins. Particularly useful if D+/D- are mapped to SBU1/SBU2 pins of USB-C.

6rw0x0usb_ref_disable

0: Enable reference signal generation for clock synchronization, 1: disable it by forcing the associated signals to zero.

7rw0x0tx_osc_test_mode

Disable (0) or enable (1) oscillator test mode. If enabled, the device constantly transmits a J/K pattern, which is useful for testing the USB clock. Note that while in oscillator test mode, the device no longer receives SOFs and consequently does not generate the reference signal for clock synchronization. The clock might drift off.

usbdev.wake_control @ 0x88

USB wake module control for suspend / resume

Reset default = 0x0, mask 0x3
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wake_ack suspend_req
BitsTypeResetNameDescription
0wo0x0suspend_req

Suspend request to the wake detection module.

Trigger the wake detection module to begin monitoring for wake-from-suspend events. When written with a 1, the wake detection module will activate. Activation may not happen immediately, and its status can be verified by checking wake_events.module_active.

1wo0x0wake_ack

Wake acknowledgement.

Signal to the wake detection module that it may release control of the pull-ups back to the main block and return to an inactive state. The release back to normal state may not happen immediately. The status can be confirmed via wake_events.module_active.

Note that this bit can also be used without powering down, such as when usbdev detects resume signaling before transitions to low power states have begun.

usbdev.wake_events @ 0x8c

USB wake module events and debug

Reset default = 0x0, mask 0x301
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bus_reset disconnected module_active
BitsTypeResetNameDescription
0ro0x0module_active

USB aon wake module is active, monitoring events and controlling the pull-ups.

7:1Reserved
8ro0x0disconnected

USB aon wake module detected VBUS was interrupted while monitoring events.

9ro0x0bus_reset

USB aon wake module detected a bus reset while monitoring events.

usbdev.buffer @ + 0x800
512 item rw window
Byte writes are not supported
 31 0 +0x800 +0x804 ... +0xff8 +0xffc

2 kB packet buffer. Divided into 32 64-byte buffers.

The packet buffer is used for sending and receiveing packets.

## Application to FPGAs

For better receive sensitivity, lower transmit jitter and to be standard compliant, a dedicated, differential USB transceiver such as the USB1T11A or the USB1T20 must be used (see Section 7.1.4.1 of the USB 2.0 specification). Depending on the selected USB transceiver, either the dp/dn or d/se0 transmit paths or can be used to interface the IP block with the transceiver. If the selected USB transceiver contains a differential receiver, its output may also be enabled and passed to the D input of the IP block.

When prototyping on FPGAs the interface can be implemented with pseudo-differential 3.3V GPIO pins for D+ and D-. The receiver will oversample to recover the bitstream and clock alignment even if there is considerable timing skew between the signal paths. The full speed transmit always uses LVCMOS output drivers (see USB 2.0 spec Figure 7-1 and Figure 7-3) but there are two possible encodings: Either the D+ and D- values are directly driven from tx_dp and tx_dn, or there is a data value from tx_d and an indicator to force SE0 from tx_se0. External to the IP, these should be combined to drive the actual pins when transmit is enabled and receive otherwise. Using standard 3.3V IO pads allows use on most FPGAs although the drive strength and series termination resistors may need to be adjusted to meet the USB signal eye. On a Xilinx Artix-7 (and less well tested Spartan-7) part, setting the driver to the 8mA, FAST setting seems to work well with a 22R series termination (and with a 0R series termination).

### FPGA Board Implementation With PMOD

The interface was developed using the Digilent Nexys Video board with a PMOD card attached. A PMOD interface with direct connection to the SoC should be used (some PMOD interfaces include 100R series resistors which break the signal requirements for USB). The PMOD card includes two USB micro-B connectors and allows two USB interfaces to be used. The D+ and D- signals have 22R series resistors (in line with the USB spec) and there is a 1.5k pullup on D+ to the pullup enable signal. There is a resistive divider to set the sense pin at half of the VBUS voltage which enables detection on the FPGA without overvoltage on the pin.

The PMOD PCB is available from OSH Park.

The PMOD design files for KiCad version 5 are in the usbdev/pmod directory. The BOM can be filled by parts from Digikey.

Item Qty Reference(s) Value LibPart Footprint Datasheet Category DK_Datasheet_Link DK_Detail_Page Description Digi-Key_PN Family MPN Manufacturer Status
1 2 J1, J2 10118193-0001LF dualpmod-rescue:10118193-0001LF-dk_USB-DVI-HDMI-Connectors digikey-footprints:USB_Micro_B_Female_10118193-0001LF http://www.amphenol-icc.com/media/wysiwyg/files/drawing/10118193.pdf Connectors, Interconnects http://www.amphenol-icc.com/media/wysiwyg/files/drawing/10118193.pdf /product-detail/en/amphenol-icc-fci/10118193-0001LF/609-4616-1-ND/2785380 CONN RCPT USB2.0 MICRO B SMD R/A 609-4616-1-ND USB, DVI, HDMI Connectors 10118193-0001LF Amphenol ICC (FCI) Active
2 1 J3 68021-412HLF dualpmod-rescue:68021-412HLF-dk_Rectangular-Connectors-Headers-Male-Pins digikey-footprints:PinHeader_6x2_P2.54mm_Horizontal https://cdn.amphenol-icc.com/media/wysiwyg/files/drawing/68020.pdf Connectors, Interconnects https://cdn.amphenol-icc.com/media/wysiwyg/files/drawing/68020.pdf /product-detail/en/amphenol-icc-fci/68021-412HLF/609-3355-ND/1878558 CONN HEADER R/A 12POS 2.54MM 609-3355-ND Rectangular Connectors - Headers, Male Pins 68021-412HLF Amphenol ICC (FCI) Active
3 4 R1, R2, R7, R8 5k1 Device:R_Small_US Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder ~ A126379CT-ND
4 4 R3, R4, R5, R6 22R Device:R_Small_US Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder ~ A126352CT-ND
5 2 R9, R10 1k5 Device:R_Small_US Resistor_SMD:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder ~ A106057CT-ND